VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 40446

Last change on this file since 40446 was 40446, checked in by vboxsync, 13 years ago

EM: One more EMInterpretInstructionCPU usage.
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1/* $Id: EMAll.cpp 40446 2012-03-13 15:16:30Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor(/Manager) - All contexts
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_EM
22#include <VBox/vmm/em.h>
23#include <VBox/vmm/mm.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/patm.h>
26#include <VBox/vmm/csam.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/iom.h>
29#include <VBox/vmm/stam.h>
30#include "EMInternal.h"
31#include <VBox/vmm/vm.h>
32#include <VBox/vmm/vmm.h>
33#include <VBox/vmm/hwaccm.h>
34#include <VBox/vmm/tm.h>
35#include <VBox/vmm/pdmapi.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/dis.h>
39#include <VBox/disopcode.h>
40#include <VBox/log.h>
41#include "internal/pgm.h"
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45
46
47/*******************************************************************************
48* Defined Constants And Macros *
49*******************************************************************************/
50/** @def EM_ASSERT_FAULT_RETURN
51 * Safety check.
52 *
53 * Could in theory misfire on a cross page boundary access...
54 *
55 * Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
56 * turns up an alias page instead of the original faulting one and annoying the
57 * heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
58 */
59#if 0
60# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
61#else
62# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
63#endif
64
65/** Used to pass information during instruction disassembly. */
66typedef struct
67{
68 PVM pVM;
69 PVMCPU pVCpu;
70 RTGCPTR GCPtr;
71 uint8_t aOpcode[8];
72} EMDISSTATE, *PEMDISSTATE;
73
74/*******************************************************************************
75* Internal Functions *
76*******************************************************************************/
77#ifndef VBOX_WITH_IEM
78DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
79 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
80#endif
81
82
83
84/**
85 * Get the current execution manager status.
86 *
87 * @returns Current status.
88 * @param pVCpu The VMCPU to operate on.
89 */
90VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu)
91{
92 return pVCpu->em.s.enmState;
93}
94
95/**
96 * Sets the current execution manager status. (use only when you know what you're doing!)
97 *
98 * @param pVCpu The VMCPU to operate on.
99 */
100VMMDECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
101{
102 /* Only allowed combination: */
103 Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
104 pVCpu->em.s.enmState = enmNewState;
105}
106
107
108/**
109 * Sets the PC for which interrupts should be inhibited.
110 *
111 * @param pVCpu The VMCPU handle.
112 * @param PC The PC.
113 */
114VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
115{
116 pVCpu->em.s.GCPtrInhibitInterrupts = PC;
117 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
118}
119
120
121/**
122 * Gets the PC for which interrupts should be inhibited.
123 *
124 * There are a few instructions which inhibits or delays interrupts
125 * for the instruction following them. These instructions are:
126 * - STI
127 * - MOV SS, r/m16
128 * - POP SS
129 *
130 * @returns The PC for which interrupts should be inhibited.
131 * @param pVCpu The VMCPU handle.
132 *
133 */
134VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
135{
136 return pVCpu->em.s.GCPtrInhibitInterrupts;
137}
138
139
140/**
141 * Prepare an MWAIT - essentials of the MONITOR instruction.
142 *
143 * @returns VINF_SUCCESS
144 * @param pVCpu The current CPU.
145 * @param rax The content of RAX.
146 * @param rcx The content of RCX.
147 * @param rdx The content of RDX.
148 */
149VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx)
150{
151 pVCpu->em.s.MWait.uMonitorRAX = rax;
152 pVCpu->em.s.MWait.uMonitorRCX = rcx;
153 pVCpu->em.s.MWait.uMonitorRDX = rdx;
154 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_MONITOR_ACTIVE;
155 /** @todo Complete MONITOR implementation. */
156 return VINF_SUCCESS;
157}
158
159
160/**
161 * Performs an MWAIT.
162 *
163 * @returns VINF_SUCCESS
164 * @param pVCpu The current CPU.
165 * @param rax The content of RAX.
166 * @param rcx The content of RCX.
167 */
168VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
169{
170 pVCpu->em.s.MWait.uMWaitRAX = rax;
171 pVCpu->em.s.MWait.uMWaitRCX = rcx;
172 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_ACTIVE;
173 if (rcx)
174 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_BREAKIRQIF0;
175 else
176 pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
177 /** @todo not completely correct?? */
178 return VINF_EM_HALT;
179}
180
181
182
183/**
184 * Determine if we should continue after encountering a hlt or mwait
185 * instruction.
186 *
187 * Clears MWAIT flags if returning @c true.
188 *
189 * @returns boolean
190 * @param pVCpu The VMCPU to operate on.
191 * @param pCtx Current CPU context.
192 */
193VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
194{
195 if ( pCtx->eflags.Bits.u1IF
196 || ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
197 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) )
198 {
199 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
200 return !!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC));
201 }
202
203 return false;
204}
205
206
207/**
208 * Locks REM execution to a single VCpu
209 *
210 * @param pVM VM handle.
211 */
212VMMDECL(void) EMRemLock(PVM pVM)
213{
214#ifdef VBOX_WITH_REM
215 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
216 return; /* early init */
217
218 Assert(!PGMIsLockOwner(pVM));
219 Assert(!IOMIsLockOwner(pVM));
220 int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
221 AssertRCSuccess(rc);
222#endif
223}
224
225
226/**
227 * Unlocks REM execution
228 *
229 * @param pVM VM handle.
230 */
231VMMDECL(void) EMRemUnlock(PVM pVM)
232{
233#ifdef VBOX_WITH_REM
234 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
235 return; /* early init */
236
237 PDMCritSectLeave(&pVM->em.s.CritSectREM);
238#endif
239}
240
241
242/**
243 * Check if this VCPU currently owns the REM lock.
244 *
245 * @returns bool owner/not owner
246 * @param pVM The VM to operate on.
247 */
248VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
249{
250#ifdef VBOX_WITH_REM
251 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
252 return true; /* early init */
253
254 return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
255#else
256 return true;
257#endif
258}
259
260
261/**
262 * Try to acquire the REM lock.
263 *
264 * @returns VBox status code
265 * @param pVM The VM to operate on.
266 */
267VMMDECL(int) EMRemTryLock(PVM pVM)
268{
269#ifdef VBOX_WITH_REM
270 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
271 return VINF_SUCCESS; /* early init */
272
273 return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
274#else
275 return VINF_SUCCESS;
276#endif
277}
278
279
280/**
281 * Read callback for disassembly function; supports reading bytes that cross a page boundary
282 *
283 * @returns VBox status code.
284 * @param pSrc GC source pointer
285 * @param pDest HC destination pointer
286 * @param cb Number of bytes to read
287 * @param dwUserdata Callback specific user data (pDis)
288 *
289 */
290static DECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t *pDest, unsigned cb, void *pvUserdata)
291{
292 PDISCPUSTATE pDis = (PDISCPUSTATE)pvUserdata;
293 PEMDISSTATE pState = (PEMDISSTATE)pDis->apvUserData[0];
294# ifndef IN_RING0
295 PVM pVM = pState->pVM;
296# endif
297 PVMCPU pVCpu = pState->pVCpu;
298
299# ifdef IN_RING0
300 int rc;
301
302 if ( pState->GCPtr
303 && pSrc + cb <= pState->GCPtr + sizeof(pState->aOpcode))
304 {
305 unsigned offset = pSrc - pState->GCPtr;
306
307 Assert(pSrc >= pState->GCPtr);
308
309 for (unsigned i=0; i<cb; i++)
310 {
311 pDest[i] = pState->aOpcode[offset + i];
312 }
313 return VINF_SUCCESS;
314 }
315
316 rc = PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, cb);
317 AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%RGv cb=%x rc=%d\n", pSrc, cb, rc));
318# elif defined(IN_RING3)
319 if (!PATMIsPatchGCAddr(pVM, pSrc))
320 {
321 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, cb);
322 AssertRC(rc);
323 }
324 else
325 memcpy(pDest, PATMR3GCPtrToHCPtr(pVM, pSrc), cb);
326
327# elif defined(IN_RC)
328 if (!PATMIsPatchGCAddr(pVM, pSrc))
329 {
330 int rc = MMGCRamRead(pVM, pDest, (void *)(uintptr_t)pSrc, cb);
331 if (rc == VERR_ACCESS_DENIED)
332 {
333 /* Recently flushed; access the data manually. */
334 rc = PGMPhysSimpleReadGCPtr(pVCpu, pDest, pSrc, cb);
335 AssertRC(rc);
336 }
337 }
338 else /* the hypervisor region is always present. */
339 memcpy(pDest, (RTRCPTR)(uintptr_t)pSrc, cb);
340
341# endif /* IN_RING3 */
342 return VINF_SUCCESS;
343}
344
345
346#ifndef IN_RC
347DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
348{
349 EMDISSTATE State;
350
351 State.pVM = pVM;
352 State.pVCpu = pVCpu;
353 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &State.aOpcode, InstrGC, sizeof(State.aOpcode));
354 if (RT_SUCCESS(rc))
355 {
356 State.GCPtr = InstrGC;
357 }
358 else
359 {
360 if (PAGE_ADDRESS(InstrGC) == PAGE_ADDRESS(InstrGC + sizeof(State.aOpcode) - 1))
361 {
362 if (rc == VERR_PAGE_TABLE_NOT_PRESENT)
363 HWACCMInvalidatePage(pVCpu, InstrGC);
364
365 Log(("emDisCoreOne: read failed with %d\n", rc));
366 return rc;
367 }
368 State.GCPtr = NIL_RTGCPTR;
369 }
370 return DISCoreOneEx(InstrGC, pDis->mode, EMReadBytes, &State, pDis, pOpsize);
371}
372
373#else /* IN_RC */
374
375DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
376{
377 EMDISSTATE State;
378
379 State.pVM = pVM;
380 State.pVCpu = pVCpu;
381 State.GCPtr = InstrGC;
382
383 return DISCoreOneEx(InstrGC, pDis->mode, EMReadBytes, &State, pDis, pOpsize);
384}
385
386#endif /* IN_RC */
387
388
389/**
390 * Disassembles one instruction.
391 *
392 * @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
393 * details.
394 * @retval VERR_EM_INTERNAL_DISAS_ERROR on DISCoreOneEx failure.
395 *
396 * @param pVM The VM handle.
397 * @param pVCpu The VMCPU handle.
398 * @param pCtxCore The context core (used for both the mode and instruction).
399 * @param pDis Where to return the parsed instruction info.
400 * @param pcbInstr Where to return the instruction size. (optional)
401 */
402VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr)
403{
404 RTGCPTR GCPtrInstr;
405 int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
406 if (RT_FAILURE(rc))
407 {
408 Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
409 pCtxCore->cs, (RTGCPTR)pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
410 return rc;
411 }
412 return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
413}
414
415
416/**
417 * Disassembles one instruction.
418 *
419 * This is used by internally by the interpreter and by trap/access handlers.
420 *
421 * @returns VBox status code.
422 * @retval VERR_EM_INTERNAL_DISAS_ERROR on DISCoreOneEx failure.
423 *
424 * @param pVM The VM handle.
425 * @param pVCpu The VMCPU handle.
426 * @param GCPtrInstr The flat address of the instruction.
427 * @param pCtxCore The context core (used to determine the cpu mode).
428 * @param pDis Where to return the parsed instruction info.
429 * @param pcbInstr Where to return the instruction size. (optional)
430 */
431VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pDis, unsigned *pcbInstr)
432{
433 int rc;
434 EMDISSTATE State;
435
436 State.pVM = pVM;
437 State.pVCpu = pVCpu;
438
439#ifdef IN_RC
440 State.GCPtr = GCPtrInstr;
441#else /* ring 0/3 */
442 rc = PGMPhysSimpleReadGCPtr(pVCpu, &State.aOpcode, GCPtrInstr, sizeof(State.aOpcode));
443 if (RT_SUCCESS(rc))
444 {
445 State.GCPtr = GCPtrInstr;
446 }
447 else
448 {
449 if (PAGE_ADDRESS(GCPtrInstr) == PAGE_ADDRESS(GCPtrInstr + sizeof(State.aOpcode) - 1))
450 {
451 if (rc == VERR_PAGE_TABLE_NOT_PRESENT)
452 HWACCMInvalidatePage(pVCpu, GCPtrInstr);
453
454 Log(("EMInterpretDisasOneEx: read failed with %d\n", rc));
455 return rc;
456 }
457 State.GCPtr = NIL_RTGCPTR;
458 }
459#endif
460
461 rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
462 EMReadBytes, &State,
463 pDis, pcbInstr);
464 if (RT_SUCCESS(rc))
465 return VINF_SUCCESS;
466 AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
467 return VERR_EM_INTERNAL_DISAS_ERROR;
468}
469
470
471/**
472 * Interprets the current instruction.
473 *
474 * @returns VBox status code.
475 * @retval VINF_* Scheduling instructions.
476 * @retval VERR_EM_INTERPRETER Something we can't cope with.
477 * @retval VERR_* Fatal errors.
478 *
479 * @param pVM The VM handle.
480 * @param pVCpu The VMCPU handle.
481 * @param pRegFrame The register frame.
482 * Updates the EIP if an instruction was executed successfully.
483 * @param pvFault The fault address (CR2).
484 * @param pcbSize Size of the write (if applicable).
485 *
486 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
487 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
488 * to worry about e.g. invalid modrm combinations (!)
489 */
490VMMDECL(VBOXSTRICTRC) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
491{
492 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
493#ifdef VBOX_WITH_IEM
494 int rc = IEMExecOneEx(pVCpu, pRegFrame, IEM_EXEC_ONE_EX_FLAGS_, pcbSize);
495 if (RT_FAILURE(rc))
496 switch (rc)
497 {
498 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
499 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
500 return VERR_EM_INTERPRETER;
501 }
502 return rc;
503#else
504 RTGCPTR pbCode;
505 VBOXSTRICTRC rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
506 if (RT_SUCCESS(rc))
507 {
508 uint32_t cbOp;
509 PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
510 pDis->mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
511 rc = emDisCoreOne(pVM, pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
512 if (RT_SUCCESS(rc))
513 {
514 Assert(cbOp == pDis->opsize);
515 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbSize);
516 if (RT_SUCCESS(rc))
517 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
518
519 return rc;
520 }
521 }
522 return VERR_EM_INTERPRETER;
523#endif
524}
525
526
527/**
528 * Interprets the current instruction using the supplied DISCPUSTATE structure.
529 *
530 * EIP is *NOT* updated!
531 *
532 * @returns VBox strict status code.
533 * @retval VINF_* Scheduling instructions. When these are returned, it
534 * starts to get a bit tricky to know whether code was
535 * executed or not... We'll address this when it becomes a problem.
536 * @retval VERR_EM_INTERPRETER Something we can't cope with.
537 * @retval VERR_* Fatal errors.
538 *
539 * @param pVM The VM handle.
540 * @param pVCpu The VMCPU handle.
541 * @param pDis The disassembler cpu state for the instruction to be
542 * interpreted.
543 * @param pRegFrame The register frame. EIP is *NOT* changed!
544 * @param pvFault The fault address (CR2).
545 * @param pcbSize Size of the write (if applicable).
546 * @param enmCodeType Code type (user/supervisor)
547 *
548 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
549 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
550 * to worry about e.g. invalid modrm combinations (!)
551 *
552 * @todo At this time we do NOT check if the instruction overwrites vital information.
553 * Make sure this can't happen!! (will add some assertions/checks later)
554 */
555VMMDECL(VBOXSTRICTRC) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
556 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
557{
558 STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
559 VBOXSTRICTRC rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
560 STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
561 if (RT_SUCCESS(rc))
562 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
563 else
564 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
565 return rc;
566}
567
568
569/**
570 * Interprets the current instruction using the supplied DISCPUSTATE structure.
571 *
572 * IP/EIP/RIP *IS* updated!
573 *
574 * @returns VBox strict status code.
575 * @retval VINF_* Scheduling instructions. When these are returned, it
576 * starts to get a bit tricky to know whether code was
577 * executed or not... We'll address this when it becomes a problem.
578 * @retval VERR_EM_INTERPRETER Something we can't cope with.
579 * @retval VERR_* Fatal errors.
580 *
581 * @param pVM The VM handle.
582 * @param pVCpu The VMCPU handle.
583 * @param pDis The disassembler cpu state for the instruction to be
584 * interpreted.
585 * @param pRegFrame The register frame. IP/EIP/RIP *IS* changed!
586 * @param pvFault The fault address (CR2).
587 * @param pcbSize Size of the write (if applicable).
588 * @param enmCodeType Code type (user/supervisor)
589 *
590 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
591 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
592 * to worry about e.g. invalid modrm combinations (!)
593 *
594 * @todo At this time we do NOT check if the instruction overwrites vital information.
595 * Make sure this can't happen!! (will add some assertions/checks later)
596 */
597VMMDECL(VBOXSTRICTRC) EMInterpretInstructionCpuUpdtPC(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
598 RTGCPTR pvFault, EMCODETYPE enmCodeType)
599{
600 STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
601 uint32_t cbIgnored;
602 VBOXSTRICTRC rc = emInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
603 STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
604 if (RT_SUCCESS(rc))
605 {
606 pRegFrame->rip += pDis->opsize; /* Move on to the next instruction. */
607 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
608 }
609 else
610 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
611 return rc;
612}
613
614#ifndef VBOX_WITH_IEM
615
616
617
618
619
620
621/*
622 *
623 * The old interpreter.
624 * The old interpreter.
625 * The old interpreter.
626 * The old interpreter.
627 * The old interpreter.
628 *
629 */
630
631DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
632{
633#ifdef IN_RC
634 int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
635 if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
636 return rc;
637 /*
638 * The page pool cache may end up here in some cases because it
639 * flushed one of the shadow mappings used by the trapping
640 * instruction and it either flushed the TLB or the CPU reused it.
641 */
642#else
643 NOREF(pVM);
644#endif
645 return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /*fMayTrap*/ false);
646}
647
648
649DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
650{
651 /* Don't use MMGCRamWrite here as it does not respect zero pages, shared
652 pages or write monitored pages. */
653 NOREF(pVM);
654 return PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /*fMayTrap*/ false);
655}
656
657
658/** Convert sel:addr to a flat GC address. */
659DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, POP_PARAMETER pParam, RTGCPTR pvAddr)
660{
661 DIS_SELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
662 return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
663}
664
665
666#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
667/**
668 * Get the mnemonic for the disassembled instruction.
669 *
670 * GC/R0 doesn't include the strings in the DIS tables because
671 * of limited space.
672 */
673static const char *emGetMnemonic(PDISCPUSTATE pDis)
674{
675 switch (pDis->pCurInstr->opcode)
676 {
677 case OP_XCHG: return "Xchg";
678 case OP_DEC: return "Dec";
679 case OP_INC: return "Inc";
680 case OP_POP: return "Pop";
681 case OP_OR: return "Or";
682 case OP_AND: return "And";
683 case OP_MOV: return "Mov";
684 case OP_INVLPG: return "InvlPg";
685 case OP_CPUID: return "CpuId";
686 case OP_MOV_CR: return "MovCRx";
687 case OP_MOV_DR: return "MovDRx";
688 case OP_LLDT: return "LLdt";
689 case OP_LGDT: return "LGdt";
690 case OP_LIDT: return "LIdt";
691 case OP_CLTS: return "Clts";
692 case OP_MONITOR: return "Monitor";
693 case OP_MWAIT: return "MWait";
694 case OP_RDMSR: return "Rdmsr";
695 case OP_WRMSR: return "Wrmsr";
696 case OP_ADD: return "Add";
697 case OP_ADC: return "Adc";
698 case OP_SUB: return "Sub";
699 case OP_SBB: return "Sbb";
700 case OP_RDTSC: return "Rdtsc";
701 case OP_STI: return "Sti";
702 case OP_CLI: return "Cli";
703 case OP_XADD: return "XAdd";
704 case OP_HLT: return "Hlt";
705 case OP_IRET: return "Iret";
706 case OP_MOVNTPS: return "MovNTPS";
707 case OP_STOSWD: return "StosWD";
708 case OP_WBINVD: return "WbInvd";
709 case OP_XOR: return "Xor";
710 case OP_BTR: return "Btr";
711 case OP_BTS: return "Bts";
712 case OP_BTC: return "Btc";
713 case OP_LMSW: return "Lmsw";
714 case OP_SMSW: return "Smsw";
715 case OP_CMPXCHG: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
716 case OP_CMPXCHG8B: return pDis->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
717
718 default:
719 Log(("Unknown opcode %d\n", pDis->pCurInstr->opcode));
720 return "???";
721 }
722}
723#endif /* VBOX_STRICT || LOG_ENABLED */
724
725
726/**
727 * XCHG instruction emulation.
728 */
729static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
730{
731 OP_PARAMVAL param1, param2;
732 NOREF(pvFault);
733
734 /* Source to make DISQueryParamVal read the register value - ugly hack */
735 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
736 if(RT_FAILURE(rc))
737 return VERR_EM_INTERPRETER;
738
739 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
740 if(RT_FAILURE(rc))
741 return VERR_EM_INTERPRETER;
742
743#ifdef IN_RC
744 if (TRPMHasTrap(pVCpu))
745 {
746 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
747 {
748#endif
749 RTGCPTR pParam1 = 0, pParam2 = 0;
750 uint64_t valpar1, valpar2;
751
752 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
753 switch(param1.type)
754 {
755 case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
756 valpar1 = param1.val.val64;
757 break;
758
759 case PARMTYPE_ADDRESS:
760 pParam1 = (RTGCPTR)param1.val.val64;
761 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
762 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
763 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
764 if (RT_FAILURE(rc))
765 {
766 AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
767 return VERR_EM_INTERPRETER;
768 }
769 break;
770
771 default:
772 AssertFailed();
773 return VERR_EM_INTERPRETER;
774 }
775
776 switch(param2.type)
777 {
778 case PARMTYPE_ADDRESS:
779 pParam2 = (RTGCPTR)param2.val.val64;
780 pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pParam2);
781 EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
782 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
783 if (RT_FAILURE(rc))
784 {
785 AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
786 }
787 break;
788
789 case PARMTYPE_IMMEDIATE:
790 valpar2 = param2.val.val64;
791 break;
792
793 default:
794 AssertFailed();
795 return VERR_EM_INTERPRETER;
796 }
797
798 /* Write value of parameter 2 to parameter 1 (reg or memory address) */
799 if (pParam1 == 0)
800 {
801 Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
802 switch(param1.size)
803 {
804 case 1: //special case for AH etc
805 rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen, (uint8_t )valpar2); break;
806 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)valpar2); break;
807 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)valpar2); break;
808 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, valpar2); break;
809 default: AssertFailedReturn(VERR_EM_INTERPRETER);
810 }
811 if (RT_FAILURE(rc))
812 return VERR_EM_INTERPRETER;
813 }
814 else
815 {
816 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
817 if (RT_FAILURE(rc))
818 {
819 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
820 return VERR_EM_INTERPRETER;
821 }
822 }
823
824 /* Write value of parameter 1 to parameter 2 (reg or memory address) */
825 if (pParam2 == 0)
826 {
827 Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
828 switch(param2.size)
829 {
830 case 1: //special case for AH etc
831 rc = DISWriteReg8(pRegFrame, pDis->param2.base.reg_gen, (uint8_t )valpar1); break;
832 case 2: rc = DISWriteReg16(pRegFrame, pDis->param2.base.reg_gen, (uint16_t)valpar1); break;
833 case 4: rc = DISWriteReg32(pRegFrame, pDis->param2.base.reg_gen, (uint32_t)valpar1); break;
834 case 8: rc = DISWriteReg64(pRegFrame, pDis->param2.base.reg_gen, valpar1); break;
835 default: AssertFailedReturn(VERR_EM_INTERPRETER);
836 }
837 if (RT_FAILURE(rc))
838 return VERR_EM_INTERPRETER;
839 }
840 else
841 {
842 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
843 if (RT_FAILURE(rc))
844 {
845 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
846 return VERR_EM_INTERPRETER;
847 }
848 }
849
850 *pcbSize = param2.size;
851 return VINF_SUCCESS;
852#ifdef IN_RC
853 }
854 }
855 return VERR_EM_INTERPRETER;
856#endif
857}
858
859
860/**
861 * INC and DEC emulation.
862 */
863static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
864 PFNEMULATEPARAM2 pfnEmulate)
865{
866 OP_PARAMVAL param1;
867 NOREF(pvFault);
868
869 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
870 if(RT_FAILURE(rc))
871 return VERR_EM_INTERPRETER;
872
873#ifdef IN_RC
874 if (TRPMHasTrap(pVCpu))
875 {
876 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
877 {
878#endif
879 RTGCPTR pParam1 = 0;
880 uint64_t valpar1;
881
882 if (param1.type == PARMTYPE_ADDRESS)
883 {
884 pParam1 = (RTGCPTR)param1.val.val64;
885 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
886#ifdef IN_RC
887 /* Safety check (in theory it could cross a page boundary and fault there though) */
888 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
889#endif
890 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
891 if (RT_FAILURE(rc))
892 {
893 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
894 return VERR_EM_INTERPRETER;
895 }
896 }
897 else
898 {
899 AssertFailed();
900 return VERR_EM_INTERPRETER;
901 }
902
903 uint32_t eflags;
904
905 eflags = pfnEmulate(&valpar1, param1.size);
906
907 /* Write result back */
908 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
909 if (RT_FAILURE(rc))
910 {
911 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
912 return VERR_EM_INTERPRETER;
913 }
914
915 /* Update guest's eflags and finish. */
916 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
917 | (eflags & (X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
918
919 /* All done! */
920 *pcbSize = param1.size;
921 return VINF_SUCCESS;
922#ifdef IN_RC
923 }
924 }
925 return VERR_EM_INTERPRETER;
926#endif
927}
928
929
930/**
931 * POP Emulation.
932 */
933static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
934{
935 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */
936 OP_PARAMVAL param1;
937 NOREF(pvFault);
938
939 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
940 if(RT_FAILURE(rc))
941 return VERR_EM_INTERPRETER;
942
943#ifdef IN_RC
944 if (TRPMHasTrap(pVCpu))
945 {
946 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
947 {
948#endif
949 RTGCPTR pParam1 = 0;
950 uint32_t valpar1;
951 RTGCPTR pStackVal;
952
953 /* Read stack value first */
954 if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
955 return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
956
957 /* Convert address; don't bother checking limits etc, as we only read here */
958 pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
959 if (pStackVal == 0)
960 return VERR_EM_INTERPRETER;
961
962 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
963 if (RT_FAILURE(rc))
964 {
965 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
966 return VERR_EM_INTERPRETER;
967 }
968
969 if (param1.type == PARMTYPE_ADDRESS)
970 {
971 pParam1 = (RTGCPTR)param1.val.val64;
972
973 /* pop [esp+xx] uses esp after the actual pop! */
974 AssertCompile(USE_REG_ESP == USE_REG_SP);
975 if ( (pDis->param1.flags & USE_BASE)
976 && (pDis->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))
977 && pDis->param1.base.reg_gen == USE_REG_ESP
978 )
979 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
980
981 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
982 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
983 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
984 if (RT_FAILURE(rc))
985 {
986 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
987 return VERR_EM_INTERPRETER;
988 }
989
990 /* Update ESP as the last step */
991 pRegFrame->esp += param1.size;
992 }
993 else
994 {
995#ifndef DEBUG_bird // annoying assertion.
996 AssertFailed();
997#endif
998 return VERR_EM_INTERPRETER;
999 }
1000
1001 /* All done! */
1002 *pcbSize = param1.size;
1003 return VINF_SUCCESS;
1004#ifdef IN_RC
1005 }
1006 }
1007 return VERR_EM_INTERPRETER;
1008#endif
1009}
1010
1011
1012/**
1013 * XOR/OR/AND Emulation.
1014 */
1015static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1016 PFNEMULATEPARAM3 pfnEmulate)
1017{
1018 OP_PARAMVAL param1, param2;
1019 NOREF(pvFault);
1020
1021 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1022 if(RT_FAILURE(rc))
1023 return VERR_EM_INTERPRETER;
1024
1025 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1026 if(RT_FAILURE(rc))
1027 return VERR_EM_INTERPRETER;
1028
1029#ifdef IN_RC
1030 if (TRPMHasTrap(pVCpu))
1031 {
1032 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1033 {
1034#endif
1035 RTGCPTR pParam1;
1036 uint64_t valpar1, valpar2;
1037
1038 if (pDis->param1.size != pDis->param2.size)
1039 {
1040 if (pDis->param1.size < pDis->param2.size)
1041 {
1042 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */
1043 return VERR_EM_INTERPRETER;
1044 }
1045 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
1046 pDis->param2.size = pDis->param1.size;
1047 param2.size = param1.size;
1048 }
1049
1050 /* The destination is always a virtual address */
1051 if (param1.type == PARMTYPE_ADDRESS)
1052 {
1053 pParam1 = (RTGCPTR)param1.val.val64;
1054 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
1055 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
1056 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
1057 if (RT_FAILURE(rc))
1058 {
1059 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1060 return VERR_EM_INTERPRETER;
1061 }
1062 }
1063 else
1064 {
1065 AssertFailed();
1066 return VERR_EM_INTERPRETER;
1067 }
1068
1069 /* Register or immediate data */
1070 switch(param2.type)
1071 {
1072 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1073 valpar2 = param2.val.val64;
1074 break;
1075
1076 default:
1077 AssertFailed();
1078 return VERR_EM_INTERPRETER;
1079 }
1080
1081 LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
1082
1083 /* Data read, emulate instruction. */
1084 uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
1085
1086 LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
1087
1088 /* Update guest's eflags and finish. */
1089 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1090 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1091
1092 /* And write it back */
1093 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
1094 if (RT_SUCCESS(rc))
1095 {
1096 /* All done! */
1097 *pcbSize = param2.size;
1098 return VINF_SUCCESS;
1099 }
1100#ifdef IN_RC
1101 }
1102 }
1103#endif
1104 return VERR_EM_INTERPRETER;
1105}
1106
1107
1108/**
1109 * LOCK XOR/OR/AND Emulation.
1110 */
1111static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1112 uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
1113{
1114 void *pvParam1;
1115 OP_PARAMVAL param1, param2;
1116 NOREF(pvFault);
1117
1118#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1119 Assert(pDis->param1.size <= 4);
1120#endif
1121
1122 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1123 if(RT_FAILURE(rc))
1124 return VERR_EM_INTERPRETER;
1125
1126 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1127 if(RT_FAILURE(rc))
1128 return VERR_EM_INTERPRETER;
1129
1130 if (pDis->param1.size != pDis->param2.size)
1131 {
1132 AssertMsgReturn(pDis->param1.size >= pDis->param2.size, /* should never happen! */
1133 ("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size),
1134 VERR_EM_INTERPRETER);
1135
1136 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
1137 pDis->param2.size = pDis->param1.size;
1138 param2.size = param1.size;
1139 }
1140
1141#ifdef IN_RC
1142 /* Safety check (in theory it could cross a page boundary and fault there though) */
1143 Assert( TRPMHasTrap(pVCpu)
1144 && (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
1145 EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
1146#endif
1147
1148 /* Register and immediate data == PARMTYPE_IMMEDIATE */
1149 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1150 RTGCUINTREG ValPar2 = param2.val.val64;
1151
1152 /* The destination is always a virtual address */
1153 AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
1154
1155 RTGCPTR GCPtrPar1 = param1.val.val64;
1156 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
1157 PGMPAGEMAPLOCK Lock;
1158 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1159 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1160
1161 /* Try emulate it with a one-shot #PF handler in place. (RC) */
1162 Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
1163
1164 RTGCUINTREG32 eflags = 0;
1165 rc = pfnEmulate(pvParam1, ValPar2, pDis->param2.size, &eflags);
1166 PGMPhysReleasePageMappingLock(pVM, &Lock);
1167 if (RT_FAILURE(rc))
1168 {
1169 Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
1170 return VERR_EM_INTERPRETER;
1171 }
1172
1173 /* Update guest's eflags and finish. */
1174 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1175 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1176
1177 *pcbSize = param2.size;
1178 return VINF_SUCCESS;
1179}
1180
1181
1182/**
1183 * ADD, ADC & SUB Emulation.
1184 */
1185static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1186 PFNEMULATEPARAM3 pfnEmulate)
1187{
1188 NOREF(pvFault);
1189 OP_PARAMVAL param1, param2;
1190 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1191 if(RT_FAILURE(rc))
1192 return VERR_EM_INTERPRETER;
1193
1194 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1195 if(RT_FAILURE(rc))
1196 return VERR_EM_INTERPRETER;
1197
1198#ifdef IN_RC
1199 if (TRPMHasTrap(pVCpu))
1200 {
1201 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1202 {
1203#endif
1204 RTGCPTR pParam1;
1205 uint64_t valpar1, valpar2;
1206
1207 if (pDis->param1.size != pDis->param2.size)
1208 {
1209 if (pDis->param1.size < pDis->param2.size)
1210 {
1211 AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->param1.size, pDis->param2.size)); /* should never happen! */
1212 return VERR_EM_INTERPRETER;
1213 }
1214 /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
1215 pDis->param2.size = pDis->param1.size;
1216 param2.size = param1.size;
1217 }
1218
1219 /* The destination is always a virtual address */
1220 if (param1.type == PARMTYPE_ADDRESS)
1221 {
1222 pParam1 = (RTGCPTR)param1.val.val64;
1223 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
1224 EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
1225 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
1226 if (RT_FAILURE(rc))
1227 {
1228 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1229 return VERR_EM_INTERPRETER;
1230 }
1231 }
1232 else
1233 {
1234#ifndef DEBUG_bird
1235 AssertFailed();
1236#endif
1237 return VERR_EM_INTERPRETER;
1238 }
1239
1240 /* Register or immediate data */
1241 switch(param2.type)
1242 {
1243 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1244 valpar2 = param2.val.val64;
1245 break;
1246
1247 default:
1248 AssertFailed();
1249 return VERR_EM_INTERPRETER;
1250 }
1251
1252 /* Data read, emulate instruction. */
1253 uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
1254
1255 /* Update guest's eflags and finish. */
1256 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1257 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1258
1259 /* And write it back */
1260 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
1261 if (RT_SUCCESS(rc))
1262 {
1263 /* All done! */
1264 *pcbSize = param2.size;
1265 return VINF_SUCCESS;
1266 }
1267#ifdef IN_RC
1268 }
1269 }
1270#endif
1271 return VERR_EM_INTERPRETER;
1272}
1273
1274
1275/**
1276 * ADC Emulation.
1277 */
1278static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1279{
1280 if (pRegFrame->eflags.Bits.u1CF)
1281 return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
1282 else
1283 return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
1284}
1285
1286
1287/**
1288 * BTR/C/S Emulation.
1289 */
1290static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1291 PFNEMULATEPARAM2UINT32 pfnEmulate)
1292{
1293 OP_PARAMVAL param1, param2;
1294 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1295 if(RT_FAILURE(rc))
1296 return VERR_EM_INTERPRETER;
1297
1298 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1299 if(RT_FAILURE(rc))
1300 return VERR_EM_INTERPRETER;
1301
1302#ifdef IN_RC
1303 if (TRPMHasTrap(pVCpu))
1304 {
1305 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1306 {
1307#endif
1308 RTGCPTR pParam1;
1309 uint64_t valpar1 = 0, valpar2;
1310 uint32_t eflags;
1311
1312 /* The destination is always a virtual address */
1313 if (param1.type != PARMTYPE_ADDRESS)
1314 return VERR_EM_INTERPRETER;
1315
1316 pParam1 = (RTGCPTR)param1.val.val64;
1317 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
1318
1319 /* Register or immediate data */
1320 switch(param2.type)
1321 {
1322 case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1323 valpar2 = param2.val.val64;
1324 break;
1325
1326 default:
1327 AssertFailed();
1328 return VERR_EM_INTERPRETER;
1329 }
1330
1331 Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
1332 pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1333 EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
1334 rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
1335 if (RT_FAILURE(rc))
1336 {
1337 AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1338 return VERR_EM_INTERPRETER;
1339 }
1340
1341 Log2(("emInterpretBtx: val=%x\n", valpar1));
1342 /* Data read, emulate bit test instruction. */
1343 eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1344
1345 Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1346
1347 /* Update guest's eflags and finish. */
1348 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1349 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1350
1351 /* And write it back */
1352 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
1353 if (RT_SUCCESS(rc))
1354 {
1355 /* All done! */
1356 *pcbSize = 1;
1357 return VINF_SUCCESS;
1358 }
1359#ifdef IN_RC
1360 }
1361 }
1362#endif
1363 return VERR_EM_INTERPRETER;
1364}
1365
1366
1367/**
1368 * LOCK BTR/C/S Emulation.
1369 */
1370static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1371 uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1372{
1373 void *pvParam1;
1374
1375 OP_PARAMVAL param1, param2;
1376 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1377 if(RT_FAILURE(rc))
1378 return VERR_EM_INTERPRETER;
1379
1380 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1381 if(RT_FAILURE(rc))
1382 return VERR_EM_INTERPRETER;
1383
1384 /* The destination is always a virtual address */
1385 if (param1.type != PARMTYPE_ADDRESS)
1386 return VERR_EM_INTERPRETER;
1387
1388 /* Register and immediate data == PARMTYPE_IMMEDIATE */
1389 AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1390 uint64_t ValPar2 = param2.val.val64;
1391
1392 /* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1393 RTGCPTR GCPtrPar1 = param1.val.val64;
1394 GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
1395 ValPar2 &= 7;
1396
1397 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
1398#ifdef IN_RC
1399 Assert(TRPMHasTrap(pVCpu));
1400 EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1401#endif
1402
1403 PGMPAGEMAPLOCK Lock;
1404 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1405 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1406
1407 Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
1408
1409 /* Try emulate it with a one-shot #PF handler in place. (RC) */
1410 RTGCUINTREG32 eflags = 0;
1411 rc = pfnEmulate(pvParam1, ValPar2, &eflags);
1412 PGMPhysReleasePageMappingLock(pVM, &Lock);
1413 if (RT_FAILURE(rc))
1414 {
1415 Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
1416 emGetMnemonic(pDis), GCPtrPar1, pDis->param2.size*8, ValPar2));
1417 return VERR_EM_INTERPRETER;
1418 }
1419
1420 Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1421
1422 /* Update guest's eflags and finish. */
1423 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1424 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1425
1426 *pcbSize = 1;
1427 return VINF_SUCCESS;
1428}
1429
1430
1431/**
1432 * MOV emulation.
1433 */
1434static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1435{
1436 NOREF(pvFault);
1437 OP_PARAMVAL param1, param2;
1438 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_DEST);
1439 if(RT_FAILURE(rc))
1440 return VERR_EM_INTERPRETER;
1441
1442 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1443 if(RT_FAILURE(rc))
1444 return VERR_EM_INTERPRETER;
1445
1446#ifdef IN_RC
1447 if (TRPMHasTrap(pVCpu))
1448 {
1449 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1450 {
1451#else
1452 /** @todo Make this the default and don't rely on TRPM information. */
1453 if (param1.type == PARMTYPE_ADDRESS)
1454 {
1455#endif
1456 RTGCPTR pDest;
1457 uint64_t val64;
1458
1459 switch(param1.type)
1460 {
1461 case PARMTYPE_IMMEDIATE:
1462 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
1463 return VERR_EM_INTERPRETER;
1464 /* fallthru */
1465
1466 case PARMTYPE_ADDRESS:
1467 pDest = (RTGCPTR)param1.val.val64;
1468 pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pDest);
1469 break;
1470
1471 default:
1472 AssertFailed();
1473 return VERR_EM_INTERPRETER;
1474 }
1475
1476 switch(param2.type)
1477 {
1478 case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1479 val64 = param2.val.val64;
1480 break;
1481
1482 default:
1483 Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
1484 return VERR_EM_INTERPRETER;
1485 }
1486#ifdef LOG_ENABLED
1487 if (pDis->mode == CPUMODE_64BIT)
1488 LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
1489 else
1490 LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
1491#endif
1492
1493 Assert(param2.size <= 8 && param2.size > 0);
1494 EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
1495 rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
1496 if (RT_FAILURE(rc))
1497 return VERR_EM_INTERPRETER;
1498
1499 *pcbSize = param2.size;
1500 }
1501 else
1502 { /* read fault */
1503 RTGCPTR pSrc;
1504 uint64_t val64;
1505
1506 /* Source */
1507 switch(param2.type)
1508 {
1509 case PARMTYPE_IMMEDIATE:
1510 if(!(param2.flags & (PARAM_VAL32|PARAM_VAL64)))
1511 return VERR_EM_INTERPRETER;
1512 /* fallthru */
1513
1514 case PARMTYPE_ADDRESS:
1515 pSrc = (RTGCPTR)param2.val.val64;
1516 pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param2, pSrc);
1517 break;
1518
1519 default:
1520 return VERR_EM_INTERPRETER;
1521 }
1522
1523 Assert(param1.size <= 8 && param1.size > 0);
1524 EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
1525 rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
1526 if (RT_FAILURE(rc))
1527 return VERR_EM_INTERPRETER;
1528
1529 /* Destination */
1530 switch(param1.type)
1531 {
1532 case PARMTYPE_REGISTER:
1533 switch(param1.size)
1534 {
1535 case 1: rc = DISWriteReg8(pRegFrame, pDis->param1.base.reg_gen, (uint8_t) val64); break;
1536 case 2: rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, (uint16_t)val64); break;
1537 case 4: rc = DISWriteReg32(pRegFrame, pDis->param1.base.reg_gen, (uint32_t)val64); break;
1538 case 8: rc = DISWriteReg64(pRegFrame, pDis->param1.base.reg_gen, val64); break;
1539 default:
1540 return VERR_EM_INTERPRETER;
1541 }
1542 if (RT_FAILURE(rc))
1543 return rc;
1544 break;
1545
1546 default:
1547 return VERR_EM_INTERPRETER;
1548 }
1549#ifdef LOG_ENABLED
1550 if (pDis->mode == CPUMODE_64BIT)
1551 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1552 else
1553 LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1554#endif
1555 }
1556 return VINF_SUCCESS;
1557#ifdef IN_RC
1558 }
1559 return VERR_EM_INTERPRETER;
1560#endif
1561}
1562
1563
1564#ifndef IN_RC
1565/**
1566 * [REP] STOSWD emulation
1567 */
1568static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1569{
1570 int rc;
1571 RTGCPTR GCDest, GCOffset;
1572 uint32_t cbSize;
1573 uint64_t cTransfers;
1574 int offIncrement;
1575 NOREF(pvFault);
1576
1577 /* Don't support any but these three prefix bytes. */
1578 if ((pDis->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))
1579 return VERR_EM_INTERPRETER;
1580
1581 switch (pDis->addrmode)
1582 {
1583 case CPUMODE_16BIT:
1584 GCOffset = pRegFrame->di;
1585 cTransfers = pRegFrame->cx;
1586 break;
1587 case CPUMODE_32BIT:
1588 GCOffset = pRegFrame->edi;
1589 cTransfers = pRegFrame->ecx;
1590 break;
1591 case CPUMODE_64BIT:
1592 GCOffset = pRegFrame->rdi;
1593 cTransfers = pRegFrame->rcx;
1594 break;
1595 default:
1596 AssertFailed();
1597 return VERR_EM_INTERPRETER;
1598 }
1599
1600 GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
1601 switch (pDis->opmode)
1602 {
1603 case CPUMODE_16BIT:
1604 cbSize = 2;
1605 break;
1606 case CPUMODE_32BIT:
1607 cbSize = 4;
1608 break;
1609 case CPUMODE_64BIT:
1610 cbSize = 8;
1611 break;
1612 default:
1613 AssertFailed();
1614 return VERR_EM_INTERPRETER;
1615 }
1616
1617 offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
1618
1619 if (!(pDis->prefix & PREFIX_REP))
1620 {
1621 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
1622
1623 rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1624 if (RT_FAILURE(rc))
1625 return VERR_EM_INTERPRETER;
1626 Assert(rc == VINF_SUCCESS);
1627
1628 /* Update (e/r)di. */
1629 switch (pDis->addrmode)
1630 {
1631 case CPUMODE_16BIT:
1632 pRegFrame->di += offIncrement;
1633 break;
1634 case CPUMODE_32BIT:
1635 pRegFrame->edi += offIncrement;
1636 break;
1637 case CPUMODE_64BIT:
1638 pRegFrame->rdi += offIncrement;
1639 break;
1640 default:
1641 AssertFailed();
1642 return VERR_EM_INTERPRETER;
1643 }
1644
1645 }
1646 else
1647 {
1648 if (!cTransfers)
1649 return VINF_SUCCESS;
1650
1651 /*
1652 * Do *not* try emulate cross page stuff here because we don't know what might
1653 * be waiting for us on the subsequent pages. The caller has only asked us to
1654 * ignore access handlers fro the current page.
1655 * This also fends off big stores which would quickly kill PGMR0DynMap.
1656 */
1657 if ( cbSize > PAGE_SIZE
1658 || cTransfers > PAGE_SIZE
1659 || (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
1660 {
1661 Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
1662 GCDest, cbSize, offIncrement, cTransfers));
1663 return VERR_EM_INTERPRETER;
1664 }
1665
1666 LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
1667 /* Access verification first; we currently can't recover properly from traps inside this instruction */
1668 rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
1669 cTransfers * cbSize,
1670 X86_PTE_RW | (CPUMGetGuestCPL(pVCpu, pRegFrame) == 3 ? X86_PTE_US : 0));
1671 if (rc != VINF_SUCCESS)
1672 {
1673 Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
1674 return VERR_EM_INTERPRETER;
1675 }
1676
1677 /* REP case */
1678 while (cTransfers)
1679 {
1680 rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
1681 if (RT_FAILURE(rc))
1682 {
1683 rc = VERR_EM_INTERPRETER;
1684 break;
1685 }
1686
1687 Assert(rc == VINF_SUCCESS);
1688 GCOffset += offIncrement;
1689 GCDest += offIncrement;
1690 cTransfers--;
1691 }
1692
1693 /* Update the registers. */
1694 switch (pDis->addrmode)
1695 {
1696 case CPUMODE_16BIT:
1697 pRegFrame->di = GCOffset;
1698 pRegFrame->cx = cTransfers;
1699 break;
1700 case CPUMODE_32BIT:
1701 pRegFrame->edi = GCOffset;
1702 pRegFrame->ecx = cTransfers;
1703 break;
1704 case CPUMODE_64BIT:
1705 pRegFrame->rdi = GCOffset;
1706 pRegFrame->rcx = cTransfers;
1707 break;
1708 default:
1709 AssertFailed();
1710 return VERR_EM_INTERPRETER;
1711 }
1712 }
1713
1714 *pcbSize = cbSize;
1715 return rc;
1716}
1717#endif /* !IN_RC */
1718
1719
1720/**
1721 * [LOCK] CMPXCHG emulation.
1722 */
1723static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1724{
1725 OP_PARAMVAL param1, param2;
1726 NOREF(pvFault);
1727
1728#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
1729 Assert(pDis->param1.size <= 4);
1730#endif
1731
1732 /* Source to make DISQueryParamVal read the register value - ugly hack */
1733 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
1734 if(RT_FAILURE(rc))
1735 return VERR_EM_INTERPRETER;
1736
1737 rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param2, &param2, PARAM_SOURCE);
1738 if(RT_FAILURE(rc))
1739 return VERR_EM_INTERPRETER;
1740
1741 uint64_t valpar;
1742 switch(param2.type)
1743 {
1744 case PARMTYPE_IMMEDIATE: /* register actually */
1745 valpar = param2.val.val64;
1746 break;
1747
1748 default:
1749 return VERR_EM_INTERPRETER;
1750 }
1751
1752 PGMPAGEMAPLOCK Lock;
1753 RTGCPTR GCPtrPar1;
1754 void *pvParam1;
1755 uint64_t eflags;
1756
1757 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
1758 switch(param1.type)
1759 {
1760 case PARMTYPE_ADDRESS:
1761 GCPtrPar1 = param1.val.val64;
1762 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
1763
1764 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1765 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1766 break;
1767
1768 default:
1769 return VERR_EM_INTERPRETER;
1770 }
1771
1772 LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
1773
1774 if (pDis->prefix & PREFIX_LOCK)
1775 eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size);
1776 else
1777 eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->param2.size);
1778
1779 LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
1780
1781 /* Update guest's eflags and finish. */
1782 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1783 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1784
1785 *pcbSize = param2.size;
1786 PGMPhysReleasePageMappingLock(pVM, &Lock);
1787 return VINF_SUCCESS;
1788}
1789
1790
1791/**
1792 * [LOCK] CMPXCHG8B emulation.
1793 */
1794static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1795{
1796 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */
1797 OP_PARAMVAL param1;
1798 NOREF(pvFault);
1799
1800 /* Source to make DISQueryParamVal read the register value - ugly hack */
1801 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
1802 if(RT_FAILURE(rc))
1803 return VERR_EM_INTERPRETER;
1804
1805 RTGCPTR GCPtrPar1;
1806 void *pvParam1;
1807 uint64_t eflags;
1808 PGMPAGEMAPLOCK Lock;
1809
1810 AssertReturn(pDis->param1.size == 8, VERR_EM_INTERPRETER);
1811 switch(param1.type)
1812 {
1813 case PARMTYPE_ADDRESS:
1814 GCPtrPar1 = param1.val.val64;
1815 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, GCPtrPar1);
1816
1817 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1818 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1819 break;
1820
1821 default:
1822 return VERR_EM_INTERPRETER;
1823 }
1824
1825 LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
1826
1827 if (pDis->prefix & PREFIX_LOCK)
1828 eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1829 else
1830 eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
1831
1832 LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1833
1834 /* Update guest's eflags and finish; note that *only* ZF is affected. */
1835 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
1836 | (eflags & (X86_EFL_ZF));
1837
1838 *pcbSize = 8;
1839 PGMPhysReleasePageMappingLock(pVM, &Lock);
1840 return VINF_SUCCESS;
1841}
1842
1843
1844#ifdef IN_RC /** @todo test+enable for HWACCM as well. */
1845/**
1846 * [LOCK] XADD emulation.
1847 */
1848static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1849{
1850 Assert(pDis->mode != CPUMODE_64BIT); /** @todo check */
1851 OP_PARAMVAL param1;
1852 void *pvParamReg2;
1853 size_t cbParamReg2;
1854 NOREF(pvFault);
1855
1856 /* Source to make DISQueryParamVal read the register value - ugly hack */
1857 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
1858 if(RT_FAILURE(rc))
1859 return VERR_EM_INTERPRETER;
1860
1861 rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->param2, &pvParamReg2, &cbParamReg2);
1862 Assert(cbParamReg2 <= 4);
1863 if(RT_FAILURE(rc))
1864 return VERR_EM_INTERPRETER;
1865
1866#ifdef IN_RC
1867 if (TRPMHasTrap(pVCpu))
1868 {
1869 if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1870 {
1871#endif
1872 RTGCPTR GCPtrPar1;
1873 void *pvParam1;
1874 uint32_t eflags;
1875 PGMPAGEMAPLOCK Lock;
1876
1877 AssertReturn(pDis->param1.size == pDis->param2.size, VERR_EM_INTERPRETER);
1878 switch(param1.type)
1879 {
1880 case PARMTYPE_ADDRESS:
1881 GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, (RTRCUINTPTR)param1.val.val64);
1882#ifdef IN_RC
1883 EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
1884#endif
1885
1886 rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
1887 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1888 break;
1889
1890 default:
1891 return VERR_EM_INTERPRETER;
1892 }
1893
1894 LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2));
1895
1896 if (pDis->prefix & PREFIX_LOCK)
1897 eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
1898 else
1899 eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
1900
1901 LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, *(uint64_t *)pvParamReg2, !!(eflags & X86_EFL_ZF) ));
1902
1903 /* Update guest's eflags and finish. */
1904 pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
1905 | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1906
1907 *pcbSize = cbParamReg2;
1908 PGMPhysReleasePageMappingLock(pVM, &Lock);
1909 return VINF_SUCCESS;
1910#ifdef IN_RC
1911 }
1912 }
1913
1914 return VERR_EM_INTERPRETER;
1915#endif
1916}
1917#endif /* IN_RC */
1918
1919
1920#ifdef IN_RC
1921/**
1922 * Interpret IRET (currently only to V86 code)
1923 *
1924 * @returns VBox status code.
1925 * @param pVM The VM handle.
1926 * @param pVCpu The VMCPU handle.
1927 * @param pRegFrame The register frame.
1928 *
1929 */
1930VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1931{
1932 RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1933 RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1934 int rc;
1935
1936 Assert(!CPUMIsGuestIn64BitCode(pVCpu, pRegFrame));
1937
1938 rc = emRamRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1939 rc |= emRamRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1940 rc |= emRamRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1941 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1942 AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1943
1944 rc |= emRamRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1945 rc |= emRamRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1946 rc |= emRamRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1947 rc |= emRamRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1948 rc |= emRamRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1949 rc |= emRamRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1950 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1951
1952 pRegFrame->eip = eip & 0xffff;
1953 pRegFrame->cs = cs;
1954
1955 /* Mask away all reserved bits */
1956 uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
1957 eflags &= uMask;
1958
1959#ifndef IN_RING0
1960 CPUMRawSetEFlags(pVCpu, pRegFrame, eflags);
1961#endif
1962 Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
1963
1964 pRegFrame->esp = esp;
1965 pRegFrame->ss = ss;
1966 pRegFrame->ds = ds;
1967 pRegFrame->es = es;
1968 pRegFrame->fs = fs;
1969 pRegFrame->gs = gs;
1970
1971 return VINF_SUCCESS;
1972}
1973#endif /* IN_RC */
1974
1975
1976/**
1977 * IRET Emulation.
1978 */
1979static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1980{
1981 /* only allow direct calls to EMInterpretIret for now */
1982 NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1983 return VERR_EM_INTERPRETER;
1984}
1985
1986/**
1987 * WBINVD Emulation.
1988 */
1989static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1990{
1991 /* Nothing to do. */
1992 NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1993 return VINF_SUCCESS;
1994}
1995
1996
1997/**
1998 * Interpret INVLPG
1999 *
2000 * @returns VBox status code.
2001 * @param pVM The VM handle.
2002 * @param pVCpu The VMCPU handle.
2003 * @param pRegFrame The register frame.
2004 * @param pAddrGC Operand address
2005 *
2006 */
2007VMMDECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
2008{
2009 /** @todo is addr always a flat linear address or ds based
2010 * (in absence of segment override prefixes)????
2011 */
2012 NOREF(pVM); NOREF(pRegFrame);
2013#ifdef IN_RC
2014 LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
2015#endif
2016 VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
2017 if ( rc == VINF_SUCCESS
2018 || rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
2019 return VINF_SUCCESS;
2020 AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
2021 ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
2022 VERR_EM_INTERPRETER);
2023 return rc;
2024}
2025
2026
2027/**
2028 * INVLPG Emulation.
2029 */
2030static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2031{
2032 OP_PARAMVAL param1;
2033 RTGCPTR addr;
2034 NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
2035
2036 VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
2037 if(RT_FAILURE(rc))
2038 return VERR_EM_INTERPRETER;
2039
2040 switch(param1.type)
2041 {
2042 case PARMTYPE_IMMEDIATE:
2043 case PARMTYPE_ADDRESS:
2044 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2045 return VERR_EM_INTERPRETER;
2046 addr = (RTGCPTR)param1.val.val64;
2047 break;
2048
2049 default:
2050 return VERR_EM_INTERPRETER;
2051 }
2052
2053 /** @todo is addr always a flat linear address or ds based
2054 * (in absence of segment override prefixes)????
2055 */
2056#ifdef IN_RC
2057 LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
2058#endif
2059 rc = PGMInvalidatePage(pVCpu, addr);
2060 if ( rc == VINF_SUCCESS
2061 || rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
2062 return VINF_SUCCESS;
2063 AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
2064 ("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
2065 VERR_EM_INTERPRETER);
2066 return rc;
2067}
2068
2069/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
2070
2071/**
2072 * Interpret CPUID given the parameters in the CPU context
2073 *
2074 * @returns VBox status code.
2075 * @param pVM The VM handle.
2076 * @param pVCpu The VMCPU handle.
2077 * @param pRegFrame The register frame.
2078 *
2079 */
2080VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2081{
2082 uint32_t iLeaf = pRegFrame->eax;
2083 NOREF(pVM);
2084
2085 /* cpuid clears the high dwords of the affected 64 bits registers. */
2086 pRegFrame->rax = 0;
2087 pRegFrame->rbx = 0;
2088 pRegFrame->rcx &= UINT64_C(0x00000000ffffffff);
2089 pRegFrame->rdx = 0;
2090
2091 /* Note: operates the same in 64 and non-64 bits mode. */
2092 CPUMGetGuestCpuId(pVCpu, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
2093 Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * CPUID Emulation.
2100 */
2101static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2102{
2103 NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
2104 int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
2105 return rc;
2106}
2107
2108
2109/**
2110 * Interpret CRx read
2111 *
2112 * @returns VBox status code.
2113 * @param pVM The VM handle.
2114 * @param pVCpu The VMCPU handle.
2115 * @param pRegFrame The register frame.
2116 * @param DestRegGen General purpose register index (USE_REG_E**))
2117 * @param SrcRegCRx CRx register index (USE_REG_CR*)
2118 *
2119 */
2120VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
2121{
2122 uint64_t val64;
2123 int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
2124 AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
2125 NOREF(pVM);
2126
2127 if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2128 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2129 else
2130 rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
2131
2132 if (RT_SUCCESS(rc))
2133 {
2134 LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
2135 return VINF_SUCCESS;
2136 }
2137 return VERR_EM_INTERPRETER;
2138}
2139
2140
2141
2142/**
2143 * Interpret CLTS
2144 *
2145 * @returns VBox status code.
2146 * @param pVM The VM handle.
2147 * @param pVCpu The VMCPU handle.
2148 *
2149 */
2150VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
2151{
2152 NOREF(pVM);
2153 uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
2154 if (!(cr0 & X86_CR0_TS))
2155 return VINF_SUCCESS;
2156 return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
2157}
2158
2159/**
2160 * CLTS Emulation.
2161 */
2162static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2163{
2164 NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
2165 return EMInterpretCLTS(pVM, pVCpu);
2166}
2167
2168
2169/**
2170 * Update CRx
2171 *
2172 * @returns VBox status code.
2173 * @param pVM The VM handle.
2174 * @param pVCpu The VMCPU handle.
2175 * @param pRegFrame The register frame.
2176 * @param DestRegCRx CRx register index (USE_REG_CR*)
2177 * @param val New CRx value
2178 *
2179 */
2180static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
2181{
2182 uint64_t oldval;
2183 uint64_t msrEFER;
2184 int rc, rc2;
2185 NOREF(pVM);
2186
2187 /** @todo Clean up this mess. */
2188 LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
2189 switch (DestRegCrx)
2190 {
2191 case USE_REG_CR0:
2192 oldval = CPUMGetGuestCR0(pVCpu);
2193#ifdef IN_RC
2194 /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
2195 if ( (val & (X86_CR0_WP | X86_CR0_AM))
2196 != (oldval & (X86_CR0_WP | X86_CR0_AM)))
2197 return VERR_EM_INTERPRETER;
2198#endif
2199 rc = VINF_SUCCESS;
2200 CPUMSetGuestCR0(pVCpu, val);
2201 val = CPUMGetGuestCR0(pVCpu);
2202 if ( (oldval & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
2203 != (val & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
2204 {
2205 /* global flush */
2206 rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
2207 AssertRCReturn(rc, rc);
2208 }
2209
2210 /* Deal with long mode enabling/disabling. */
2211 msrEFER = CPUMGetGuestEFER(pVCpu);
2212 if (msrEFER & MSR_K6_EFER_LME)
2213 {
2214 if ( !(oldval & X86_CR0_PG)
2215 && (val & X86_CR0_PG))
2216 {
2217 /* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2218 if (pRegFrame->csHid.Attr.n.u1Long)
2219 {
2220 AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
2221 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2222 }
2223
2224 /* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2225 if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
2226 {
2227 AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
2228 return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
2229 }
2230 msrEFER |= MSR_K6_EFER_LMA;
2231 }
2232 else
2233 if ( (oldval & X86_CR0_PG)
2234 && !(val & X86_CR0_PG))
2235 {
2236 msrEFER &= ~MSR_K6_EFER_LMA;
2237 /* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
2238 }
2239 CPUMSetGuestEFER(pVCpu, msrEFER);
2240 }
2241 rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
2242 return rc2 == VINF_SUCCESS ? rc : rc2;
2243
2244 case USE_REG_CR2:
2245 rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
2246 return VINF_SUCCESS;
2247
2248 case USE_REG_CR3:
2249 /* Reloading the current CR3 means the guest just wants to flush the TLBs */
2250 rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
2251 if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
2252 {
2253 /* flush */
2254 rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
2255 AssertRC(rc);
2256 }
2257 return rc;
2258
2259 case USE_REG_CR4:
2260 oldval = CPUMGetGuestCR4(pVCpu);
2261 rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
2262 val = CPUMGetGuestCR4(pVCpu);
2263
2264 /* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
2265 msrEFER = CPUMGetGuestEFER(pVCpu);
2266 if ( (msrEFER & MSR_K6_EFER_LMA)
2267 && (oldval & X86_CR4_PAE)
2268 && !(val & X86_CR4_PAE))
2269 {
2270 return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
2271 }
2272
2273 rc = VINF_SUCCESS;
2274 if ( (oldval & (X86_CR4_PGE|X86_CR4_PAE|X86_CR4_PSE))
2275 != (val & (X86_CR4_PGE|X86_CR4_PAE|X86_CR4_PSE)))
2276 {
2277 /* global flush */
2278 rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
2279 AssertRCReturn(rc, rc);
2280 }
2281
2282 /* Feeling extremely lazy. */
2283# ifdef IN_RC
2284 if ( (oldval & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME))
2285 != (val & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME)))
2286 {
2287 Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
2288 VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
2289 }
2290# endif
2291 if ((val ^ oldval) & X86_CR4_VME)
2292 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2293
2294 rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
2295 return rc2 == VINF_SUCCESS ? rc : rc2;
2296
2297 case USE_REG_CR8:
2298 return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2299
2300 default:
2301 AssertFailed();
2302 case USE_REG_CR1: /* illegal op */
2303 break;
2304 }
2305 return VERR_EM_INTERPRETER;
2306}
2307
2308/**
2309 * Interpret CRx write
2310 *
2311 * @returns VBox status code.
2312 * @param pVM The VM handle.
2313 * @param pVCpu The VMCPU handle.
2314 * @param pRegFrame The register frame.
2315 * @param DestRegCRx CRx register index (USE_REG_CR*)
2316 * @param SrcRegGen General purpose register index (USE_REG_E**))
2317 *
2318 */
2319VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
2320{
2321 uint64_t val;
2322 int rc;
2323
2324 if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2325 {
2326 rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2327 }
2328 else
2329 {
2330 uint32_t val32;
2331 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2332 val = val32;
2333 }
2334
2335 if (RT_SUCCESS(rc))
2336 return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
2337
2338 return VERR_EM_INTERPRETER;
2339}
2340
2341/**
2342 * Interpret LMSW
2343 *
2344 * @returns VBox status code.
2345 * @param pVM The VM handle.
2346 * @param pVCpu The VMCPU handle.
2347 * @param pRegFrame The register frame.
2348 * @param u16Data LMSW source data.
2349 *
2350 */
2351VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
2352{
2353 uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
2354
2355 /* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
2356 uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
2357 | (u16Data & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS));
2358
2359 return emUpdateCRx(pVM, pVCpu, pRegFrame, USE_REG_CR0, NewCr0);
2360}
2361
2362/**
2363 * LMSW Emulation.
2364 */
2365static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2366{
2367 OP_PARAMVAL param1;
2368 uint32_t val;
2369 NOREF(pvFault); NOREF(pcbSize);
2370
2371 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
2372 if(RT_FAILURE(rc))
2373 return VERR_EM_INTERPRETER;
2374
2375 switch(param1.type)
2376 {
2377 case PARMTYPE_IMMEDIATE:
2378 case PARMTYPE_ADDRESS:
2379 if(!(param1.flags & PARAM_VAL16))
2380 return VERR_EM_INTERPRETER;
2381 val = param1.val.val32;
2382 break;
2383
2384 default:
2385 return VERR_EM_INTERPRETER;
2386 }
2387
2388 LogFlow(("emInterpretLmsw %x\n", val));
2389 return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
2390}
2391
2392#ifdef EM_EMULATE_SMSW
2393/**
2394 * SMSW Emulation.
2395 */
2396static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2397{
2398 OP_PARAMVAL param1;
2399 uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
2400
2401 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
2402 if(RT_FAILURE(rc))
2403 return VERR_EM_INTERPRETER;
2404
2405 switch(param1.type)
2406 {
2407 case PARMTYPE_IMMEDIATE:
2408 if(param1.size != sizeof(uint16_t))
2409 return VERR_EM_INTERPRETER;
2410 LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->param1.base.reg_gen, cr0));
2411 rc = DISWriteReg16(pRegFrame, pDis->param1.base.reg_gen, cr0);
2412 break;
2413
2414 case PARMTYPE_ADDRESS:
2415 {
2416 RTGCPTR pParam1;
2417
2418 /* Actually forced to 16 bits regardless of the operand size. */
2419 if(param1.size != sizeof(uint16_t))
2420 return VERR_EM_INTERPRETER;
2421
2422 pParam1 = (RTGCPTR)param1.val.val64;
2423 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, pParam1);
2424 LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
2425
2426 rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
2427 if (RT_FAILURE(rc))
2428 {
2429 AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2430 return VERR_EM_INTERPRETER;
2431 }
2432 break;
2433 }
2434
2435 default:
2436 return VERR_EM_INTERPRETER;
2437 }
2438
2439 LogFlow(("emInterpretSmsw %x\n", cr0));
2440 return rc;
2441}
2442#endif
2443
2444/**
2445 * MOV CRx
2446 */
2447static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2448{
2449 NOREF(pvFault); NOREF(pcbSize);
2450 if ((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_CR)
2451 return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_ctrl);
2452
2453 if (pDis->param1.flags == USE_REG_CR && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64))
2454 return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_ctrl, pDis->param2.base.reg_gen);
2455
2456 AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
2457}
2458
2459
2460/**
2461 * Interpret DRx write
2462 *
2463 * @returns VBox status code.
2464 * @param pVM The VM handle.
2465 * @param pVCpu The VMCPU handle.
2466 * @param pRegFrame The register frame.
2467 * @param DestRegDRx DRx register index (USE_REG_DR*)
2468 * @param SrcRegGen General purpose register index (USE_REG_E**))
2469 *
2470 */
2471VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
2472{
2473 uint64_t val;
2474 int rc;
2475 NOREF(pVM);
2476
2477 if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2478 {
2479 rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
2480 }
2481 else
2482 {
2483 uint32_t val32;
2484 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
2485 val = val32;
2486 }
2487
2488 if (RT_SUCCESS(rc))
2489 {
2490 /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
2491 rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, val);
2492 if (RT_SUCCESS(rc))
2493 return rc;
2494 AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
2495 }
2496 return VERR_EM_INTERPRETER;
2497}
2498
2499
2500/**
2501 * Interpret DRx read
2502 *
2503 * @returns VBox status code.
2504 * @param pVM The VM handle.
2505 * @param pVCpu The VMCPU handle.
2506 * @param pRegFrame The register frame.
2507 * @param DestRegGen General purpose register index (USE_REG_E**))
2508 * @param SrcRegDRx DRx register index (USE_REG_DR*)
2509 *
2510 */
2511VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
2512{
2513 uint64_t val64;
2514 NOREF(pVM);
2515
2516 int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
2517 AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
2518 if (CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
2519 {
2520 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
2521 }
2522 else
2523 rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
2524
2525 if (RT_SUCCESS(rc))
2526 return VINF_SUCCESS;
2527
2528 return VERR_EM_INTERPRETER;
2529}
2530
2531
2532/**
2533 * MOV DRx
2534 */
2535static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2536{
2537 int rc = VERR_EM_INTERPRETER;
2538 NOREF(pvFault); NOREF(pcbSize);
2539
2540 if((pDis->param1.flags == USE_REG_GEN32 || pDis->param1.flags == USE_REG_GEN64) && pDis->param2.flags == USE_REG_DBG)
2541 {
2542 rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_gen, pDis->param2.base.reg_dbg);
2543 }
2544 else
2545 if(pDis->param1.flags == USE_REG_DBG && (pDis->param2.flags == USE_REG_GEN32 || pDis->param2.flags == USE_REG_GEN64))
2546 {
2547 rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->param1.base.reg_dbg, pDis->param2.base.reg_gen);
2548 }
2549 else
2550 AssertMsgFailed(("Unexpected debug register move\n"));
2551
2552 return rc;
2553}
2554
2555
2556/**
2557 * LLDT Emulation.
2558 */
2559static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2560{
2561 OP_PARAMVAL param1;
2562 RTSEL sel;
2563 NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
2564
2565 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
2566 if(RT_FAILURE(rc))
2567 return VERR_EM_INTERPRETER;
2568
2569 switch(param1.type)
2570 {
2571 case PARMTYPE_ADDRESS:
2572 return VERR_EM_INTERPRETER; //feeling lazy right now
2573
2574 case PARMTYPE_IMMEDIATE:
2575 if(!(param1.flags & PARAM_VAL16))
2576 return VERR_EM_INTERPRETER;
2577 sel = (RTSEL)param1.val.val16;
2578 break;
2579
2580 default:
2581 return VERR_EM_INTERPRETER;
2582 }
2583
2584#ifdef IN_RING0
2585 /* Only for the VT-x real-mode emulation case. */
2586 AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
2587 CPUMSetGuestLDTR(pVCpu, sel);
2588 return VINF_SUCCESS;
2589#else
2590 if (sel == 0)
2591 {
2592 if (CPUMGetHyperLDTR(pVCpu) == 0)
2593 {
2594 // this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
2595 return VINF_SUCCESS;
2596 }
2597 }
2598 //still feeling lazy
2599 return VERR_EM_INTERPRETER;
2600#endif
2601}
2602
2603#ifdef IN_RING0
2604/**
2605 * LIDT/LGDT Emulation.
2606 */
2607static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2608{
2609 OP_PARAMVAL param1;
2610 RTGCPTR pParam1;
2611 X86XDTR32 dtr32;
2612 NOREF(pvFault); NOREF(pcbSize);
2613
2614 Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
2615
2616 /* Only for the VT-x real-mode emulation case. */
2617 AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
2618
2619 int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->param1, &param1, PARAM_SOURCE);
2620 if(RT_FAILURE(rc))
2621 return VERR_EM_INTERPRETER;
2622
2623 switch(param1.type)
2624 {
2625 case PARMTYPE_ADDRESS:
2626 pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->param1, param1.val.val16);
2627 break;
2628
2629 default:
2630 return VERR_EM_INTERPRETER;
2631 }
2632
2633 rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
2634 AssertRCReturn(rc, VERR_EM_INTERPRETER);
2635
2636 if (!(pDis->prefix & PREFIX_OPSIZE))
2637 dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
2638
2639 if (pDis->pCurInstr->opcode == OP_LIDT)
2640 CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
2641 else
2642 CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
2643
2644 return VINF_SUCCESS;
2645}
2646#endif
2647
2648
2649#ifdef IN_RC
2650/**
2651 * STI Emulation.
2652 *
2653 * @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
2654 */
2655static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2656{
2657 NOREF(pcbSize);
2658 PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
2659
2660 if(!pGCState)
2661 {
2662 Assert(pGCState);
2663 return VERR_EM_INTERPRETER;
2664 }
2665 pGCState->uVMFlags |= X86_EFL_IF;
2666
2667 Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
2668 Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
2669
2670 pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->opsize;
2671 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2672
2673 return VINF_SUCCESS;
2674}
2675#endif /* IN_RC */
2676
2677
2678/**
2679 * HLT Emulation.
2680 */
2681static VBOXSTRICTRC
2682emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2683{
2684 NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
2685 return VINF_EM_HALT;
2686}
2687
2688
2689/**
2690 * Interpret RDTSC
2691 *
2692 * @returns VBox status code.
2693 * @param pVM The VM handle.
2694 * @param pVCpu The VMCPU handle.
2695 * @param pRegFrame The register frame.
2696 *
2697 */
2698VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2699{
2700 unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2701
2702 if (uCR4 & X86_CR4_TSD)
2703 return VERR_EM_INTERPRETER; /* genuine #GP */
2704
2705 uint64_t uTicks = TMCpuTickGet(pVCpu);
2706
2707 /* Same behaviour in 32 & 64 bits mode */
2708 pRegFrame->rax = (uint32_t)uTicks;
2709 pRegFrame->rdx = (uTicks >> 32ULL);
2710
2711 NOREF(pVM);
2712 return VINF_SUCCESS;
2713}
2714
2715/**
2716 * Interpret RDTSCP
2717 *
2718 * @returns VBox status code.
2719 * @param pVM The VM handle.
2720 * @param pVCpu The VMCPU handle.
2721 * @param pCtx The CPU context.
2722 *
2723 */
2724VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2725{
2726 unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2727
2728 if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
2729 {
2730 AssertFailed();
2731 return VERR_EM_INTERPRETER; /* genuine #UD */
2732 }
2733
2734 if (uCR4 & X86_CR4_TSD)
2735 return VERR_EM_INTERPRETER; /* genuine #GP */
2736
2737 uint64_t uTicks = TMCpuTickGet(pVCpu);
2738
2739 /* Same behaviour in 32 & 64 bits mode */
2740 pCtx->rax = (uint32_t)uTicks;
2741 pCtx->rdx = (uTicks >> 32ULL);
2742 /* Low dword of the TSC_AUX msr only. */
2743 CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);
2744 pCtx->rcx &= UINT32_C(0xffffffff);
2745
2746 return VINF_SUCCESS;
2747}
2748
2749/**
2750 * RDTSC Emulation.
2751 */
2752static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2753{
2754 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
2755 return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
2756}
2757
2758/**
2759 * Interpret RDPMC
2760 *
2761 * @returns VBox status code.
2762 * @param pVM The VM handle.
2763 * @param pVCpu The VMCPU handle.
2764 * @param pRegFrame The register frame.
2765 *
2766 */
2767VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2768{
2769 unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
2770
2771 /* If X86_CR4_PCE is not set, then CPL must be zero. */
2772 if ( !(uCR4 & X86_CR4_PCE)
2773 && CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
2774 {
2775 Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
2776 return VERR_EM_INTERPRETER; /* genuine #GP */
2777 }
2778
2779 /* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
2780 pRegFrame->rax = 0;
2781 pRegFrame->rdx = 0;
2782 /** @todo We should trigger a #GP here if the cpu doesn't support the index in ecx. */
2783
2784 NOREF(pVM);
2785 return VINF_SUCCESS;
2786}
2787
2788/**
2789 * RDPMC Emulation
2790 */
2791static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2792{
2793 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
2794 return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
2795}
2796
2797
2798/**
2799 * MONITOR Emulation.
2800 */
2801VMMDECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2802{
2803 uint32_t u32Dummy, u32ExtFeatures, cpl;
2804 NOREF(pVM);
2805
2806 if (pRegFrame->ecx != 0)
2807 {
2808 Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
2809 return VERR_EM_INTERPRETER; /* illegal value. */
2810 }
2811
2812 /* Get the current privilege level. */
2813 cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2814 if (cpl != 0)
2815 return VERR_EM_INTERPRETER; /* supervisor only */
2816
2817 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2818 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2819 return VERR_EM_INTERPRETER; /* not supported */
2820
2821 EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx);
2822 return VINF_SUCCESS;
2823}
2824
2825static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2826{
2827 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
2828 return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
2829}
2830
2831
2832/**
2833 * MWAIT Emulation.
2834 */
2835VMMDECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2836{
2837 uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
2838 NOREF(pVM);
2839
2840 /* Get the current privilege level. */
2841 cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
2842 if (cpl != 0)
2843 return VERR_EM_INTERPRETER; /* supervisor only */
2844
2845 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2846 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2847 return VERR_EM_INTERPRETER; /* not supported */
2848
2849 /*
2850 * CPUID.05H.ECX[0] defines support for power management extensions (eax)
2851 * CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
2852 */
2853 CPUMGetGuestCpuId(pVCpu, 5, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
2854 if (pRegFrame->ecx > 1)
2855 {
2856 Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
2857 return VERR_EM_INTERPRETER; /* illegal value. */
2858 }
2859
2860 if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
2861 {
2862 Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
2863 return VERR_EM_INTERPRETER; /* illegal value. */
2864 }
2865
2866 return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
2867}
2868
2869static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2870{
2871 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
2872 return EMInterpretMWait(pVM, pVCpu, pRegFrame);
2873}
2874
2875
2876#ifdef LOG_ENABLED
2877static const char *emMSRtoString(uint32_t uMsr)
2878{
2879 switch (uMsr)
2880 {
2881 case MSR_IA32_APICBASE:
2882 return "MSR_IA32_APICBASE";
2883 case MSR_IA32_CR_PAT:
2884 return "MSR_IA32_CR_PAT";
2885 case MSR_IA32_SYSENTER_CS:
2886 return "MSR_IA32_SYSENTER_CS";
2887 case MSR_IA32_SYSENTER_EIP:
2888 return "MSR_IA32_SYSENTER_EIP";
2889 case MSR_IA32_SYSENTER_ESP:
2890 return "MSR_IA32_SYSENTER_ESP";
2891 case MSR_K6_EFER:
2892 return "MSR_K6_EFER";
2893 case MSR_K8_SF_MASK:
2894 return "MSR_K8_SF_MASK";
2895 case MSR_K6_STAR:
2896 return "MSR_K6_STAR";
2897 case MSR_K8_LSTAR:
2898 return "MSR_K8_LSTAR";
2899 case MSR_K8_CSTAR:
2900 return "MSR_K8_CSTAR";
2901 case MSR_K8_FS_BASE:
2902 return "MSR_K8_FS_BASE";
2903 case MSR_K8_GS_BASE:
2904 return "MSR_K8_GS_BASE";
2905 case MSR_K8_KERNEL_GS_BASE:
2906 return "MSR_K8_KERNEL_GS_BASE";
2907 case MSR_K8_TSC_AUX:
2908 return "MSR_K8_TSC_AUX";
2909 case MSR_IA32_BIOS_SIGN_ID:
2910 return "Unsupported MSR_IA32_BIOS_SIGN_ID";
2911 case MSR_IA32_PLATFORM_ID:
2912 return "Unsupported MSR_IA32_PLATFORM_ID";
2913 case MSR_IA32_BIOS_UPDT_TRIG:
2914 return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
2915 case MSR_IA32_TSC:
2916 return "MSR_IA32_TSC";
2917 case MSR_IA32_MISC_ENABLE:
2918 return "MSR_IA32_MISC_ENABLE";
2919 case MSR_IA32_MTRR_CAP:
2920 return "MSR_IA32_MTRR_CAP";
2921 case MSR_IA32_MCP_CAP:
2922 return "Unsupported MSR_IA32_MCP_CAP";
2923 case MSR_IA32_MCP_STATUS:
2924 return "Unsupported MSR_IA32_MCP_STATUS";
2925 case MSR_IA32_MCP_CTRL:
2926 return "Unsupported MSR_IA32_MCP_CTRL";
2927 case MSR_IA32_MTRR_DEF_TYPE:
2928 return "MSR_IA32_MTRR_DEF_TYPE";
2929 case MSR_K7_EVNTSEL0:
2930 return "Unsupported MSR_K7_EVNTSEL0";
2931 case MSR_K7_EVNTSEL1:
2932 return "Unsupported MSR_K7_EVNTSEL1";
2933 case MSR_K7_EVNTSEL2:
2934 return "Unsupported MSR_K7_EVNTSEL2";
2935 case MSR_K7_EVNTSEL3:
2936 return "Unsupported MSR_K7_EVNTSEL3";
2937 case MSR_IA32_MC0_CTL:
2938 return "Unsupported MSR_IA32_MC0_CTL";
2939 case MSR_IA32_MC0_STATUS:
2940 return "Unsupported MSR_IA32_MC0_STATUS";
2941 case MSR_IA32_PERFEVTSEL0:
2942 return "Unsupported MSR_IA32_PERFEVTSEL0";
2943 case MSR_IA32_PERFEVTSEL1:
2944 return "Unsupported MSR_IA32_PERFEVTSEL1";
2945 case MSR_IA32_PERF_STATUS:
2946 return "MSR_IA32_PERF_STATUS";
2947 case MSR_IA32_PLATFORM_INFO:
2948 return "MSR_IA32_PLATFORM_INFO";
2949 case MSR_IA32_PERF_CTL:
2950 return "Unsupported MSR_IA32_PERF_CTL";
2951 case MSR_K7_PERFCTR0:
2952 return "Unsupported MSR_K7_PERFCTR0";
2953 case MSR_K7_PERFCTR1:
2954 return "Unsupported MSR_K7_PERFCTR1";
2955 case MSR_K7_PERFCTR2:
2956 return "Unsupported MSR_K7_PERFCTR2";
2957 case MSR_K7_PERFCTR3:
2958 return "Unsupported MSR_K7_PERFCTR3";
2959 case MSR_IA32_PMC0:
2960 return "Unsupported MSR_IA32_PMC0";
2961 case MSR_IA32_PMC1:
2962 return "Unsupported MSR_IA32_PMC1";
2963 case MSR_IA32_PMC2:
2964 return "Unsupported MSR_IA32_PMC2";
2965 case MSR_IA32_PMC3:
2966 return "Unsupported MSR_IA32_PMC3";
2967 }
2968 return "Unknown MSR";
2969}
2970#endif /* LOG_ENABLED */
2971
2972
2973/**
2974 * Interpret RDMSR
2975 *
2976 * @returns VBox status code.
2977 * @param pVM The VM handle.
2978 * @param pVCpu The VMCPU handle.
2979 * @param pRegFrame The register frame.
2980 */
2981VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
2982{
2983 /** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
2984 * That version clears the high dwords of both RDX & RAX */
2985 NOREF(pVM);
2986
2987 /* Get the current privilege level. */
2988 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
2989 return VERR_EM_INTERPRETER; /* supervisor only */
2990
2991 uint64_t uValue;
2992 int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
2993 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2994 {
2995 Assert(rc == VERR_CPUM_RAISE_GP_0);
2996 return VERR_EM_INTERPRETER;
2997 }
2998 pRegFrame->rax = (uint32_t) uValue;
2999 pRegFrame->rdx = (uint32_t)(uValue >> 32);
3000 LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
3001 return rc;
3002}
3003
3004
3005/**
3006 * RDMSR Emulation.
3007 */
3008static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3009{
3010 /* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3011 different, so we play safe by completely disassembling the instruction. */
3012 Assert(!(pDis->prefix & PREFIX_REX));
3013 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3014 return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3015}
3016
3017
3018/**
3019 * Interpret WRMSR
3020 *
3021 * @returns VBox status code.
3022 * @param pVM The VM handle.
3023 * @param pVCpu The VMCPU handle.
3024 * @param pRegFrame The register frame.
3025 */
3026VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3027{
3028 /* Check the current privilege level, this instruction is supervisor only. */
3029 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
3030 return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
3031
3032 int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
3033 if (rc != VINF_SUCCESS)
3034 {
3035 Assert(rc == VERR_CPUM_RAISE_GP_0);
3036 return VERR_EM_INTERPRETER;
3037 }
3038 LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
3039 RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
3040 NOREF(pVM);
3041 return rc;
3042}
3043
3044
3045/**
3046 * WRMSR Emulation.
3047 */
3048static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3049{
3050 NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3051 return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3052}
3053
3054
3055/**
3056 * Internal worker.
3057 * @copydoc EMInterpretInstructionCPU
3058 */
3059DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3060 RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3061{
3062 Assert(enmCodeType == EMCODETYPE_SUPERVISOR || enmCodeType == EMCODETYPE_ALL);
3063 Assert(pcbSize);
3064 *pcbSize = 0;
3065
3066 if (enmCodeType == EMCODETYPE_SUPERVISOR)
3067 {
3068 /*
3069 * Only supervisor guest code!!
3070 * And no complicated prefixes.
3071 */
3072 /* Get the current privilege level. */
3073 uint32_t cpl = CPUMGetGuestCPL(pVCpu, pRegFrame);
3074 if ( cpl != 0
3075 && pDis->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3076 {
3077 Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3078 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3079 return VERR_EM_INTERPRETER;
3080 }
3081 }
3082 else
3083 Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3084
3085#ifdef IN_RC
3086 if ( (pDis->prefix & (PREFIX_REPNE | PREFIX_REP))
3087 || ( (pDis->prefix & PREFIX_LOCK)
3088 && pDis->pCurInstr->opcode != OP_CMPXCHG
3089 && pDis->pCurInstr->opcode != OP_CMPXCHG8B
3090 && pDis->pCurInstr->opcode != OP_XADD
3091 && pDis->pCurInstr->opcode != OP_OR
3092 && pDis->pCurInstr->opcode != OP_AND
3093 && pDis->pCurInstr->opcode != OP_XOR
3094 && pDis->pCurInstr->opcode != OP_BTR
3095 )
3096 )
3097#else
3098 if ( (pDis->prefix & PREFIX_REPNE)
3099 || ( (pDis->prefix & PREFIX_REP)
3100 && pDis->pCurInstr->opcode != OP_STOSWD
3101 )
3102 || ( (pDis->prefix & PREFIX_LOCK)
3103 && pDis->pCurInstr->opcode != OP_OR
3104 && pDis->pCurInstr->opcode != OP_AND
3105 && pDis->pCurInstr->opcode != OP_XOR
3106 && pDis->pCurInstr->opcode != OP_BTR
3107 && pDis->pCurInstr->opcode != OP_CMPXCHG
3108 && pDis->pCurInstr->opcode != OP_CMPXCHG8B
3109 )
3110 )
3111#endif
3112 {
3113 //Log(("EMInterpretInstruction: wrong prefix!!\n"));
3114 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3115 return VERR_EM_INTERPRETER;
3116 }
3117
3118#if HC_ARCH_BITS == 32
3119 /*
3120 * Unable to emulate most >4 bytes accesses in 32 bits mode.
3121 * Whitelisted instructions are safe.
3122 */
3123 if ( pDis->param1.size > 4
3124 && CPUMIsGuestIn64BitCode(pVCpu, pRegFrame))
3125 {
3126 uint32_t uOpCode = pDis->pCurInstr->opcode;
3127 if ( uOpCode != OP_STOSWD
3128 && uOpCode != OP_MOV
3129 && uOpCode != OP_CMPXCHG8B
3130 && uOpCode != OP_XCHG
3131 && uOpCode != OP_BTS
3132 && uOpCode != OP_BTR
3133 && uOpCode != OP_BTC
3134# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3135 && uOpCode != OP_CMPXCHG /* solaris */
3136 && uOpCode != OP_AND /* windows */
3137 && uOpCode != OP_OR /* windows */
3138 && uOpCode != OP_XOR /* because we can */
3139 && uOpCode != OP_ADD /* windows (dripple) */
3140 && uOpCode != OP_ADC /* because we can */
3141 && uOpCode != OP_SUB /* because we can */
3142 /** @todo OP_BTS or is that a different kind of failure? */
3143# endif
3144 )
3145 {
3146# ifdef VBOX_WITH_STATISTICS
3147 switch (pDis->pCurInstr->opcode)
3148 {
3149# define INTERPRET_FAILED_CASE(opcode, Instr) \
3150 case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3151 INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3152 INTERPRET_FAILED_CASE(OP_DEC,Dec);
3153 INTERPRET_FAILED_CASE(OP_INC,Inc);
3154 INTERPRET_FAILED_CASE(OP_POP,Pop);
3155 INTERPRET_FAILED_CASE(OP_OR, Or);
3156 INTERPRET_FAILED_CASE(OP_XOR,Xor);
3157 INTERPRET_FAILED_CASE(OP_AND,And);
3158 INTERPRET_FAILED_CASE(OP_MOV,Mov);
3159 INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3160 INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3161 INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3162 INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3163 INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3164 INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3165 INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3166 INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3167 INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3168 INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3169 INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3170 INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3171 INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3172 INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3173 INTERPRET_FAILED_CASE(OP_ADD,Add);
3174 INTERPRET_FAILED_CASE(OP_SUB,Sub);
3175 INTERPRET_FAILED_CASE(OP_ADC,Adc);
3176 INTERPRET_FAILED_CASE(OP_BTR,Btr);
3177 INTERPRET_FAILED_CASE(OP_BTS,Bts);
3178 INTERPRET_FAILED_CASE(OP_BTC,Btc);
3179 INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3180 INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3181 INTERPRET_FAILED_CASE(OP_STI, Sti);
3182 INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3183 INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3184 INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3185 INTERPRET_FAILED_CASE(OP_IRET,Iret);
3186 INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3187 INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3188# undef INTERPRET_FAILED_CASE
3189 default:
3190 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3191 break;
3192 }
3193# endif /* VBOX_WITH_STATISTICS */
3194 return VERR_EM_INTERPRETER;
3195 }
3196 }
3197#endif
3198
3199 VBOXSTRICTRC rc;
3200#if (defined(VBOX_STRICT) || defined(LOG_ENABLED))
3201 LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3202#endif
3203 switch (pDis->pCurInstr->opcode)
3204 {
3205 /*
3206 * Macros for generating the right case statements.
3207 */
3208# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3209 case opcode:\
3210 if (pDis->prefix & PREFIX_LOCK) \
3211 rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3212 else \
3213 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3214 if (RT_SUCCESS(rc)) \
3215 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3216 else \
3217 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3218 return rc
3219#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3220 case opcode:\
3221 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3222 if (RT_SUCCESS(rc)) \
3223 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3224 else \
3225 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3226 return rc
3227
3228#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3229 INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3230#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3231 INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3232
3233#define INTERPRET_CASE(opcode, Instr) \
3234 case opcode:\
3235 rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3236 if (RT_SUCCESS(rc)) \
3237 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3238 else \
3239 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3240 return rc
3241
3242#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3243 case opcode:\
3244 rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3245 if (RT_SUCCESS(rc)) \
3246 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3247 else \
3248 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3249 return rc
3250
3251#define INTERPRET_STAT_CASE(opcode, Instr) \
3252 case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3253
3254 /*
3255 * The actual case statements.
3256 */
3257 INTERPRET_CASE(OP_XCHG,Xchg);
3258 INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3259 INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3260 INTERPRET_CASE(OP_POP,Pop);
3261 INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3262 INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3263 INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3264 INTERPRET_CASE(OP_MOV,Mov);
3265#ifndef IN_RC
3266 INTERPRET_CASE(OP_STOSWD,StosWD);
3267#endif
3268 INTERPRET_CASE(OP_INVLPG,InvlPg);
3269 INTERPRET_CASE(OP_CPUID,CpuId);
3270 INTERPRET_CASE(OP_MOV_CR,MovCRx);
3271 INTERPRET_CASE(OP_MOV_DR,MovDRx);
3272#ifdef IN_RING0
3273 INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3274 INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3275#endif
3276 INTERPRET_CASE(OP_LLDT,LLdt);
3277 INTERPRET_CASE(OP_LMSW,Lmsw);
3278#ifdef EM_EMULATE_SMSW
3279 INTERPRET_CASE(OP_SMSW,Smsw);
3280#endif
3281 INTERPRET_CASE(OP_CLTS,Clts);
3282 INTERPRET_CASE(OP_MONITOR, Monitor);
3283 INTERPRET_CASE(OP_MWAIT, MWait);
3284 INTERPRET_CASE(OP_RDMSR, Rdmsr);
3285 INTERPRET_CASE(OP_WRMSR, Wrmsr);
3286 INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3287 INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3288 INTERPRET_CASE(OP_ADC,Adc);
3289 INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3290 INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3291 INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3292 INTERPRET_CASE(OP_RDPMC,Rdpmc);
3293 INTERPRET_CASE(OP_RDTSC,Rdtsc);
3294 INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3295#ifdef IN_RC
3296 INTERPRET_CASE(OP_STI,Sti);
3297 INTERPRET_CASE(OP_XADD, XAdd);
3298#endif
3299 INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3300 INTERPRET_CASE(OP_HLT,Hlt);
3301 INTERPRET_CASE(OP_IRET,Iret);
3302 INTERPRET_CASE(OP_WBINVD,WbInvd);
3303#ifdef VBOX_WITH_STATISTICS
3304# ifndef IN_RC
3305 INTERPRET_STAT_CASE(OP_XADD, XAdd);
3306# endif
3307 INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3308#endif
3309
3310 default:
3311 Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->opcode));
3312 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3313 return VERR_EM_INTERPRETER;
3314
3315#undef INTERPRET_CASE_EX_PARAM2
3316#undef INTERPRET_STAT_CASE
3317#undef INTERPRET_CASE_EX
3318#undef INTERPRET_CASE
3319 } /* switch (opcode) */
3320 /* not reached */
3321}
3322
3323#endif /* !VBOX_WITH_IEM */
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