EMAll.cpp@ 45312

Last change on this file since 45312 was 45301, checked in by vboxsync, 12 years ago
IOM: Preparing to use read/write critsect.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 139.2 KB

Line
1	/* $Id: EMAll.cpp 45301 2013-04-03 09:51:13Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/pgm.h>
28	#ifdef VBOX_WITH_IEM
29	# include <VBox/vmm/iem.h>
30	#endif
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/stam.h>
33	#include "EMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/vmm/hm.h>
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include "internal/pgm.h"
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49	#ifndef IN_RC
50	#undef VBOX_WITH_IEM
51	#endif
52	#ifdef VBOX_WITH_IEM
53	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
54	//# define VBOX_SAME_AS_EM
55	//# define VBOX_COMPARE_IEM_LAST
56	#endif
57
58	#ifdef VBOX_WITH_RAW_RING1
59	#define EM_EMULATE_SMSW
60	#endif
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** @def EM_ASSERT_FAULT_RETURN
66	* Safety check.
67	*
68	* Could in theory misfire on a cross page boundary access...
69	*
70	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
71	* turns up an alias page instead of the original faulting one and annoying the
72	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
73	*/
74	#if 0
75	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
76	#else
77	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
78	#endif
79
80
81	/*******************************************************************************
82	* Internal Functions *
83	*******************************************************************************/
84	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
85	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
86	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
87	#endif
88
89
90	/*******************************************************************************
91	* Global Variables *
92	*******************************************************************************/
93	#ifdef VBOX_COMPARE_IEM_AND_EM
94	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
95	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
96	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
97	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
98	static uint32_t g_fIncomingFFs;
99	static CPUMCTX g_IncomingCtx;
100	static bool g_fIgnoreRaxRdx = false;
101
102	static uint32_t g_fEmFFs;
103	static CPUMCTX g_EmCtx;
104	static uint8_t g_abEmWrote[256];
105	static size_t g_cbEmWrote;
106
107	static uint32_t g_fIemFFs;
108	static CPUMCTX g_IemCtx;
109	extern uint8_t g_abIemWrote[256];
110	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
111	extern size_t g_cbIemWrote;
112	#else
113	static size_t g_cbIemWrote;
114	#endif
115	#endif
116
117
118	/**
119	* Get the current execution manager status.
120	*
121	* @returns Current status.
122	* @param pVCpu Pointer to the VMCPU.
123	*/
124	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
125	{
126	return pVCpu->em.s.enmState;
127	}
128
129	/**
130	* Sets the current execution manager status. (use only when you know what you're doing!)
131	*
132	* @param pVCpu Pointer to the VMCPU.
133	*/
134	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
135	{
136	/* Only allowed combination: */
137	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
138	pVCpu->em.s.enmState = enmNewState;
139	}
140
141
142	/**
143	* Sets the PC for which interrupts should be inhibited.
144	*
145	* @param pVCpu Pointer to the VMCPU.
146	* @param PC The PC.
147	*/
148	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
149	{
150	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
151	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
152	}
153
154
155	/**
156	* Gets the PC for which interrupts should be inhibited.
157	*
158	* There are a few instructions which inhibits or delays interrupts
159	* for the instruction following them. These instructions are:
160	* - STI
161	* - MOV SS, r/m16
162	* - POP SS
163	*
164	* @returns The PC for which interrupts should be inhibited.
165	* @param pVCpu Pointer to the VMCPU.
166	*
167	*/
168	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
169	{
170	return pVCpu->em.s.GCPtrInhibitInterrupts;
171	}
172
173
174	/**
175	* Prepare an MWAIT - essentials of the MONITOR instruction.
176	*
177	* @returns VINF_SUCCESS
178	* @param pVCpu The current CPU.
179	* @param rax The content of RAX.
180	* @param rcx The content of RCX.
181	* @param rdx The content of RDX.
182	*/
183	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx)
184	{
185	pVCpu->em.s.MWait.uMonitorRAX = rax;
186	pVCpu->em.s.MWait.uMonitorRCX = rcx;
187	pVCpu->em.s.MWait.uMonitorRDX = rdx;
188	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
189	/** @todo Complete MONITOR implementation. */
190	return VINF_SUCCESS;
191	}
192
193
194	/**
195	* Performs an MWAIT.
196	*
197	* @returns VINF_SUCCESS
198	* @param pVCpu The current CPU.
199	* @param rax The content of RAX.
200	* @param rcx The content of RCX.
201	*/
202	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
203	{
204	pVCpu->em.s.MWait.uMWaitRAX = rax;
205	pVCpu->em.s.MWait.uMWaitRCX = rcx;
206	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
207	if (rcx)
208	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
209	else
210	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
211	/** @todo not completely correct?? */
212	return VINF_EM_HALT;
213	}
214
215
216
217	/**
218	* Determine if we should continue after encountering a hlt or mwait
219	* instruction.
220	*
221	* Clears MWAIT flags if returning @c true.
222	*
223	* @returns boolean
224	* @param pVCpu Pointer to the VMCPU.
225	* @param pCtx Current CPU context.
226	*/
227	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
228	{
229	if ( pCtx->eflags.Bits.u1IF
230	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
231	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
232	{
233	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
234	return !!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
235	}
236
237	return false;
238	}
239
240
241	/**
242	* Locks REM execution to a single VCPU.
243	*
244	* @param pVM Pointer to the VM.
245	*/
246	VMMDECL(void) EMRemLock(PVM pVM)
247	{
248	#ifdef VBOX_WITH_REM
249	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
250	return; /* early init */
251
252	Assert(!PGMIsLockOwner(pVM));
253	Assert(!IOMIsLockWriteOwner(pVM));
254	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
255	AssertRCSuccess(rc);
256	#endif
257	}
258
259
260	/**
261	* Unlocks REM execution
262	*
263	* @param pVM Pointer to the VM.
264	*/
265	VMMDECL(void) EMRemUnlock(PVM pVM)
266	{
267	#ifdef VBOX_WITH_REM
268	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
269	return; /* early init */
270
271	PDMCritSectLeave(&pVM->em.s.CritSectREM);
272	#endif
273	}
274
275
276	/**
277	* Check if this VCPU currently owns the REM lock.
278	*
279	* @returns bool owner/not owner
280	* @param pVM Pointer to the VM.
281	*/
282	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
283	{
284	#ifdef VBOX_WITH_REM
285	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
286	return true; /* early init */
287
288	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
289	#else
290	return true;
291	#endif
292	}
293
294
295	/**
296	* Try to acquire the REM lock.
297	*
298	* @returns VBox status code
299	* @param pVM Pointer to the VM.
300	*/
301	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
302	{
303	#ifdef VBOX_WITH_REM
304	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
305	return VINF_SUCCESS; /* early init */
306
307	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
308	#else
309	return VINF_SUCCESS;
310	#endif
311	}
312
313
314	/**
315	* @callback_method_impl{FNDISREADBYTES}
316	*/
317	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
318	{
319	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
320	#if defined(IN_RC) \|\| defined(IN_RING3)
321	PVM pVM = pVCpu->CTX_SUFF(pVM);
322	#endif
323	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
324	int rc;
325
326	/*
327	* Figure how much we can or must read.
328	*/
329	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
330	if (cbToRead > cbMaxRead)
331	cbToRead = cbMaxRead;
332	else if (cbToRead < cbMinRead)
333	cbToRead = cbMinRead;
334
335	#if defined(IN_RC) \|\| defined(IN_RING3)
336	/*
337	* We might be called upon to interpret an instruction in a patch.
338	*/
339	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
340	{
341	# ifdef IN_RC
342	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
343	# else
344	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
345	# endif
346	rc = VINF_SUCCESS;
347	}
348	else
349	#endif
350	{
351	# ifdef IN_RC
352	/*
353	* Try access it thru the shadow page tables first. Fall back on the
354	* slower PGM method if it fails because the TLB or page table was
355	* modified recently.
356	*/
357	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
358	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
359	{
360	cbToRead = cbMinRead;
361	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
362	}
363	if (rc == VERR_ACCESS_DENIED)
364	#endif
365	{
366	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
367	if (RT_FAILURE(rc))
368	{
369	if (cbToRead > cbMinRead)
370	{
371	cbToRead = cbMinRead;
372	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
373	}
374	if (RT_FAILURE(rc))
375	{
376	#ifndef IN_RC
377	/*
378	* If we fail to find the page via the guest's page tables
379	* we invalidate the page in the host TLB (pertaining to
380	* the guest in the NestedPaging case). See @bugref{6043}.
381	*/
382	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
383	{
384	HMInvalidatePage(pVCpu, uSrcAddr);
385	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
386	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
387	}
388	#endif
389	}
390	}
391	}
392	}
393
394	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
395	return rc;
396	}
397
398
399	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
400	{
401	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
402	}
403
404
405	/**
406	* Disassembles the current instruction.
407	*
408	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
409	* details.
410	* @retval VERR_EM_INTERNAL_DISAS_ERROR on DISCoreOneEx failure.
411	*
412	* @param pVM Pointer to the VM.
413	* @param pVCpu Pointer to the VMCPU.
414	* @param pDis Where to return the parsed instruction info.
415	* @param pcbInstr Where to return the instruction size. (optional)
416	*/
417	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
418	{
419	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
420	RTGCPTR GCPtrInstr;
421	#if 0
422	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
423	#else
424	/** @todo Get the CPU mode as well while we're at it! */
425	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
426	pCtxCore->rip, &GCPtrInstr);
427	#endif
428	if (RT_FAILURE(rc))
429	{
430	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
431	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
432	return rc;
433	}
434	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
435	}
436
437
438	/**
439	* Disassembles one instruction.
440	*
441	* This is used by internally by the interpreter and by trap/access handlers.
442	*
443	* @returns VBox status code.
444	* @retval VERR_EM_INTERNAL_DISAS_ERROR on DISCoreOneEx failure.
445	*
446	* @param pVM Pointer to the VM.
447	* @param pVCpu Pointer to the VMCPU.
448	* @param GCPtrInstr The flat address of the instruction.
449	* @param pCtxCore The context core (used to determine the cpu mode).
450	* @param pDis Where to return the parsed instruction info.
451	* @param pcbInstr Where to return the instruction size. (optional)
452	*/
453	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
454	PDISCPUSTATE pDis, unsigned *pcbInstr)
455	{
456	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
457	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
458	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
459	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
460	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
461	if (RT_SUCCESS(rc))
462	return VINF_SUCCESS;
463	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
464	return VERR_EM_INTERNAL_DISAS_ERROR;
465	}
466
467
468	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
469	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
470	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
471	uint32_t cbEm, uint32_t cbIem)
472	{
473	/* Quick compare. */
474	if ( rcEm == rcIem
475	&& cbEm == cbIem
476	&& g_cbEmWrote == g_cbIemWrote
477	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
478	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
479	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
480	)
481	return;
482
483	/* Report exact differences. */
484	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
485	if (rcEm != rcIem)
486	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
487	else if (cbEm != cbIem)
488	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
489
490	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
491	{
492	if (g_cbIemWrote != g_cbEmWrote)
493	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
494	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
495	{
496	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
497	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
498	}
499
500	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
501	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
502	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
503
504	# define CHECK_FIELD(a_Field) \
505	do \
506	{ \
507	if (pEmCtx->a_Field != pIemCtx->a_Field) \
508	{ \
509	switch (sizeof(pEmCtx->a_Field)) \
510	{ \
511	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
512	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
513	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
514	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
515	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
516	} \
517	cDiffs++; \
518	} \
519	} while (0)
520
521	# define CHECK_BIT_FIELD(a_Field) \
522	do \
523	{ \
524	if (pEmCtx->a_Field != pIemCtx->a_Field) \
525	{ \
526	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
527	cDiffs++; \
528	} \
529	} while (0)
530
531	# define CHECK_SEL(a_Sel) \
532	do \
533	{ \
534	CHECK_FIELD(a_Sel.Sel); \
535	CHECK_FIELD(a_Sel.Attr.u); \
536	CHECK_FIELD(a_Sel.u64Base); \
537	CHECK_FIELD(a_Sel.u32Limit); \
538	CHECK_FIELD(a_Sel.fFlags); \
539	} while (0)
540
541	unsigned cDiffs = 0;
542	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
543	{
544	RTLogPrintf(" the FPU state differs\n");
545	cDiffs++;
546	CHECK_FIELD(fpu.FCW);
547	CHECK_FIELD(fpu.FSW);
548	CHECK_FIELD(fpu.FTW);
549	CHECK_FIELD(fpu.FOP);
550	CHECK_FIELD(fpu.FPUIP);
551	CHECK_FIELD(fpu.CS);
552	CHECK_FIELD(fpu.Rsrvd1);
553	CHECK_FIELD(fpu.FPUDP);
554	CHECK_FIELD(fpu.DS);
555	CHECK_FIELD(fpu.Rsrvd2);
556	CHECK_FIELD(fpu.MXCSR);
557	CHECK_FIELD(fpu.MXCSR_MASK);
558	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
559	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
560	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
561	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
562	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
563	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
564	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
565	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
566	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
567	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
568	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
569	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
570	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
571	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
572	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
573	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
574	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
575	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
576	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
577	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
578	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
579	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
580	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
581	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
582	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
583	CHECK_FIELD(fpu.au32RsrvdRest[i]);
584	}
585	CHECK_FIELD(rip);
586	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
587	{
588	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
589	CHECK_BIT_FIELD(rflags.Bits.u1CF);
590	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
591	CHECK_BIT_FIELD(rflags.Bits.u1PF);
592	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
593	CHECK_BIT_FIELD(rflags.Bits.u1AF);
594	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
595	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
596	CHECK_BIT_FIELD(rflags.Bits.u1SF);
597	CHECK_BIT_FIELD(rflags.Bits.u1TF);
598	CHECK_BIT_FIELD(rflags.Bits.u1IF);
599	CHECK_BIT_FIELD(rflags.Bits.u1DF);
600	CHECK_BIT_FIELD(rflags.Bits.u1OF);
601	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
602	CHECK_BIT_FIELD(rflags.Bits.u1NT);
603	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
604	CHECK_BIT_FIELD(rflags.Bits.u1RF);
605	CHECK_BIT_FIELD(rflags.Bits.u1VM);
606	CHECK_BIT_FIELD(rflags.Bits.u1AC);
607	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
608	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
609	CHECK_BIT_FIELD(rflags.Bits.u1ID);
610	}
611
612	if (!g_fIgnoreRaxRdx)
613	CHECK_FIELD(rax);
614	CHECK_FIELD(rcx);
615	if (!g_fIgnoreRaxRdx)
616	CHECK_FIELD(rdx);
617	CHECK_FIELD(rbx);
618	CHECK_FIELD(rsp);
619	CHECK_FIELD(rbp);
620	CHECK_FIELD(rsi);
621	CHECK_FIELD(rdi);
622	CHECK_FIELD(r8);
623	CHECK_FIELD(r9);
624	CHECK_FIELD(r10);
625	CHECK_FIELD(r11);
626	CHECK_FIELD(r12);
627	CHECK_FIELD(r13);
628	CHECK_SEL(cs);
629	CHECK_SEL(ss);
630	CHECK_SEL(ds);
631	CHECK_SEL(es);
632	CHECK_SEL(fs);
633	CHECK_SEL(gs);
634	CHECK_FIELD(cr0);
635	CHECK_FIELD(cr2);
636	CHECK_FIELD(cr3);
637	CHECK_FIELD(cr4);
638	CHECK_FIELD(dr[0]);
639	CHECK_FIELD(dr[1]);
640	CHECK_FIELD(dr[2]);
641	CHECK_FIELD(dr[3]);
642	CHECK_FIELD(dr[6]);
643	CHECK_FIELD(dr[7]);
644	CHECK_FIELD(gdtr.cbGdt);
645	CHECK_FIELD(gdtr.pGdt);
646	CHECK_FIELD(idtr.cbIdt);
647	CHECK_FIELD(idtr.pIdt);
648	CHECK_SEL(ldtr);
649	CHECK_SEL(tr);
650	CHECK_FIELD(SysEnter.cs);
651	CHECK_FIELD(SysEnter.eip);
652	CHECK_FIELD(SysEnter.esp);
653	CHECK_FIELD(msrEFER);
654	CHECK_FIELD(msrSTAR);
655	CHECK_FIELD(msrPAT);
656	CHECK_FIELD(msrLSTAR);
657	CHECK_FIELD(msrCSTAR);
658	CHECK_FIELD(msrSFMASK);
659	CHECK_FIELD(msrKERNELGSBASE);
660
661	# undef CHECK_FIELD
662	# undef CHECK_BIT_FIELD
663	}
664	}
665	#endif /* VBOX_COMPARE_IEM_AND_EM */
666
667
668	/**
669	* Interprets the current instruction.
670	*
671	* @returns VBox status code.
672	* @retval VINF_* Scheduling instructions.
673	* @retval VERR_EM_INTERPRETER Something we can't cope with.
674	* @retval VERR_* Fatal errors.
675	*
676	* @param pVCpu Pointer to the VMCPU.
677	* @param pRegFrame The register frame.
678	* Updates the EIP if an instruction was executed successfully.
679	* @param pvFault The fault address (CR2).
680	* @param pcbSize Size of the write (if applicable).
681	*
682	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
683	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
684	* to worry about e.g. invalid modrm combinations (!)
685	*/
686	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
687	{
688	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
689	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
690	#ifdef VBOX_WITH_IEM
691	NOREF(pvFault);
692
693	# ifdef VBOX_COMPARE_IEM_AND_EM
694	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
695	g_IncomingCtx = *pCtx;
696	g_fIncomingFFs = pVCpu->fLocalForcedActions;
697	g_cbEmWrote = g_cbIemWrote = 0;
698
699	# ifdef VBOX_COMPARE_IEM_FIRST
700	/* IEM */
701	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
702	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
703	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
704	rcIem = VERR_EM_INTERPRETER;
705	g_IemCtx = *pCtx;
706	g_fIemFFs = pVCpu->fLocalForcedActions;
707	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
708	*pCtx = g_IncomingCtx;
709	# endif
710
711	/* EM */
712	RTGCPTR pbCode;
713	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
714	if (RT_SUCCESS(rcEm))
715	{
716	uint32_t cbOp;
717	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
718	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
719	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
720	if (RT_SUCCESS(rcEm))
721	{
722	Assert(cbOp == pDis->cbInstr);
723	uint32_t cbIgnored;
724	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
725	if (RT_SUCCESS(rcEm))
726	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
727
728	}
729	rcEm = VERR_EM_INTERPRETER;
730	}
731	else
732	rcEm = VERR_EM_INTERPRETER;
733	# ifdef VBOX_SAME_AS_EM
734	if (rcEm == VERR_EM_INTERPRETER)
735	{
736	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
737	return rcEm;
738	}
739	# endif
740	g_EmCtx = *pCtx;
741	g_fEmFFs = pVCpu->fLocalForcedActions;
742	VBOXSTRICTRC rc = rcEm;
743
744	# ifdef VBOX_COMPARE_IEM_LAST
745	/* IEM */
746	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
747	*pCtx = g_IncomingCtx;
748	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
749	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
750	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
751	rcIem = VERR_EM_INTERPRETER;
752	g_IemCtx = *pCtx;
753	g_fIemFFs = pVCpu->fLocalForcedActions;
754	rc = rcIem;
755	# endif
756
757	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
758	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
759	# endif
760
761	# else
762	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
763	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
764	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
765	rc = VERR_EM_INTERPRETER;
766	# endif
767	if (rc != VINF_SUCCESS)
768	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
769
770	return rc;
771	#else
772	RTGCPTR pbCode;
773	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
774	if (RT_SUCCESS(rc))
775	{
776	uint32_t cbOp;
777	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
778	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
779	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
780	if (RT_SUCCESS(rc))
781	{
782	Assert(cbOp == pDis->cbInstr);
783	uint32_t cbIgnored;
784	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
785	if (RT_SUCCESS(rc))
786	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
787
788	return rc;
789	}
790	}
791	return VERR_EM_INTERPRETER;
792	#endif
793	}
794
795
796	/**
797	* Interprets the current instruction.
798	*
799	* @returns VBox status code.
800	* @retval VINF_* Scheduling instructions.
801	* @retval VERR_EM_INTERPRETER Something we can't cope with.
802	* @retval VERR_* Fatal errors.
803	*
804	* @param pVM Pointer to the VM.
805	* @param pVCpu Pointer to the VMCPU.
806	* @param pRegFrame The register frame.
807	* Updates the EIP if an instruction was executed successfully.
808	* @param pvFault The fault address (CR2).
809	* @param pcbWritten Size of the write (if applicable).
810	*
811	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
812	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
813	* to worry about e.g. invalid modrm combinations (!)
814	*/
815	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
816	{
817	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
818	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
819	#ifdef VBOX_WITH_IEM
820	NOREF(pvFault);
821
822	# ifdef VBOX_COMPARE_IEM_AND_EM
823	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
824	g_IncomingCtx = *pCtx;
825	g_fIncomingFFs = pVCpu->fLocalForcedActions;
826	g_cbEmWrote = g_cbIemWrote = 0;
827
828	# ifdef VBOX_COMPARE_IEM_FIRST
829	/* IEM */
830	uint32_t cbIemWritten = 0;
831	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
832	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
833	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
834	rcIem = VERR_EM_INTERPRETER;
835	g_IemCtx = *pCtx;
836	g_fIemFFs = pVCpu->fLocalForcedActions;
837	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
838	*pCtx = g_IncomingCtx;
839	# endif
840
841	/* EM */
842	uint32_t cbEmWritten = 0;
843	RTGCPTR pbCode;
844	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
845	if (RT_SUCCESS(rcEm))
846	{
847	uint32_t cbOp;
848	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
849	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
850	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
851	if (RT_SUCCESS(rcEm))
852	{
853	Assert(cbOp == pDis->cbInstr);
854	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
855	if (RT_SUCCESS(rcEm))
856	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
857
858	}
859	else
860	rcEm = VERR_EM_INTERPRETER;
861	}
862	else
863	rcEm = VERR_EM_INTERPRETER;
864	# ifdef VBOX_SAME_AS_EM
865	if (rcEm == VERR_EM_INTERPRETER)
866	{
867	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
868	return rcEm;
869	}
870	# endif
871	g_EmCtx = *pCtx;
872	g_fEmFFs = pVCpu->fLocalForcedActions;
873	*pcbWritten = cbEmWritten;
874	VBOXSTRICTRC rc = rcEm;
875
876	# ifdef VBOX_COMPARE_IEM_LAST
877	/* IEM */
878	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
879	*pCtx = g_IncomingCtx;
880	uint32_t cbIemWritten = 0;
881	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
882	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
883	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
884	rcIem = VERR_EM_INTERPRETER;
885	g_IemCtx = *pCtx;
886	g_fIemFFs = pVCpu->fLocalForcedActions;
887	*pcbWritten = cbIemWritten;
888	rc = rcIem;
889	# endif
890
891	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
892	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
893	# endif
894
895	# else
896	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
897	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
898	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
899	rc = VERR_EM_INTERPRETER;
900	# endif
901	if (rc != VINF_SUCCESS)
902	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
903
904	return rc;
905	#else
906	RTGCPTR pbCode;
907	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
908	if (RT_SUCCESS(rc))
909	{
910	uint32_t cbOp;
911	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
912	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
913	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
914	if (RT_SUCCESS(rc))
915	{
916	Assert(cbOp == pDis->cbInstr);
917	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
918	if (RT_SUCCESS(rc))
919	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
920
921	return rc;
922	}
923	}
924	return VERR_EM_INTERPRETER;
925	#endif
926	}
927
928
929	/**
930	* Interprets the current instruction using the supplied DISCPUSTATE structure.
931	*
932	* IP/EIP/RIP IS updated!
933	*
934	* @returns VBox strict status code.
935	* @retval VINF_* Scheduling instructions. When these are returned, it
936	* starts to get a bit tricky to know whether code was
937	* executed or not... We'll address this when it becomes a problem.
938	* @retval VERR_EM_INTERPRETER Something we can't cope with.
939	* @retval VERR_* Fatal errors.
940	*
941	* @param pVM Pointer to the VM.
942	* @param pVCpu Pointer to the VMCPU.
943	* @param pDis The disassembler cpu state for the instruction to be
944	* interpreted.
945	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
946	* @param pvFault The fault address (CR2).
947	* @param pcbSize Size of the write (if applicable).
948	* @param enmCodeType Code type (user/supervisor)
949	*
950	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
951	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
952	* to worry about e.g. invalid modrm combinations (!)
953	*
954	* @todo At this time we do NOT check if the instruction overwrites vital information.
955	* Make sure this can't happen!! (will add some assertions/checks later)
956	*/
957	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
958	RTGCPTR pvFault, EMCODETYPE enmCodeType)
959	{
960	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
961	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
962	#ifdef VBOX_WITH_IEM
963	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
964
965	# ifdef VBOX_COMPARE_IEM_AND_EM
966	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
967	g_IncomingCtx = *pCtx;
968	g_fIncomingFFs = pVCpu->fLocalForcedActions;
969	g_cbEmWrote = g_cbIemWrote = 0;
970
971	# ifdef VBOX_COMPARE_IEM_FIRST
972	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
973	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
974	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
975	rcIem = VERR_EM_INTERPRETER;
976	g_IemCtx = *pCtx;
977	g_fIemFFs = pVCpu->fLocalForcedActions;
978	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
979	*pCtx = g_IncomingCtx;
980	# endif
981
982	/* EM */
983	uint32_t cbIgnored;
984	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
985	if (RT_SUCCESS(rcEm))
986	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
987	# ifdef VBOX_SAME_AS_EM
988	if (rcEm == VERR_EM_INTERPRETER)
989	{
990	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
991	return rcEm;
992	}
993	# endif
994	g_EmCtx = *pCtx;
995	g_fEmFFs = pVCpu->fLocalForcedActions;
996	VBOXSTRICTRC rc = rcEm;
997
998	# ifdef VBOX_COMPARE_IEM_LAST
999	/* IEM */
1000	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1001	*pCtx = g_IncomingCtx;
1002	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1003	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1004	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1005	rcIem = VERR_EM_INTERPRETER;
1006	g_IemCtx = *pCtx;
1007	g_fIemFFs = pVCpu->fLocalForcedActions;
1008	rc = rcIem;
1009	# endif
1010
1011	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1012	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1013	# endif
1014
1015	# else
1016	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1017	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1018	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1019	rc = VERR_EM_INTERPRETER;
1020	# endif
1021
1022	if (rc != VINF_SUCCESS)
1023	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1024
1025	return rc;
1026	#else
1027	uint32_t cbIgnored;
1028	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1029	if (RT_SUCCESS(rc))
1030	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1031	return rc;
1032	#endif
1033	}
1034
1035	#ifdef IN_RC
1036
1037	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1038	{
1039	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1040	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1041	return rc;
1042	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1043	}
1044
1045
1046	/**
1047	* Interpret IRET (currently only to V86 code) - PATM only.
1048	*
1049	* @returns VBox status code.
1050	* @param pVM Pointer to the VM.
1051	* @param pVCpu Pointer to the VMCPU.
1052	* @param pRegFrame The register frame.
1053	*
1054	*/
1055	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1056	{
1057	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1058	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1059	int rc;
1060
1061	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1062	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1063	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1064	* this function. Fear that it may guru on us, thus not converted to
1065	* IEM. */
1066
1067	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1068	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1069	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1070	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1071	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1072
1073	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1074	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1075	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1076	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1077	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1078	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1079	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1080
1081	pRegFrame->eip = eip & 0xffff;
1082	pRegFrame->cs.Sel = cs;
1083
1084	/* Mask away all reserved bits */
1085	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1086	eflags &= uMask;
1087
1088	CPUMRawSetEFlags(pVCpu, eflags);
1089	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1090
1091	pRegFrame->esp = esp;
1092	pRegFrame->ss.Sel = ss;
1093	pRegFrame->ds.Sel = ds;
1094	pRegFrame->es.Sel = es;
1095	pRegFrame->fs.Sel = fs;
1096	pRegFrame->gs.Sel = gs;
1097
1098	return VINF_SUCCESS;
1099	}
1100
1101	/**
1102	* IRET Emulation.
1103	*/
1104	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1105	{
1106	#ifdef VBOX_WITH_RAW_RING1
1107	NOREF(pvFault); NOREF(pcbSize);
1108	if (EMIsRawRing1Enabled(pVM))
1109	{
1110	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1111	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1112	int rc;
1113	uint32_t cpl, rpl;
1114
1115	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1116	/* @todo: we don't verify all the edge cases that generate #GP faults */
1117
1118	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1119	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1120	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1121	* this function. Fear that it may guru on us, thus not converted to
1122	* IEM. */
1123
1124	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1125	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1126	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1127	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1128	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1129
1130	/* Deal with V86 above. */
1131	if (eflags & X86_EFL_VM)
1132	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1133
1134	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1135	rpl = cs & X86_SEL_RPL;
1136
1137	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1138	if (rpl != cpl)
1139	{
1140	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1141	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1142	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1143	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1144	Log(("emInterpretIret: SS:ESP=%04X:08X\n", ss, esp));
1145	pRegFrame->ss.Sel = ss;
1146	pRegFrame->esp = esp;
1147	}
1148	pRegFrame->cs.Sel = cs;
1149	pRegFrame->eip = eip;
1150
1151	/* Adjust CS & SS as required. */
1152	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1153
1154	/* Mask away all reserved bits */
1155	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1156	eflags &= uMask;
1157
1158	CPUMRawSetEFlags(pVCpu, eflags);
1159	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1160	return VINF_SUCCESS;
1161	}
1162	#else
1163	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1164	#endif
1165	return VERR_EM_INTERPRETER;
1166	}
1167
1168	#endif /* IN_RC */
1169
1170
1171
1172	/*
1173	*
1174	* Old interpreter primitives used by HM, move/eliminate later.
1175	* Old interpreter primitives used by HM, move/eliminate later.
1176	* Old interpreter primitives used by HM, move/eliminate later.
1177	* Old interpreter primitives used by HM, move/eliminate later.
1178	* Old interpreter primitives used by HM, move/eliminate later.
1179	*
1180	*/
1181
1182
1183	/**
1184	* Interpret CPUID given the parameters in the CPU context.
1185	*
1186	* @returns VBox status code.
1187	* @param pVM Pointer to the VM.
1188	* @param pVCpu Pointer to the VMCPU.
1189	* @param pRegFrame The register frame.
1190	*
1191	*/
1192	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1193	{
1194	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1195	uint32_t iLeaf = pRegFrame->eax;
1196	NOREF(pVM);
1197
1198	/* cpuid clears the high dwords of the affected 64 bits registers. */
1199	pRegFrame->rax = 0;
1200	pRegFrame->rbx = 0;
1201	pRegFrame->rcx &= UINT64_C(0x00000000ffffffff);
1202	pRegFrame->rdx = 0;
1203
1204	/* Note: operates the same in 64 and non-64 bits mode. */
1205	CPUMGetGuestCpuId(pVCpu, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1206	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/**
1212	* Interpret RDTSC.
1213	*
1214	* @returns VBox status code.
1215	* @param pVM Pointer to the VM.
1216	* @param pVCpu Pointer to the VMCPU.
1217	* @param pRegFrame The register frame.
1218	*
1219	*/
1220	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1221	{
1222	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1223	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1224
1225	if (uCR4 & X86_CR4_TSD)
1226	return VERR_EM_INTERPRETER; /* genuine #GP */
1227
1228	uint64_t uTicks = TMCpuTickGet(pVCpu);
1229
1230	/* Same behaviour in 32 & 64 bits mode */
1231	pRegFrame->rax = (uint32_t)uTicks;
1232	pRegFrame->rdx = (uTicks >> 32ULL);
1233	#ifdef VBOX_COMPARE_IEM_AND_EM
1234	g_fIgnoreRaxRdx = true;
1235	#endif
1236
1237	NOREF(pVM);
1238	return VINF_SUCCESS;
1239	}
1240
1241	/**
1242	* Interpret RDTSCP.
1243	*
1244	* @returns VBox status code.
1245	* @param pVM Pointer to the VM.
1246	* @param pVCpu Pointer to the VMCPU.
1247	* @param pCtx The CPU context.
1248	*
1249	*/
1250	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1251	{
1252	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1253	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1254
1255	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1256	{
1257	AssertFailed();
1258	return VERR_EM_INTERPRETER; /* genuine #UD */
1259	}
1260
1261	if (uCR4 & X86_CR4_TSD)
1262	return VERR_EM_INTERPRETER; /* genuine #GP */
1263
1264	uint64_t uTicks = TMCpuTickGet(pVCpu);
1265
1266	/* Same behaviour in 32 & 64 bits mode */
1267	pCtx->rax = (uint32_t)uTicks;
1268	pCtx->rdx = (uTicks >> 32ULL);
1269	#ifdef VBOX_COMPARE_IEM_AND_EM
1270	g_fIgnoreRaxRdx = true;
1271	#endif
1272	/* Low dword of the TSC_AUX msr only. */
1273	CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);
1274	pCtx->rcx &= UINT32_C(0xffffffff);
1275
1276	return VINF_SUCCESS;
1277	}
1278
1279	/**
1280	* Interpret RDPMC.
1281	*
1282	* @returns VBox status code.
1283	* @param pVM Pointer to the VM.
1284	* @param pVCpu Pointer to the VMCPU.
1285	* @param pRegFrame The register frame.
1286	*
1287	*/
1288	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1289	{
1290	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1291	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1292
1293	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1294	if ( !(uCR4 & X86_CR4_PCE)
1295	&& CPUMGetGuestCPL(pVCpu) != 0)
1296	{
1297	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1298	return VERR_EM_INTERPRETER; /* genuine #GP */
1299	}
1300
1301	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1302	pRegFrame->rax = 0;
1303	pRegFrame->rdx = 0;
1304	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1305	* but see @bugref{3472}! */
1306
1307	NOREF(pVM);
1308	return VINF_SUCCESS;
1309	}
1310
1311
1312	/**
1313	* MWAIT Emulation.
1314	*/
1315	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1316	{
1317	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1318	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1319	NOREF(pVM);
1320
1321	/* Get the current privilege level. */
1322	cpl = CPUMGetGuestCPL(pVCpu);
1323	if (cpl != 0)
1324	return VERR_EM_INTERPRETER; /* supervisor only */
1325
1326	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1327	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1328	return VERR_EM_INTERPRETER; /* not supported */
1329
1330	/*
1331	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1332	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1333	*/
1334	CPUMGetGuestCpuId(pVCpu, 5, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1335	if (pRegFrame->ecx > 1)
1336	{
1337	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1338	return VERR_EM_INTERPRETER; /* illegal value. */
1339	}
1340
1341	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1342	{
1343	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1344	return VERR_EM_INTERPRETER; /* illegal value. */
1345	}
1346
1347	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1348	}
1349
1350
1351	/**
1352	* MONITOR Emulation.
1353	*/
1354	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1355	{
1356	uint32_t u32Dummy, u32ExtFeatures, cpl;
1357	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1358	NOREF(pVM);
1359
1360	if (pRegFrame->ecx != 0)
1361	{
1362	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1363	return VERR_EM_INTERPRETER; /* illegal value. */
1364	}
1365
1366	/* Get the current privilege level. */
1367	cpl = CPUMGetGuestCPL(pVCpu);
1368	if (cpl != 0)
1369	return VERR_EM_INTERPRETER; /* supervisor only */
1370
1371	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1372	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1373	return VERR_EM_INTERPRETER; /* not supported */
1374
1375	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx);
1376	return VINF_SUCCESS;
1377	}
1378
1379
1380	/* VT-x only: */
1381
1382	/**
1383	* Interpret INVLPG.
1384	*
1385	* @returns VBox status code.
1386	* @param pVM Pointer to the VM.
1387	* @param pVCpu Pointer to the VMCPU.
1388	* @param pRegFrame The register frame.
1389	* @param pAddrGC Operand address.
1390	*
1391	*/
1392	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1393	{
1394	/** @todo is addr always a flat linear address or ds based
1395	* (in absence of segment override prefixes)????
1396	*/
1397	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1398	NOREF(pVM); NOREF(pRegFrame);
1399	#ifdef IN_RC
1400	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1401	#endif
1402	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1403	if ( rc == VINF_SUCCESS
1404	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1405	return VINF_SUCCESS;
1406	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1407	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1408	VERR_EM_INTERPRETER);
1409	return rc;
1410	}
1411
1412
1413	/**
1414	* Update CRx.
1415	*
1416	* @returns VBox status code.
1417	* @param pVM Pointer to the VM.
1418	* @param pVCpu Pointer to the VMCPU.
1419	* @param pRegFrame The register frame.
1420	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1421	* @param val New CRx value
1422	*
1423	*/
1424	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1425	{
1426	uint64_t oldval;
1427	uint64_t msrEFER;
1428	int rc, rc2;
1429	NOREF(pVM);
1430
1431	/** @todo Clean up this mess. */
1432	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1433	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1434	switch (DestRegCrx)
1435	{
1436	case DISCREG_CR0:
1437	oldval = CPUMGetGuestCR0(pVCpu);
1438	#ifdef IN_RC
1439	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1440	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1441	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1442	return VERR_EM_INTERPRETER;
1443	#endif
1444	rc = VINF_SUCCESS;
1445	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1446	CPUMSetGuestCR0(pVCpu, val);
1447	#else
1448	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1449	#endif
1450	val = CPUMGetGuestCR0(pVCpu);
1451	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1452	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1453	{
1454	/* global flush */
1455	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1456	AssertRCReturn(rc, rc);
1457	}
1458
1459	/* Deal with long mode enabling/disabling. */
1460	msrEFER = CPUMGetGuestEFER(pVCpu);
1461	if (msrEFER & MSR_K6_EFER_LME)
1462	{
1463	if ( !(oldval & X86_CR0_PG)
1464	&& (val & X86_CR0_PG))
1465	{
1466	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1467	if (pRegFrame->cs.Attr.n.u1Long)
1468	{
1469	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1470	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1471	}
1472
1473	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1474	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1475	{
1476	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1477	return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
1478	}
1479	msrEFER \|= MSR_K6_EFER_LMA;
1480	}
1481	else
1482	if ( (oldval & X86_CR0_PG)
1483	&& !(val & X86_CR0_PG))
1484	{
1485	msrEFER &= ~MSR_K6_EFER_LMA;
1486	/* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1487	}
1488	CPUMSetGuestEFER(pVCpu, msrEFER);
1489	}
1490	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1491	return rc2 == VINF_SUCCESS ? rc : rc2;
1492
1493	case DISCREG_CR2:
1494	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1495	return VINF_SUCCESS;
1496
1497	case DISCREG_CR3:
1498	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1499	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1500	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1501	{
1502	/* flush */
1503	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1504	AssertRC(rc);
1505	}
1506	return rc;
1507
1508	case DISCREG_CR4:
1509	oldval = CPUMGetGuestCR4(pVCpu);
1510	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1511	val = CPUMGetGuestCR4(pVCpu);
1512
1513	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1514	msrEFER = CPUMGetGuestEFER(pVCpu);
1515	if ( (msrEFER & MSR_K6_EFER_LMA)
1516	&& (oldval & X86_CR4_PAE)
1517	&& !(val & X86_CR4_PAE))
1518	{
1519	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1520	}
1521
1522	rc = VINF_SUCCESS;
1523	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1524	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1525	{
1526	/* global flush */
1527	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1528	AssertRCReturn(rc, rc);
1529	}
1530
1531	/* Feeling extremely lazy. */
1532	# ifdef IN_RC
1533	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1534	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1535	{
1536	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1537	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1538	}
1539	# endif
1540	if ((val ^ oldval) & X86_CR4_VME)
1541	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1542
1543	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1544	return rc2 == VINF_SUCCESS ? rc : rc2;
1545
1546	case DISCREG_CR8:
1547	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1548
1549	default:
1550	AssertFailed();
1551	case DISCREG_CR1: /* illegal op */
1552	break;
1553	}
1554	return VERR_EM_INTERPRETER;
1555	}
1556
1557
1558	/**
1559	* Interpret CRx write.
1560	*
1561	* @returns VBox status code.
1562	* @param pVM Pointer to the VM.
1563	* @param pVCpu Pointer to the VMCPU.
1564	* @param pRegFrame The register frame.
1565	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1566	* @param SrcRegGen General purpose register index (USE_REG_E**))
1567	*
1568	*/
1569	VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1570	{
1571	uint64_t val;
1572	int rc;
1573	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1574
1575	if (CPUMIsGuestIn64BitCode(pVCpu))
1576	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1577	else
1578	{
1579	uint32_t val32;
1580	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1581	val = val32;
1582	}
1583
1584	if (RT_SUCCESS(rc))
1585	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1586
1587	return VERR_EM_INTERPRETER;
1588	}
1589
1590	/**
1591	* Interpret LMSW.
1592	*
1593	* @returns VBox status code.
1594	* @param pVM Pointer to the VM.
1595	* @param pVCpu Pointer to the VMCPU.
1596	* @param pRegFrame The register frame.
1597	* @param u16Data LMSW source data.
1598	*
1599	*/
1600	VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
1601	{
1602	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1603	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
1604
1605	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1606	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1607	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1608
1609	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
1610	}
1611
1612
1613	/**
1614	* Interpret CLTS.
1615	*
1616	* @returns VBox status code.
1617	* @param pVM Pointer to the VM.
1618	* @param pVCpu Pointer to the VMCPU.
1619	*
1620	*/
1621	VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
1622	{
1623	NOREF(pVM);
1624
1625	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
1626	if (!(cr0 & X86_CR0_TS))
1627	return VINF_SUCCESS;
1628	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
1629	}
1630
1631
1632	/**
1633	* Interpret CRx read.
1634	*
1635	* @returns VBox status code.
1636	* @param pVM Pointer to the VM.
1637	* @param pVCpu Pointer to the VMCPU.
1638	* @param pRegFrame The register frame.
1639	* @param DestRegGen General purpose register index (USE_REG_E**))
1640	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1641	*
1642	*/
1643	VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1644	{
1645	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1646	uint64_t val64;
1647	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1648	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1649	NOREF(pVM);
1650
1651	if (CPUMIsGuestIn64BitCode(pVCpu))
1652	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1653	else
1654	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1655
1656	if (RT_SUCCESS(rc))
1657	{
1658	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1659	return VINF_SUCCESS;
1660	}
1661	return VERR_EM_INTERPRETER;
1662	}
1663
1664
1665	/**
1666	* Interpret DRx write.
1667	*
1668	* @returns VBox status code.
1669	* @param pVM Pointer to the VM.
1670	* @param pVCpu Pointer to the VMCPU.
1671	* @param pRegFrame The register frame.
1672	* @param DestRegDRx DRx register index (USE_REG_DR*)
1673	* @param SrcRegGen General purpose register index (USE_REG_E**))
1674	*
1675	*/
1676	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1677	{
1678	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1679	uint64_t val;
1680	int rc;
1681	NOREF(pVM);
1682
1683	if (CPUMIsGuestIn64BitCode(pVCpu))
1684	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1685	else
1686	{
1687	uint32_t val32;
1688	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1689	val = val32;
1690	}
1691
1692	if (RT_SUCCESS(rc))
1693	{
1694	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1695	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, val);
1696	if (RT_SUCCESS(rc))
1697	return rc;
1698	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1699	}
1700	return VERR_EM_INTERPRETER;
1701	}
1702
1703
1704	/**
1705	* Interpret DRx read.
1706	*
1707	* @returns VBox status code.
1708	* @param pVM Pointer to the VM.
1709	* @param pVCpu Pointer to the VMCPU.
1710	* @param pRegFrame The register frame.
1711	* @param DestRegGen General purpose register index (USE_REG_E**))
1712	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1713	*
1714	*/
1715	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1716	{
1717	uint64_t val64;
1718	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1719	NOREF(pVM);
1720
1721	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1722	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1723	if (CPUMIsGuestIn64BitCode(pVCpu))
1724	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1725	else
1726	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1727
1728	if (RT_SUCCESS(rc))
1729	return VINF_SUCCESS;
1730
1731	return VERR_EM_INTERPRETER;
1732	}
1733
1734
1735	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1736
1737
1738
1739
1740
1741
1742	/*
1743	*
1744	* The old interpreter.
1745	* The old interpreter.
1746	* The old interpreter.
1747	* The old interpreter.
1748	* The old interpreter.
1749	*
1750	*/
1751
1752	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1753	{
1754	#ifdef IN_RC
1755	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1756	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1757	return rc;
1758	/*
1759	* The page pool cache may end up here in some cases because it
1760	* flushed one of the shadow mappings used by the trapping
1761	* instruction and it either flushed the TLB or the CPU reused it.
1762	*/
1763	#else
1764	NOREF(pVM);
1765	#endif
1766	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1767	}
1768
1769
1770	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1771	{
1772	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1773	pages or write monitored pages. */
1774	NOREF(pVM);
1775	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1776	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1777	#else
1778	int rc = VINF_SUCCESS;
1779	#endif
1780	#ifdef VBOX_COMPARE_IEM_AND_EM
1781	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1782	g_cbEmWrote = cb;
1783	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1784	#endif
1785	return rc;
1786	}
1787
1788
1789	/** Convert sel:addr to a flat GC address. */
1790	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1791	{
1792	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1793	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1794	}
1795
1796
1797	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1798	/**
1799	* Get the mnemonic for the disassembled instruction.
1800	*
1801	* GC/R0 doesn't include the strings in the DIS tables because
1802	* of limited space.
1803	*/
1804	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1805	{
1806	switch (pDis->pCurInstr->uOpcode)
1807	{
1808	case OP_XCHG: return "Xchg";
1809	case OP_DEC: return "Dec";
1810	case OP_INC: return "Inc";
1811	case OP_POP: return "Pop";
1812	case OP_OR: return "Or";
1813	case OP_AND: return "And";
1814	case OP_MOV: return "Mov";
1815	case OP_INVLPG: return "InvlPg";
1816	case OP_CPUID: return "CpuId";
1817	case OP_MOV_CR: return "MovCRx";
1818	case OP_MOV_DR: return "MovDRx";
1819	case OP_LLDT: return "LLdt";
1820	case OP_LGDT: return "LGdt";
1821	case OP_LIDT: return "LIdt";
1822	case OP_CLTS: return "Clts";
1823	case OP_MONITOR: return "Monitor";
1824	case OP_MWAIT: return "MWait";
1825	case OP_RDMSR: return "Rdmsr";
1826	case OP_WRMSR: return "Wrmsr";
1827	case OP_ADD: return "Add";
1828	case OP_ADC: return "Adc";
1829	case OP_SUB: return "Sub";
1830	case OP_SBB: return "Sbb";
1831	case OP_RDTSC: return "Rdtsc";
1832	case OP_STI: return "Sti";
1833	case OP_CLI: return "Cli";
1834	case OP_XADD: return "XAdd";
1835	case OP_HLT: return "Hlt";
1836	case OP_IRET: return "Iret";
1837	case OP_MOVNTPS: return "MovNTPS";
1838	case OP_STOSWD: return "StosWD";
1839	case OP_WBINVD: return "WbInvd";
1840	case OP_XOR: return "Xor";
1841	case OP_BTR: return "Btr";
1842	case OP_BTS: return "Bts";
1843	case OP_BTC: return "Btc";
1844	case OP_LMSW: return "Lmsw";
1845	case OP_SMSW: return "Smsw";
1846	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1847	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1848
1849	default:
1850	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1851	return "???";
1852	}
1853	}
1854	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1855
1856
1857	/**
1858	* XCHG instruction emulation.
1859	*/
1860	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1861	{
1862	DISQPVPARAMVAL param1, param2;
1863	NOREF(pvFault);
1864
1865	/* Source to make DISQueryParamVal read the register value - ugly hack */
1866	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
1867	if(RT_FAILURE(rc))
1868	return VERR_EM_INTERPRETER;
1869
1870	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
1871	if(RT_FAILURE(rc))
1872	return VERR_EM_INTERPRETER;
1873
1874	#ifdef IN_RC
1875	if (TRPMHasTrap(pVCpu))
1876	{
1877	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1878	{
1879	#endif
1880	RTGCPTR pParam1 = 0, pParam2 = 0;
1881	uint64_t valpar1, valpar2;
1882
1883	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
1884	switch(param1.type)
1885	{
1886	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
1887	valpar1 = param1.val.val64;
1888	break;
1889
1890	case DISQPV_TYPE_ADDRESS:
1891	pParam1 = (RTGCPTR)param1.val.val64;
1892	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
1893	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
1894	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
1895	if (RT_FAILURE(rc))
1896	{
1897	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1898	return VERR_EM_INTERPRETER;
1899	}
1900	break;
1901
1902	default:
1903	AssertFailed();
1904	return VERR_EM_INTERPRETER;
1905	}
1906
1907	switch(param2.type)
1908	{
1909	case DISQPV_TYPE_ADDRESS:
1910	pParam2 = (RTGCPTR)param2.val.val64;
1911	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
1912	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
1913	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
1914	if (RT_FAILURE(rc))
1915	{
1916	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1917	}
1918	break;
1919
1920	case DISQPV_TYPE_IMMEDIATE:
1921	valpar2 = param2.val.val64;
1922	break;
1923
1924	default:
1925	AssertFailed();
1926	return VERR_EM_INTERPRETER;
1927	}
1928
1929	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
1930	if (pParam1 == 0)
1931	{
1932	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
1933	switch(param1.size)
1934	{
1935	case 1: //special case for AH etc
1936	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
1937	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
1938	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
1939	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
1940	default: AssertFailedReturn(VERR_EM_INTERPRETER);
1941	}
1942	if (RT_FAILURE(rc))
1943	return VERR_EM_INTERPRETER;
1944	}
1945	else
1946	{
1947	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
1948	if (RT_FAILURE(rc))
1949	{
1950	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1951	return VERR_EM_INTERPRETER;
1952	}
1953	}
1954
1955	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
1956	if (pParam2 == 0)
1957	{
1958	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
1959	switch(param2.size)
1960	{
1961	case 1: //special case for AH etc
1962	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
1963	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
1964	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
1965	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
1966	default: AssertFailedReturn(VERR_EM_INTERPRETER);
1967	}
1968	if (RT_FAILURE(rc))
1969	return VERR_EM_INTERPRETER;
1970	}
1971	else
1972	{
1973	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
1974	if (RT_FAILURE(rc))
1975	{
1976	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1977	return VERR_EM_INTERPRETER;
1978	}
1979	}
1980
1981	*pcbSize = param2.size;
1982	return VINF_SUCCESS;
1983	#ifdef IN_RC
1984	}
1985	}
1986	return VERR_EM_INTERPRETER;
1987	#endif
1988	}
1989
1990
1991	/**
1992	* INC and DEC emulation.
1993	*/
1994	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1995	PFNEMULATEPARAM2 pfnEmulate)
1996	{
1997	DISQPVPARAMVAL param1;
1998	NOREF(pvFault);
1999
2000	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2001	if(RT_FAILURE(rc))
2002	return VERR_EM_INTERPRETER;
2003
2004	#ifdef IN_RC
2005	if (TRPMHasTrap(pVCpu))
2006	{
2007	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2008	{
2009	#endif
2010	RTGCPTR pParam1 = 0;
2011	uint64_t valpar1;
2012
2013	if (param1.type == DISQPV_TYPE_ADDRESS)
2014	{
2015	pParam1 = (RTGCPTR)param1.val.val64;
2016	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2017	#ifdef IN_RC
2018	/* Safety check (in theory it could cross a page boundary and fault there though) */
2019	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2020	#endif
2021	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2022	if (RT_FAILURE(rc))
2023	{
2024	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2025	return VERR_EM_INTERPRETER;
2026	}
2027	}
2028	else
2029	{
2030	AssertFailed();
2031	return VERR_EM_INTERPRETER;
2032	}
2033
2034	uint32_t eflags;
2035
2036	eflags = pfnEmulate(&valpar1, param1.size);
2037
2038	/* Write result back */
2039	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2040	if (RT_FAILURE(rc))
2041	{
2042	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2043	return VERR_EM_INTERPRETER;
2044	}
2045
2046	/* Update guest's eflags and finish. */
2047	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2048	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2049
2050	/* All done! */
2051	*pcbSize = param1.size;
2052	return VINF_SUCCESS;
2053	#ifdef IN_RC
2054	}
2055	}
2056	return VERR_EM_INTERPRETER;
2057	#endif
2058	}
2059
2060
2061	/**
2062	* POP Emulation.
2063	*/
2064	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2065	{
2066	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2067	DISQPVPARAMVAL param1;
2068	NOREF(pvFault);
2069
2070	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2071	if(RT_FAILURE(rc))
2072	return VERR_EM_INTERPRETER;
2073
2074	#ifdef IN_RC
2075	if (TRPMHasTrap(pVCpu))
2076	{
2077	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2078	{
2079	#endif
2080	RTGCPTR pParam1 = 0;
2081	uint32_t valpar1;
2082	RTGCPTR pStackVal;
2083
2084	/* Read stack value first */
2085	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2086	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2087
2088	/* Convert address; don't bother checking limits etc, as we only read here */
2089	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2090	if (pStackVal == 0)
2091	return VERR_EM_INTERPRETER;
2092
2093	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2094	if (RT_FAILURE(rc))
2095	{
2096	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2097	return VERR_EM_INTERPRETER;
2098	}
2099
2100	if (param1.type == DISQPV_TYPE_ADDRESS)
2101	{
2102	pParam1 = (RTGCPTR)param1.val.val64;
2103
2104	/* pop [esp+xx] uses esp after the actual pop! */
2105	AssertCompile(DISGREG_ESP == DISGREG_SP);
2106	if ( (pDis->Param1.fUse & DISUSE_BASE)
2107	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2108	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2109	)
2110	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2111
2112	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2113	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2114	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2115	if (RT_FAILURE(rc))
2116	{
2117	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2118	return VERR_EM_INTERPRETER;
2119	}
2120
2121	/* Update ESP as the last step */
2122	pRegFrame->esp += param1.size;
2123	}
2124	else
2125	{
2126	#ifndef DEBUG_bird // annoying assertion.
2127	AssertFailed();
2128	#endif
2129	return VERR_EM_INTERPRETER;
2130	}
2131
2132	/* All done! */
2133	*pcbSize = param1.size;
2134	return VINF_SUCCESS;
2135	#ifdef IN_RC
2136	}
2137	}
2138	return VERR_EM_INTERPRETER;
2139	#endif
2140	}
2141
2142
2143	/**
2144	* XOR/OR/AND Emulation.
2145	*/
2146	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2147	PFNEMULATEPARAM3 pfnEmulate)
2148	{
2149	DISQPVPARAMVAL param1, param2;
2150	NOREF(pvFault);
2151
2152	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2153	if(RT_FAILURE(rc))
2154	return VERR_EM_INTERPRETER;
2155
2156	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2157	if(RT_FAILURE(rc))
2158	return VERR_EM_INTERPRETER;
2159
2160	#ifdef IN_RC
2161	if (TRPMHasTrap(pVCpu))
2162	{
2163	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2164	{
2165	#endif
2166	RTGCPTR pParam1;
2167	uint64_t valpar1, valpar2;
2168
2169	if (pDis->Param1.cb != pDis->Param2.cb)
2170	{
2171	if (pDis->Param1.cb < pDis->Param2.cb)
2172	{
2173	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2174	return VERR_EM_INTERPRETER;
2175	}
2176	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2177	pDis->Param2.cb = pDis->Param1.cb;
2178	param2.size = param1.size;
2179	}
2180
2181	/* The destination is always a virtual address */
2182	if (param1.type == DISQPV_TYPE_ADDRESS)
2183	{
2184	pParam1 = (RTGCPTR)param1.val.val64;
2185	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2186	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2187	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2188	if (RT_FAILURE(rc))
2189	{
2190	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2191	return VERR_EM_INTERPRETER;
2192	}
2193	}
2194	else
2195	{
2196	AssertFailed();
2197	return VERR_EM_INTERPRETER;
2198	}
2199
2200	/* Register or immediate data */
2201	switch(param2.type)
2202	{
2203	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2204	valpar2 = param2.val.val64;
2205	break;
2206
2207	default:
2208	AssertFailed();
2209	return VERR_EM_INTERPRETER;
2210	}
2211
2212	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2213
2214	/* Data read, emulate instruction. */
2215	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2216
2217	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2218
2219	/* Update guest's eflags and finish. */
2220	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2221	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2222
2223	/* And write it back */
2224	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2225	if (RT_SUCCESS(rc))
2226	{
2227	/* All done! */
2228	*pcbSize = param2.size;
2229	return VINF_SUCCESS;
2230	}
2231	#ifdef IN_RC
2232	}
2233	}
2234	#endif
2235	return VERR_EM_INTERPRETER;
2236	}
2237
2238
2239	#ifndef VBOX_COMPARE_IEM_AND_EM
2240	/**
2241	* LOCK XOR/OR/AND Emulation.
2242	*/
2243	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2244	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2245	{
2246	void *pvParam1;
2247	DISQPVPARAMVAL param1, param2;
2248	NOREF(pvFault);
2249
2250	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2251	Assert(pDis->Param1.cb <= 4);
2252	#endif
2253
2254	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2255	if(RT_FAILURE(rc))
2256	return VERR_EM_INTERPRETER;
2257
2258	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2259	if(RT_FAILURE(rc))
2260	return VERR_EM_INTERPRETER;
2261
2262	if (pDis->Param1.cb != pDis->Param2.cb)
2263	{
2264	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2265	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2266	VERR_EM_INTERPRETER);
2267
2268	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2269	pDis->Param2.cb = pDis->Param1.cb;
2270	param2.size = param1.size;
2271	}
2272
2273	#ifdef IN_RC
2274	/* Safety check (in theory it could cross a page boundary and fault there though) */
2275	Assert( TRPMHasTrap(pVCpu)
2276	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2277	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2278	#endif
2279
2280	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2281	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2282	RTGCUINTREG ValPar2 = param2.val.val64;
2283
2284	/* The destination is always a virtual address */
2285	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2286
2287	RTGCPTR GCPtrPar1 = param1.val.val64;
2288	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2289	PGMPAGEMAPLOCK Lock;
2290	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2291	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2292
2293	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2294	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2295
2296	RTGCUINTREG32 eflags = 0;
2297	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2298	PGMPhysReleasePageMappingLock(pVM, &Lock);
2299	if (RT_FAILURE(rc))
2300	{
2301	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2302	return VERR_EM_INTERPRETER;
2303	}
2304
2305	/* Update guest's eflags and finish. */
2306	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2307	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2308
2309	*pcbSize = param2.size;
2310	return VINF_SUCCESS;
2311	}
2312	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2313
2314
2315	/**
2316	* ADD, ADC & SUB Emulation.
2317	*/
2318	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2319	PFNEMULATEPARAM3 pfnEmulate)
2320	{
2321	NOREF(pvFault);
2322	DISQPVPARAMVAL param1, param2;
2323	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2324	if(RT_FAILURE(rc))
2325	return VERR_EM_INTERPRETER;
2326
2327	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2328	if(RT_FAILURE(rc))
2329	return VERR_EM_INTERPRETER;
2330
2331	#ifdef IN_RC
2332	if (TRPMHasTrap(pVCpu))
2333	{
2334	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2335	{
2336	#endif
2337	RTGCPTR pParam1;
2338	uint64_t valpar1, valpar2;
2339
2340	if (pDis->Param1.cb != pDis->Param2.cb)
2341	{
2342	if (pDis->Param1.cb < pDis->Param2.cb)
2343	{
2344	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2345	return VERR_EM_INTERPRETER;
2346	}
2347	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2348	pDis->Param2.cb = pDis->Param1.cb;
2349	param2.size = param1.size;
2350	}
2351
2352	/* The destination is always a virtual address */
2353	if (param1.type == DISQPV_TYPE_ADDRESS)
2354	{
2355	pParam1 = (RTGCPTR)param1.val.val64;
2356	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2357	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2358	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2359	if (RT_FAILURE(rc))
2360	{
2361	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2362	return VERR_EM_INTERPRETER;
2363	}
2364	}
2365	else
2366	{
2367	#ifndef DEBUG_bird
2368	AssertFailed();
2369	#endif
2370	return VERR_EM_INTERPRETER;
2371	}
2372
2373	/* Register or immediate data */
2374	switch(param2.type)
2375	{
2376	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2377	valpar2 = param2.val.val64;
2378	break;
2379
2380	default:
2381	AssertFailed();
2382	return VERR_EM_INTERPRETER;
2383	}
2384
2385	/* Data read, emulate instruction. */
2386	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2387
2388	/* Update guest's eflags and finish. */
2389	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2390	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2391
2392	/* And write it back */
2393	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2394	if (RT_SUCCESS(rc))
2395	{
2396	/* All done! */
2397	*pcbSize = param2.size;
2398	return VINF_SUCCESS;
2399	}
2400	#ifdef IN_RC
2401	}
2402	}
2403	#endif
2404	return VERR_EM_INTERPRETER;
2405	}
2406
2407
2408	/**
2409	* ADC Emulation.
2410	*/
2411	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2412	{
2413	if (pRegFrame->eflags.Bits.u1CF)
2414	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2415	else
2416	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2417	}
2418
2419
2420	/**
2421	* BTR/C/S Emulation.
2422	*/
2423	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2424	PFNEMULATEPARAM2UINT32 pfnEmulate)
2425	{
2426	DISQPVPARAMVAL param1, param2;
2427	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2428	if(RT_FAILURE(rc))
2429	return VERR_EM_INTERPRETER;
2430
2431	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2432	if(RT_FAILURE(rc))
2433	return VERR_EM_INTERPRETER;
2434
2435	#ifdef IN_RC
2436	if (TRPMHasTrap(pVCpu))
2437	{
2438	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2439	{
2440	#endif
2441	RTGCPTR pParam1;
2442	uint64_t valpar1 = 0, valpar2;
2443	uint32_t eflags;
2444
2445	/* The destination is always a virtual address */
2446	if (param1.type != DISQPV_TYPE_ADDRESS)
2447	return VERR_EM_INTERPRETER;
2448
2449	pParam1 = (RTGCPTR)param1.val.val64;
2450	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2451
2452	/* Register or immediate data */
2453	switch(param2.type)
2454	{
2455	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2456	valpar2 = param2.val.val64;
2457	break;
2458
2459	default:
2460	AssertFailed();
2461	return VERR_EM_INTERPRETER;
2462	}
2463
2464	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2465	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2466	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
2467	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2468	if (RT_FAILURE(rc))
2469	{
2470	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2471	return VERR_EM_INTERPRETER;
2472	}
2473
2474	Log2(("emInterpretBtx: val=%x\n", valpar1));
2475	/* Data read, emulate bit test instruction. */
2476	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2477
2478	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2479
2480	/* Update guest's eflags and finish. */
2481	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2482	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2483
2484	/* And write it back */
2485	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2486	if (RT_SUCCESS(rc))
2487	{
2488	/* All done! */
2489	*pcbSize = 1;
2490	return VINF_SUCCESS;
2491	}
2492	#ifdef IN_RC
2493	}
2494	}
2495	#endif
2496	return VERR_EM_INTERPRETER;
2497	}
2498
2499
2500	#ifndef VBOX_COMPARE_IEM_AND_EM
2501	/**
2502	* LOCK BTR/C/S Emulation.
2503	*/
2504	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2505	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2506	{
2507	void *pvParam1;
2508
2509	DISQPVPARAMVAL param1, param2;
2510	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2511	if(RT_FAILURE(rc))
2512	return VERR_EM_INTERPRETER;
2513
2514	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2515	if(RT_FAILURE(rc))
2516	return VERR_EM_INTERPRETER;
2517
2518	/* The destination is always a virtual address */
2519	if (param1.type != DISQPV_TYPE_ADDRESS)
2520	return VERR_EM_INTERPRETER;
2521
2522	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2523	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2524	uint64_t ValPar2 = param2.val.val64;
2525
2526	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2527	RTGCPTR GCPtrPar1 = param1.val.val64;
2528	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2529	ValPar2 &= 7;
2530
2531	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2532	#ifdef IN_RC
2533	Assert(TRPMHasTrap(pVCpu));
2534	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2535	#endif
2536
2537	PGMPAGEMAPLOCK Lock;
2538	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2539	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2540
2541	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2542
2543	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2544	RTGCUINTREG32 eflags = 0;
2545	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2546	PGMPhysReleasePageMappingLock(pVM, &Lock);
2547	if (RT_FAILURE(rc))
2548	{
2549	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2550	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2551	return VERR_EM_INTERPRETER;
2552	}
2553
2554	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2555
2556	/* Update guest's eflags and finish. */
2557	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2558	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2559
2560	*pcbSize = 1;
2561	return VINF_SUCCESS;
2562	}
2563	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2564
2565
2566	/**
2567	* MOV emulation.
2568	*/
2569	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2570	{
2571	NOREF(pvFault);
2572	DISQPVPARAMVAL param1, param2;
2573	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2574	if(RT_FAILURE(rc))
2575	return VERR_EM_INTERPRETER;
2576
2577	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2578	if(RT_FAILURE(rc))
2579	return VERR_EM_INTERPRETER;
2580
2581	if (param1.type == DISQPV_TYPE_ADDRESS)
2582	{
2583	RTGCPTR pDest;
2584	uint64_t val64;
2585
2586	switch(param1.type)
2587	{
2588	case DISQPV_TYPE_IMMEDIATE:
2589	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2590	return VERR_EM_INTERPRETER;
2591	/* fallthru */
2592
2593	case DISQPV_TYPE_ADDRESS:
2594	pDest = (RTGCPTR)param1.val.val64;
2595	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2596	break;
2597
2598	default:
2599	AssertFailed();
2600	return VERR_EM_INTERPRETER;
2601	}
2602
2603	switch(param2.type)
2604	{
2605	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2606	val64 = param2.val.val64;
2607	break;
2608
2609	default:
2610	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2611	return VERR_EM_INTERPRETER;
2612	}
2613	#ifdef LOG_ENABLED
2614	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2615	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2616	else
2617	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2618	#endif
2619
2620	Assert(param2.size <= 8 && param2.size > 0);
2621	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2622	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2623	if (RT_FAILURE(rc))
2624	return VERR_EM_INTERPRETER;
2625
2626	*pcbSize = param2.size;
2627	}
2628	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2629	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2630	else if ( param1.type == DISQPV_TYPE_REGISTER
2631	&& param2.type == DISQPV_TYPE_REGISTER)
2632	{
2633	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2634	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2635	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2636
2637	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2638	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2639
2640	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2641	switch (param1.size)
2642	{
2643	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2644	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2645	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2646	default:
2647	AssertFailed();
2648	return VERR_EM_INTERPRETER;
2649	}
2650	AssertRCReturn(rc, rc);
2651	}
2652	#endif
2653	else
2654	{ /* read fault */
2655	RTGCPTR pSrc;
2656	uint64_t val64;
2657
2658	/* Source */
2659	switch(param2.type)
2660	{
2661	case DISQPV_TYPE_IMMEDIATE:
2662	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2663	return VERR_EM_INTERPRETER;
2664	/* fallthru */
2665
2666	case DISQPV_TYPE_ADDRESS:
2667	pSrc = (RTGCPTR)param2.val.val64;
2668	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2669	break;
2670
2671	default:
2672	return VERR_EM_INTERPRETER;
2673	}
2674
2675	Assert(param1.size <= 8 && param1.size > 0);
2676	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2677	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2678	if (RT_FAILURE(rc))
2679	return VERR_EM_INTERPRETER;
2680
2681	/* Destination */
2682	switch(param1.type)
2683	{
2684	case DISQPV_TYPE_REGISTER:
2685	switch(param1.size)
2686	{
2687	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2688	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2689	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2690	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2691	default:
2692	return VERR_EM_INTERPRETER;
2693	}
2694	if (RT_FAILURE(rc))
2695	return rc;
2696	break;
2697
2698	default:
2699	return VERR_EM_INTERPRETER;
2700	}
2701	#ifdef LOG_ENABLED
2702	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2703	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2704	else
2705	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2706	#endif
2707	}
2708	return VINF_SUCCESS;
2709	}
2710
2711
2712	#ifndef IN_RC
2713	/**
2714	* [REP] STOSWD emulation
2715	*/
2716	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2717	{
2718	int rc;
2719	RTGCPTR GCDest, GCOffset;
2720	uint32_t cbSize;
2721	uint64_t cTransfers;
2722	int offIncrement;
2723	NOREF(pvFault);
2724
2725	/* Don't support any but these three prefix bytes. */
2726	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2727	return VERR_EM_INTERPRETER;
2728
2729	switch (pDis->uAddrMode)
2730	{
2731	case DISCPUMODE_16BIT:
2732	GCOffset = pRegFrame->di;
2733	cTransfers = pRegFrame->cx;
2734	break;
2735	case DISCPUMODE_32BIT:
2736	GCOffset = pRegFrame->edi;
2737	cTransfers = pRegFrame->ecx;
2738	break;
2739	case DISCPUMODE_64BIT:
2740	GCOffset = pRegFrame->rdi;
2741	cTransfers = pRegFrame->rcx;
2742	break;
2743	default:
2744	AssertFailed();
2745	return VERR_EM_INTERPRETER;
2746	}
2747
2748	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2749	switch (pDis->uOpMode)
2750	{
2751	case DISCPUMODE_16BIT:
2752	cbSize = 2;
2753	break;
2754	case DISCPUMODE_32BIT:
2755	cbSize = 4;
2756	break;
2757	case DISCPUMODE_64BIT:
2758	cbSize = 8;
2759	break;
2760	default:
2761	AssertFailed();
2762	return VERR_EM_INTERPRETER;
2763	}
2764
2765	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2766
2767	if (!(pDis->fPrefix & DISPREFIX_REP))
2768	{
2769	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2770
2771	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2772	if (RT_FAILURE(rc))
2773	return VERR_EM_INTERPRETER;
2774	Assert(rc == VINF_SUCCESS);
2775
2776	/* Update (e/r)di. */
2777	switch (pDis->uAddrMode)
2778	{
2779	case DISCPUMODE_16BIT:
2780	pRegFrame->di += offIncrement;
2781	break;
2782	case DISCPUMODE_32BIT:
2783	pRegFrame->edi += offIncrement;
2784	break;
2785	case DISCPUMODE_64BIT:
2786	pRegFrame->rdi += offIncrement;
2787	break;
2788	default:
2789	AssertFailed();
2790	return VERR_EM_INTERPRETER;
2791	}
2792
2793	}
2794	else
2795	{
2796	if (!cTransfers)
2797	return VINF_SUCCESS;
2798
2799	/*
2800	* Do not try emulate cross page stuff here because we don't know what might
2801	* be waiting for us on the subsequent pages. The caller has only asked us to
2802	* ignore access handlers fro the current page.
2803	* This also fends off big stores which would quickly kill PGMR0DynMap.
2804	*/
2805	if ( cbSize > PAGE_SIZE
2806	\|\| cTransfers > PAGE_SIZE
2807	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2808	{
2809	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2810	GCDest, cbSize, offIncrement, cTransfers));
2811	return VERR_EM_INTERPRETER;
2812	}
2813
2814	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2815	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2816	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2817	cTransfers * cbSize,
2818	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2819	if (rc != VINF_SUCCESS)
2820	{
2821	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2822	return VERR_EM_INTERPRETER;
2823	}
2824
2825	/* REP case */
2826	while (cTransfers)
2827	{
2828	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2829	if (RT_FAILURE(rc))
2830	{
2831	rc = VERR_EM_INTERPRETER;
2832	break;
2833	}
2834
2835	Assert(rc == VINF_SUCCESS);
2836	GCOffset += offIncrement;
2837	GCDest += offIncrement;
2838	cTransfers--;
2839	}
2840
2841	/* Update the registers. */
2842	switch (pDis->uAddrMode)
2843	{
2844	case DISCPUMODE_16BIT:
2845	pRegFrame->di = GCOffset;
2846	pRegFrame->cx = cTransfers;
2847	break;
2848	case DISCPUMODE_32BIT:
2849	pRegFrame->edi = GCOffset;
2850	pRegFrame->ecx = cTransfers;
2851	break;
2852	case DISCPUMODE_64BIT:
2853	pRegFrame->rdi = GCOffset;
2854	pRegFrame->rcx = cTransfers;
2855	break;
2856	default:
2857	AssertFailed();
2858	return VERR_EM_INTERPRETER;
2859	}
2860	}
2861
2862	*pcbSize = cbSize;
2863	return rc;
2864	}
2865	#endif /* !IN_RC */
2866
2867
2868	/**
2869	* [LOCK] CMPXCHG emulation.
2870	*/
2871	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2872	{
2873	DISQPVPARAMVAL param1, param2;
2874	NOREF(pvFault);
2875
2876	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2877	Assert(pDis->Param1.cb <= 4);
2878	#endif
2879
2880	/* Source to make DISQueryParamVal read the register value - ugly hack */
2881	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2882	if(RT_FAILURE(rc))
2883	return VERR_EM_INTERPRETER;
2884
2885	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2886	if(RT_FAILURE(rc))
2887	return VERR_EM_INTERPRETER;
2888
2889	uint64_t valpar;
2890	switch(param2.type)
2891	{
2892	case DISQPV_TYPE_IMMEDIATE: /* register actually */
2893	valpar = param2.val.val64;
2894	break;
2895
2896	default:
2897	return VERR_EM_INTERPRETER;
2898	}
2899
2900	PGMPAGEMAPLOCK Lock;
2901	RTGCPTR GCPtrPar1;
2902	void *pvParam1;
2903	uint64_t eflags;
2904
2905	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2906	switch(param1.type)
2907	{
2908	case DISQPV_TYPE_ADDRESS:
2909	GCPtrPar1 = param1.val.val64;
2910	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2911
2912	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2913	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2914	break;
2915
2916	default:
2917	return VERR_EM_INTERPRETER;
2918	}
2919
2920	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
2921
2922	#ifndef VBOX_COMPARE_IEM_AND_EM
2923	if (pDis->fPrefix & DISPREFIX_LOCK)
2924	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
2925	else
2926	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
2927	#else /* VBOX_COMPARE_IEM_AND_EM */
2928	uint64_t u64;
2929	switch (pDis->Param2.cb)
2930	{
2931	case 1: u64 = (uint8_t )pvParam1; break;
2932	case 2: u64 = (uint16_t )pvParam1; break;
2933	case 4: u64 = (uint32_t )pvParam1; break;
2934	default:
2935	case 8: u64 = (uint64_t )pvParam1; break;
2936	}
2937	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
2938	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
2939	#endif /* VBOX_COMPARE_IEM_AND_EM */
2940
2941	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
2942
2943	/* Update guest's eflags and finish. */
2944	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2945	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2946
2947	*pcbSize = param2.size;
2948	PGMPhysReleasePageMappingLock(pVM, &Lock);
2949	return VINF_SUCCESS;
2950	}
2951
2952
2953	/**
2954	* [LOCK] CMPXCHG8B emulation.
2955	*/
2956	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2957	{
2958	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2959	DISQPVPARAMVAL param1;
2960	NOREF(pvFault);
2961
2962	/* Source to make DISQueryParamVal read the register value - ugly hack */
2963	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2964	if(RT_FAILURE(rc))
2965	return VERR_EM_INTERPRETER;
2966
2967	RTGCPTR GCPtrPar1;
2968	void *pvParam1;
2969	uint64_t eflags;
2970	PGMPAGEMAPLOCK Lock;
2971
2972	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
2973	switch(param1.type)
2974	{
2975	case DISQPV_TYPE_ADDRESS:
2976	GCPtrPar1 = param1.val.val64;
2977	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2978
2979	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2980	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2981	break;
2982
2983	default:
2984	return VERR_EM_INTERPRETER;
2985	}
2986
2987	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
2988
2989	#ifndef VBOX_COMPARE_IEM_AND_EM
2990	if (pDis->fPrefix & DISPREFIX_LOCK)
2991	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2992	else
2993	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2994	#else /* VBOX_COMPARE_IEM_AND_EM */
2995	uint64_t u64 = (uint64_t )pvParam1;
2996	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2997	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
2998	#endif /* VBOX_COMPARE_IEM_AND_EM */
2999
3000	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3001
3002	/* Update guest's eflags and finish; note that only ZF is affected. */
3003	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3004	\| (eflags & (X86_EFL_ZF));
3005
3006	*pcbSize = 8;
3007	PGMPhysReleasePageMappingLock(pVM, &Lock);
3008	return VINF_SUCCESS;
3009	}
3010
3011
3012	#ifdef IN_RC /** @todo test+enable for HM as well. */
3013	/**
3014	* [LOCK] XADD emulation.
3015	*/
3016	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3017	{
3018	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3019	DISQPVPARAMVAL param1;
3020	void *pvParamReg2;
3021	size_t cbParamReg2;
3022	NOREF(pvFault);
3023
3024	/* Source to make DISQueryParamVal read the register value - ugly hack */
3025	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3026	if(RT_FAILURE(rc))
3027	return VERR_EM_INTERPRETER;
3028
3029	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3030	Assert(cbParamReg2 <= 4);
3031	if(RT_FAILURE(rc))
3032	return VERR_EM_INTERPRETER;
3033
3034	#ifdef IN_RC
3035	if (TRPMHasTrap(pVCpu))
3036	{
3037	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3038	{
3039	#endif
3040	RTGCPTR GCPtrPar1;
3041	void *pvParam1;
3042	uint32_t eflags;
3043	PGMPAGEMAPLOCK Lock;
3044
3045	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3046	switch(param1.type)
3047	{
3048	case DISQPV_TYPE_ADDRESS:
3049	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3050	#ifdef IN_RC
3051	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3052	#endif
3053
3054	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3055	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3056	break;
3057
3058	default:
3059	return VERR_EM_INTERPRETER;
3060	}
3061
3062	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3063
3064	#ifndef VBOX_COMPARE_IEM_AND_EM
3065	if (pDis->fPrefix & DISPREFIX_LOCK)
3066	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3067	else
3068	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3069	#else /* VBOX_COMPARE_IEM_AND_EM */
3070	uint64_t u64;
3071	switch (cbParamReg2)
3072	{
3073	case 1: u64 = (uint8_t )pvParam1; break;
3074	case 2: u64 = (uint16_t )pvParam1; break;
3075	case 4: u64 = (uint32_t )pvParam1; break;
3076	default:
3077	case 8: u64 = (uint64_t )pvParam1; break;
3078	}
3079	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3080	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3081	#endif /* VBOX_COMPARE_IEM_AND_EM */
3082
3083	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3084
3085	/* Update guest's eflags and finish. */
3086	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3087	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3088
3089	*pcbSize = cbParamReg2;
3090	PGMPhysReleasePageMappingLock(pVM, &Lock);
3091	return VINF_SUCCESS;
3092	#ifdef IN_RC
3093	}
3094	}
3095
3096	return VERR_EM_INTERPRETER;
3097	#endif
3098	}
3099	#endif /* IN_RC */
3100
3101
3102	/**
3103	* WBINVD Emulation.
3104	*/
3105	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3106	{
3107	/* Nothing to do. */
3108	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3109	return VINF_SUCCESS;
3110	}
3111
3112
3113	/**
3114	* INVLPG Emulation.
3115	*/
3116	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3117	{
3118	DISQPVPARAMVAL param1;
3119	RTGCPTR addr;
3120	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3121
3122	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3123	if(RT_FAILURE(rc))
3124	return VERR_EM_INTERPRETER;
3125
3126	switch(param1.type)
3127	{
3128	case DISQPV_TYPE_IMMEDIATE:
3129	case DISQPV_TYPE_ADDRESS:
3130	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3131	return VERR_EM_INTERPRETER;
3132	addr = (RTGCPTR)param1.val.val64;
3133	break;
3134
3135	default:
3136	return VERR_EM_INTERPRETER;
3137	}
3138
3139	/** @todo is addr always a flat linear address or ds based
3140	* (in absence of segment override prefixes)????
3141	*/
3142	#ifdef IN_RC
3143	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3144	#endif
3145	rc = PGMInvalidatePage(pVCpu, addr);
3146	if ( rc == VINF_SUCCESS
3147	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3148	return VINF_SUCCESS;
3149	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3150	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3151	VERR_EM_INTERPRETER);
3152	return rc;
3153	}
3154
3155	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3156
3157	/**
3158	* CPUID Emulation.
3159	*/
3160	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3161	{
3162	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3163	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3164	return rc;
3165	}
3166
3167
3168	/**
3169	* CLTS Emulation.
3170	*/
3171	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3172	{
3173	NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3174	return EMInterpretCLTS(pVM, pVCpu);
3175	}
3176
3177
3178	/**
3179	* LMSW Emulation.
3180	*/
3181	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3182	{
3183	DISQPVPARAMVAL param1;
3184	uint32_t val;
3185	NOREF(pvFault); NOREF(pcbSize);
3186
3187	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3188	if(RT_FAILURE(rc))
3189	return VERR_EM_INTERPRETER;
3190
3191	switch(param1.type)
3192	{
3193	case DISQPV_TYPE_IMMEDIATE:
3194	case DISQPV_TYPE_ADDRESS:
3195	if(!(param1.flags & DISQPV_FLAG_16))
3196	return VERR_EM_INTERPRETER;
3197	val = param1.val.val32;
3198	break;
3199
3200	default:
3201	return VERR_EM_INTERPRETER;
3202	}
3203
3204	LogFlow(("emInterpretLmsw %x\n", val));
3205	return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
3206	}
3207
3208	#ifdef EM_EMULATE_SMSW
3209	/**
3210	* SMSW Emulation.
3211	*/
3212	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3213	{
3214	DISQPVPARAMVAL param1;
3215	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3216
3217	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3218	if(RT_FAILURE(rc))
3219	return VERR_EM_INTERPRETER;
3220
3221	switch(param1.type)
3222	{
3223	case DISQPV_TYPE_IMMEDIATE:
3224	if(param1.size != sizeof(uint16_t))
3225	return VERR_EM_INTERPRETER;
3226	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3227	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3228	break;
3229
3230	case DISQPV_TYPE_ADDRESS:
3231	{
3232	RTGCPTR pParam1;
3233
3234	/* Actually forced to 16 bits regardless of the operand size. */
3235	if(param1.size != sizeof(uint16_t))
3236	return VERR_EM_INTERPRETER;
3237
3238	pParam1 = (RTGCPTR)param1.val.val64;
3239	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3240	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3241
3242	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3243	if (RT_FAILURE(rc))
3244	{
3245	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3246	return VERR_EM_INTERPRETER;
3247	}
3248	break;
3249	}
3250
3251	default:
3252	return VERR_EM_INTERPRETER;
3253	}
3254
3255	LogFlow(("emInterpretSmsw %x\n", cr0));
3256	return rc;
3257	}
3258	#endif
3259
3260	/**
3261	* MOV CRx
3262	*/
3263	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3264	{
3265	NOREF(pvFault); NOREF(pcbSize);
3266	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3267	return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3268
3269	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3270	return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3271
3272	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3273	}
3274
3275
3276	/**
3277	* MOV DRx
3278	*/
3279	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3280	{
3281	int rc = VERR_EM_INTERPRETER;
3282	NOREF(pvFault); NOREF(pcbSize);
3283
3284	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3285	{
3286	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3287	}
3288	else
3289	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3290	{
3291	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3292	}
3293	else
3294	AssertMsgFailed(("Unexpected debug register move\n"));
3295
3296	return rc;
3297	}
3298
3299
3300	/**
3301	* LLDT Emulation.
3302	*/
3303	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3304	{
3305	DISQPVPARAMVAL param1;
3306	RTSEL sel;
3307	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3308
3309	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3310	if(RT_FAILURE(rc))
3311	return VERR_EM_INTERPRETER;
3312
3313	switch(param1.type)
3314	{
3315	case DISQPV_TYPE_ADDRESS:
3316	return VERR_EM_INTERPRETER; //feeling lazy right now
3317
3318	case DISQPV_TYPE_IMMEDIATE:
3319	if(!(param1.flags & DISQPV_FLAG_16))
3320	return VERR_EM_INTERPRETER;
3321	sel = (RTSEL)param1.val.val16;
3322	break;
3323
3324	default:
3325	return VERR_EM_INTERPRETER;
3326	}
3327
3328	#ifdef IN_RING0
3329	/* Only for the VT-x real-mode emulation case. */
3330	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3331	CPUMSetGuestLDTR(pVCpu, sel);
3332	return VINF_SUCCESS;
3333	#else
3334	if (sel == 0)
3335	{
3336	if (CPUMGetHyperLDTR(pVCpu) == 0)
3337	{
3338	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3339	return VINF_SUCCESS;
3340	}
3341	}
3342	//still feeling lazy
3343	return VERR_EM_INTERPRETER;
3344	#endif
3345	}
3346
3347	#ifdef IN_RING0
3348	/**
3349	* LIDT/LGDT Emulation.
3350	*/
3351	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3352	{
3353	DISQPVPARAMVAL param1;
3354	RTGCPTR pParam1;
3355	X86XDTR32 dtr32;
3356	NOREF(pvFault); NOREF(pcbSize);
3357
3358	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3359
3360	/* Only for the VT-x real-mode emulation case. */
3361	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3362
3363	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3364	if(RT_FAILURE(rc))
3365	return VERR_EM_INTERPRETER;
3366
3367	switch(param1.type)
3368	{
3369	case DISQPV_TYPE_ADDRESS:
3370	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3371	break;
3372
3373	default:
3374	return VERR_EM_INTERPRETER;
3375	}
3376
3377	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3378	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3379
3380	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3381	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3382
3383	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3384	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3385	else
3386	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3387
3388	return VINF_SUCCESS;
3389	}
3390	#endif
3391
3392
3393	#ifdef IN_RC
3394	/**
3395	* STI Emulation.
3396	*
3397	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3398	*/
3399	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3400	{
3401	NOREF(pcbSize);
3402	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
3403
3404	if(!pGCState)
3405	{
3406	Assert(pGCState);
3407	return VERR_EM_INTERPRETER;
3408	}
3409	pGCState->uVMFlags \|= X86_EFL_IF;
3410
3411	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3412	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3413
3414	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3415	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3416
3417	return VINF_SUCCESS;
3418	}
3419	#endif /* IN_RC */
3420
3421
3422	/**
3423	* HLT Emulation.
3424	*/
3425	static VBOXSTRICTRC
3426	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3427	{
3428	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3429	return VINF_EM_HALT;
3430	}
3431
3432
3433	/**
3434	* RDTSC Emulation.
3435	*/
3436	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3437	{
3438	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3439	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3440	}
3441
3442	/**
3443	* RDPMC Emulation
3444	*/
3445	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3446	{
3447	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3448	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3449	}
3450
3451
3452	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3453	{
3454	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3455	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3456	}
3457
3458
3459	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3460	{
3461	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3462	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3463	}
3464
3465
3466	#ifdef LOG_ENABLED
3467	static const char *emMSRtoString(uint32_t uMsr)
3468	{
3469	switch (uMsr)
3470	{
3471	case MSR_IA32_APICBASE:
3472	return "MSR_IA32_APICBASE";
3473	case MSR_IA32_CR_PAT:
3474	return "MSR_IA32_CR_PAT";
3475	case MSR_IA32_SYSENTER_CS:
3476	return "MSR_IA32_SYSENTER_CS";
3477	case MSR_IA32_SYSENTER_EIP:
3478	return "MSR_IA32_SYSENTER_EIP";
3479	case MSR_IA32_SYSENTER_ESP:
3480	return "MSR_IA32_SYSENTER_ESP";
3481	case MSR_K6_EFER:
3482	return "MSR_K6_EFER";
3483	case MSR_K8_SF_MASK:
3484	return "MSR_K8_SF_MASK";
3485	case MSR_K6_STAR:
3486	return "MSR_K6_STAR";
3487	case MSR_K8_LSTAR:
3488	return "MSR_K8_LSTAR";
3489	case MSR_K8_CSTAR:
3490	return "MSR_K8_CSTAR";
3491	case MSR_K8_FS_BASE:
3492	return "MSR_K8_FS_BASE";
3493	case MSR_K8_GS_BASE:
3494	return "MSR_K8_GS_BASE";
3495	case MSR_K8_KERNEL_GS_BASE:
3496	return "MSR_K8_KERNEL_GS_BASE";
3497	case MSR_K8_TSC_AUX:
3498	return "MSR_K8_TSC_AUX";
3499	case MSR_IA32_BIOS_SIGN_ID:
3500	return "Unsupported MSR_IA32_BIOS_SIGN_ID";
3501	case MSR_IA32_PLATFORM_ID:
3502	return "Unsupported MSR_IA32_PLATFORM_ID";
3503	case MSR_IA32_BIOS_UPDT_TRIG:
3504	return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
3505	case MSR_IA32_TSC:
3506	return "MSR_IA32_TSC";
3507	case MSR_IA32_MISC_ENABLE:
3508	return "MSR_IA32_MISC_ENABLE";
3509	case MSR_IA32_MTRR_CAP:
3510	return "MSR_IA32_MTRR_CAP";
3511	case MSR_IA32_MCP_CAP:
3512	return "Unsupported MSR_IA32_MCP_CAP";
3513	case MSR_IA32_MCP_STATUS:
3514	return "Unsupported MSR_IA32_MCP_STATUS";
3515	case MSR_IA32_MCP_CTRL:
3516	return "Unsupported MSR_IA32_MCP_CTRL";
3517	case MSR_IA32_MTRR_DEF_TYPE:
3518	return "MSR_IA32_MTRR_DEF_TYPE";
3519	case MSR_K7_EVNTSEL0:
3520	return "Unsupported MSR_K7_EVNTSEL0";
3521	case MSR_K7_EVNTSEL1:
3522	return "Unsupported MSR_K7_EVNTSEL1";
3523	case MSR_K7_EVNTSEL2:
3524	return "Unsupported MSR_K7_EVNTSEL2";
3525	case MSR_K7_EVNTSEL3:
3526	return "Unsupported MSR_K7_EVNTSEL3";
3527	case MSR_IA32_MC0_CTL:
3528	return "Unsupported MSR_IA32_MC0_CTL";
3529	case MSR_IA32_MC0_STATUS:
3530	return "Unsupported MSR_IA32_MC0_STATUS";
3531	case MSR_IA32_PERFEVTSEL0:
3532	return "Unsupported MSR_IA32_PERFEVTSEL0";
3533	case MSR_IA32_PERFEVTSEL1:
3534	return "Unsupported MSR_IA32_PERFEVTSEL1";
3535	case MSR_IA32_PERF_STATUS:
3536	return "MSR_IA32_PERF_STATUS";
3537	case MSR_IA32_PLATFORM_INFO:
3538	return "MSR_IA32_PLATFORM_INFO";
3539	case MSR_IA32_PERF_CTL:
3540	return "Unsupported MSR_IA32_PERF_CTL";
3541	case MSR_K7_PERFCTR0:
3542	return "Unsupported MSR_K7_PERFCTR0";
3543	case MSR_K7_PERFCTR1:
3544	return "Unsupported MSR_K7_PERFCTR1";
3545	case MSR_K7_PERFCTR2:
3546	return "Unsupported MSR_K7_PERFCTR2";
3547	case MSR_K7_PERFCTR3:
3548	return "Unsupported MSR_K7_PERFCTR3";
3549	case MSR_IA32_PMC0:
3550	return "Unsupported MSR_IA32_PMC0";
3551	case MSR_IA32_PMC1:
3552	return "Unsupported MSR_IA32_PMC1";
3553	case MSR_IA32_PMC2:
3554	return "Unsupported MSR_IA32_PMC2";
3555	case MSR_IA32_PMC3:
3556	return "Unsupported MSR_IA32_PMC3";
3557	}
3558	return "Unknown MSR";
3559	}
3560	#endif /* LOG_ENABLED */
3561
3562
3563	/**
3564	* Interpret RDMSR
3565	*
3566	* @returns VBox status code.
3567	* @param pVM Pointer to the VM.
3568	* @param pVCpu Pointer to the VMCPU.
3569	* @param pRegFrame The register frame.
3570	*/
3571	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3572	{
3573	NOREF(pVM);
3574
3575	/* Get the current privilege level. */
3576	if (CPUMGetGuestCPL(pVCpu) != 0)
3577	{
3578	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
3579	return VERR_EM_INTERPRETER; /* supervisor only */
3580	}
3581
3582	uint64_t uValue;
3583	int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
3584	if (RT_UNLIKELY(rc != VINF_SUCCESS))
3585	{
3586	Assert(rc == VERR_CPUM_RAISE_GP_0);
3587	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
3588	return VERR_EM_INTERPRETER;
3589	}
3590	pRegFrame->rax = (uint32_t) uValue;
3591	pRegFrame->rdx = (uint32_t)(uValue >> 32);
3592	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
3593	return rc;
3594	}
3595
3596
3597	/**
3598	* RDMSR Emulation.
3599	*/
3600	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3601	{
3602	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3603	different, so we play safe by completely disassembling the instruction. */
3604	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3605	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3606	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3607	}
3608
3609
3610	/**
3611	* Interpret WRMSR
3612	*
3613	* @returns VBox status code.
3614	* @param pVM Pointer to the VM.
3615	* @param pVCpu Pointer to the VMCPU.
3616	* @param pRegFrame The register frame.
3617	*/
3618	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3619	{
3620	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3621
3622	/* Check the current privilege level, this instruction is supervisor only. */
3623	if (CPUMGetGuestCPL(pVCpu) != 0)
3624	{
3625	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
3626	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
3627	}
3628
3629	int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
3630	if (rc != VINF_SUCCESS)
3631	{
3632	Assert(rc == VERR_CPUM_RAISE_GP_0);
3633	Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
3634	return VERR_EM_INTERPRETER;
3635	}
3636	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
3637	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
3638	NOREF(pVM);
3639	return rc;
3640	}
3641
3642
3643	/**
3644	* WRMSR Emulation.
3645	*/
3646	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3647	{
3648	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3649	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3650	}
3651
3652
3653	/**
3654	* Internal worker.
3655	* @copydoc emInterpretInstructionCPUOuter
3656	*/
3657	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3658	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3659	{
3660	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3661	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3662	Assert(pcbSize);
3663	*pcbSize = 0;
3664
3665	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3666	{
3667	/*
3668	* Only supervisor guest code!!
3669	* And no complicated prefixes.
3670	*/
3671	/* Get the current privilege level. */
3672	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3673	#ifdef VBOX_WITH_RAW_RING1
3674	if ( !EMIsRawRing1Enabled(pVM)
3675	\|\| cpl > 1
3676	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3677	)
3678	{
3679	#endif
3680	if ( cpl != 0
3681	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3682	{
3683	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3684	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3685	return VERR_EM_INTERPRETER;
3686	}
3687	#ifdef VBOX_WITH_RAW_RING1
3688	}
3689	#endif
3690	}
3691	else
3692	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3693
3694	#ifdef IN_RC
3695	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3696	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3697	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3698	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3699	&& pDis->pCurInstr->uOpcode != OP_XADD
3700	&& pDis->pCurInstr->uOpcode != OP_OR
3701	&& pDis->pCurInstr->uOpcode != OP_AND
3702	&& pDis->pCurInstr->uOpcode != OP_XOR
3703	&& pDis->pCurInstr->uOpcode != OP_BTR
3704	)
3705	)
3706	#else
3707	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3708	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3709	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3710	)
3711	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3712	&& pDis->pCurInstr->uOpcode != OP_OR
3713	&& pDis->pCurInstr->uOpcode != OP_AND
3714	&& pDis->pCurInstr->uOpcode != OP_XOR
3715	&& pDis->pCurInstr->uOpcode != OP_BTR
3716	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3717	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3718	)
3719	)
3720	#endif
3721	{
3722	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3723	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3724	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3725	return VERR_EM_INTERPRETER;
3726	}
3727
3728	#if HC_ARCH_BITS == 32
3729	/*
3730	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3731	* Whitelisted instructions are safe.
3732	*/
3733	if ( pDis->Param1.cb > 4
3734	&& CPUMIsGuestIn64BitCode(pVCpu))
3735	{
3736	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3737	if ( uOpCode != OP_STOSWD
3738	&& uOpCode != OP_MOV
3739	&& uOpCode != OP_CMPXCHG8B
3740	&& uOpCode != OP_XCHG
3741	&& uOpCode != OP_BTS
3742	&& uOpCode != OP_BTR
3743	&& uOpCode != OP_BTC
3744	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3745	&& uOpCode != OP_CMPXCHG /* solaris */
3746	&& uOpCode != OP_AND /* windows */
3747	&& uOpCode != OP_OR /* windows */
3748	&& uOpCode != OP_XOR /* because we can */
3749	&& uOpCode != OP_ADD /* windows (dripple) */
3750	&& uOpCode != OP_ADC /* because we can */
3751	&& uOpCode != OP_SUB /* because we can */
3752	/** @todo OP_BTS or is that a different kind of failure? */
3753	# endif
3754	)
3755	{
3756	# ifdef VBOX_WITH_STATISTICS
3757	switch (pDis->pCurInstr->uOpcode)
3758	{
3759	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3760	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3761	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3762	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3763	INTERPRET_FAILED_CASE(OP_INC,Inc);
3764	INTERPRET_FAILED_CASE(OP_POP,Pop);
3765	INTERPRET_FAILED_CASE(OP_OR, Or);
3766	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3767	INTERPRET_FAILED_CASE(OP_AND,And);
3768	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3769	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3770	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3771	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3772	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3773	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3774	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3775	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3776	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3777	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3778	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3779	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3780	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3781	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3782	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3783	INTERPRET_FAILED_CASE(OP_ADD,Add);
3784	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3785	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3786	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3787	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3788	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3789	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3790	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3791	INTERPRET_FAILED_CASE(OP_STI, Sti);
3792	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3793	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3794	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3795	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3796	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3797	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3798	# undef INTERPRET_FAILED_CASE
3799	default:
3800	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3801	break;
3802	}
3803	# endif /* VBOX_WITH_STATISTICS */
3804	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3805	return VERR_EM_INTERPRETER;
3806	}
3807	}
3808	#endif
3809
3810	VBOXSTRICTRC rc;
3811	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3812	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3813	#endif
3814	switch (pDis->pCurInstr->uOpcode)
3815	{
3816	/*
3817	* Macros for generating the right case statements.
3818	*/
3819	# ifndef VBOX_COMPARE_IEM_AND_EM
3820	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3821	case opcode:\
3822	if (pDis->fPrefix & DISPREFIX_LOCK) \
3823	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3824	else \
3825	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3826	if (RT_SUCCESS(rc)) \
3827	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3828	else \
3829	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3830	return rc
3831	# else /* VBOX_COMPARE_IEM_AND_EM */
3832	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3833	case opcode:\
3834	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3835	if (RT_SUCCESS(rc)) \
3836	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3837	else \
3838	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3839	return rc
3840	# endif /* VBOX_COMPARE_IEM_AND_EM */
3841
3842	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3843	case opcode:\
3844	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3845	if (RT_SUCCESS(rc)) \
3846	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3847	else \
3848	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3849	return rc
3850
3851	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3852	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3853	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3854	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3855
3856	#define INTERPRET_CASE(opcode, Instr) \
3857	case opcode:\
3858	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3859	if (RT_SUCCESS(rc)) \
3860	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3861	else \
3862	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3863	return rc
3864
3865	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3866	case opcode:\
3867	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3868	if (RT_SUCCESS(rc)) \
3869	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3870	else \
3871	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3872	return rc
3873
3874	#define INTERPRET_STAT_CASE(opcode, Instr) \
3875	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3876
3877	/*
3878	* The actual case statements.
3879	*/
3880	INTERPRET_CASE(OP_XCHG,Xchg);
3881	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3882	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3883	INTERPRET_CASE(OP_POP,Pop);
3884	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3885	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3886	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3887	INTERPRET_CASE(OP_MOV,Mov);
3888	#ifndef IN_RC
3889	INTERPRET_CASE(OP_STOSWD,StosWD);
3890	#endif
3891	INTERPRET_CASE(OP_INVLPG,InvlPg);
3892	INTERPRET_CASE(OP_CPUID,CpuId);
3893	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3894	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3895	#ifdef IN_RING0
3896	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3897	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3898	#endif
3899	INTERPRET_CASE(OP_LLDT,LLdt);
3900	INTERPRET_CASE(OP_LMSW,Lmsw);
3901	#ifdef EM_EMULATE_SMSW
3902	INTERPRET_CASE(OP_SMSW,Smsw);
3903	#endif
3904	INTERPRET_CASE(OP_CLTS,Clts);
3905	INTERPRET_CASE(OP_MONITOR, Monitor);
3906	INTERPRET_CASE(OP_MWAIT, MWait);
3907	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3908	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3909	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3910	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3911	INTERPRET_CASE(OP_ADC,Adc);
3912	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3913	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3914	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3915	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3916	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3917	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3918	#ifdef IN_RC
3919	INTERPRET_CASE(OP_STI,Sti);
3920	INTERPRET_CASE(OP_XADD, XAdd);
3921	INTERPRET_CASE(OP_IRET,Iret);
3922	#endif
3923	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3924	INTERPRET_CASE(OP_HLT,Hlt);
3925	INTERPRET_CASE(OP_WBINVD,WbInvd);
3926	#ifdef VBOX_WITH_STATISTICS
3927	# ifndef IN_RC
3928	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3929	# endif
3930	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3931	#endif
3932
3933	default:
3934	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3935	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3936	return VERR_EM_INTERPRETER;
3937
3938	#undef INTERPRET_CASE_EX_PARAM2
3939	#undef INTERPRET_STAT_CASE
3940	#undef INTERPRET_CASE_EX
3941	#undef INTERPRET_CASE
3942	} /* switch (opcode) */
3943	/* not reached */
3944	}
3945
3946	/**
3947	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3948	*
3949	* EIP is NOT updated!
3950	*
3951	* @returns VBox strict status code.
3952	* @retval VINF_* Scheduling instructions. When these are returned, it
3953	* starts to get a bit tricky to know whether code was
3954	* executed or not... We'll address this when it becomes a problem.
3955	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3956	* @retval VERR_* Fatal errors.
3957	*
3958	* @param pVCpu Pointer to the VMCPU.
3959	* @param pDis The disassembler cpu state for the instruction to be
3960	* interpreted.
3961	* @param pRegFrame The register frame. EIP is NOT changed!
3962	* @param pvFault The fault address (CR2).
3963	* @param pcbSize Size of the write (if applicable).
3964	* @param enmCodeType Code type (user/supervisor)
3965	*
3966	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3967	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3968	* to worry about e.g. invalid modrm combinations (!)
3969	*
3970	* @todo At this time we do NOT check if the instruction overwrites vital information.
3971	* Make sure this can't happen!! (will add some assertions/checks later)
3972	*/
3973	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3974	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3975	{
3976	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3977	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3978	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3979	if (RT_SUCCESS(rc))
3980	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3981	else
3982	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3983	return rc;
3984	}
3985
3986
3987	#endif /* !VBOX_WITH_IEM */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 45312

Download in other formats: