EMAll.cpp@ 48569

Last change on this file since 48569 was 48442, checked in by vboxsync, 11 years ago
VMM: Comment and doxygen.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 140.1 KB

Line
1	/* $Id: EMAll.cpp 48442 2013-09-11 17:36:23Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/pgm.h>
28	#ifdef VBOX_WITH_IEM
29	# include <VBox/vmm/iem.h>
30	#endif
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/stam.h>
33	#include "EMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/vmm/hm.h>
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include "internal/pgm.h"
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49	#ifndef IN_RC
50	#undef VBOX_WITH_IEM
51	#endif
52	#ifdef VBOX_WITH_IEM
53	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
54	//# define VBOX_SAME_AS_EM
55	//# define VBOX_COMPARE_IEM_LAST
56	#endif
57
58	#ifdef VBOX_WITH_RAW_RING1
59	# define EM_EMULATE_SMSW
60	#endif
61
62
63	/*******************************************************************************
64	* Defined Constants And Macros *
65	*******************************************************************************/
66	/** @def EM_ASSERT_FAULT_RETURN
67	* Safety check.
68	*
69	* Could in theory misfire on a cross page boundary access...
70	*
71	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
72	* turns up an alias page instead of the original faulting one and annoying the
73	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
74	*/
75	#if 0
76	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
77	#else
78	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
79	#endif
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
86	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
87	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
88	#endif
89
90
91	/*******************************************************************************
92	* Global Variables *
93	*******************************************************************************/
94	#ifdef VBOX_COMPARE_IEM_AND_EM
95	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
96	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
97	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
98	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
99	static uint32_t g_fIncomingFFs;
100	static CPUMCTX g_IncomingCtx;
101	static bool g_fIgnoreRaxRdx = false;
102
103	static uint32_t g_fEmFFs;
104	static CPUMCTX g_EmCtx;
105	static uint8_t g_abEmWrote[256];
106	static size_t g_cbEmWrote;
107
108	static uint32_t g_fIemFFs;
109	static CPUMCTX g_IemCtx;
110	extern uint8_t g_abIemWrote[256];
111	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
112	extern size_t g_cbIemWrote;
113	#else
114	static size_t g_cbIemWrote;
115	#endif
116	#endif
117
118
119	/**
120	* Get the current execution manager status.
121	*
122	* @returns Current status.
123	* @param pVCpu Pointer to the VMCPU.
124	*/
125	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
126	{
127	return pVCpu->em.s.enmState;
128	}
129
130	/**
131	* Sets the current execution manager status. (use only when you know what you're doing!)
132	*
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
136	{
137	/* Only allowed combination: */
138	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
139	pVCpu->em.s.enmState = enmNewState;
140	}
141
142
143	/**
144	* Sets the PC for which interrupts should be inhibited.
145	*
146	* @param pVCpu Pointer to the VMCPU.
147	* @param PC The PC.
148	*/
149	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
150	{
151	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
152	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
153	}
154
155
156	/**
157	* Gets the PC for which interrupts should be inhibited.
158	*
159	* There are a few instructions which inhibits or delays interrupts
160	* for the instruction following them. These instructions are:
161	* - STI
162	* - MOV SS, r/m16
163	* - POP SS
164	*
165	* @returns The PC for which interrupts should be inhibited.
166	* @param pVCpu Pointer to the VMCPU.
167	*
168	*/
169	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
170	{
171	return pVCpu->em.s.GCPtrInhibitInterrupts;
172	}
173
174
175	/**
176	* Prepare an MWAIT - essentials of the MONITOR instruction.
177	*
178	* @returns VINF_SUCCESS
179	* @param pVCpu The current CPU.
180	* @param rax The content of RAX.
181	* @param rcx The content of RCX.
182	* @param rdx The content of RDX.
183	* @param GCPhys The physical address corresponding to rax.
184	*/
185	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
186	{
187	pVCpu->em.s.MWait.uMonitorRAX = rax;
188	pVCpu->em.s.MWait.uMonitorRCX = rcx;
189	pVCpu->em.s.MWait.uMonitorRDX = rdx;
190	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
191	/** @todo Make use of GCPhys. */
192	/** @todo Complete MONITOR implementation. */
193	return VINF_SUCCESS;
194	}
195
196
197	/**
198	* Performs an MWAIT.
199	*
200	* @returns VINF_SUCCESS
201	* @param pVCpu The current CPU.
202	* @param rax The content of RAX.
203	* @param rcx The content of RCX.
204	*/
205	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
206	{
207	pVCpu->em.s.MWait.uMWaitRAX = rax;
208	pVCpu->em.s.MWait.uMWaitRCX = rcx;
209	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
210	if (rcx)
211	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
212	else
213	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
214	/** @todo not completely correct?? */
215	return VINF_EM_HALT;
216	}
217
218
219
220	/**
221	* Determine if we should continue after encountering a mwait instruction.
222	*
223	* Clears MWAIT flags if returning @c true.
224	*
225	* @returns true if we should continue, false if we should halt.
226	* @param pVCpu Pointer to the VMCPU.
227	* @param pCtx Current CPU context.
228	*/
229	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
230	{
231	if ( pCtx->eflags.Bits.u1IF
232	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
233	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
234	{
235	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
236	{
237	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
238	return true;
239	}
240	}
241
242	return false;
243	}
244
245
246	/**
247	* Determine if we should continue after encountering a hlt instruction.
248	*
249	* @returns true if we should continue, false if we should halt.
250	* @param pVCpu Pointer to the VMCPU.
251	* @param pCtx Current CPU context.
252	*/
253	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
254	{
255	if (pCtx->eflags.Bits.u1IF)
256	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
257	return false;
258	}
259
260
261	/**
262	* Locks REM execution to a single VCPU.
263	*
264	* @param pVM Pointer to the VM.
265	*/
266	VMMDECL(void) EMRemLock(PVM pVM)
267	{
268	#ifdef VBOX_WITH_REM
269	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
270	return; /* early init */
271
272	Assert(!PGMIsLockOwner(pVM));
273	Assert(!IOMIsLockWriteOwner(pVM));
274	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
275	AssertRCSuccess(rc);
276	#endif
277	}
278
279
280	/**
281	* Unlocks REM execution
282	*
283	* @param pVM Pointer to the VM.
284	*/
285	VMMDECL(void) EMRemUnlock(PVM pVM)
286	{
287	#ifdef VBOX_WITH_REM
288	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
289	return; /* early init */
290
291	PDMCritSectLeave(&pVM->em.s.CritSectREM);
292	#endif
293	}
294
295
296	/**
297	* Check if this VCPU currently owns the REM lock.
298	*
299	* @returns bool owner/not owner
300	* @param pVM Pointer to the VM.
301	*/
302	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
303	{
304	#ifdef VBOX_WITH_REM
305	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
306	return true; /* early init */
307
308	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
309	#else
310	return true;
311	#endif
312	}
313
314
315	/**
316	* Try to acquire the REM lock.
317	*
318	* @returns VBox status code
319	* @param pVM Pointer to the VM.
320	*/
321	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
322	{
323	#ifdef VBOX_WITH_REM
324	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
325	return VINF_SUCCESS; /* early init */
326
327	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
328	#else
329	return VINF_SUCCESS;
330	#endif
331	}
332
333
334	/**
335	* @callback_method_impl{FNDISREADBYTES}
336	*/
337	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
338	{
339	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
340	#if defined(IN_RC) \|\| defined(IN_RING3)
341	PVM pVM = pVCpu->CTX_SUFF(pVM);
342	#endif
343	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
344	int rc;
345
346	/*
347	* Figure how much we can or must read.
348	*/
349	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
350	if (cbToRead > cbMaxRead)
351	cbToRead = cbMaxRead;
352	else if (cbToRead < cbMinRead)
353	cbToRead = cbMinRead;
354
355	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
356	/*
357	* We might be called upon to interpret an instruction in a patch.
358	*/
359	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
360	{
361	# ifdef IN_RC
362	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
363	# else
364	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
365	# endif
366	rc = VINF_SUCCESS;
367	}
368	else
369	#endif
370	{
371	# ifdef IN_RC
372	/*
373	* Try access it thru the shadow page tables first. Fall back on the
374	* slower PGM method if it fails because the TLB or page table was
375	* modified recently.
376	*/
377	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
378	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
379	{
380	cbToRead = cbMinRead;
381	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
382	}
383	if (rc == VERR_ACCESS_DENIED)
384	#endif
385	{
386	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
387	if (RT_FAILURE(rc))
388	{
389	if (cbToRead > cbMinRead)
390	{
391	cbToRead = cbMinRead;
392	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
393	}
394	if (RT_FAILURE(rc))
395	{
396	#ifndef IN_RC
397	/*
398	* If we fail to find the page via the guest's page tables
399	* we invalidate the page in the host TLB (pertaining to
400	* the guest in the NestedPaging case). See @bugref{6043}.
401	*/
402	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
403	{
404	HMInvalidatePage(pVCpu, uSrcAddr);
405	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
406	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
407	}
408	#endif
409	}
410	}
411	}
412	}
413
414	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
415	return rc;
416	}
417
418
419	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
420	{
421	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
422	}
423
424
425	/**
426	* Disassembles the current instruction.
427	*
428	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
429	* details.
430	*
431	* @param pVM Pointer to the VM.
432	* @param pVCpu Pointer to the VMCPU.
433	* @param pDis Where to return the parsed instruction info.
434	* @param pcbInstr Where to return the instruction size. (optional)
435	*/
436	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
437	{
438	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
439	RTGCPTR GCPtrInstr;
440	#if 0
441	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
442	#else
443	/** @todo Get the CPU mode as well while we're at it! */
444	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
445	pCtxCore->rip, &GCPtrInstr);
446	#endif
447	if (RT_FAILURE(rc))
448	{
449	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
450	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
451	return rc;
452	}
453	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
454	}
455
456
457	/**
458	* Disassembles one instruction.
459	*
460	* This is used by internally by the interpreter and by trap/access handlers.
461	*
462	* @returns VBox status code.
463	*
464	* @param pVM Pointer to the VM.
465	* @param pVCpu Pointer to the VMCPU.
466	* @param GCPtrInstr The flat address of the instruction.
467	* @param pCtxCore The context core (used to determine the cpu mode).
468	* @param pDis Where to return the parsed instruction info.
469	* @param pcbInstr Where to return the instruction size. (optional)
470	*/
471	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
472	PDISCPUSTATE pDis, unsigned *pcbInstr)
473	{
474	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
475	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
476	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
477	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
478	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
479	if (RT_SUCCESS(rc))
480	return VINF_SUCCESS;
481	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
482	return rc;
483	}
484
485
486	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
487	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
488	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
489	uint32_t cbEm, uint32_t cbIem)
490	{
491	/* Quick compare. */
492	if ( rcEm == rcIem
493	&& cbEm == cbIem
494	&& g_cbEmWrote == g_cbIemWrote
495	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
496	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
497	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
498	)
499	return;
500
501	/* Report exact differences. */
502	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
503	if (rcEm != rcIem)
504	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
505	else if (cbEm != cbIem)
506	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
507
508	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
509	{
510	if (g_cbIemWrote != g_cbEmWrote)
511	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
512	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
513	{
514	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
515	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
516	}
517
518	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
519	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
520	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
521
522	# define CHECK_FIELD(a_Field) \
523	do \
524	{ \
525	if (pEmCtx->a_Field != pIemCtx->a_Field) \
526	{ \
527	switch (sizeof(pEmCtx->a_Field)) \
528	{ \
529	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
530	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
531	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
532	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
533	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
534	} \
535	cDiffs++; \
536	} \
537	} while (0)
538
539	# define CHECK_BIT_FIELD(a_Field) \
540	do \
541	{ \
542	if (pEmCtx->a_Field != pIemCtx->a_Field) \
543	{ \
544	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
545	cDiffs++; \
546	} \
547	} while (0)
548
549	# define CHECK_SEL(a_Sel) \
550	do \
551	{ \
552	CHECK_FIELD(a_Sel.Sel); \
553	CHECK_FIELD(a_Sel.Attr.u); \
554	CHECK_FIELD(a_Sel.u64Base); \
555	CHECK_FIELD(a_Sel.u32Limit); \
556	CHECK_FIELD(a_Sel.fFlags); \
557	} while (0)
558
559	unsigned cDiffs = 0;
560	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
561	{
562	RTLogPrintf(" the FPU state differs\n");
563	cDiffs++;
564	CHECK_FIELD(fpu.FCW);
565	CHECK_FIELD(fpu.FSW);
566	CHECK_FIELD(fpu.FTW);
567	CHECK_FIELD(fpu.FOP);
568	CHECK_FIELD(fpu.FPUIP);
569	CHECK_FIELD(fpu.CS);
570	CHECK_FIELD(fpu.Rsrvd1);
571	CHECK_FIELD(fpu.FPUDP);
572	CHECK_FIELD(fpu.DS);
573	CHECK_FIELD(fpu.Rsrvd2);
574	CHECK_FIELD(fpu.MXCSR);
575	CHECK_FIELD(fpu.MXCSR_MASK);
576	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
577	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
578	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
579	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
580	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
581	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
582	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
583	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
584	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
585	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
586	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
587	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
588	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
589	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
594	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
595	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
596	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
597	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
598	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
599	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
600	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
601	CHECK_FIELD(fpu.au32RsrvdRest[i]);
602	}
603	CHECK_FIELD(rip);
604	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
605	{
606	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
607	CHECK_BIT_FIELD(rflags.Bits.u1CF);
608	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
609	CHECK_BIT_FIELD(rflags.Bits.u1PF);
610	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
611	CHECK_BIT_FIELD(rflags.Bits.u1AF);
612	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
613	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
614	CHECK_BIT_FIELD(rflags.Bits.u1SF);
615	CHECK_BIT_FIELD(rflags.Bits.u1TF);
616	CHECK_BIT_FIELD(rflags.Bits.u1IF);
617	CHECK_BIT_FIELD(rflags.Bits.u1DF);
618	CHECK_BIT_FIELD(rflags.Bits.u1OF);
619	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
620	CHECK_BIT_FIELD(rflags.Bits.u1NT);
621	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
622	CHECK_BIT_FIELD(rflags.Bits.u1RF);
623	CHECK_BIT_FIELD(rflags.Bits.u1VM);
624	CHECK_BIT_FIELD(rflags.Bits.u1AC);
625	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
626	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
627	CHECK_BIT_FIELD(rflags.Bits.u1ID);
628	}
629
630	if (!g_fIgnoreRaxRdx)
631	CHECK_FIELD(rax);
632	CHECK_FIELD(rcx);
633	if (!g_fIgnoreRaxRdx)
634	CHECK_FIELD(rdx);
635	CHECK_FIELD(rbx);
636	CHECK_FIELD(rsp);
637	CHECK_FIELD(rbp);
638	CHECK_FIELD(rsi);
639	CHECK_FIELD(rdi);
640	CHECK_FIELD(r8);
641	CHECK_FIELD(r9);
642	CHECK_FIELD(r10);
643	CHECK_FIELD(r11);
644	CHECK_FIELD(r12);
645	CHECK_FIELD(r13);
646	CHECK_SEL(cs);
647	CHECK_SEL(ss);
648	CHECK_SEL(ds);
649	CHECK_SEL(es);
650	CHECK_SEL(fs);
651	CHECK_SEL(gs);
652	CHECK_FIELD(cr0);
653	CHECK_FIELD(cr2);
654	CHECK_FIELD(cr3);
655	CHECK_FIELD(cr4);
656	CHECK_FIELD(dr[0]);
657	CHECK_FIELD(dr[1]);
658	CHECK_FIELD(dr[2]);
659	CHECK_FIELD(dr[3]);
660	CHECK_FIELD(dr[6]);
661	CHECK_FIELD(dr[7]);
662	CHECK_FIELD(gdtr.cbGdt);
663	CHECK_FIELD(gdtr.pGdt);
664	CHECK_FIELD(idtr.cbIdt);
665	CHECK_FIELD(idtr.pIdt);
666	CHECK_SEL(ldtr);
667	CHECK_SEL(tr);
668	CHECK_FIELD(SysEnter.cs);
669	CHECK_FIELD(SysEnter.eip);
670	CHECK_FIELD(SysEnter.esp);
671	CHECK_FIELD(msrEFER);
672	CHECK_FIELD(msrSTAR);
673	CHECK_FIELD(msrPAT);
674	CHECK_FIELD(msrLSTAR);
675	CHECK_FIELD(msrCSTAR);
676	CHECK_FIELD(msrSFMASK);
677	CHECK_FIELD(msrKERNELGSBASE);
678
679	# undef CHECK_FIELD
680	# undef CHECK_BIT_FIELD
681	}
682	}
683	#endif /* VBOX_COMPARE_IEM_AND_EM */
684
685
686	/**
687	* Interprets the current instruction.
688	*
689	* @returns VBox status code.
690	* @retval VINF_* Scheduling instructions.
691	* @retval VERR_EM_INTERPRETER Something we can't cope with.
692	* @retval VERR_* Fatal errors.
693	*
694	* @param pVCpu Pointer to the VMCPU.
695	* @param pRegFrame The register frame.
696	* Updates the EIP if an instruction was executed successfully.
697	* @param pvFault The fault address (CR2).
698	* @param pcbSize Size of the write (if applicable).
699	*
700	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
701	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
702	* to worry about e.g. invalid modrm combinations (!)
703	*/
704	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
705	{
706	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
707	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
708	#ifdef VBOX_WITH_IEM
709	NOREF(pvFault);
710
711	# ifdef VBOX_COMPARE_IEM_AND_EM
712	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
713	g_IncomingCtx = *pCtx;
714	g_fIncomingFFs = pVCpu->fLocalForcedActions;
715	g_cbEmWrote = g_cbIemWrote = 0;
716
717	# ifdef VBOX_COMPARE_IEM_FIRST
718	/* IEM */
719	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
720	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
721	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
722	rcIem = VERR_EM_INTERPRETER;
723	g_IemCtx = *pCtx;
724	g_fIemFFs = pVCpu->fLocalForcedActions;
725	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
726	*pCtx = g_IncomingCtx;
727	# endif
728
729	/* EM */
730	RTGCPTR pbCode;
731	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
732	if (RT_SUCCESS(rcEm))
733	{
734	uint32_t cbOp;
735	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
736	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
737	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
738	if (RT_SUCCESS(rcEm))
739	{
740	Assert(cbOp == pDis->cbInstr);
741	uint32_t cbIgnored;
742	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
743	if (RT_SUCCESS(rcEm))
744	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
745
746	}
747	rcEm = VERR_EM_INTERPRETER;
748	}
749	else
750	rcEm = VERR_EM_INTERPRETER;
751	# ifdef VBOX_SAME_AS_EM
752	if (rcEm == VERR_EM_INTERPRETER)
753	{
754	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
755	return rcEm;
756	}
757	# endif
758	g_EmCtx = *pCtx;
759	g_fEmFFs = pVCpu->fLocalForcedActions;
760	VBOXSTRICTRC rc = rcEm;
761
762	# ifdef VBOX_COMPARE_IEM_LAST
763	/* IEM */
764	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
765	*pCtx = g_IncomingCtx;
766	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
767	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
768	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
769	rcIem = VERR_EM_INTERPRETER;
770	g_IemCtx = *pCtx;
771	g_fIemFFs = pVCpu->fLocalForcedActions;
772	rc = rcIem;
773	# endif
774
775	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
776	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
777	# endif
778
779	# else
780	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
781	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
782	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
783	rc = VERR_EM_INTERPRETER;
784	# endif
785	if (rc != VINF_SUCCESS)
786	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
787
788	return rc;
789	#else
790	RTGCPTR pbCode;
791	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
792	if (RT_SUCCESS(rc))
793	{
794	uint32_t cbOp;
795	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
796	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
797	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
798	if (RT_SUCCESS(rc))
799	{
800	Assert(cbOp == pDis->cbInstr);
801	uint32_t cbIgnored;
802	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
803	if (RT_SUCCESS(rc))
804	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
805
806	return rc;
807	}
808	}
809	return VERR_EM_INTERPRETER;
810	#endif
811	}
812
813
814	/**
815	* Interprets the current instruction.
816	*
817	* @returns VBox status code.
818	* @retval VINF_* Scheduling instructions.
819	* @retval VERR_EM_INTERPRETER Something we can't cope with.
820	* @retval VERR_* Fatal errors.
821	*
822	* @param pVM Pointer to the VM.
823	* @param pVCpu Pointer to the VMCPU.
824	* @param pRegFrame The register frame.
825	* Updates the EIP if an instruction was executed successfully.
826	* @param pvFault The fault address (CR2).
827	* @param pcbWritten Size of the write (if applicable).
828	*
829	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
830	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
831	* to worry about e.g. invalid modrm combinations (!)
832	*/
833	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
834	{
835	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
836	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
837	#ifdef VBOX_WITH_IEM
838	NOREF(pvFault);
839
840	# ifdef VBOX_COMPARE_IEM_AND_EM
841	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
842	g_IncomingCtx = *pCtx;
843	g_fIncomingFFs = pVCpu->fLocalForcedActions;
844	g_cbEmWrote = g_cbIemWrote = 0;
845
846	# ifdef VBOX_COMPARE_IEM_FIRST
847	/* IEM */
848	uint32_t cbIemWritten = 0;
849	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
850	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
851	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
852	rcIem = VERR_EM_INTERPRETER;
853	g_IemCtx = *pCtx;
854	g_fIemFFs = pVCpu->fLocalForcedActions;
855	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
856	*pCtx = g_IncomingCtx;
857	# endif
858
859	/* EM */
860	uint32_t cbEmWritten = 0;
861	RTGCPTR pbCode;
862	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
863	if (RT_SUCCESS(rcEm))
864	{
865	uint32_t cbOp;
866	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
867	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
868	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
869	if (RT_SUCCESS(rcEm))
870	{
871	Assert(cbOp == pDis->cbInstr);
872	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
873	if (RT_SUCCESS(rcEm))
874	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
875
876	}
877	else
878	rcEm = VERR_EM_INTERPRETER;
879	}
880	else
881	rcEm = VERR_EM_INTERPRETER;
882	# ifdef VBOX_SAME_AS_EM
883	if (rcEm == VERR_EM_INTERPRETER)
884	{
885	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
886	return rcEm;
887	}
888	# endif
889	g_EmCtx = *pCtx;
890	g_fEmFFs = pVCpu->fLocalForcedActions;
891	*pcbWritten = cbEmWritten;
892	VBOXSTRICTRC rc = rcEm;
893
894	# ifdef VBOX_COMPARE_IEM_LAST
895	/* IEM */
896	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
897	*pCtx = g_IncomingCtx;
898	uint32_t cbIemWritten = 0;
899	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
900	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
901	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
902	rcIem = VERR_EM_INTERPRETER;
903	g_IemCtx = *pCtx;
904	g_fIemFFs = pVCpu->fLocalForcedActions;
905	*pcbWritten = cbIemWritten;
906	rc = rcIem;
907	# endif
908
909	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
910	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
911	# endif
912
913	# else
914	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
915	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
916	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
917	rc = VERR_EM_INTERPRETER;
918	# endif
919	if (rc != VINF_SUCCESS)
920	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
921
922	return rc;
923	#else
924	RTGCPTR pbCode;
925	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
926	if (RT_SUCCESS(rc))
927	{
928	uint32_t cbOp;
929	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
930	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
931	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
932	if (RT_SUCCESS(rc))
933	{
934	Assert(cbOp == pDis->cbInstr);
935	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
936	if (RT_SUCCESS(rc))
937	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
938
939	return rc;
940	}
941	}
942	return VERR_EM_INTERPRETER;
943	#endif
944	}
945
946
947	/**
948	* Interprets the current instruction using the supplied DISCPUSTATE structure.
949	*
950	* IP/EIP/RIP IS updated!
951	*
952	* @returns VBox strict status code.
953	* @retval VINF_* Scheduling instructions. When these are returned, it
954	* starts to get a bit tricky to know whether code was
955	* executed or not... We'll address this when it becomes a problem.
956	* @retval VERR_EM_INTERPRETER Something we can't cope with.
957	* @retval VERR_* Fatal errors.
958	*
959	* @param pVM Pointer to the VM.
960	* @param pVCpu Pointer to the VMCPU.
961	* @param pDis The disassembler cpu state for the instruction to be
962	* interpreted.
963	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
964	* @param pvFault The fault address (CR2).
965	* @param pcbSize Size of the write (if applicable).
966	* @param enmCodeType Code type (user/supervisor)
967	*
968	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
969	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
970	* to worry about e.g. invalid modrm combinations (!)
971	*
972	* @todo At this time we do NOT check if the instruction overwrites vital information.
973	* Make sure this can't happen!! (will add some assertions/checks later)
974	*/
975	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
976	RTGCPTR pvFault, EMCODETYPE enmCodeType)
977	{
978	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
979	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
980	#ifdef VBOX_WITH_IEM
981	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
982
983	# ifdef VBOX_COMPARE_IEM_AND_EM
984	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
985	g_IncomingCtx = *pCtx;
986	g_fIncomingFFs = pVCpu->fLocalForcedActions;
987	g_cbEmWrote = g_cbIemWrote = 0;
988
989	# ifdef VBOX_COMPARE_IEM_FIRST
990	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
991	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
992	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
993	rcIem = VERR_EM_INTERPRETER;
994	g_IemCtx = *pCtx;
995	g_fIemFFs = pVCpu->fLocalForcedActions;
996	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
997	*pCtx = g_IncomingCtx;
998	# endif
999
1000	/* EM */
1001	uint32_t cbIgnored;
1002	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1003	if (RT_SUCCESS(rcEm))
1004	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1005	# ifdef VBOX_SAME_AS_EM
1006	if (rcEm == VERR_EM_INTERPRETER)
1007	{
1008	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1009	return rcEm;
1010	}
1011	# endif
1012	g_EmCtx = *pCtx;
1013	g_fEmFFs = pVCpu->fLocalForcedActions;
1014	VBOXSTRICTRC rc = rcEm;
1015
1016	# ifdef VBOX_COMPARE_IEM_LAST
1017	/* IEM */
1018	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1019	*pCtx = g_IncomingCtx;
1020	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1021	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1022	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1023	rcIem = VERR_EM_INTERPRETER;
1024	g_IemCtx = *pCtx;
1025	g_fIemFFs = pVCpu->fLocalForcedActions;
1026	rc = rcIem;
1027	# endif
1028
1029	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1030	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1031	# endif
1032
1033	# else
1034	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1035	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1036	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1037	rc = VERR_EM_INTERPRETER;
1038	# endif
1039
1040	if (rc != VINF_SUCCESS)
1041	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1042
1043	return rc;
1044	#else
1045	uint32_t cbIgnored;
1046	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1047	if (RT_SUCCESS(rc))
1048	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1049	return rc;
1050	#endif
1051	}
1052
1053	#ifdef IN_RC
1054
1055	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1056	{
1057	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1058	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1059	return rc;
1060	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1061	}
1062
1063
1064	/**
1065	* Interpret IRET (currently only to V86 code) - PATM only.
1066	*
1067	* @returns VBox status code.
1068	* @param pVM Pointer to the VM.
1069	* @param pVCpu Pointer to the VMCPU.
1070	* @param pRegFrame The register frame.
1071	*
1072	*/
1073	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1074	{
1075	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1076	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1077	int rc;
1078
1079	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1080	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1081	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1082	* this function. Fear that it may guru on us, thus not converted to
1083	* IEM. */
1084
1085	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1086	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1087	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1088	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1089	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1090
1091	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1092	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1093	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1094	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1097	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1098
1099	pRegFrame->eip = eip & 0xffff;
1100	pRegFrame->cs.Sel = cs;
1101
1102	/* Mask away all reserved bits */
1103	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1104	eflags &= uMask;
1105
1106	CPUMRawSetEFlags(pVCpu, eflags);
1107	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1108
1109	pRegFrame->esp = esp;
1110	pRegFrame->ss.Sel = ss;
1111	pRegFrame->ds.Sel = ds;
1112	pRegFrame->es.Sel = es;
1113	pRegFrame->fs.Sel = fs;
1114	pRegFrame->gs.Sel = gs;
1115
1116	return VINF_SUCCESS;
1117	}
1118
1119	/**
1120	* IRET Emulation.
1121	*/
1122	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1123	{
1124	#ifdef VBOX_WITH_RAW_RING1
1125	NOREF(pvFault); NOREF(pcbSize);
1126	if (EMIsRawRing1Enabled(pVM))
1127	{
1128	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1129	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1130	int rc;
1131	uint32_t cpl, rpl;
1132
1133	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1134	/* @todo: we don't verify all the edge cases that generate #GP faults */
1135
1136	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1137	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1138	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1139	* this function. Fear that it may guru on us, thus not converted to
1140	* IEM. */
1141
1142	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1143	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1144	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1145	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1146	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1147
1148	/* Deal with V86 above. */
1149	if (eflags & X86_EFL_VM)
1150	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1151
1152	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1153	rpl = cs & X86_SEL_RPL;
1154
1155	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1156	if (rpl != cpl)
1157	{
1158	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1159	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1160	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1161	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1162	Log(("emInterpretIret: SS:ESP=%04X:08X\n", ss, esp));
1163	pRegFrame->ss.Sel = ss;
1164	pRegFrame->esp = esp;
1165	}
1166	pRegFrame->cs.Sel = cs;
1167	pRegFrame->eip = eip;
1168
1169	/* Adjust CS & SS as required. */
1170	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1171
1172	/* Mask away all reserved bits */
1173	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1174	eflags &= uMask;
1175
1176	CPUMRawSetEFlags(pVCpu, eflags);
1177	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1178	return VINF_SUCCESS;
1179	}
1180	#else
1181	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1182	#endif
1183	return VERR_EM_INTERPRETER;
1184	}
1185
1186	#endif /* IN_RC */
1187
1188
1189
1190	/*
1191	*
1192	* Old interpreter primitives used by HM, move/eliminate later.
1193	* Old interpreter primitives used by HM, move/eliminate later.
1194	* Old interpreter primitives used by HM, move/eliminate later.
1195	* Old interpreter primitives used by HM, move/eliminate later.
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	*
1198	*/
1199
1200
1201	/**
1202	* Interpret CPUID given the parameters in the CPU context.
1203	*
1204	* @returns VBox status code.
1205	* @param pVM Pointer to the VM.
1206	* @param pVCpu Pointer to the VMCPU.
1207	* @param pRegFrame The register frame.
1208	*
1209	*/
1210	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1211	{
1212	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1213	uint32_t iLeaf = pRegFrame->eax;
1214	NOREF(pVM);
1215
1216	/* cpuid clears the high dwords of the affected 64 bits registers. */
1217	pRegFrame->rax = 0;
1218	pRegFrame->rbx = 0;
1219	pRegFrame->rcx &= UINT64_C(0x00000000ffffffff);
1220	pRegFrame->rdx = 0;
1221
1222	/* Note: operates the same in 64 and non-64 bits mode. */
1223	CPUMGetGuestCpuId(pVCpu, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1224	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1225	return VINF_SUCCESS;
1226	}
1227
1228
1229	/**
1230	* Interpret RDTSC.
1231	*
1232	* @returns VBox status code.
1233	* @param pVM Pointer to the VM.
1234	* @param pVCpu Pointer to the VMCPU.
1235	* @param pRegFrame The register frame.
1236	*
1237	*/
1238	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1239	{
1240	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1241	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1242
1243	if (uCR4 & X86_CR4_TSD)
1244	return VERR_EM_INTERPRETER; /* genuine #GP */
1245
1246	uint64_t uTicks = TMCpuTickGet(pVCpu);
1247
1248	/* Same behaviour in 32 & 64 bits mode */
1249	pRegFrame->rax = (uint32_t)uTicks;
1250	pRegFrame->rdx = (uTicks >> 32ULL);
1251	#ifdef VBOX_COMPARE_IEM_AND_EM
1252	g_fIgnoreRaxRdx = true;
1253	#endif
1254
1255	NOREF(pVM);
1256	return VINF_SUCCESS;
1257	}
1258
1259	/**
1260	* Interpret RDTSCP.
1261	*
1262	* @returns VBox status code.
1263	* @param pVM Pointer to the VM.
1264	* @param pVCpu Pointer to the VMCPU.
1265	* @param pCtx The CPU context.
1266	*
1267	*/
1268	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1269	{
1270	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1271	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1272
1273	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1274	{
1275	AssertFailed();
1276	return VERR_EM_INTERPRETER; /* genuine #UD */
1277	}
1278
1279	if (uCR4 & X86_CR4_TSD)
1280	return VERR_EM_INTERPRETER; /* genuine #GP */
1281
1282	uint64_t uTicks = TMCpuTickGet(pVCpu);
1283
1284	/* Same behaviour in 32 & 64 bits mode */
1285	pCtx->rax = (uint32_t)uTicks;
1286	pCtx->rdx = (uTicks >> 32ULL);
1287	#ifdef VBOX_COMPARE_IEM_AND_EM
1288	g_fIgnoreRaxRdx = true;
1289	#endif
1290	/* Low dword of the TSC_AUX msr only. */
1291	CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);
1292	pCtx->rcx &= UINT32_C(0xffffffff);
1293
1294	return VINF_SUCCESS;
1295	}
1296
1297	/**
1298	* Interpret RDPMC.
1299	*
1300	* @returns VBox status code.
1301	* @param pVM Pointer to the VM.
1302	* @param pVCpu Pointer to the VMCPU.
1303	* @param pRegFrame The register frame.
1304	*
1305	*/
1306	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1307	{
1308	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1309	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1310
1311	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1312	if ( !(uCR4 & X86_CR4_PCE)
1313	&& CPUMGetGuestCPL(pVCpu) != 0)
1314	{
1315	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1316	return VERR_EM_INTERPRETER; /* genuine #GP */
1317	}
1318
1319	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1320	pRegFrame->rax = 0;
1321	pRegFrame->rdx = 0;
1322	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1323	* but see @bugref{3472}! */
1324
1325	NOREF(pVM);
1326	return VINF_SUCCESS;
1327	}
1328
1329
1330	/**
1331	* MWAIT Emulation.
1332	*/
1333	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1334	{
1335	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1336	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1337	NOREF(pVM);
1338
1339	/* Get the current privilege level. */
1340	cpl = CPUMGetGuestCPL(pVCpu);
1341	if (cpl != 0)
1342	return VERR_EM_INTERPRETER; /* supervisor only */
1343
1344	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1345	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1346	return VERR_EM_INTERPRETER; /* not supported */
1347
1348	/*
1349	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1350	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1351	*/
1352	CPUMGetGuestCpuId(pVCpu, 5, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1353	if (pRegFrame->ecx > 1)
1354	{
1355	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1356	return VERR_EM_INTERPRETER; /* illegal value. */
1357	}
1358
1359	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1360	{
1361	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1362	return VERR_EM_INTERPRETER; /* illegal value. */
1363	}
1364
1365	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1366	}
1367
1368
1369	/**
1370	* MONITOR Emulation.
1371	*/
1372	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1373	{
1374	uint32_t u32Dummy, u32ExtFeatures, cpl;
1375	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1376	NOREF(pVM);
1377
1378	if (pRegFrame->ecx != 0)
1379	{
1380	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1381	return VERR_EM_INTERPRETER; /* illegal value. */
1382	}
1383
1384	/* Get the current privilege level. */
1385	cpl = CPUMGetGuestCPL(pVCpu);
1386	if (cpl != 0)
1387	return VERR_EM_INTERPRETER; /* supervisor only */
1388
1389	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1390	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1391	return VERR_EM_INTERPRETER; /* not supported */
1392
1393	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1394	return VINF_SUCCESS;
1395	}
1396
1397
1398	/* VT-x only: */
1399
1400	/**
1401	* Interpret INVLPG.
1402	*
1403	* @returns VBox status code.
1404	* @param pVM Pointer to the VM.
1405	* @param pVCpu Pointer to the VMCPU.
1406	* @param pRegFrame The register frame.
1407	* @param pAddrGC Operand address.
1408	*
1409	*/
1410	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1411	{
1412	/** @todo is addr always a flat linear address or ds based
1413	* (in absence of segment override prefixes)????
1414	*/
1415	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1416	NOREF(pVM); NOREF(pRegFrame);
1417	#ifdef IN_RC
1418	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1419	#endif
1420	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1421	if ( rc == VINF_SUCCESS
1422	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1423	return VINF_SUCCESS;
1424	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1425	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1426	VERR_EM_INTERPRETER);
1427	return rc;
1428	}
1429
1430
1431	/**
1432	* Update CRx.
1433	*
1434	* @returns VBox status code.
1435	* @param pVM Pointer to the VM.
1436	* @param pVCpu Pointer to the VMCPU.
1437	* @param pRegFrame The register frame.
1438	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1439	* @param val New CRx value
1440	*
1441	*/
1442	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1443	{
1444	uint64_t oldval;
1445	uint64_t msrEFER;
1446	int rc, rc2;
1447	NOREF(pVM);
1448
1449	/** @todo Clean up this mess. */
1450	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1451	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1452	switch (DestRegCrx)
1453	{
1454	case DISCREG_CR0:
1455	oldval = CPUMGetGuestCR0(pVCpu);
1456	#ifdef IN_RC
1457	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1458	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1459	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1460	return VERR_EM_INTERPRETER;
1461	#endif
1462	rc = VINF_SUCCESS;
1463	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1464	CPUMSetGuestCR0(pVCpu, val);
1465	#else
1466	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1467	#endif
1468	val = CPUMGetGuestCR0(pVCpu);
1469	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1470	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1471	{
1472	/* global flush */
1473	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1474	AssertRCReturn(rc, rc);
1475	}
1476
1477	/* Deal with long mode enabling/disabling. */
1478	msrEFER = CPUMGetGuestEFER(pVCpu);
1479	if (msrEFER & MSR_K6_EFER_LME)
1480	{
1481	if ( !(oldval & X86_CR0_PG)
1482	&& (val & X86_CR0_PG))
1483	{
1484	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1485	if (pRegFrame->cs.Attr.n.u1Long)
1486	{
1487	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1488	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1489	}
1490
1491	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1492	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1493	{
1494	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1495	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1496	}
1497	msrEFER \|= MSR_K6_EFER_LMA;
1498	}
1499	else
1500	if ( (oldval & X86_CR0_PG)
1501	&& !(val & X86_CR0_PG))
1502	{
1503	msrEFER &= ~MSR_K6_EFER_LMA;
1504	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1505	}
1506	CPUMSetGuestEFER(pVCpu, msrEFER);
1507	}
1508	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1509	return rc2 == VINF_SUCCESS ? rc : rc2;
1510
1511	case DISCREG_CR2:
1512	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1513	return VINF_SUCCESS;
1514
1515	case DISCREG_CR3:
1516	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1517	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1518	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1519	{
1520	/* flush */
1521	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1522	AssertRC(rc);
1523	}
1524	return rc;
1525
1526	case DISCREG_CR4:
1527	oldval = CPUMGetGuestCR4(pVCpu);
1528	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1529	val = CPUMGetGuestCR4(pVCpu);
1530
1531	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1532	msrEFER = CPUMGetGuestEFER(pVCpu);
1533	if ( (msrEFER & MSR_K6_EFER_LMA)
1534	&& (oldval & X86_CR4_PAE)
1535	&& !(val & X86_CR4_PAE))
1536	{
1537	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1538	}
1539
1540	rc = VINF_SUCCESS;
1541	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1542	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1543	{
1544	/* global flush */
1545	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1546	AssertRCReturn(rc, rc);
1547	}
1548
1549	/* Feeling extremely lazy. */
1550	# ifdef IN_RC
1551	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1552	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1553	{
1554	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1555	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1556	}
1557	# endif
1558	# ifdef VBOX_WITH_RAW_MODE
1559	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1560	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1561	# endif
1562
1563	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1564	return rc2 == VINF_SUCCESS ? rc : rc2;
1565
1566	case DISCREG_CR8:
1567	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1568
1569	default:
1570	AssertFailed();
1571	case DISCREG_CR1: /* illegal op */
1572	break;
1573	}
1574	return VERR_EM_INTERPRETER;
1575	}
1576
1577
1578	/**
1579	* Interpret CRx write.
1580	*
1581	* @returns VBox status code.
1582	* @param pVM Pointer to the VM.
1583	* @param pVCpu Pointer to the VMCPU.
1584	* @param pRegFrame The register frame.
1585	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1586	* @param SrcRegGen General purpose register index (USE_REG_E**))
1587	*
1588	*/
1589	VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1590	{
1591	uint64_t val;
1592	int rc;
1593	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1594
1595	if (CPUMIsGuestIn64BitCode(pVCpu))
1596	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1597	else
1598	{
1599	uint32_t val32;
1600	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1601	val = val32;
1602	}
1603
1604	if (RT_SUCCESS(rc))
1605	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1606
1607	return VERR_EM_INTERPRETER;
1608	}
1609
1610	/**
1611	* Interpret LMSW.
1612	*
1613	* @returns VBox status code.
1614	* @param pVM Pointer to the VM.
1615	* @param pVCpu Pointer to the VMCPU.
1616	* @param pRegFrame The register frame.
1617	* @param u16Data LMSW source data.
1618	*
1619	*/
1620	VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
1621	{
1622	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1623	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
1624
1625	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1626	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1627	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1628
1629	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
1630	}
1631
1632
1633	/**
1634	* Interpret CLTS.
1635	*
1636	* @returns VBox status code.
1637	* @param pVM Pointer to the VM.
1638	* @param pVCpu Pointer to the VMCPU.
1639	*
1640	*/
1641	VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
1642	{
1643	NOREF(pVM);
1644
1645	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
1646	if (!(cr0 & X86_CR0_TS))
1647	return VINF_SUCCESS;
1648	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
1649	}
1650
1651
1652	#ifdef LOG_ENABLED
1653	static const char *emMSRtoString(uint32_t uMsr)
1654	{
1655	switch (uMsr)
1656	{
1657	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1658	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1659	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1660	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1661	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1662	case MSR_K6_EFER: return "MSR_K6_EFER";
1663	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1664	case MSR_K6_STAR: return "MSR_K6_STAR";
1665	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1666	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1667	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1668	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1669	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1670	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1671	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1672	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1673	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1674	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1675	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1676	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1677	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1678	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1679	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1680	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1681	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1682	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1683	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1684	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1685	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1686	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1687	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1688	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1689	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1690	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1691	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1692	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1693	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1694	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1695	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1696	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1697	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1698	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1699	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1700	}
1701	return "Unknown MSR";
1702	}
1703	#endif /* LOG_ENABLED */
1704
1705
1706	/**
1707	* Interpret RDMSR
1708	*
1709	* @returns VBox status code.
1710	* @param pVM Pointer to the VM.
1711	* @param pVCpu Pointer to the VMCPU.
1712	* @param pRegFrame The register frame.
1713	*/
1714	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1715	{
1716	NOREF(pVM);
1717
1718	/* Get the current privilege level. */
1719	if (CPUMGetGuestCPL(pVCpu) != 0)
1720	{
1721	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1722	return VERR_EM_INTERPRETER; /* supervisor only */
1723	}
1724
1725	uint64_t uValue;
1726	int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1727	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1728	{
1729	Assert(rc == VERR_CPUM_RAISE_GP_0);
1730	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
1731	return VERR_EM_INTERPRETER;
1732	}
1733	pRegFrame->rax = (uint32_t) uValue;
1734	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1735	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1736	return rc;
1737	}
1738
1739
1740	/**
1741	* Interpret WRMSR
1742	*
1743	* @returns VBox status code.
1744	* @param pVM Pointer to the VM.
1745	* @param pVCpu Pointer to the VMCPU.
1746	* @param pRegFrame The register frame.
1747	*/
1748	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1749	{
1750	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1751
1752	/* Check the current privilege level, this instruction is supervisor only. */
1753	if (CPUMGetGuestCPL(pVCpu) != 0)
1754	{
1755	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1756	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1757	}
1758
1759	int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1760	if (rc != VINF_SUCCESS)
1761	{
1762	Assert(rc == VERR_CPUM_RAISE_GP_0);
1763	Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
1764	return VERR_EM_INTERPRETER;
1765	}
1766	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1767	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1768	NOREF(pVM);
1769	return rc;
1770	}
1771
1772
1773	/**
1774	* Interpret CRx read.
1775	*
1776	* @returns VBox status code.
1777	* @param pVM Pointer to the VM.
1778	* @param pVCpu Pointer to the VMCPU.
1779	* @param pRegFrame The register frame.
1780	* @param DestRegGen General purpose register index (USE_REG_E**))
1781	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1782	*
1783	*/
1784	VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1785	{
1786	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1787	uint64_t val64;
1788	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1789	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1790	NOREF(pVM);
1791
1792	if (CPUMIsGuestIn64BitCode(pVCpu))
1793	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1794	else
1795	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1796
1797	if (RT_SUCCESS(rc))
1798	{
1799	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1800	return VINF_SUCCESS;
1801	}
1802	return VERR_EM_INTERPRETER;
1803	}
1804
1805
1806	/**
1807	* Interpret DRx write.
1808	*
1809	* @returns VBox status code.
1810	* @param pVM Pointer to the VM.
1811	* @param pVCpu Pointer to the VMCPU.
1812	* @param pRegFrame The register frame.
1813	* @param DestRegDRx DRx register index (USE_REG_DR*)
1814	* @param SrcRegGen General purpose register index (USE_REG_E**))
1815	*
1816	*/
1817	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1818	{
1819	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1820	uint64_t val;
1821	int rc;
1822	NOREF(pVM);
1823
1824	if (CPUMIsGuestIn64BitCode(pVCpu))
1825	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1826	else
1827	{
1828	uint32_t val32;
1829	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1830	val = val32;
1831	}
1832
1833	if (RT_SUCCESS(rc))
1834	{
1835	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1836	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, val);
1837	if (RT_SUCCESS(rc))
1838	return rc;
1839	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1840	}
1841	return VERR_EM_INTERPRETER;
1842	}
1843
1844
1845	/**
1846	* Interpret DRx read.
1847	*
1848	* @returns VBox status code.
1849	* @param pVM Pointer to the VM.
1850	* @param pVCpu Pointer to the VMCPU.
1851	* @param pRegFrame The register frame.
1852	* @param DestRegGen General purpose register index (USE_REG_E**))
1853	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1854	*
1855	*/
1856	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1857	{
1858	uint64_t val64;
1859	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1860	NOREF(pVM);
1861
1862	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1863	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1864	if (CPUMIsGuestIn64BitCode(pVCpu))
1865	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1866	else
1867	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1868
1869	if (RT_SUCCESS(rc))
1870	return VINF_SUCCESS;
1871
1872	return VERR_EM_INTERPRETER;
1873	}
1874
1875
1876	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1877
1878
1879
1880
1881
1882
1883	/*
1884	*
1885	* The old interpreter.
1886	* The old interpreter.
1887	* The old interpreter.
1888	* The old interpreter.
1889	* The old interpreter.
1890	*
1891	*/
1892
1893	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1894	{
1895	#ifdef IN_RC
1896	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1897	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1898	return rc;
1899	/*
1900	* The page pool cache may end up here in some cases because it
1901	* flushed one of the shadow mappings used by the trapping
1902	* instruction and it either flushed the TLB or the CPU reused it.
1903	*/
1904	#else
1905	NOREF(pVM);
1906	#endif
1907	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1908	}
1909
1910
1911	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1912	{
1913	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1914	pages or write monitored pages. */
1915	NOREF(pVM);
1916	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1917	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1918	#else
1919	int rc = VINF_SUCCESS;
1920	#endif
1921	#ifdef VBOX_COMPARE_IEM_AND_EM
1922	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1923	g_cbEmWrote = cb;
1924	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1925	#endif
1926	return rc;
1927	}
1928
1929
1930	/** Convert sel:addr to a flat GC address. */
1931	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1932	{
1933	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1934	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1935	}
1936
1937
1938	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1939	/**
1940	* Get the mnemonic for the disassembled instruction.
1941	*
1942	* GC/R0 doesn't include the strings in the DIS tables because
1943	* of limited space.
1944	*/
1945	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1946	{
1947	switch (pDis->pCurInstr->uOpcode)
1948	{
1949	case OP_XCHG: return "Xchg";
1950	case OP_DEC: return "Dec";
1951	case OP_INC: return "Inc";
1952	case OP_POP: return "Pop";
1953	case OP_OR: return "Or";
1954	case OP_AND: return "And";
1955	case OP_MOV: return "Mov";
1956	case OP_INVLPG: return "InvlPg";
1957	case OP_CPUID: return "CpuId";
1958	case OP_MOV_CR: return "MovCRx";
1959	case OP_MOV_DR: return "MovDRx";
1960	case OP_LLDT: return "LLdt";
1961	case OP_LGDT: return "LGdt";
1962	case OP_LIDT: return "LIdt";
1963	case OP_CLTS: return "Clts";
1964	case OP_MONITOR: return "Monitor";
1965	case OP_MWAIT: return "MWait";
1966	case OP_RDMSR: return "Rdmsr";
1967	case OP_WRMSR: return "Wrmsr";
1968	case OP_ADD: return "Add";
1969	case OP_ADC: return "Adc";
1970	case OP_SUB: return "Sub";
1971	case OP_SBB: return "Sbb";
1972	case OP_RDTSC: return "Rdtsc";
1973	case OP_STI: return "Sti";
1974	case OP_CLI: return "Cli";
1975	case OP_XADD: return "XAdd";
1976	case OP_HLT: return "Hlt";
1977	case OP_IRET: return "Iret";
1978	case OP_MOVNTPS: return "MovNTPS";
1979	case OP_STOSWD: return "StosWD";
1980	case OP_WBINVD: return "WbInvd";
1981	case OP_XOR: return "Xor";
1982	case OP_BTR: return "Btr";
1983	case OP_BTS: return "Bts";
1984	case OP_BTC: return "Btc";
1985	case OP_LMSW: return "Lmsw";
1986	case OP_SMSW: return "Smsw";
1987	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1988	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1989
1990	default:
1991	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1992	return "???";
1993	}
1994	}
1995	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1996
1997
1998	/**
1999	* XCHG instruction emulation.
2000	*/
2001	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2002	{
2003	DISQPVPARAMVAL param1, param2;
2004	NOREF(pvFault);
2005
2006	/* Source to make DISQueryParamVal read the register value - ugly hack */
2007	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2008	if(RT_FAILURE(rc))
2009	return VERR_EM_INTERPRETER;
2010
2011	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2012	if(RT_FAILURE(rc))
2013	return VERR_EM_INTERPRETER;
2014
2015	#ifdef IN_RC
2016	if (TRPMHasTrap(pVCpu))
2017	{
2018	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2019	{
2020	#endif
2021	RTGCPTR pParam1 = 0, pParam2 = 0;
2022	uint64_t valpar1, valpar2;
2023
2024	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2025	switch(param1.type)
2026	{
2027	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2028	valpar1 = param1.val.val64;
2029	break;
2030
2031	case DISQPV_TYPE_ADDRESS:
2032	pParam1 = (RTGCPTR)param1.val.val64;
2033	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2034	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2035	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2036	if (RT_FAILURE(rc))
2037	{
2038	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2039	return VERR_EM_INTERPRETER;
2040	}
2041	break;
2042
2043	default:
2044	AssertFailed();
2045	return VERR_EM_INTERPRETER;
2046	}
2047
2048	switch(param2.type)
2049	{
2050	case DISQPV_TYPE_ADDRESS:
2051	pParam2 = (RTGCPTR)param2.val.val64;
2052	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2053	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2054	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2055	if (RT_FAILURE(rc))
2056	{
2057	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2058	}
2059	break;
2060
2061	case DISQPV_TYPE_IMMEDIATE:
2062	valpar2 = param2.val.val64;
2063	break;
2064
2065	default:
2066	AssertFailed();
2067	return VERR_EM_INTERPRETER;
2068	}
2069
2070	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2071	if (pParam1 == 0)
2072	{
2073	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2074	switch(param1.size)
2075	{
2076	case 1: //special case for AH etc
2077	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2078	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2079	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2080	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2081	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2082	}
2083	if (RT_FAILURE(rc))
2084	return VERR_EM_INTERPRETER;
2085	}
2086	else
2087	{
2088	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2089	if (RT_FAILURE(rc))
2090	{
2091	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2092	return VERR_EM_INTERPRETER;
2093	}
2094	}
2095
2096	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2097	if (pParam2 == 0)
2098	{
2099	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2100	switch(param2.size)
2101	{
2102	case 1: //special case for AH etc
2103	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2104	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2105	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2106	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2107	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2108	}
2109	if (RT_FAILURE(rc))
2110	return VERR_EM_INTERPRETER;
2111	}
2112	else
2113	{
2114	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2115	if (RT_FAILURE(rc))
2116	{
2117	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2118	return VERR_EM_INTERPRETER;
2119	}
2120	}
2121
2122	*pcbSize = param2.size;
2123	return VINF_SUCCESS;
2124	#ifdef IN_RC
2125	}
2126	}
2127	return VERR_EM_INTERPRETER;
2128	#endif
2129	}
2130
2131
2132	/**
2133	* INC and DEC emulation.
2134	*/
2135	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2136	PFNEMULATEPARAM2 pfnEmulate)
2137	{
2138	DISQPVPARAMVAL param1;
2139	NOREF(pvFault);
2140
2141	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2142	if(RT_FAILURE(rc))
2143	return VERR_EM_INTERPRETER;
2144
2145	#ifdef IN_RC
2146	if (TRPMHasTrap(pVCpu))
2147	{
2148	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2149	{
2150	#endif
2151	RTGCPTR pParam1 = 0;
2152	uint64_t valpar1;
2153
2154	if (param1.type == DISQPV_TYPE_ADDRESS)
2155	{
2156	pParam1 = (RTGCPTR)param1.val.val64;
2157	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2158	#ifdef IN_RC
2159	/* Safety check (in theory it could cross a page boundary and fault there though) */
2160	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2161	#endif
2162	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2163	if (RT_FAILURE(rc))
2164	{
2165	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2166	return VERR_EM_INTERPRETER;
2167	}
2168	}
2169	else
2170	{
2171	AssertFailed();
2172	return VERR_EM_INTERPRETER;
2173	}
2174
2175	uint32_t eflags;
2176
2177	eflags = pfnEmulate(&valpar1, param1.size);
2178
2179	/* Write result back */
2180	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2181	if (RT_FAILURE(rc))
2182	{
2183	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2184	return VERR_EM_INTERPRETER;
2185	}
2186
2187	/* Update guest's eflags and finish. */
2188	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2189	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2190
2191	/* All done! */
2192	*pcbSize = param1.size;
2193	return VINF_SUCCESS;
2194	#ifdef IN_RC
2195	}
2196	}
2197	return VERR_EM_INTERPRETER;
2198	#endif
2199	}
2200
2201
2202	/**
2203	* POP Emulation.
2204	*/
2205	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2206	{
2207	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2208	DISQPVPARAMVAL param1;
2209	NOREF(pvFault);
2210
2211	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2212	if(RT_FAILURE(rc))
2213	return VERR_EM_INTERPRETER;
2214
2215	#ifdef IN_RC
2216	if (TRPMHasTrap(pVCpu))
2217	{
2218	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2219	{
2220	#endif
2221	RTGCPTR pParam1 = 0;
2222	uint32_t valpar1;
2223	RTGCPTR pStackVal;
2224
2225	/* Read stack value first */
2226	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2227	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2228
2229	/* Convert address; don't bother checking limits etc, as we only read here */
2230	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2231	if (pStackVal == 0)
2232	return VERR_EM_INTERPRETER;
2233
2234	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2235	if (RT_FAILURE(rc))
2236	{
2237	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2238	return VERR_EM_INTERPRETER;
2239	}
2240
2241	if (param1.type == DISQPV_TYPE_ADDRESS)
2242	{
2243	pParam1 = (RTGCPTR)param1.val.val64;
2244
2245	/* pop [esp+xx] uses esp after the actual pop! */
2246	AssertCompile(DISGREG_ESP == DISGREG_SP);
2247	if ( (pDis->Param1.fUse & DISUSE_BASE)
2248	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2249	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2250	)
2251	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2252
2253	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2254	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2255	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2256	if (RT_FAILURE(rc))
2257	{
2258	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2259	return VERR_EM_INTERPRETER;
2260	}
2261
2262	/* Update ESP as the last step */
2263	pRegFrame->esp += param1.size;
2264	}
2265	else
2266	{
2267	#ifndef DEBUG_bird // annoying assertion.
2268	AssertFailed();
2269	#endif
2270	return VERR_EM_INTERPRETER;
2271	}
2272
2273	/* All done! */
2274	*pcbSize = param1.size;
2275	return VINF_SUCCESS;
2276	#ifdef IN_RC
2277	}
2278	}
2279	return VERR_EM_INTERPRETER;
2280	#endif
2281	}
2282
2283
2284	/**
2285	* XOR/OR/AND Emulation.
2286	*/
2287	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2288	PFNEMULATEPARAM3 pfnEmulate)
2289	{
2290	DISQPVPARAMVAL param1, param2;
2291	NOREF(pvFault);
2292
2293	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2294	if(RT_FAILURE(rc))
2295	return VERR_EM_INTERPRETER;
2296
2297	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2298	if(RT_FAILURE(rc))
2299	return VERR_EM_INTERPRETER;
2300
2301	#ifdef IN_RC
2302	if (TRPMHasTrap(pVCpu))
2303	{
2304	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2305	{
2306	#endif
2307	RTGCPTR pParam1;
2308	uint64_t valpar1, valpar2;
2309
2310	if (pDis->Param1.cb != pDis->Param2.cb)
2311	{
2312	if (pDis->Param1.cb < pDis->Param2.cb)
2313	{
2314	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2315	return VERR_EM_INTERPRETER;
2316	}
2317	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2318	pDis->Param2.cb = pDis->Param1.cb;
2319	param2.size = param1.size;
2320	}
2321
2322	/* The destination is always a virtual address */
2323	if (param1.type == DISQPV_TYPE_ADDRESS)
2324	{
2325	pParam1 = (RTGCPTR)param1.val.val64;
2326	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2327	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2328	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2329	if (RT_FAILURE(rc))
2330	{
2331	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2332	return VERR_EM_INTERPRETER;
2333	}
2334	}
2335	else
2336	{
2337	AssertFailed();
2338	return VERR_EM_INTERPRETER;
2339	}
2340
2341	/* Register or immediate data */
2342	switch(param2.type)
2343	{
2344	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2345	valpar2 = param2.val.val64;
2346	break;
2347
2348	default:
2349	AssertFailed();
2350	return VERR_EM_INTERPRETER;
2351	}
2352
2353	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2354
2355	/* Data read, emulate instruction. */
2356	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2357
2358	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2359
2360	/* Update guest's eflags and finish. */
2361	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2362	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2363
2364	/* And write it back */
2365	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2366	if (RT_SUCCESS(rc))
2367	{
2368	/* All done! */
2369	*pcbSize = param2.size;
2370	return VINF_SUCCESS;
2371	}
2372	#ifdef IN_RC
2373	}
2374	}
2375	#endif
2376	return VERR_EM_INTERPRETER;
2377	}
2378
2379
2380	#ifndef VBOX_COMPARE_IEM_AND_EM
2381	/**
2382	* LOCK XOR/OR/AND Emulation.
2383	*/
2384	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2385	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2386	{
2387	void *pvParam1;
2388	DISQPVPARAMVAL param1, param2;
2389	NOREF(pvFault);
2390
2391	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2392	Assert(pDis->Param1.cb <= 4);
2393	#endif
2394
2395	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2396	if(RT_FAILURE(rc))
2397	return VERR_EM_INTERPRETER;
2398
2399	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2400	if(RT_FAILURE(rc))
2401	return VERR_EM_INTERPRETER;
2402
2403	if (pDis->Param1.cb != pDis->Param2.cb)
2404	{
2405	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2406	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2407	VERR_EM_INTERPRETER);
2408
2409	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2410	pDis->Param2.cb = pDis->Param1.cb;
2411	param2.size = param1.size;
2412	}
2413
2414	#ifdef IN_RC
2415	/* Safety check (in theory it could cross a page boundary and fault there though) */
2416	Assert( TRPMHasTrap(pVCpu)
2417	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2418	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2419	#endif
2420
2421	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2422	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2423	RTGCUINTREG ValPar2 = param2.val.val64;
2424
2425	/* The destination is always a virtual address */
2426	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2427
2428	RTGCPTR GCPtrPar1 = param1.val.val64;
2429	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2430	PGMPAGEMAPLOCK Lock;
2431	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2432	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2433
2434	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2435	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2436
2437	RTGCUINTREG32 eflags = 0;
2438	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2439	PGMPhysReleasePageMappingLock(pVM, &Lock);
2440	if (RT_FAILURE(rc))
2441	{
2442	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2443	return VERR_EM_INTERPRETER;
2444	}
2445
2446	/* Update guest's eflags and finish. */
2447	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2448	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2449
2450	*pcbSize = param2.size;
2451	return VINF_SUCCESS;
2452	}
2453	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2454
2455
2456	/**
2457	* ADD, ADC & SUB Emulation.
2458	*/
2459	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2460	PFNEMULATEPARAM3 pfnEmulate)
2461	{
2462	NOREF(pvFault);
2463	DISQPVPARAMVAL param1, param2;
2464	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2465	if(RT_FAILURE(rc))
2466	return VERR_EM_INTERPRETER;
2467
2468	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2469	if(RT_FAILURE(rc))
2470	return VERR_EM_INTERPRETER;
2471
2472	#ifdef IN_RC
2473	if (TRPMHasTrap(pVCpu))
2474	{
2475	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2476	{
2477	#endif
2478	RTGCPTR pParam1;
2479	uint64_t valpar1, valpar2;
2480
2481	if (pDis->Param1.cb != pDis->Param2.cb)
2482	{
2483	if (pDis->Param1.cb < pDis->Param2.cb)
2484	{
2485	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2486	return VERR_EM_INTERPRETER;
2487	}
2488	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2489	pDis->Param2.cb = pDis->Param1.cb;
2490	param2.size = param1.size;
2491	}
2492
2493	/* The destination is always a virtual address */
2494	if (param1.type == DISQPV_TYPE_ADDRESS)
2495	{
2496	pParam1 = (RTGCPTR)param1.val.val64;
2497	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2498	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2499	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2500	if (RT_FAILURE(rc))
2501	{
2502	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2503	return VERR_EM_INTERPRETER;
2504	}
2505	}
2506	else
2507	{
2508	#ifndef DEBUG_bird
2509	AssertFailed();
2510	#endif
2511	return VERR_EM_INTERPRETER;
2512	}
2513
2514	/* Register or immediate data */
2515	switch(param2.type)
2516	{
2517	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2518	valpar2 = param2.val.val64;
2519	break;
2520
2521	default:
2522	AssertFailed();
2523	return VERR_EM_INTERPRETER;
2524	}
2525
2526	/* Data read, emulate instruction. */
2527	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2528
2529	/* Update guest's eflags and finish. */
2530	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2531	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2532
2533	/* And write it back */
2534	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2535	if (RT_SUCCESS(rc))
2536	{
2537	/* All done! */
2538	*pcbSize = param2.size;
2539	return VINF_SUCCESS;
2540	}
2541	#ifdef IN_RC
2542	}
2543	}
2544	#endif
2545	return VERR_EM_INTERPRETER;
2546	}
2547
2548
2549	/**
2550	* ADC Emulation.
2551	*/
2552	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2553	{
2554	if (pRegFrame->eflags.Bits.u1CF)
2555	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2556	else
2557	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2558	}
2559
2560
2561	/**
2562	* BTR/C/S Emulation.
2563	*/
2564	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2565	PFNEMULATEPARAM2UINT32 pfnEmulate)
2566	{
2567	DISQPVPARAMVAL param1, param2;
2568	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2569	if(RT_FAILURE(rc))
2570	return VERR_EM_INTERPRETER;
2571
2572	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2573	if(RT_FAILURE(rc))
2574	return VERR_EM_INTERPRETER;
2575
2576	#ifdef IN_RC
2577	if (TRPMHasTrap(pVCpu))
2578	{
2579	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2580	{
2581	#endif
2582	RTGCPTR pParam1;
2583	uint64_t valpar1 = 0, valpar2;
2584	uint32_t eflags;
2585
2586	/* The destination is always a virtual address */
2587	if (param1.type != DISQPV_TYPE_ADDRESS)
2588	return VERR_EM_INTERPRETER;
2589
2590	pParam1 = (RTGCPTR)param1.val.val64;
2591	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2592
2593	/* Register or immediate data */
2594	switch(param2.type)
2595	{
2596	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2597	valpar2 = param2.val.val64;
2598	break;
2599
2600	default:
2601	AssertFailed();
2602	return VERR_EM_INTERPRETER;
2603	}
2604
2605	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2606	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2607	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
2608	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2609	if (RT_FAILURE(rc))
2610	{
2611	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2612	return VERR_EM_INTERPRETER;
2613	}
2614
2615	Log2(("emInterpretBtx: val=%x\n", valpar1));
2616	/* Data read, emulate bit test instruction. */
2617	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2618
2619	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2620
2621	/* Update guest's eflags and finish. */
2622	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2623	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2624
2625	/* And write it back */
2626	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2627	if (RT_SUCCESS(rc))
2628	{
2629	/* All done! */
2630	*pcbSize = 1;
2631	return VINF_SUCCESS;
2632	}
2633	#ifdef IN_RC
2634	}
2635	}
2636	#endif
2637	return VERR_EM_INTERPRETER;
2638	}
2639
2640
2641	#ifndef VBOX_COMPARE_IEM_AND_EM
2642	/**
2643	* LOCK BTR/C/S Emulation.
2644	*/
2645	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2646	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2647	{
2648	void *pvParam1;
2649
2650	DISQPVPARAMVAL param1, param2;
2651	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2652	if(RT_FAILURE(rc))
2653	return VERR_EM_INTERPRETER;
2654
2655	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2656	if(RT_FAILURE(rc))
2657	return VERR_EM_INTERPRETER;
2658
2659	/* The destination is always a virtual address */
2660	if (param1.type != DISQPV_TYPE_ADDRESS)
2661	return VERR_EM_INTERPRETER;
2662
2663	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2664	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2665	uint64_t ValPar2 = param2.val.val64;
2666
2667	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2668	RTGCPTR GCPtrPar1 = param1.val.val64;
2669	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2670	ValPar2 &= 7;
2671
2672	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2673	#ifdef IN_RC
2674	Assert(TRPMHasTrap(pVCpu));
2675	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2676	#endif
2677
2678	PGMPAGEMAPLOCK Lock;
2679	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2680	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2681
2682	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2683
2684	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2685	RTGCUINTREG32 eflags = 0;
2686	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2687	PGMPhysReleasePageMappingLock(pVM, &Lock);
2688	if (RT_FAILURE(rc))
2689	{
2690	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2691	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2692	return VERR_EM_INTERPRETER;
2693	}
2694
2695	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2696
2697	/* Update guest's eflags and finish. */
2698	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2699	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2700
2701	*pcbSize = 1;
2702	return VINF_SUCCESS;
2703	}
2704	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2705
2706
2707	/**
2708	* MOV emulation.
2709	*/
2710	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2711	{
2712	NOREF(pvFault);
2713	DISQPVPARAMVAL param1, param2;
2714	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2715	if(RT_FAILURE(rc))
2716	return VERR_EM_INTERPRETER;
2717
2718	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2719	if(RT_FAILURE(rc))
2720	return VERR_EM_INTERPRETER;
2721
2722	if (param1.type == DISQPV_TYPE_ADDRESS)
2723	{
2724	RTGCPTR pDest;
2725	uint64_t val64;
2726
2727	switch(param1.type)
2728	{
2729	case DISQPV_TYPE_IMMEDIATE:
2730	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2731	return VERR_EM_INTERPRETER;
2732	/* fallthru */
2733
2734	case DISQPV_TYPE_ADDRESS:
2735	pDest = (RTGCPTR)param1.val.val64;
2736	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2737	break;
2738
2739	default:
2740	AssertFailed();
2741	return VERR_EM_INTERPRETER;
2742	}
2743
2744	switch(param2.type)
2745	{
2746	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2747	val64 = param2.val.val64;
2748	break;
2749
2750	default:
2751	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2752	return VERR_EM_INTERPRETER;
2753	}
2754	#ifdef LOG_ENABLED
2755	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2756	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2757	else
2758	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2759	#endif
2760
2761	Assert(param2.size <= 8 && param2.size > 0);
2762	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2763	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2764	if (RT_FAILURE(rc))
2765	return VERR_EM_INTERPRETER;
2766
2767	*pcbSize = param2.size;
2768	}
2769	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2770	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2771	else if ( param1.type == DISQPV_TYPE_REGISTER
2772	&& param2.type == DISQPV_TYPE_REGISTER)
2773	{
2774	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2775	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2776	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2777
2778	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2779	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2780
2781	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2782	switch (param1.size)
2783	{
2784	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2785	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2786	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2787	default:
2788	AssertFailed();
2789	return VERR_EM_INTERPRETER;
2790	}
2791	AssertRCReturn(rc, rc);
2792	}
2793	#endif
2794	else
2795	{ /* read fault */
2796	RTGCPTR pSrc;
2797	uint64_t val64;
2798
2799	/* Source */
2800	switch(param2.type)
2801	{
2802	case DISQPV_TYPE_IMMEDIATE:
2803	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2804	return VERR_EM_INTERPRETER;
2805	/* fallthru */
2806
2807	case DISQPV_TYPE_ADDRESS:
2808	pSrc = (RTGCPTR)param2.val.val64;
2809	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2810	break;
2811
2812	default:
2813	return VERR_EM_INTERPRETER;
2814	}
2815
2816	Assert(param1.size <= 8 && param1.size > 0);
2817	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2818	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2819	if (RT_FAILURE(rc))
2820	return VERR_EM_INTERPRETER;
2821
2822	/* Destination */
2823	switch(param1.type)
2824	{
2825	case DISQPV_TYPE_REGISTER:
2826	switch(param1.size)
2827	{
2828	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2829	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2830	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2831	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2832	default:
2833	return VERR_EM_INTERPRETER;
2834	}
2835	if (RT_FAILURE(rc))
2836	return rc;
2837	break;
2838
2839	default:
2840	return VERR_EM_INTERPRETER;
2841	}
2842	#ifdef LOG_ENABLED
2843	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2844	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2845	else
2846	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2847	#endif
2848	}
2849	return VINF_SUCCESS;
2850	}
2851
2852
2853	#ifndef IN_RC
2854	/**
2855	* [REP] STOSWD emulation
2856	*/
2857	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2858	{
2859	int rc;
2860	RTGCPTR GCDest, GCOffset;
2861	uint32_t cbSize;
2862	uint64_t cTransfers;
2863	int offIncrement;
2864	NOREF(pvFault);
2865
2866	/* Don't support any but these three prefix bytes. */
2867	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2868	return VERR_EM_INTERPRETER;
2869
2870	switch (pDis->uAddrMode)
2871	{
2872	case DISCPUMODE_16BIT:
2873	GCOffset = pRegFrame->di;
2874	cTransfers = pRegFrame->cx;
2875	break;
2876	case DISCPUMODE_32BIT:
2877	GCOffset = pRegFrame->edi;
2878	cTransfers = pRegFrame->ecx;
2879	break;
2880	case DISCPUMODE_64BIT:
2881	GCOffset = pRegFrame->rdi;
2882	cTransfers = pRegFrame->rcx;
2883	break;
2884	default:
2885	AssertFailed();
2886	return VERR_EM_INTERPRETER;
2887	}
2888
2889	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2890	switch (pDis->uOpMode)
2891	{
2892	case DISCPUMODE_16BIT:
2893	cbSize = 2;
2894	break;
2895	case DISCPUMODE_32BIT:
2896	cbSize = 4;
2897	break;
2898	case DISCPUMODE_64BIT:
2899	cbSize = 8;
2900	break;
2901	default:
2902	AssertFailed();
2903	return VERR_EM_INTERPRETER;
2904	}
2905
2906	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2907
2908	if (!(pDis->fPrefix & DISPREFIX_REP))
2909	{
2910	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2911
2912	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2913	if (RT_FAILURE(rc))
2914	return VERR_EM_INTERPRETER;
2915	Assert(rc == VINF_SUCCESS);
2916
2917	/* Update (e/r)di. */
2918	switch (pDis->uAddrMode)
2919	{
2920	case DISCPUMODE_16BIT:
2921	pRegFrame->di += offIncrement;
2922	break;
2923	case DISCPUMODE_32BIT:
2924	pRegFrame->edi += offIncrement;
2925	break;
2926	case DISCPUMODE_64BIT:
2927	pRegFrame->rdi += offIncrement;
2928	break;
2929	default:
2930	AssertFailed();
2931	return VERR_EM_INTERPRETER;
2932	}
2933
2934	}
2935	else
2936	{
2937	if (!cTransfers)
2938	return VINF_SUCCESS;
2939
2940	/*
2941	* Do not try emulate cross page stuff here because we don't know what might
2942	* be waiting for us on the subsequent pages. The caller has only asked us to
2943	* ignore access handlers fro the current page.
2944	* This also fends off big stores which would quickly kill PGMR0DynMap.
2945	*/
2946	if ( cbSize > PAGE_SIZE
2947	\|\| cTransfers > PAGE_SIZE
2948	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2949	{
2950	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2951	GCDest, cbSize, offIncrement, cTransfers));
2952	return VERR_EM_INTERPRETER;
2953	}
2954
2955	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2956	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2957	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2958	cTransfers * cbSize,
2959	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2960	if (rc != VINF_SUCCESS)
2961	{
2962	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2963	return VERR_EM_INTERPRETER;
2964	}
2965
2966	/* REP case */
2967	while (cTransfers)
2968	{
2969	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2970	if (RT_FAILURE(rc))
2971	{
2972	rc = VERR_EM_INTERPRETER;
2973	break;
2974	}
2975
2976	Assert(rc == VINF_SUCCESS);
2977	GCOffset += offIncrement;
2978	GCDest += offIncrement;
2979	cTransfers--;
2980	}
2981
2982	/* Update the registers. */
2983	switch (pDis->uAddrMode)
2984	{
2985	case DISCPUMODE_16BIT:
2986	pRegFrame->di = GCOffset;
2987	pRegFrame->cx = cTransfers;
2988	break;
2989	case DISCPUMODE_32BIT:
2990	pRegFrame->edi = GCOffset;
2991	pRegFrame->ecx = cTransfers;
2992	break;
2993	case DISCPUMODE_64BIT:
2994	pRegFrame->rdi = GCOffset;
2995	pRegFrame->rcx = cTransfers;
2996	break;
2997	default:
2998	AssertFailed();
2999	return VERR_EM_INTERPRETER;
3000	}
3001	}
3002
3003	*pcbSize = cbSize;
3004	return rc;
3005	}
3006	#endif /* !IN_RC */
3007
3008
3009	/**
3010	* [LOCK] CMPXCHG emulation.
3011	*/
3012	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3013	{
3014	DISQPVPARAMVAL param1, param2;
3015	NOREF(pvFault);
3016
3017	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
3018	Assert(pDis->Param1.cb <= 4);
3019	#endif
3020
3021	/* Source to make DISQueryParamVal read the register value - ugly hack */
3022	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3023	if(RT_FAILURE(rc))
3024	return VERR_EM_INTERPRETER;
3025
3026	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3027	if(RT_FAILURE(rc))
3028	return VERR_EM_INTERPRETER;
3029
3030	uint64_t valpar;
3031	switch(param2.type)
3032	{
3033	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3034	valpar = param2.val.val64;
3035	break;
3036
3037	default:
3038	return VERR_EM_INTERPRETER;
3039	}
3040
3041	PGMPAGEMAPLOCK Lock;
3042	RTGCPTR GCPtrPar1;
3043	void *pvParam1;
3044	uint64_t eflags;
3045
3046	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3047	switch(param1.type)
3048	{
3049	case DISQPV_TYPE_ADDRESS:
3050	GCPtrPar1 = param1.val.val64;
3051	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3052
3053	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3054	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3055	break;
3056
3057	default:
3058	return VERR_EM_INTERPRETER;
3059	}
3060
3061	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3062
3063	#ifndef VBOX_COMPARE_IEM_AND_EM
3064	if (pDis->fPrefix & DISPREFIX_LOCK)
3065	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3066	else
3067	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3068	#else /* VBOX_COMPARE_IEM_AND_EM */
3069	uint64_t u64;
3070	switch (pDis->Param2.cb)
3071	{
3072	case 1: u64 = (uint8_t )pvParam1; break;
3073	case 2: u64 = (uint16_t )pvParam1; break;
3074	case 4: u64 = (uint32_t )pvParam1; break;
3075	default:
3076	case 8: u64 = (uint64_t )pvParam1; break;
3077	}
3078	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3079	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3080	#endif /* VBOX_COMPARE_IEM_AND_EM */
3081
3082	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3083
3084	/* Update guest's eflags and finish. */
3085	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3086	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3087
3088	*pcbSize = param2.size;
3089	PGMPhysReleasePageMappingLock(pVM, &Lock);
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/**
3095	* [LOCK] CMPXCHG8B emulation.
3096	*/
3097	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3098	{
3099	DISQPVPARAMVAL param1;
3100	NOREF(pvFault);
3101
3102	/* Source to make DISQueryParamVal read the register value - ugly hack */
3103	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3104	if(RT_FAILURE(rc))
3105	return VERR_EM_INTERPRETER;
3106
3107	RTGCPTR GCPtrPar1;
3108	void *pvParam1;
3109	uint64_t eflags;
3110	PGMPAGEMAPLOCK Lock;
3111
3112	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3113	switch(param1.type)
3114	{
3115	case DISQPV_TYPE_ADDRESS:
3116	GCPtrPar1 = param1.val.val64;
3117	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3118
3119	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3120	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3121	break;
3122
3123	default:
3124	return VERR_EM_INTERPRETER;
3125	}
3126
3127	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
3128
3129	#ifndef VBOX_COMPARE_IEM_AND_EM
3130	if (pDis->fPrefix & DISPREFIX_LOCK)
3131	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3132	else
3133	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3134	#else /* VBOX_COMPARE_IEM_AND_EM */
3135	uint64_t u64 = (uint64_t )pvParam1;
3136	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3137	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3138	#endif /* VBOX_COMPARE_IEM_AND_EM */
3139
3140	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3141
3142	/* Update guest's eflags and finish; note that only ZF is affected. */
3143	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3144	\| (eflags & (X86_EFL_ZF));
3145
3146	*pcbSize = 8;
3147	PGMPhysReleasePageMappingLock(pVM, &Lock);
3148	return VINF_SUCCESS;
3149	}
3150
3151
3152	#ifdef IN_RC /** @todo test+enable for HM as well. */
3153	/**
3154	* [LOCK] XADD emulation.
3155	*/
3156	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3157	{
3158	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3159	DISQPVPARAMVAL param1;
3160	void *pvParamReg2;
3161	size_t cbParamReg2;
3162	NOREF(pvFault);
3163
3164	/* Source to make DISQueryParamVal read the register value - ugly hack */
3165	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3166	if(RT_FAILURE(rc))
3167	return VERR_EM_INTERPRETER;
3168
3169	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3170	Assert(cbParamReg2 <= 4);
3171	if(RT_FAILURE(rc))
3172	return VERR_EM_INTERPRETER;
3173
3174	#ifdef IN_RC
3175	if (TRPMHasTrap(pVCpu))
3176	{
3177	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3178	{
3179	#endif
3180	RTGCPTR GCPtrPar1;
3181	void *pvParam1;
3182	uint32_t eflags;
3183	PGMPAGEMAPLOCK Lock;
3184
3185	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3186	switch(param1.type)
3187	{
3188	case DISQPV_TYPE_ADDRESS:
3189	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3190	#ifdef IN_RC
3191	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3192	#endif
3193
3194	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3195	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3196	break;
3197
3198	default:
3199	return VERR_EM_INTERPRETER;
3200	}
3201
3202	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3203
3204	#ifndef VBOX_COMPARE_IEM_AND_EM
3205	if (pDis->fPrefix & DISPREFIX_LOCK)
3206	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3207	else
3208	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3209	#else /* VBOX_COMPARE_IEM_AND_EM */
3210	uint64_t u64;
3211	switch (cbParamReg2)
3212	{
3213	case 1: u64 = (uint8_t )pvParam1; break;
3214	case 2: u64 = (uint16_t )pvParam1; break;
3215	case 4: u64 = (uint32_t )pvParam1; break;
3216	default:
3217	case 8: u64 = (uint64_t )pvParam1; break;
3218	}
3219	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3220	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3221	#endif /* VBOX_COMPARE_IEM_AND_EM */
3222
3223	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3224
3225	/* Update guest's eflags and finish. */
3226	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3227	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3228
3229	*pcbSize = cbParamReg2;
3230	PGMPhysReleasePageMappingLock(pVM, &Lock);
3231	return VINF_SUCCESS;
3232	#ifdef IN_RC
3233	}
3234	}
3235
3236	return VERR_EM_INTERPRETER;
3237	#endif
3238	}
3239	#endif /* IN_RC */
3240
3241
3242	/**
3243	* WBINVD Emulation.
3244	*/
3245	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3246	{
3247	/* Nothing to do. */
3248	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3249	return VINF_SUCCESS;
3250	}
3251
3252
3253	/**
3254	* INVLPG Emulation.
3255	*/
3256	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3257	{
3258	DISQPVPARAMVAL param1;
3259	RTGCPTR addr;
3260	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3261
3262	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3263	if(RT_FAILURE(rc))
3264	return VERR_EM_INTERPRETER;
3265
3266	switch(param1.type)
3267	{
3268	case DISQPV_TYPE_IMMEDIATE:
3269	case DISQPV_TYPE_ADDRESS:
3270	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3271	return VERR_EM_INTERPRETER;
3272	addr = (RTGCPTR)param1.val.val64;
3273	break;
3274
3275	default:
3276	return VERR_EM_INTERPRETER;
3277	}
3278
3279	/** @todo is addr always a flat linear address or ds based
3280	* (in absence of segment override prefixes)????
3281	*/
3282	#ifdef IN_RC
3283	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3284	#endif
3285	rc = PGMInvalidatePage(pVCpu, addr);
3286	if ( rc == VINF_SUCCESS
3287	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3288	return VINF_SUCCESS;
3289	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3290	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3291	VERR_EM_INTERPRETER);
3292	return rc;
3293	}
3294
3295	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3296
3297	/**
3298	* CPUID Emulation.
3299	*/
3300	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3301	{
3302	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3303	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3304	return rc;
3305	}
3306
3307
3308	/**
3309	* CLTS Emulation.
3310	*/
3311	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3312	{
3313	NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3314	return EMInterpretCLTS(pVM, pVCpu);
3315	}
3316
3317
3318	/**
3319	* LMSW Emulation.
3320	*/
3321	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3322	{
3323	DISQPVPARAMVAL param1;
3324	uint32_t val;
3325	NOREF(pvFault); NOREF(pcbSize);
3326
3327	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3328	if(RT_FAILURE(rc))
3329	return VERR_EM_INTERPRETER;
3330
3331	switch(param1.type)
3332	{
3333	case DISQPV_TYPE_IMMEDIATE:
3334	case DISQPV_TYPE_ADDRESS:
3335	if(!(param1.flags & DISQPV_FLAG_16))
3336	return VERR_EM_INTERPRETER;
3337	val = param1.val.val32;
3338	break;
3339
3340	default:
3341	return VERR_EM_INTERPRETER;
3342	}
3343
3344	LogFlow(("emInterpretLmsw %x\n", val));
3345	return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
3346	}
3347
3348	#ifdef EM_EMULATE_SMSW
3349	/**
3350	* SMSW Emulation.
3351	*/
3352	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3353	{
3354	DISQPVPARAMVAL param1;
3355	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3356
3357	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3358	if(RT_FAILURE(rc))
3359	return VERR_EM_INTERPRETER;
3360
3361	switch(param1.type)
3362	{
3363	case DISQPV_TYPE_IMMEDIATE:
3364	if(param1.size != sizeof(uint16_t))
3365	return VERR_EM_INTERPRETER;
3366	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3367	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3368	break;
3369
3370	case DISQPV_TYPE_ADDRESS:
3371	{
3372	RTGCPTR pParam1;
3373
3374	/* Actually forced to 16 bits regardless of the operand size. */
3375	if(param1.size != sizeof(uint16_t))
3376	return VERR_EM_INTERPRETER;
3377
3378	pParam1 = (RTGCPTR)param1.val.val64;
3379	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3380	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3381
3382	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3383	if (RT_FAILURE(rc))
3384	{
3385	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3386	return VERR_EM_INTERPRETER;
3387	}
3388	break;
3389	}
3390
3391	default:
3392	return VERR_EM_INTERPRETER;
3393	}
3394
3395	LogFlow(("emInterpretSmsw %x\n", cr0));
3396	return rc;
3397	}
3398	#endif
3399
3400	/**
3401	* MOV CRx
3402	*/
3403	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3404	{
3405	NOREF(pvFault); NOREF(pcbSize);
3406	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3407	return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3408
3409	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3410	return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3411
3412	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3413	}
3414
3415
3416	/**
3417	* MOV DRx
3418	*/
3419	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3420	{
3421	int rc = VERR_EM_INTERPRETER;
3422	NOREF(pvFault); NOREF(pcbSize);
3423
3424	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3425	{
3426	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3427	}
3428	else
3429	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3430	{
3431	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3432	}
3433	else
3434	AssertMsgFailed(("Unexpected debug register move\n"));
3435
3436	return rc;
3437	}
3438
3439
3440	/**
3441	* LLDT Emulation.
3442	*/
3443	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3444	{
3445	DISQPVPARAMVAL param1;
3446	RTSEL sel;
3447	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3448
3449	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3450	if(RT_FAILURE(rc))
3451	return VERR_EM_INTERPRETER;
3452
3453	switch(param1.type)
3454	{
3455	case DISQPV_TYPE_ADDRESS:
3456	return VERR_EM_INTERPRETER; //feeling lazy right now
3457
3458	case DISQPV_TYPE_IMMEDIATE:
3459	if(!(param1.flags & DISQPV_FLAG_16))
3460	return VERR_EM_INTERPRETER;
3461	sel = (RTSEL)param1.val.val16;
3462	break;
3463
3464	default:
3465	return VERR_EM_INTERPRETER;
3466	}
3467
3468	#ifdef IN_RING0
3469	/* Only for the VT-x real-mode emulation case. */
3470	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3471	CPUMSetGuestLDTR(pVCpu, sel);
3472	return VINF_SUCCESS;
3473	#else
3474	if (sel == 0)
3475	{
3476	if (CPUMGetHyperLDTR(pVCpu) == 0)
3477	{
3478	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3479	return VINF_SUCCESS;
3480	}
3481	}
3482	//still feeling lazy
3483	return VERR_EM_INTERPRETER;
3484	#endif
3485	}
3486
3487	#ifdef IN_RING0
3488	/**
3489	* LIDT/LGDT Emulation.
3490	*/
3491	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3492	{
3493	DISQPVPARAMVAL param1;
3494	RTGCPTR pParam1;
3495	X86XDTR32 dtr32;
3496	NOREF(pvFault); NOREF(pcbSize);
3497
3498	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3499
3500	/* Only for the VT-x real-mode emulation case. */
3501	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3502
3503	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3504	if(RT_FAILURE(rc))
3505	return VERR_EM_INTERPRETER;
3506
3507	switch(param1.type)
3508	{
3509	case DISQPV_TYPE_ADDRESS:
3510	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3511	break;
3512
3513	default:
3514	return VERR_EM_INTERPRETER;
3515	}
3516
3517	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3518	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3519
3520	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3521	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3522
3523	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3524	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3525	else
3526	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3527
3528	return VINF_SUCCESS;
3529	}
3530	#endif
3531
3532
3533	#ifdef IN_RC
3534	/**
3535	* STI Emulation.
3536	*
3537	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3538	*/
3539	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3540	{
3541	NOREF(pcbSize);
3542	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3543
3544	if(!pGCState)
3545	{
3546	Assert(pGCState);
3547	return VERR_EM_INTERPRETER;
3548	}
3549	pGCState->uVMFlags \|= X86_EFL_IF;
3550
3551	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3552	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3553
3554	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3555	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3556
3557	return VINF_SUCCESS;
3558	}
3559	#endif /* IN_RC */
3560
3561
3562	/**
3563	* HLT Emulation.
3564	*/
3565	static VBOXSTRICTRC
3566	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3567	{
3568	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3569	return VINF_EM_HALT;
3570	}
3571
3572
3573	/**
3574	* RDTSC Emulation.
3575	*/
3576	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3577	{
3578	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3579	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3580	}
3581
3582	/**
3583	* RDPMC Emulation
3584	*/
3585	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3586	{
3587	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3588	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3589	}
3590
3591
3592	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3593	{
3594	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3595	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3596	}
3597
3598
3599	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3600	{
3601	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3602	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3603	}
3604
3605
3606	/**
3607	* RDMSR Emulation.
3608	*/
3609	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3610	{
3611	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3612	different, so we play safe by completely disassembling the instruction. */
3613	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3614	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3615	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3616	}
3617
3618
3619	/**
3620	* WRMSR Emulation.
3621	*/
3622	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3623	{
3624	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3625	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3626	}
3627
3628
3629	/**
3630	* Internal worker.
3631	* @copydoc emInterpretInstructionCPUOuter
3632	*/
3633	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3634	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3635	{
3636	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3637	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3638	Assert(pcbSize);
3639	*pcbSize = 0;
3640
3641	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3642	{
3643	/*
3644	* Only supervisor guest code!!
3645	* And no complicated prefixes.
3646	*/
3647	/* Get the current privilege level. */
3648	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3649	#ifdef VBOX_WITH_RAW_RING1
3650	if ( !EMIsRawRing1Enabled(pVM)
3651	\|\| cpl > 1
3652	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3653	)
3654	#endif
3655	{
3656	if ( cpl != 0
3657	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3658	{
3659	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3660	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3661	return VERR_EM_INTERPRETER;
3662	}
3663	}
3664	}
3665	else
3666	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3667
3668	#ifdef IN_RC
3669	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3670	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3671	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3672	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3673	&& pDis->pCurInstr->uOpcode != OP_XADD
3674	&& pDis->pCurInstr->uOpcode != OP_OR
3675	&& pDis->pCurInstr->uOpcode != OP_AND
3676	&& pDis->pCurInstr->uOpcode != OP_XOR
3677	&& pDis->pCurInstr->uOpcode != OP_BTR
3678	)
3679	)
3680	#else
3681	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3682	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3683	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3684	)
3685	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3686	&& pDis->pCurInstr->uOpcode != OP_OR
3687	&& pDis->pCurInstr->uOpcode != OP_AND
3688	&& pDis->pCurInstr->uOpcode != OP_XOR
3689	&& pDis->pCurInstr->uOpcode != OP_BTR
3690	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3691	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3692	)
3693	)
3694	#endif
3695	{
3696	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3697	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3698	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3699	return VERR_EM_INTERPRETER;
3700	}
3701
3702	#if HC_ARCH_BITS == 32
3703	/*
3704	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3705	* Whitelisted instructions are safe.
3706	*/
3707	if ( pDis->Param1.cb > 4
3708	&& CPUMIsGuestIn64BitCode(pVCpu))
3709	{
3710	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3711	if ( uOpCode != OP_STOSWD
3712	&& uOpCode != OP_MOV
3713	&& uOpCode != OP_CMPXCHG8B
3714	&& uOpCode != OP_XCHG
3715	&& uOpCode != OP_BTS
3716	&& uOpCode != OP_BTR
3717	&& uOpCode != OP_BTC
3718	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3719	&& uOpCode != OP_CMPXCHG /* solaris */
3720	&& uOpCode != OP_AND /* windows */
3721	&& uOpCode != OP_OR /* windows */
3722	&& uOpCode != OP_XOR /* because we can */
3723	&& uOpCode != OP_ADD /* windows (dripple) */
3724	&& uOpCode != OP_ADC /* because we can */
3725	&& uOpCode != OP_SUB /* because we can */
3726	/** @todo OP_BTS or is that a different kind of failure? */
3727	# endif
3728	)
3729	{
3730	# ifdef VBOX_WITH_STATISTICS
3731	switch (pDis->pCurInstr->uOpcode)
3732	{
3733	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3734	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3735	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3736	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3737	INTERPRET_FAILED_CASE(OP_INC,Inc);
3738	INTERPRET_FAILED_CASE(OP_POP,Pop);
3739	INTERPRET_FAILED_CASE(OP_OR, Or);
3740	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3741	INTERPRET_FAILED_CASE(OP_AND,And);
3742	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3743	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3744	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3745	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3746	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3747	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3748	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3749	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3750	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3751	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3752	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3753	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3754	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3755	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3756	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3757	INTERPRET_FAILED_CASE(OP_ADD,Add);
3758	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3759	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3760	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3761	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3762	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3763	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3764	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3765	INTERPRET_FAILED_CASE(OP_STI, Sti);
3766	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3767	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3768	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3769	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3770	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3771	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3772	# undef INTERPRET_FAILED_CASE
3773	default:
3774	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3775	break;
3776	}
3777	# endif /* VBOX_WITH_STATISTICS */
3778	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3779	return VERR_EM_INTERPRETER;
3780	}
3781	}
3782	#endif
3783
3784	VBOXSTRICTRC rc;
3785	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3786	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3787	#endif
3788	switch (pDis->pCurInstr->uOpcode)
3789	{
3790	/*
3791	* Macros for generating the right case statements.
3792	*/
3793	# ifndef VBOX_COMPARE_IEM_AND_EM
3794	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3795	case opcode:\
3796	if (pDis->fPrefix & DISPREFIX_LOCK) \
3797	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3798	else \
3799	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3800	if (RT_SUCCESS(rc)) \
3801	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3802	else \
3803	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3804	return rc
3805	# else /* VBOX_COMPARE_IEM_AND_EM */
3806	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3807	case opcode:\
3808	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3809	if (RT_SUCCESS(rc)) \
3810	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3811	else \
3812	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3813	return rc
3814	# endif /* VBOX_COMPARE_IEM_AND_EM */
3815
3816	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3817	case opcode:\
3818	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3819	if (RT_SUCCESS(rc)) \
3820	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3821	else \
3822	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3823	return rc
3824
3825	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3826	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3827	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3828	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3829
3830	#define INTERPRET_CASE(opcode, Instr) \
3831	case opcode:\
3832	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3833	if (RT_SUCCESS(rc)) \
3834	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3835	else \
3836	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3837	return rc
3838
3839	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3840	case opcode:\
3841	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3842	if (RT_SUCCESS(rc)) \
3843	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3844	else \
3845	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3846	return rc
3847
3848	#define INTERPRET_STAT_CASE(opcode, Instr) \
3849	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3850
3851	/*
3852	* The actual case statements.
3853	*/
3854	INTERPRET_CASE(OP_XCHG,Xchg);
3855	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3856	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3857	INTERPRET_CASE(OP_POP,Pop);
3858	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3859	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3860	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3861	INTERPRET_CASE(OP_MOV,Mov);
3862	#ifndef IN_RC
3863	INTERPRET_CASE(OP_STOSWD,StosWD);
3864	#endif
3865	INTERPRET_CASE(OP_INVLPG,InvlPg);
3866	INTERPRET_CASE(OP_CPUID,CpuId);
3867	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3868	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3869	#ifdef IN_RING0
3870	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3871	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3872	#endif
3873	INTERPRET_CASE(OP_LLDT,LLdt);
3874	INTERPRET_CASE(OP_LMSW,Lmsw);
3875	#ifdef EM_EMULATE_SMSW
3876	INTERPRET_CASE(OP_SMSW,Smsw);
3877	#endif
3878	INTERPRET_CASE(OP_CLTS,Clts);
3879	INTERPRET_CASE(OP_MONITOR, Monitor);
3880	INTERPRET_CASE(OP_MWAIT, MWait);
3881	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3882	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3883	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3884	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3885	INTERPRET_CASE(OP_ADC,Adc);
3886	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3887	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3888	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3889	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3890	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3891	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3892	#ifdef IN_RC
3893	INTERPRET_CASE(OP_STI,Sti);
3894	INTERPRET_CASE(OP_XADD, XAdd);
3895	INTERPRET_CASE(OP_IRET,Iret);
3896	#endif
3897	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3898	INTERPRET_CASE(OP_HLT,Hlt);
3899	INTERPRET_CASE(OP_WBINVD,WbInvd);
3900	#ifdef VBOX_WITH_STATISTICS
3901	# ifndef IN_RC
3902	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3903	# endif
3904	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3905	#endif
3906
3907	default:
3908	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3909	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3910	return VERR_EM_INTERPRETER;
3911
3912	#undef INTERPRET_CASE_EX_PARAM2
3913	#undef INTERPRET_STAT_CASE
3914	#undef INTERPRET_CASE_EX
3915	#undef INTERPRET_CASE
3916	} /* switch (opcode) */
3917	/* not reached */
3918	}
3919
3920	/**
3921	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3922	*
3923	* EIP is NOT updated!
3924	*
3925	* @returns VBox strict status code.
3926	* @retval VINF_* Scheduling instructions. When these are returned, it
3927	* starts to get a bit tricky to know whether code was
3928	* executed or not... We'll address this when it becomes a problem.
3929	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3930	* @retval VERR_* Fatal errors.
3931	*
3932	* @param pVCpu Pointer to the VMCPU.
3933	* @param pDis The disassembler cpu state for the instruction to be
3934	* interpreted.
3935	* @param pRegFrame The register frame. EIP is NOT changed!
3936	* @param pvFault The fault address (CR2).
3937	* @param pcbSize Size of the write (if applicable).
3938	* @param enmCodeType Code type (user/supervisor)
3939	*
3940	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3941	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3942	* to worry about e.g. invalid modrm combinations (!)
3943	*
3944	* @todo At this time we do NOT check if the instruction overwrites vital information.
3945	* Make sure this can't happen!! (will add some assertions/checks later)
3946	*/
3947	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3948	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3949	{
3950	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3951	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3952	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3953	if (RT_SUCCESS(rc))
3954	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3955	else
3956	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3957	return rc;
3958	}
3959
3960
3961	#endif /* !VBOX_WITH_IEM */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 48569

Download in other formats: