EMAll.cpp@ 50590

Last change on this file since 50590 was 49975, checked in by vboxsync, 11 years ago
EM: Make sure the RA1 and RAZ bits of DR6 and DR7 are enforced. Fixes netware debug assertion in HM.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 140.5 KB

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1	/* $Id: EMAll.cpp 49975 2013-12-18 14:04:47Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_EM
22	#include <VBox/vmm/em.h>
23	#include <VBox/vmm/mm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/pgm.h>
28	#ifdef VBOX_WITH_IEM
29	# include <VBox/vmm/iem.h>
30	#endif
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/stam.h>
33	#include "EMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/vmm.h>
36	#include <VBox/vmm/hm.h>
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/pdmapi.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <VBox/dis.h>
42	#include <VBox/disopcode.h>
43	#include <VBox/log.h>
44	#include "internal/pgm.h"
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49	#ifndef IN_RC
50	#undef VBOX_WITH_IEM
51	#endif
52	#ifdef VBOX_WITH_IEM
53	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
54	//# define VBOX_SAME_AS_EM
55	//# define VBOX_COMPARE_IEM_LAST
56	#endif
57
58	#ifdef VBOX_WITH_RAW_RING1
59	# define EM_EMULATE_SMSW
60	#endif
61
62
63	/*******************************************************************************
64	* Defined Constants And Macros *
65	*******************************************************************************/
66	/** @def EM_ASSERT_FAULT_RETURN
67	* Safety check.
68	*
69	* Could in theory misfire on a cross page boundary access...
70	*
71	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
72	* turns up an alias page instead of the original faulting one and annoying the
73	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
74	*/
75	#if 0
76	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
77	#else
78	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
79	#endif
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
86	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
87	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
88	#endif
89
90
91	/*******************************************************************************
92	* Global Variables *
93	*******************************************************************************/
94	#ifdef VBOX_COMPARE_IEM_AND_EM
95	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
96	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
97	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
98	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
99	static uint32_t g_fIncomingFFs;
100	static CPUMCTX g_IncomingCtx;
101	static bool g_fIgnoreRaxRdx = false;
102
103	static uint32_t g_fEmFFs;
104	static CPUMCTX g_EmCtx;
105	static uint8_t g_abEmWrote[256];
106	static size_t g_cbEmWrote;
107
108	static uint32_t g_fIemFFs;
109	static CPUMCTX g_IemCtx;
110	extern uint8_t g_abIemWrote[256];
111	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
112	extern size_t g_cbIemWrote;
113	#else
114	static size_t g_cbIemWrote;
115	#endif
116	#endif
117
118
119	/**
120	* Get the current execution manager status.
121	*
122	* @returns Current status.
123	* @param pVCpu Pointer to the VMCPU.
124	*/
125	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
126	{
127	return pVCpu->em.s.enmState;
128	}
129
130	/**
131	* Sets the current execution manager status. (use only when you know what you're doing!)
132	*
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
136	{
137	/* Only allowed combination: */
138	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
139	pVCpu->em.s.enmState = enmNewState;
140	}
141
142
143	/**
144	* Sets the PC for which interrupts should be inhibited.
145	*
146	* @param pVCpu Pointer to the VMCPU.
147	* @param PC The PC.
148	*/
149	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
150	{
151	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
152	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
153	}
154
155
156	/**
157	* Gets the PC for which interrupts should be inhibited.
158	*
159	* There are a few instructions which inhibits or delays interrupts
160	* for the instruction following them. These instructions are:
161	* - STI
162	* - MOV SS, r/m16
163	* - POP SS
164	*
165	* @returns The PC for which interrupts should be inhibited.
166	* @param pVCpu Pointer to the VMCPU.
167	*
168	*/
169	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
170	{
171	return pVCpu->em.s.GCPtrInhibitInterrupts;
172	}
173
174
175	/**
176	* Prepare an MWAIT - essentials of the MONITOR instruction.
177	*
178	* @returns VINF_SUCCESS
179	* @param pVCpu The current CPU.
180	* @param rax The content of RAX.
181	* @param rcx The content of RCX.
182	* @param rdx The content of RDX.
183	* @param GCPhys The physical address corresponding to rax.
184	*/
185	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
186	{
187	pVCpu->em.s.MWait.uMonitorRAX = rax;
188	pVCpu->em.s.MWait.uMonitorRCX = rcx;
189	pVCpu->em.s.MWait.uMonitorRDX = rdx;
190	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
191	/** @todo Make use of GCPhys. */
192	NOREF(GCPhys);
193	/** @todo Complete MONITOR implementation. */
194	return VINF_SUCCESS;
195	}
196
197
198	/**
199	* Performs an MWAIT.
200	*
201	* @returns VINF_SUCCESS
202	* @param pVCpu The current CPU.
203	* @param rax The content of RAX.
204	* @param rcx The content of RCX.
205	*/
206	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
207	{
208	pVCpu->em.s.MWait.uMWaitRAX = rax;
209	pVCpu->em.s.MWait.uMWaitRCX = rcx;
210	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
211	if (rcx)
212	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
213	else
214	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
215	/** @todo not completely correct?? */
216	return VINF_EM_HALT;
217	}
218
219
220
221	/**
222	* Determine if we should continue after encountering a mwait instruction.
223	*
224	* Clears MWAIT flags if returning @c true.
225	*
226	* @returns true if we should continue, false if we should halt.
227	* @param pVCpu Pointer to the VMCPU.
228	* @param pCtx Current CPU context.
229	*/
230	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
231	{
232	if ( pCtx->eflags.Bits.u1IF
233	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
234	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
235	{
236	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
237	{
238	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
239	return true;
240	}
241	}
242
243	return false;
244	}
245
246
247	/**
248	* Determine if we should continue after encountering a hlt instruction.
249	*
250	* @returns true if we should continue, false if we should halt.
251	* @param pVCpu Pointer to the VMCPU.
252	* @param pCtx Current CPU context.
253	*/
254	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
255	{
256	if (pCtx->eflags.Bits.u1IF)
257	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
258	return false;
259	}
260
261
262	/**
263	* Locks REM execution to a single VCPU.
264	*
265	* @param pVM Pointer to the VM.
266	*/
267	VMMDECL(void) EMRemLock(PVM pVM)
268	{
269	#ifdef VBOX_WITH_REM
270	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
271	return; /* early init */
272
273	Assert(!PGMIsLockOwner(pVM));
274	Assert(!IOMIsLockWriteOwner(pVM));
275	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
276	AssertRCSuccess(rc);
277	#endif
278	}
279
280
281	/**
282	* Unlocks REM execution
283	*
284	* @param pVM Pointer to the VM.
285	*/
286	VMMDECL(void) EMRemUnlock(PVM pVM)
287	{
288	#ifdef VBOX_WITH_REM
289	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
290	return; /* early init */
291
292	PDMCritSectLeave(&pVM->em.s.CritSectREM);
293	#endif
294	}
295
296
297	/**
298	* Check if this VCPU currently owns the REM lock.
299	*
300	* @returns bool owner/not owner
301	* @param pVM Pointer to the VM.
302	*/
303	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
304	{
305	#ifdef VBOX_WITH_REM
306	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
307	return true; /* early init */
308
309	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
310	#else
311	return true;
312	#endif
313	}
314
315
316	/**
317	* Try to acquire the REM lock.
318	*
319	* @returns VBox status code
320	* @param pVM Pointer to the VM.
321	*/
322	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
323	{
324	#ifdef VBOX_WITH_REM
325	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
326	return VINF_SUCCESS; /* early init */
327
328	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
329	#else
330	return VINF_SUCCESS;
331	#endif
332	}
333
334
335	/**
336	* @callback_method_impl{FNDISREADBYTES}
337	*/
338	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
339	{
340	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
341	#if defined(IN_RC) \|\| defined(IN_RING3)
342	PVM pVM = pVCpu->CTX_SUFF(pVM);
343	#endif
344	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
345	int rc;
346
347	/*
348	* Figure how much we can or must read.
349	*/
350	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
351	if (cbToRead > cbMaxRead)
352	cbToRead = cbMaxRead;
353	else if (cbToRead < cbMinRead)
354	cbToRead = cbMinRead;
355
356	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
357	/*
358	* We might be called upon to interpret an instruction in a patch.
359	*/
360	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
361	{
362	# ifdef IN_RC
363	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
364	# else
365	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
366	# endif
367	rc = VINF_SUCCESS;
368	}
369	else
370	#endif
371	{
372	# ifdef IN_RC
373	/*
374	* Try access it thru the shadow page tables first. Fall back on the
375	* slower PGM method if it fails because the TLB or page table was
376	* modified recently.
377	*/
378	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
379	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
380	{
381	cbToRead = cbMinRead;
382	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
383	}
384	if (rc == VERR_ACCESS_DENIED)
385	#endif
386	{
387	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
388	if (RT_FAILURE(rc))
389	{
390	if (cbToRead > cbMinRead)
391	{
392	cbToRead = cbMinRead;
393	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
394	}
395	if (RT_FAILURE(rc))
396	{
397	#ifndef IN_RC
398	/*
399	* If we fail to find the page via the guest's page tables
400	* we invalidate the page in the host TLB (pertaining to
401	* the guest in the NestedPaging case). See @bugref{6043}.
402	*/
403	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
404	{
405	HMInvalidatePage(pVCpu, uSrcAddr);
406	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
407	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
408	}
409	#endif
410	}
411	}
412	}
413	}
414
415	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
416	return rc;
417	}
418
419
420	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
421	{
422	NOREF(pVM);
423	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
424	}
425
426
427	/**
428	* Disassembles the current instruction.
429	*
430	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
431	* details.
432	*
433	* @param pVM Pointer to the VM.
434	* @param pVCpu Pointer to the VMCPU.
435	* @param pDis Where to return the parsed instruction info.
436	* @param pcbInstr Where to return the instruction size. (optional)
437	*/
438	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
439	{
440	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
441	RTGCPTR GCPtrInstr;
442	#if 0
443	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
444	#else
445	/** @todo Get the CPU mode as well while we're at it! */
446	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
447	pCtxCore->rip, &GCPtrInstr);
448	#endif
449	if (RT_FAILURE(rc))
450	{
451	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
452	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
453	return rc;
454	}
455	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
456	}
457
458
459	/**
460	* Disassembles one instruction.
461	*
462	* This is used by internally by the interpreter and by trap/access handlers.
463	*
464	* @returns VBox status code.
465	*
466	* @param pVM Pointer to the VM.
467	* @param pVCpu Pointer to the VMCPU.
468	* @param GCPtrInstr The flat address of the instruction.
469	* @param pCtxCore The context core (used to determine the cpu mode).
470	* @param pDis Where to return the parsed instruction info.
471	* @param pcbInstr Where to return the instruction size. (optional)
472	*/
473	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
474	PDISCPUSTATE pDis, unsigned *pcbInstr)
475	{
476	NOREF(pVM);
477	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu));
478	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
479	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
480	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
481	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
482	if (RT_SUCCESS(rc))
483	return VINF_SUCCESS;
484	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
485	return rc;
486	}
487
488
489	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
490	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
491	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
492	uint32_t cbEm, uint32_t cbIem)
493	{
494	/* Quick compare. */
495	if ( rcEm == rcIem
496	&& cbEm == cbIem
497	&& g_cbEmWrote == g_cbIemWrote
498	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
499	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
500	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
501	)
502	return;
503
504	/* Report exact differences. */
505	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
506	if (rcEm != rcIem)
507	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
508	else if (cbEm != cbIem)
509	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
510
511	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
512	{
513	if (g_cbIemWrote != g_cbEmWrote)
514	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
515	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
516	{
517	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
518	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
519	}
520
521	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
522	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
523	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
524
525	# define CHECK_FIELD(a_Field) \
526	do \
527	{ \
528	if (pEmCtx->a_Field != pIemCtx->a_Field) \
529	{ \
530	switch (sizeof(pEmCtx->a_Field)) \
531	{ \
532	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
533	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
534	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
535	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
536	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
537	} \
538	cDiffs++; \
539	} \
540	} while (0)
541
542	# define CHECK_BIT_FIELD(a_Field) \
543	do \
544	{ \
545	if (pEmCtx->a_Field != pIemCtx->a_Field) \
546	{ \
547	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
548	cDiffs++; \
549	} \
550	} while (0)
551
552	# define CHECK_SEL(a_Sel) \
553	do \
554	{ \
555	CHECK_FIELD(a_Sel.Sel); \
556	CHECK_FIELD(a_Sel.Attr.u); \
557	CHECK_FIELD(a_Sel.u64Base); \
558	CHECK_FIELD(a_Sel.u32Limit); \
559	CHECK_FIELD(a_Sel.fFlags); \
560	} while (0)
561
562	unsigned cDiffs = 0;
563	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
564	{
565	RTLogPrintf(" the FPU state differs\n");
566	cDiffs++;
567	CHECK_FIELD(fpu.FCW);
568	CHECK_FIELD(fpu.FSW);
569	CHECK_FIELD(fpu.FTW);
570	CHECK_FIELD(fpu.FOP);
571	CHECK_FIELD(fpu.FPUIP);
572	CHECK_FIELD(fpu.CS);
573	CHECK_FIELD(fpu.Rsrvd1);
574	CHECK_FIELD(fpu.FPUDP);
575	CHECK_FIELD(fpu.DS);
576	CHECK_FIELD(fpu.Rsrvd2);
577	CHECK_FIELD(fpu.MXCSR);
578	CHECK_FIELD(fpu.MXCSR_MASK);
579	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
580	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
581	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
582	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
583	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
584	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
585	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
586	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
587	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
588	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
589	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
590	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
591	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
597	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
598	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
599	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
600	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
601	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
602	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
603	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
604	CHECK_FIELD(fpu.au32RsrvdRest[i]);
605	}
606	CHECK_FIELD(rip);
607	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
608	{
609	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
610	CHECK_BIT_FIELD(rflags.Bits.u1CF);
611	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
612	CHECK_BIT_FIELD(rflags.Bits.u1PF);
613	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
614	CHECK_BIT_FIELD(rflags.Bits.u1AF);
615	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
616	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
617	CHECK_BIT_FIELD(rflags.Bits.u1SF);
618	CHECK_BIT_FIELD(rflags.Bits.u1TF);
619	CHECK_BIT_FIELD(rflags.Bits.u1IF);
620	CHECK_BIT_FIELD(rflags.Bits.u1DF);
621	CHECK_BIT_FIELD(rflags.Bits.u1OF);
622	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
623	CHECK_BIT_FIELD(rflags.Bits.u1NT);
624	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
625	CHECK_BIT_FIELD(rflags.Bits.u1RF);
626	CHECK_BIT_FIELD(rflags.Bits.u1VM);
627	CHECK_BIT_FIELD(rflags.Bits.u1AC);
628	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
629	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
630	CHECK_BIT_FIELD(rflags.Bits.u1ID);
631	}
632
633	if (!g_fIgnoreRaxRdx)
634	CHECK_FIELD(rax);
635	CHECK_FIELD(rcx);
636	if (!g_fIgnoreRaxRdx)
637	CHECK_FIELD(rdx);
638	CHECK_FIELD(rbx);
639	CHECK_FIELD(rsp);
640	CHECK_FIELD(rbp);
641	CHECK_FIELD(rsi);
642	CHECK_FIELD(rdi);
643	CHECK_FIELD(r8);
644	CHECK_FIELD(r9);
645	CHECK_FIELD(r10);
646	CHECK_FIELD(r11);
647	CHECK_FIELD(r12);
648	CHECK_FIELD(r13);
649	CHECK_SEL(cs);
650	CHECK_SEL(ss);
651	CHECK_SEL(ds);
652	CHECK_SEL(es);
653	CHECK_SEL(fs);
654	CHECK_SEL(gs);
655	CHECK_FIELD(cr0);
656	CHECK_FIELD(cr2);
657	CHECK_FIELD(cr3);
658	CHECK_FIELD(cr4);
659	CHECK_FIELD(dr[0]);
660	CHECK_FIELD(dr[1]);
661	CHECK_FIELD(dr[2]);
662	CHECK_FIELD(dr[3]);
663	CHECK_FIELD(dr[6]);
664	CHECK_FIELD(dr[7]);
665	CHECK_FIELD(gdtr.cbGdt);
666	CHECK_FIELD(gdtr.pGdt);
667	CHECK_FIELD(idtr.cbIdt);
668	CHECK_FIELD(idtr.pIdt);
669	CHECK_SEL(ldtr);
670	CHECK_SEL(tr);
671	CHECK_FIELD(SysEnter.cs);
672	CHECK_FIELD(SysEnter.eip);
673	CHECK_FIELD(SysEnter.esp);
674	CHECK_FIELD(msrEFER);
675	CHECK_FIELD(msrSTAR);
676	CHECK_FIELD(msrPAT);
677	CHECK_FIELD(msrLSTAR);
678	CHECK_FIELD(msrCSTAR);
679	CHECK_FIELD(msrSFMASK);
680	CHECK_FIELD(msrKERNELGSBASE);
681
682	# undef CHECK_FIELD
683	# undef CHECK_BIT_FIELD
684	}
685	}
686	#endif /* VBOX_COMPARE_IEM_AND_EM */
687
688
689	/**
690	* Interprets the current instruction.
691	*
692	* @returns VBox status code.
693	* @retval VINF_* Scheduling instructions.
694	* @retval VERR_EM_INTERPRETER Something we can't cope with.
695	* @retval VERR_* Fatal errors.
696	*
697	* @param pVCpu Pointer to the VMCPU.
698	* @param pRegFrame The register frame.
699	* Updates the EIP if an instruction was executed successfully.
700	* @param pvFault The fault address (CR2).
701	* @param pcbSize Size of the write (if applicable).
702	*
703	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
704	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
705	* to worry about e.g. invalid modrm combinations (!)
706	*/
707	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
708	{
709	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
710	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
711	#ifdef VBOX_WITH_IEM
712	NOREF(pvFault);
713
714	# ifdef VBOX_COMPARE_IEM_AND_EM
715	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
716	g_IncomingCtx = *pCtx;
717	g_fIncomingFFs = pVCpu->fLocalForcedActions;
718	g_cbEmWrote = g_cbIemWrote = 0;
719
720	# ifdef VBOX_COMPARE_IEM_FIRST
721	/* IEM */
722	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
723	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
724	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
725	rcIem = VERR_EM_INTERPRETER;
726	g_IemCtx = *pCtx;
727	g_fIemFFs = pVCpu->fLocalForcedActions;
728	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
729	*pCtx = g_IncomingCtx;
730	# endif
731
732	/* EM */
733	RTGCPTR pbCode;
734	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
735	if (RT_SUCCESS(rcEm))
736	{
737	uint32_t cbOp;
738	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
739	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
740	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
741	if (RT_SUCCESS(rcEm))
742	{
743	Assert(cbOp == pDis->cbInstr);
744	uint32_t cbIgnored;
745	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
746	if (RT_SUCCESS(rcEm))
747	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
748
749	}
750	rcEm = VERR_EM_INTERPRETER;
751	}
752	else
753	rcEm = VERR_EM_INTERPRETER;
754	# ifdef VBOX_SAME_AS_EM
755	if (rcEm == VERR_EM_INTERPRETER)
756	{
757	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
758	return rcEm;
759	}
760	# endif
761	g_EmCtx = *pCtx;
762	g_fEmFFs = pVCpu->fLocalForcedActions;
763	VBOXSTRICTRC rc = rcEm;
764
765	# ifdef VBOX_COMPARE_IEM_LAST
766	/* IEM */
767	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
768	*pCtx = g_IncomingCtx;
769	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
770	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
771	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
772	rcIem = VERR_EM_INTERPRETER;
773	g_IemCtx = *pCtx;
774	g_fIemFFs = pVCpu->fLocalForcedActions;
775	rc = rcIem;
776	# endif
777
778	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
779	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
780	# endif
781
782	# else
783	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
784	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
785	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
786	rc = VERR_EM_INTERPRETER;
787	# endif
788	if (rc != VINF_SUCCESS)
789	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
790
791	return rc;
792	#else
793	RTGCPTR pbCode;
794	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
795	if (RT_SUCCESS(rc))
796	{
797	uint32_t cbOp;
798	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
799	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
800	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
801	if (RT_SUCCESS(rc))
802	{
803	Assert(cbOp == pDis->cbInstr);
804	uint32_t cbIgnored;
805	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
806	if (RT_SUCCESS(rc))
807	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
808
809	return rc;
810	}
811	}
812	return VERR_EM_INTERPRETER;
813	#endif
814	}
815
816
817	/**
818	* Interprets the current instruction.
819	*
820	* @returns VBox status code.
821	* @retval VINF_* Scheduling instructions.
822	* @retval VERR_EM_INTERPRETER Something we can't cope with.
823	* @retval VERR_* Fatal errors.
824	*
825	* @param pVM Pointer to the VM.
826	* @param pVCpu Pointer to the VMCPU.
827	* @param pRegFrame The register frame.
828	* Updates the EIP if an instruction was executed successfully.
829	* @param pvFault The fault address (CR2).
830	* @param pcbWritten Size of the write (if applicable).
831	*
832	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
833	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
834	* to worry about e.g. invalid modrm combinations (!)
835	*/
836	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
837	{
838	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
839	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
840	#ifdef VBOX_WITH_IEM
841	NOREF(pvFault);
842
843	# ifdef VBOX_COMPARE_IEM_AND_EM
844	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
845	g_IncomingCtx = *pCtx;
846	g_fIncomingFFs = pVCpu->fLocalForcedActions;
847	g_cbEmWrote = g_cbIemWrote = 0;
848
849	# ifdef VBOX_COMPARE_IEM_FIRST
850	/* IEM */
851	uint32_t cbIemWritten = 0;
852	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
853	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
854	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
855	rcIem = VERR_EM_INTERPRETER;
856	g_IemCtx = *pCtx;
857	g_fIemFFs = pVCpu->fLocalForcedActions;
858	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
859	*pCtx = g_IncomingCtx;
860	# endif
861
862	/* EM */
863	uint32_t cbEmWritten = 0;
864	RTGCPTR pbCode;
865	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
866	if (RT_SUCCESS(rcEm))
867	{
868	uint32_t cbOp;
869	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
870	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
871	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
872	if (RT_SUCCESS(rcEm))
873	{
874	Assert(cbOp == pDis->cbInstr);
875	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
876	if (RT_SUCCESS(rcEm))
877	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
878
879	}
880	else
881	rcEm = VERR_EM_INTERPRETER;
882	}
883	else
884	rcEm = VERR_EM_INTERPRETER;
885	# ifdef VBOX_SAME_AS_EM
886	if (rcEm == VERR_EM_INTERPRETER)
887	{
888	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
889	return rcEm;
890	}
891	# endif
892	g_EmCtx = *pCtx;
893	g_fEmFFs = pVCpu->fLocalForcedActions;
894	*pcbWritten = cbEmWritten;
895	VBOXSTRICTRC rc = rcEm;
896
897	# ifdef VBOX_COMPARE_IEM_LAST
898	/* IEM */
899	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
900	*pCtx = g_IncomingCtx;
901	uint32_t cbIemWritten = 0;
902	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
903	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
904	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
905	rcIem = VERR_EM_INTERPRETER;
906	g_IemCtx = *pCtx;
907	g_fIemFFs = pVCpu->fLocalForcedActions;
908	*pcbWritten = cbIemWritten;
909	rc = rcIem;
910	# endif
911
912	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
913	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
914	# endif
915
916	# else
917	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
918	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
919	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
920	rc = VERR_EM_INTERPRETER;
921	# endif
922	if (rc != VINF_SUCCESS)
923	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
924
925	return rc;
926	#else
927	RTGCPTR pbCode;
928	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
929	if (RT_SUCCESS(rc))
930	{
931	uint32_t cbOp;
932	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
933	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
934	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
935	if (RT_SUCCESS(rc))
936	{
937	Assert(cbOp == pDis->cbInstr);
938	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
939	if (RT_SUCCESS(rc))
940	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
941
942	return rc;
943	}
944	}
945	return VERR_EM_INTERPRETER;
946	#endif
947	}
948
949
950	/**
951	* Interprets the current instruction using the supplied DISCPUSTATE structure.
952	*
953	* IP/EIP/RIP IS updated!
954	*
955	* @returns VBox strict status code.
956	* @retval VINF_* Scheduling instructions. When these are returned, it
957	* starts to get a bit tricky to know whether code was
958	* executed or not... We'll address this when it becomes a problem.
959	* @retval VERR_EM_INTERPRETER Something we can't cope with.
960	* @retval VERR_* Fatal errors.
961	*
962	* @param pVM Pointer to the VM.
963	* @param pVCpu Pointer to the VMCPU.
964	* @param pDis The disassembler cpu state for the instruction to be
965	* interpreted.
966	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
967	* @param pvFault The fault address (CR2).
968	* @param pcbSize Size of the write (if applicable).
969	* @param enmCodeType Code type (user/supervisor)
970	*
971	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
972	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
973	* to worry about e.g. invalid modrm combinations (!)
974	*
975	* @todo At this time we do NOT check if the instruction overwrites vital information.
976	* Make sure this can't happen!! (will add some assertions/checks later)
977	*/
978	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
979	RTGCPTR pvFault, EMCODETYPE enmCodeType)
980	{
981	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
982	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
983	#ifdef VBOX_WITH_IEM
984	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
985
986	# ifdef VBOX_COMPARE_IEM_AND_EM
987	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
988	g_IncomingCtx = *pCtx;
989	g_fIncomingFFs = pVCpu->fLocalForcedActions;
990	g_cbEmWrote = g_cbIemWrote = 0;
991
992	# ifdef VBOX_COMPARE_IEM_FIRST
993	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
994	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
995	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
996	rcIem = VERR_EM_INTERPRETER;
997	g_IemCtx = *pCtx;
998	g_fIemFFs = pVCpu->fLocalForcedActions;
999	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1000	*pCtx = g_IncomingCtx;
1001	# endif
1002
1003	/* EM */
1004	uint32_t cbIgnored;
1005	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1006	if (RT_SUCCESS(rcEm))
1007	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1008	# ifdef VBOX_SAME_AS_EM
1009	if (rcEm == VERR_EM_INTERPRETER)
1010	{
1011	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1012	return rcEm;
1013	}
1014	# endif
1015	g_EmCtx = *pCtx;
1016	g_fEmFFs = pVCpu->fLocalForcedActions;
1017	VBOXSTRICTRC rc = rcEm;
1018
1019	# ifdef VBOX_COMPARE_IEM_LAST
1020	/* IEM */
1021	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1022	*pCtx = g_IncomingCtx;
1023	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1024	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1025	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1026	rcIem = VERR_EM_INTERPRETER;
1027	g_IemCtx = *pCtx;
1028	g_fIemFFs = pVCpu->fLocalForcedActions;
1029	rc = rcIem;
1030	# endif
1031
1032	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1033	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1034	# endif
1035
1036	# else
1037	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1038	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1039	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1040	rc = VERR_EM_INTERPRETER;
1041	# endif
1042
1043	if (rc != VINF_SUCCESS)
1044	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1045
1046	return rc;
1047	#else
1048	uint32_t cbIgnored;
1049	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1050	if (RT_SUCCESS(rc))
1051	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1052	return rc;
1053	#endif
1054	}
1055
1056	#ifdef IN_RC
1057
1058	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1059	{
1060	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1061	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1062	return rc;
1063	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1064	}
1065
1066
1067	/**
1068	* Interpret IRET (currently only to V86 code) - PATM only.
1069	*
1070	* @returns VBox status code.
1071	* @param pVM Pointer to the VM.
1072	* @param pVCpu Pointer to the VMCPU.
1073	* @param pRegFrame The register frame.
1074	*
1075	*/
1076	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1077	{
1078	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1079	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1080	int rc;
1081
1082	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1083	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1084	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1085	* this function. Fear that it may guru on us, thus not converted to
1086	* IEM. */
1087
1088	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1089	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1090	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1091	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1092	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1093
1094	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1099	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1100	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1101
1102	pRegFrame->eip = eip & 0xffff;
1103	pRegFrame->cs.Sel = cs;
1104
1105	/* Mask away all reserved bits */
1106	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1107	eflags &= uMask;
1108
1109	CPUMRawSetEFlags(pVCpu, eflags);
1110	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1111
1112	pRegFrame->esp = esp;
1113	pRegFrame->ss.Sel = ss;
1114	pRegFrame->ds.Sel = ds;
1115	pRegFrame->es.Sel = es;
1116	pRegFrame->fs.Sel = fs;
1117	pRegFrame->gs.Sel = gs;
1118
1119	return VINF_SUCCESS;
1120	}
1121
1122	/**
1123	* IRET Emulation.
1124	*/
1125	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1126	{
1127	#ifdef VBOX_WITH_RAW_RING1
1128	NOREF(pvFault); NOREF(pcbSize);
1129	if (EMIsRawRing1Enabled(pVM))
1130	{
1131	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1132	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1133	int rc;
1134	uint32_t cpl, rpl;
1135
1136	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1137	/* @todo: we don't verify all the edge cases that generate #GP faults */
1138
1139	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1140	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1141	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1142	* this function. Fear that it may guru on us, thus not converted to
1143	* IEM. */
1144
1145	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1146	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1147	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1148	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1149	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1150
1151	/* Deal with V86 above. */
1152	if (eflags & X86_EFL_VM)
1153	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1154
1155	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1156	rpl = cs & X86_SEL_RPL;
1157
1158	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1159	if (rpl != cpl)
1160	{
1161	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1163	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1164	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1165	Log(("emInterpretIret: SS:ESP=%04X:08X\n", ss, esp));
1166	pRegFrame->ss.Sel = ss;
1167	pRegFrame->esp = esp;
1168	}
1169	pRegFrame->cs.Sel = cs;
1170	pRegFrame->eip = eip;
1171
1172	/* Adjust CS & SS as required. */
1173	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1174
1175	/* Mask away all reserved bits */
1176	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1177	eflags &= uMask;
1178
1179	CPUMRawSetEFlags(pVCpu, eflags);
1180	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1181	return VINF_SUCCESS;
1182	}
1183	#else
1184	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1185	#endif
1186	return VERR_EM_INTERPRETER;
1187	}
1188
1189	#endif /* IN_RC */
1190
1191
1192
1193	/*
1194	*
1195	* Old interpreter primitives used by HM, move/eliminate later.
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	* Old interpreter primitives used by HM, move/eliminate later.
1200	*
1201	*/
1202
1203
1204	/**
1205	* Interpret CPUID given the parameters in the CPU context.
1206	*
1207	* @returns VBox status code.
1208	* @param pVM Pointer to the VM.
1209	* @param pVCpu Pointer to the VMCPU.
1210	* @param pRegFrame The register frame.
1211	*
1212	*/
1213	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1214	{
1215	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1216	uint32_t iLeaf = pRegFrame->eax;
1217	NOREF(pVM);
1218
1219	/* cpuid clears the high dwords of the affected 64 bits registers. */
1220	pRegFrame->rax = 0;
1221	pRegFrame->rbx = 0;
1222	pRegFrame->rcx &= UINT64_C(0x00000000ffffffff);
1223	pRegFrame->rdx = 0;
1224
1225	/* Note: operates the same in 64 and non-64 bits mode. */
1226	CPUMGetGuestCpuId(pVCpu, iLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1227	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1228	return VINF_SUCCESS;
1229	}
1230
1231
1232	/**
1233	* Interpret RDTSC.
1234	*
1235	* @returns VBox status code.
1236	* @param pVM Pointer to the VM.
1237	* @param pVCpu Pointer to the VMCPU.
1238	* @param pRegFrame The register frame.
1239	*
1240	*/
1241	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1242	{
1243	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1244	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1245
1246	if (uCR4 & X86_CR4_TSD)
1247	return VERR_EM_INTERPRETER; /* genuine #GP */
1248
1249	uint64_t uTicks = TMCpuTickGet(pVCpu);
1250
1251	/* Same behaviour in 32 & 64 bits mode */
1252	pRegFrame->rax = (uint32_t)uTicks;
1253	pRegFrame->rdx = (uTicks >> 32ULL);
1254	#ifdef VBOX_COMPARE_IEM_AND_EM
1255	g_fIgnoreRaxRdx = true;
1256	#endif
1257
1258	NOREF(pVM);
1259	return VINF_SUCCESS;
1260	}
1261
1262	/**
1263	* Interpret RDTSCP.
1264	*
1265	* @returns VBox status code.
1266	* @param pVM Pointer to the VM.
1267	* @param pVCpu Pointer to the VMCPU.
1268	* @param pCtx The CPU context.
1269	*
1270	*/
1271	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1272	{
1273	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1274	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1275
1276	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1277	{
1278	AssertFailed();
1279	return VERR_EM_INTERPRETER; /* genuine #UD */
1280	}
1281
1282	if (uCR4 & X86_CR4_TSD)
1283	return VERR_EM_INTERPRETER; /* genuine #GP */
1284
1285	uint64_t uTicks = TMCpuTickGet(pVCpu);
1286
1287	/* Same behaviour in 32 & 64 bits mode */
1288	pCtx->rax = (uint32_t)uTicks;
1289	pCtx->rdx = (uTicks >> 32ULL);
1290	#ifdef VBOX_COMPARE_IEM_AND_EM
1291	g_fIgnoreRaxRdx = true;
1292	#endif
1293	/* Low dword of the TSC_AUX msr only. */
1294	CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);
1295	pCtx->rcx &= UINT32_C(0xffffffff);
1296
1297	return VINF_SUCCESS;
1298	}
1299
1300	/**
1301	* Interpret RDPMC.
1302	*
1303	* @returns VBox status code.
1304	* @param pVM Pointer to the VM.
1305	* @param pVCpu Pointer to the VMCPU.
1306	* @param pRegFrame The register frame.
1307	*
1308	*/
1309	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1310	{
1311	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1312	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1313
1314	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1315	if ( !(uCR4 & X86_CR4_PCE)
1316	&& CPUMGetGuestCPL(pVCpu) != 0)
1317	{
1318	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1319	return VERR_EM_INTERPRETER; /* genuine #GP */
1320	}
1321
1322	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1323	pRegFrame->rax = 0;
1324	pRegFrame->rdx = 0;
1325	/** @todo We should trigger a #GP here if the CPU doesn't support the index in ecx
1326	* but see @bugref{3472}! */
1327
1328	NOREF(pVM);
1329	return VINF_SUCCESS;
1330	}
1331
1332
1333	/**
1334	* MWAIT Emulation.
1335	*/
1336	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1337	{
1338	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1339	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1340	NOREF(pVM);
1341
1342	/* Get the current privilege level. */
1343	cpl = CPUMGetGuestCPL(pVCpu);
1344	if (cpl != 0)
1345	return VERR_EM_INTERPRETER; /* supervisor only */
1346
1347	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1348	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1349	return VERR_EM_INTERPRETER; /* not supported */
1350
1351	/*
1352	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1353	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1354	*/
1355	CPUMGetGuestCpuId(pVCpu, 5, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1356	if (pRegFrame->ecx > 1)
1357	{
1358	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1359	return VERR_EM_INTERPRETER; /* illegal value. */
1360	}
1361
1362	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1363	{
1364	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1365	return VERR_EM_INTERPRETER; /* illegal value. */
1366	}
1367
1368	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1369	}
1370
1371
1372	/**
1373	* MONITOR Emulation.
1374	*/
1375	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1376	{
1377	uint32_t u32Dummy, u32ExtFeatures, cpl;
1378	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1379	NOREF(pVM);
1380
1381	if (pRegFrame->ecx != 0)
1382	{
1383	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1384	return VERR_EM_INTERPRETER; /* illegal value. */
1385	}
1386
1387	/* Get the current privilege level. */
1388	cpl = CPUMGetGuestCPL(pVCpu);
1389	if (cpl != 0)
1390	return VERR_EM_INTERPRETER; /* supervisor only */
1391
1392	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1393	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1394	return VERR_EM_INTERPRETER; /* not supported */
1395
1396	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1397	return VINF_SUCCESS;
1398	}
1399
1400
1401	/* VT-x only: */
1402
1403	/**
1404	* Interpret INVLPG.
1405	*
1406	* @returns VBox status code.
1407	* @param pVM Pointer to the VM.
1408	* @param pVCpu Pointer to the VMCPU.
1409	* @param pRegFrame The register frame.
1410	* @param pAddrGC Operand address.
1411	*
1412	*/
1413	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1414	{
1415	/** @todo is addr always a flat linear address or ds based
1416	* (in absence of segment override prefixes)????
1417	*/
1418	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1419	NOREF(pVM); NOREF(pRegFrame);
1420	#ifdef IN_RC
1421	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1422	#endif
1423	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1424	if ( rc == VINF_SUCCESS
1425	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1426	return VINF_SUCCESS;
1427	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1428	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1429	VERR_EM_INTERPRETER);
1430	return rc;
1431	}
1432
1433
1434	/**
1435	* Update CRx.
1436	*
1437	* @returns VBox status code.
1438	* @param pVM Pointer to the VM.
1439	* @param pVCpu Pointer to the VMCPU.
1440	* @param pRegFrame The register frame.
1441	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1442	* @param val New CRx value
1443	*
1444	*/
1445	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1446	{
1447	uint64_t oldval;
1448	uint64_t msrEFER;
1449	int rc, rc2;
1450	NOREF(pVM);
1451
1452	/** @todo Clean up this mess. */
1453	LogFlow(("EMInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1454	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1455	switch (DestRegCrx)
1456	{
1457	case DISCREG_CR0:
1458	oldval = CPUMGetGuestCR0(pVCpu);
1459	#ifdef IN_RC
1460	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1461	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1462	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1463	return VERR_EM_INTERPRETER;
1464	#endif
1465	rc = VINF_SUCCESS;
1466	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1467	CPUMSetGuestCR0(pVCpu, val);
1468	#else
1469	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1470	#endif
1471	val = CPUMGetGuestCR0(pVCpu);
1472	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1473	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1474	{
1475	/* global flush */
1476	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1477	AssertRCReturn(rc, rc);
1478	}
1479
1480	/* Deal with long mode enabling/disabling. */
1481	msrEFER = CPUMGetGuestEFER(pVCpu);
1482	if (msrEFER & MSR_K6_EFER_LME)
1483	{
1484	if ( !(oldval & X86_CR0_PG)
1485	&& (val & X86_CR0_PG))
1486	{
1487	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1488	if (pRegFrame->cs.Attr.n.u1Long)
1489	{
1490	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1491	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1492	}
1493
1494	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1495	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1496	{
1497	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1498	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1499	}
1500	msrEFER \|= MSR_K6_EFER_LMA;
1501	}
1502	else
1503	if ( (oldval & X86_CR0_PG)
1504	&& !(val & X86_CR0_PG))
1505	{
1506	msrEFER &= ~MSR_K6_EFER_LMA;
1507	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1508	}
1509	CPUMSetGuestEFER(pVCpu, msrEFER);
1510	}
1511	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1512	return rc2 == VINF_SUCCESS ? rc : rc2;
1513
1514	case DISCREG_CR2:
1515	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1516	return VINF_SUCCESS;
1517
1518	case DISCREG_CR3:
1519	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1520	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1521	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1522	{
1523	/* flush */
1524	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1525	AssertRC(rc);
1526	}
1527	return rc;
1528
1529	case DISCREG_CR4:
1530	oldval = CPUMGetGuestCR4(pVCpu);
1531	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1532	val = CPUMGetGuestCR4(pVCpu);
1533
1534	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1535	msrEFER = CPUMGetGuestEFER(pVCpu);
1536	if ( (msrEFER & MSR_K6_EFER_LMA)
1537	&& (oldval & X86_CR4_PAE)
1538	&& !(val & X86_CR4_PAE))
1539	{
1540	return VERR_EM_INTERPRETER; /** @todo generate #GP(0) */
1541	}
1542
1543	rc = VINF_SUCCESS;
1544	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1545	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1546	{
1547	/* global flush */
1548	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1549	AssertRCReturn(rc, rc);
1550	}
1551
1552	/* Feeling extremely lazy. */
1553	# ifdef IN_RC
1554	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1555	!= (val & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1556	{
1557	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1558	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1559	}
1560	# endif
1561	# ifdef VBOX_WITH_RAW_MODE
1562	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1563	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1564	# endif
1565
1566	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1567	return rc2 == VINF_SUCCESS ? rc : rc2;
1568
1569	case DISCREG_CR8:
1570	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1571
1572	default:
1573	AssertFailed();
1574	case DISCREG_CR1: /* illegal op */
1575	break;
1576	}
1577	return VERR_EM_INTERPRETER;
1578	}
1579
1580
1581	/**
1582	* Interpret CRx write.
1583	*
1584	* @returns VBox status code.
1585	* @param pVM Pointer to the VM.
1586	* @param pVCpu Pointer to the VMCPU.
1587	* @param pRegFrame The register frame.
1588	* @param DestRegCRx CRx register index (DISUSE_REG_CR*)
1589	* @param SrcRegGen General purpose register index (USE_REG_E**))
1590	*
1591	*/
1592	VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1593	{
1594	uint64_t val;
1595	int rc;
1596	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1597
1598	if (CPUMIsGuestIn64BitCode(pVCpu))
1599	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1600	else
1601	{
1602	uint32_t val32;
1603	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1604	val = val32;
1605	}
1606
1607	if (RT_SUCCESS(rc))
1608	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1609
1610	return VERR_EM_INTERPRETER;
1611	}
1612
1613	/**
1614	* Interpret LMSW.
1615	*
1616	* @returns VBox status code.
1617	* @param pVM Pointer to the VM.
1618	* @param pVCpu Pointer to the VMCPU.
1619	* @param pRegFrame The register frame.
1620	* @param u16Data LMSW source data.
1621	*
1622	*/
1623	VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
1624	{
1625	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1626	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
1627
1628	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1629	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1630	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1631
1632	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
1633	}
1634
1635
1636	/**
1637	* Interpret CLTS.
1638	*
1639	* @returns VBox status code.
1640	* @param pVM Pointer to the VM.
1641	* @param pVCpu Pointer to the VMCPU.
1642	*
1643	*/
1644	VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu)
1645	{
1646	NOREF(pVM);
1647
1648	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
1649	if (!(cr0 & X86_CR0_TS))
1650	return VINF_SUCCESS;
1651	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
1652	}
1653
1654
1655	#ifdef LOG_ENABLED
1656	static const char *emMSRtoString(uint32_t uMsr)
1657	{
1658	switch (uMsr)
1659	{
1660	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1661	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1662	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1663	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1664	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1665	case MSR_K6_EFER: return "MSR_K6_EFER";
1666	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1667	case MSR_K6_STAR: return "MSR_K6_STAR";
1668	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1669	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1670	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1671	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1672	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1673	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1674	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1675	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1676	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1677	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1678	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1679	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1680	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1681	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1682	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1683	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1684	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1685	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1686	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1687	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1688	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1689	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1690	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1691	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1692	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1693	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1694	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1695	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1696	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1697	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1698	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1699	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1700	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1701	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1702	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1703	}
1704	return "Unknown MSR";
1705	}
1706	#endif /* LOG_ENABLED */
1707
1708
1709	/**
1710	* Interpret RDMSR
1711	*
1712	* @returns VBox status code.
1713	* @param pVM Pointer to the VM.
1714	* @param pVCpu Pointer to the VMCPU.
1715	* @param pRegFrame The register frame.
1716	*/
1717	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1718	{
1719	NOREF(pVM);
1720
1721	/* Get the current privilege level. */
1722	if (CPUMGetGuestCPL(pVCpu) != 0)
1723	{
1724	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1725	return VERR_EM_INTERPRETER; /* supervisor only */
1726	}
1727
1728	uint64_t uValue;
1729	int rc = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1730	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1731	{
1732	Assert(rc == VERR_CPUM_RAISE_GP_0);
1733	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", rc));
1734	return VERR_EM_INTERPRETER;
1735	}
1736	pRegFrame->rax = (uint32_t) uValue;
1737	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1738	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1739	return rc;
1740	}
1741
1742
1743	/**
1744	* Interpret WRMSR
1745	*
1746	* @returns VBox status code.
1747	* @param pVM Pointer to the VM.
1748	* @param pVCpu Pointer to the VMCPU.
1749	* @param pRegFrame The register frame.
1750	*/
1751	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1752	{
1753	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1754
1755	/* Check the current privilege level, this instruction is supervisor only. */
1756	if (CPUMGetGuestCPL(pVCpu) != 0)
1757	{
1758	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1759	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1760	}
1761
1762	int rc = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1763	if (rc != VINF_SUCCESS)
1764	{
1765	Assert(rc == VERR_CPUM_RAISE_GP_0);
1766	Log4(("EM: Refuse WRMSR: rc=%d\n", rc));
1767	return VERR_EM_INTERPRETER;
1768	}
1769	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1770	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1771	NOREF(pVM);
1772	return rc;
1773	}
1774
1775
1776	/**
1777	* Interpret CRx read.
1778	*
1779	* @returns VBox status code.
1780	* @param pVM Pointer to the VM.
1781	* @param pVCpu Pointer to the VMCPU.
1782	* @param pRegFrame The register frame.
1783	* @param DestRegGen General purpose register index (USE_REG_E**))
1784	* @param SrcRegCRx CRx register index (DISUSE_REG_CR*)
1785	*
1786	*/
1787	VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1788	{
1789	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1790	uint64_t val64;
1791	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1792	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1793	NOREF(pVM);
1794
1795	if (CPUMIsGuestIn64BitCode(pVCpu))
1796	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1797	else
1798	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1799
1800	if (RT_SUCCESS(rc))
1801	{
1802	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1803	return VINF_SUCCESS;
1804	}
1805	return VERR_EM_INTERPRETER;
1806	}
1807
1808
1809	/**
1810	* Interpret DRx write.
1811	*
1812	* @returns VBox status code.
1813	* @param pVM Pointer to the VM.
1814	* @param pVCpu Pointer to the VMCPU.
1815	* @param pRegFrame The register frame.
1816	* @param DestRegDRx DRx register index (USE_REG_DR*)
1817	* @param SrcRegGen General purpose register index (USE_REG_E**))
1818	*
1819	*/
1820	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1821	{
1822	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1823	uint64_t uNewDrX;
1824	int rc;
1825	NOREF(pVM);
1826
1827	if (CPUMIsGuestIn64BitCode(pVCpu))
1828	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1829	else
1830	{
1831	uint32_t val32;
1832	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1833	uNewDrX = val32;
1834	}
1835
1836	if (RT_SUCCESS(rc))
1837	{
1838	if (DestRegDrx == 6)
1839	{
1840	uNewDrX \|= X86_DR6_RA1_MASK;
1841	uNewDrX &= ~X86_DR6_RAZ_MASK;
1842	}
1843	else if (DestRegDrx == 7)
1844	{
1845	uNewDrX \|= X86_DR7_RA1_MASK;
1846	uNewDrX &= ~X86_DR7_RAZ_MASK;
1847	}
1848
1849	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1850	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1851	if (RT_SUCCESS(rc))
1852	return rc;
1853	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1854	}
1855	return VERR_EM_INTERPRETER;
1856	}
1857
1858
1859	/**
1860	* Interpret DRx read.
1861	*
1862	* @returns VBox status code.
1863	* @param pVM Pointer to the VM.
1864	* @param pVCpu Pointer to the VMCPU.
1865	* @param pRegFrame The register frame.
1866	* @param DestRegGen General purpose register index (USE_REG_E**))
1867	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1868	*
1869	*/
1870	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1871	{
1872	uint64_t val64;
1873	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1874	NOREF(pVM);
1875
1876	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1877	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1878	if (CPUMIsGuestIn64BitCode(pVCpu))
1879	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1880	else
1881	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1882
1883	if (RT_SUCCESS(rc))
1884	return VINF_SUCCESS;
1885
1886	return VERR_EM_INTERPRETER;
1887	}
1888
1889
1890	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1891
1892
1893
1894
1895
1896
1897	/*
1898	*
1899	* The old interpreter.
1900	* The old interpreter.
1901	* The old interpreter.
1902	* The old interpreter.
1903	* The old interpreter.
1904	*
1905	*/
1906
1907	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1908	{
1909	#ifdef IN_RC
1910	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1911	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1912	return rc;
1913	/*
1914	* The page pool cache may end up here in some cases because it
1915	* flushed one of the shadow mappings used by the trapping
1916	* instruction and it either flushed the TLB or the CPU reused it.
1917	*/
1918	#else
1919	NOREF(pVM);
1920	#endif
1921	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1922	}
1923
1924
1925	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1926	{
1927	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1928	pages or write monitored pages. */
1929	NOREF(pVM);
1930	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1931	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1932	#else
1933	int rc = VINF_SUCCESS;
1934	#endif
1935	#ifdef VBOX_COMPARE_IEM_AND_EM
1936	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1937	g_cbEmWrote = cb;
1938	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1939	#endif
1940	return rc;
1941	}
1942
1943
1944	/** Convert sel:addr to a flat GC address. */
1945	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1946	{
1947	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1948	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1949	}
1950
1951
1952	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1953	/**
1954	* Get the mnemonic for the disassembled instruction.
1955	*
1956	* GC/R0 doesn't include the strings in the DIS tables because
1957	* of limited space.
1958	*/
1959	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1960	{
1961	switch (pDis->pCurInstr->uOpcode)
1962	{
1963	case OP_XCHG: return "Xchg";
1964	case OP_DEC: return "Dec";
1965	case OP_INC: return "Inc";
1966	case OP_POP: return "Pop";
1967	case OP_OR: return "Or";
1968	case OP_AND: return "And";
1969	case OP_MOV: return "Mov";
1970	case OP_INVLPG: return "InvlPg";
1971	case OP_CPUID: return "CpuId";
1972	case OP_MOV_CR: return "MovCRx";
1973	case OP_MOV_DR: return "MovDRx";
1974	case OP_LLDT: return "LLdt";
1975	case OP_LGDT: return "LGdt";
1976	case OP_LIDT: return "LIdt";
1977	case OP_CLTS: return "Clts";
1978	case OP_MONITOR: return "Monitor";
1979	case OP_MWAIT: return "MWait";
1980	case OP_RDMSR: return "Rdmsr";
1981	case OP_WRMSR: return "Wrmsr";
1982	case OP_ADD: return "Add";
1983	case OP_ADC: return "Adc";
1984	case OP_SUB: return "Sub";
1985	case OP_SBB: return "Sbb";
1986	case OP_RDTSC: return "Rdtsc";
1987	case OP_STI: return "Sti";
1988	case OP_CLI: return "Cli";
1989	case OP_XADD: return "XAdd";
1990	case OP_HLT: return "Hlt";
1991	case OP_IRET: return "Iret";
1992	case OP_MOVNTPS: return "MovNTPS";
1993	case OP_STOSWD: return "StosWD";
1994	case OP_WBINVD: return "WbInvd";
1995	case OP_XOR: return "Xor";
1996	case OP_BTR: return "Btr";
1997	case OP_BTS: return "Bts";
1998	case OP_BTC: return "Btc";
1999	case OP_LMSW: return "Lmsw";
2000	case OP_SMSW: return "Smsw";
2001	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
2002	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
2003
2004	default:
2005	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
2006	return "???";
2007	}
2008	}
2009	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
2010
2011
2012	/**
2013	* XCHG instruction emulation.
2014	*/
2015	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2016	{
2017	DISQPVPARAMVAL param1, param2;
2018	NOREF(pvFault);
2019
2020	/* Source to make DISQueryParamVal read the register value - ugly hack */
2021	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2022	if(RT_FAILURE(rc))
2023	return VERR_EM_INTERPRETER;
2024
2025	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2026	if(RT_FAILURE(rc))
2027	return VERR_EM_INTERPRETER;
2028
2029	#ifdef IN_RC
2030	if (TRPMHasTrap(pVCpu))
2031	{
2032	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2033	{
2034	#endif
2035	RTGCPTR pParam1 = 0, pParam2 = 0;
2036	uint64_t valpar1, valpar2;
2037
2038	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2039	switch(param1.type)
2040	{
2041	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2042	valpar1 = param1.val.val64;
2043	break;
2044
2045	case DISQPV_TYPE_ADDRESS:
2046	pParam1 = (RTGCPTR)param1.val.val64;
2047	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2048	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2049	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2050	if (RT_FAILURE(rc))
2051	{
2052	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2053	return VERR_EM_INTERPRETER;
2054	}
2055	break;
2056
2057	default:
2058	AssertFailed();
2059	return VERR_EM_INTERPRETER;
2060	}
2061
2062	switch(param2.type)
2063	{
2064	case DISQPV_TYPE_ADDRESS:
2065	pParam2 = (RTGCPTR)param2.val.val64;
2066	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2067	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2068	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2069	if (RT_FAILURE(rc))
2070	{
2071	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2072	}
2073	break;
2074
2075	case DISQPV_TYPE_IMMEDIATE:
2076	valpar2 = param2.val.val64;
2077	break;
2078
2079	default:
2080	AssertFailed();
2081	return VERR_EM_INTERPRETER;
2082	}
2083
2084	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2085	if (pParam1 == 0)
2086	{
2087	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2088	switch(param1.size)
2089	{
2090	case 1: //special case for AH etc
2091	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2092	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2093	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2094	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2095	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2096	}
2097	if (RT_FAILURE(rc))
2098	return VERR_EM_INTERPRETER;
2099	}
2100	else
2101	{
2102	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2103	if (RT_FAILURE(rc))
2104	{
2105	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2106	return VERR_EM_INTERPRETER;
2107	}
2108	}
2109
2110	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2111	if (pParam2 == 0)
2112	{
2113	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2114	switch(param2.size)
2115	{
2116	case 1: //special case for AH etc
2117	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2118	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2119	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2120	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2121	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2122	}
2123	if (RT_FAILURE(rc))
2124	return VERR_EM_INTERPRETER;
2125	}
2126	else
2127	{
2128	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2129	if (RT_FAILURE(rc))
2130	{
2131	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2132	return VERR_EM_INTERPRETER;
2133	}
2134	}
2135
2136	*pcbSize = param2.size;
2137	return VINF_SUCCESS;
2138	#ifdef IN_RC
2139	}
2140	}
2141	return VERR_EM_INTERPRETER;
2142	#endif
2143	}
2144
2145
2146	/**
2147	* INC and DEC emulation.
2148	*/
2149	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2150	PFNEMULATEPARAM2 pfnEmulate)
2151	{
2152	DISQPVPARAMVAL param1;
2153	NOREF(pvFault);
2154
2155	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2156	if(RT_FAILURE(rc))
2157	return VERR_EM_INTERPRETER;
2158
2159	#ifdef IN_RC
2160	if (TRPMHasTrap(pVCpu))
2161	{
2162	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2163	{
2164	#endif
2165	RTGCPTR pParam1 = 0;
2166	uint64_t valpar1;
2167
2168	if (param1.type == DISQPV_TYPE_ADDRESS)
2169	{
2170	pParam1 = (RTGCPTR)param1.val.val64;
2171	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2172	#ifdef IN_RC
2173	/* Safety check (in theory it could cross a page boundary and fault there though) */
2174	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2175	#endif
2176	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2177	if (RT_FAILURE(rc))
2178	{
2179	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2180	return VERR_EM_INTERPRETER;
2181	}
2182	}
2183	else
2184	{
2185	AssertFailed();
2186	return VERR_EM_INTERPRETER;
2187	}
2188
2189	uint32_t eflags;
2190
2191	eflags = pfnEmulate(&valpar1, param1.size);
2192
2193	/* Write result back */
2194	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2195	if (RT_FAILURE(rc))
2196	{
2197	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2198	return VERR_EM_INTERPRETER;
2199	}
2200
2201	/* Update guest's eflags and finish. */
2202	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2203	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2204
2205	/* All done! */
2206	*pcbSize = param1.size;
2207	return VINF_SUCCESS;
2208	#ifdef IN_RC
2209	}
2210	}
2211	return VERR_EM_INTERPRETER;
2212	#endif
2213	}
2214
2215
2216	/**
2217	* POP Emulation.
2218	*/
2219	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2220	{
2221	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2222	DISQPVPARAMVAL param1;
2223	NOREF(pvFault);
2224
2225	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2226	if(RT_FAILURE(rc))
2227	return VERR_EM_INTERPRETER;
2228
2229	#ifdef IN_RC
2230	if (TRPMHasTrap(pVCpu))
2231	{
2232	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2233	{
2234	#endif
2235	RTGCPTR pParam1 = 0;
2236	uint32_t valpar1;
2237	RTGCPTR pStackVal;
2238
2239	/* Read stack value first */
2240	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2241	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2242
2243	/* Convert address; don't bother checking limits etc, as we only read here */
2244	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2245	if (pStackVal == 0)
2246	return VERR_EM_INTERPRETER;
2247
2248	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2249	if (RT_FAILURE(rc))
2250	{
2251	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2252	return VERR_EM_INTERPRETER;
2253	}
2254
2255	if (param1.type == DISQPV_TYPE_ADDRESS)
2256	{
2257	pParam1 = (RTGCPTR)param1.val.val64;
2258
2259	/* pop [esp+xx] uses esp after the actual pop! */
2260	AssertCompile(DISGREG_ESP == DISGREG_SP);
2261	if ( (pDis->Param1.fUse & DISUSE_BASE)
2262	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2263	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2264	)
2265	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2266
2267	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2268	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2269	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2270	if (RT_FAILURE(rc))
2271	{
2272	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2273	return VERR_EM_INTERPRETER;
2274	}
2275
2276	/* Update ESP as the last step */
2277	pRegFrame->esp += param1.size;
2278	}
2279	else
2280	{
2281	#ifndef DEBUG_bird // annoying assertion.
2282	AssertFailed();
2283	#endif
2284	return VERR_EM_INTERPRETER;
2285	}
2286
2287	/* All done! */
2288	*pcbSize = param1.size;
2289	return VINF_SUCCESS;
2290	#ifdef IN_RC
2291	}
2292	}
2293	return VERR_EM_INTERPRETER;
2294	#endif
2295	}
2296
2297
2298	/**
2299	* XOR/OR/AND Emulation.
2300	*/
2301	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2302	PFNEMULATEPARAM3 pfnEmulate)
2303	{
2304	DISQPVPARAMVAL param1, param2;
2305	NOREF(pvFault);
2306
2307	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2308	if(RT_FAILURE(rc))
2309	return VERR_EM_INTERPRETER;
2310
2311	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2312	if(RT_FAILURE(rc))
2313	return VERR_EM_INTERPRETER;
2314
2315	#ifdef IN_RC
2316	if (TRPMHasTrap(pVCpu))
2317	{
2318	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2319	{
2320	#endif
2321	RTGCPTR pParam1;
2322	uint64_t valpar1, valpar2;
2323
2324	if (pDis->Param1.cb != pDis->Param2.cb)
2325	{
2326	if (pDis->Param1.cb < pDis->Param2.cb)
2327	{
2328	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2329	return VERR_EM_INTERPRETER;
2330	}
2331	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2332	pDis->Param2.cb = pDis->Param1.cb;
2333	param2.size = param1.size;
2334	}
2335
2336	/* The destination is always a virtual address */
2337	if (param1.type == DISQPV_TYPE_ADDRESS)
2338	{
2339	pParam1 = (RTGCPTR)param1.val.val64;
2340	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2341	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2342	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2343	if (RT_FAILURE(rc))
2344	{
2345	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2346	return VERR_EM_INTERPRETER;
2347	}
2348	}
2349	else
2350	{
2351	AssertFailed();
2352	return VERR_EM_INTERPRETER;
2353	}
2354
2355	/* Register or immediate data */
2356	switch(param2.type)
2357	{
2358	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2359	valpar2 = param2.val.val64;
2360	break;
2361
2362	default:
2363	AssertFailed();
2364	return VERR_EM_INTERPRETER;
2365	}
2366
2367	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2368
2369	/* Data read, emulate instruction. */
2370	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2371
2372	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2373
2374	/* Update guest's eflags and finish. */
2375	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2376	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2377
2378	/* And write it back */
2379	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2380	if (RT_SUCCESS(rc))
2381	{
2382	/* All done! */
2383	*pcbSize = param2.size;
2384	return VINF_SUCCESS;
2385	}
2386	#ifdef IN_RC
2387	}
2388	}
2389	#endif
2390	return VERR_EM_INTERPRETER;
2391	}
2392
2393
2394	#ifndef VBOX_COMPARE_IEM_AND_EM
2395	/**
2396	* LOCK XOR/OR/AND Emulation.
2397	*/
2398	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2399	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2400	{
2401	void *pvParam1;
2402	DISQPVPARAMVAL param1, param2;
2403	NOREF(pvFault);
2404
2405	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
2406	Assert(pDis->Param1.cb <= 4);
2407	#endif
2408
2409	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2410	if(RT_FAILURE(rc))
2411	return VERR_EM_INTERPRETER;
2412
2413	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2414	if(RT_FAILURE(rc))
2415	return VERR_EM_INTERPRETER;
2416
2417	if (pDis->Param1.cb != pDis->Param2.cb)
2418	{
2419	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2420	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2421	VERR_EM_INTERPRETER);
2422
2423	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2424	pDis->Param2.cb = pDis->Param1.cb;
2425	param2.size = param1.size;
2426	}
2427
2428	#ifdef IN_RC
2429	/* Safety check (in theory it could cross a page boundary and fault there though) */
2430	Assert( TRPMHasTrap(pVCpu)
2431	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2432	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2433	#endif
2434
2435	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2436	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2437	RTGCUINTREG ValPar2 = param2.val.val64;
2438
2439	/* The destination is always a virtual address */
2440	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2441
2442	RTGCPTR GCPtrPar1 = param1.val.val64;
2443	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2444	PGMPAGEMAPLOCK Lock;
2445	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2446	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2447
2448	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2449	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2450
2451	RTGCUINTREG32 eflags = 0;
2452	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2453	PGMPhysReleasePageMappingLock(pVM, &Lock);
2454	if (RT_FAILURE(rc))
2455	{
2456	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2457	return VERR_EM_INTERPRETER;
2458	}
2459
2460	/* Update guest's eflags and finish. */
2461	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2462	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2463
2464	*pcbSize = param2.size;
2465	return VINF_SUCCESS;
2466	}
2467	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2468
2469
2470	/**
2471	* ADD, ADC & SUB Emulation.
2472	*/
2473	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2474	PFNEMULATEPARAM3 pfnEmulate)
2475	{
2476	NOREF(pvFault);
2477	DISQPVPARAMVAL param1, param2;
2478	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2479	if(RT_FAILURE(rc))
2480	return VERR_EM_INTERPRETER;
2481
2482	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2483	if(RT_FAILURE(rc))
2484	return VERR_EM_INTERPRETER;
2485
2486	#ifdef IN_RC
2487	if (TRPMHasTrap(pVCpu))
2488	{
2489	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2490	{
2491	#endif
2492	RTGCPTR pParam1;
2493	uint64_t valpar1, valpar2;
2494
2495	if (pDis->Param1.cb != pDis->Param2.cb)
2496	{
2497	if (pDis->Param1.cb < pDis->Param2.cb)
2498	{
2499	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2500	return VERR_EM_INTERPRETER;
2501	}
2502	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2503	pDis->Param2.cb = pDis->Param1.cb;
2504	param2.size = param1.size;
2505	}
2506
2507	/* The destination is always a virtual address */
2508	if (param1.type == DISQPV_TYPE_ADDRESS)
2509	{
2510	pParam1 = (RTGCPTR)param1.val.val64;
2511	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2512	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2513	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2514	if (RT_FAILURE(rc))
2515	{
2516	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2517	return VERR_EM_INTERPRETER;
2518	}
2519	}
2520	else
2521	{
2522	#ifndef DEBUG_bird
2523	AssertFailed();
2524	#endif
2525	return VERR_EM_INTERPRETER;
2526	}
2527
2528	/* Register or immediate data */
2529	switch(param2.type)
2530	{
2531	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2532	valpar2 = param2.val.val64;
2533	break;
2534
2535	default:
2536	AssertFailed();
2537	return VERR_EM_INTERPRETER;
2538	}
2539
2540	/* Data read, emulate instruction. */
2541	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2542
2543	/* Update guest's eflags and finish. */
2544	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2545	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2546
2547	/* And write it back */
2548	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2549	if (RT_SUCCESS(rc))
2550	{
2551	/* All done! */
2552	*pcbSize = param2.size;
2553	return VINF_SUCCESS;
2554	}
2555	#ifdef IN_RC
2556	}
2557	}
2558	#endif
2559	return VERR_EM_INTERPRETER;
2560	}
2561
2562
2563	/**
2564	* ADC Emulation.
2565	*/
2566	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2567	{
2568	if (pRegFrame->eflags.Bits.u1CF)
2569	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2570	else
2571	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2572	}
2573
2574
2575	/**
2576	* BTR/C/S Emulation.
2577	*/
2578	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2579	PFNEMULATEPARAM2UINT32 pfnEmulate)
2580	{
2581	DISQPVPARAMVAL param1, param2;
2582	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2583	if(RT_FAILURE(rc))
2584	return VERR_EM_INTERPRETER;
2585
2586	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2587	if(RT_FAILURE(rc))
2588	return VERR_EM_INTERPRETER;
2589
2590	#ifdef IN_RC
2591	if (TRPMHasTrap(pVCpu))
2592	{
2593	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2594	{
2595	#endif
2596	RTGCPTR pParam1;
2597	uint64_t valpar1 = 0, valpar2;
2598	uint32_t eflags;
2599
2600	/* The destination is always a virtual address */
2601	if (param1.type != DISQPV_TYPE_ADDRESS)
2602	return VERR_EM_INTERPRETER;
2603
2604	pParam1 = (RTGCPTR)param1.val.val64;
2605	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2606
2607	/* Register or immediate data */
2608	switch(param2.type)
2609	{
2610	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2611	valpar2 = param2.val.val64;
2612	break;
2613
2614	default:
2615	AssertFailed();
2616	return VERR_EM_INTERPRETER;
2617	}
2618
2619	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2620	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2621	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
2622	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2623	if (RT_FAILURE(rc))
2624	{
2625	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2626	return VERR_EM_INTERPRETER;
2627	}
2628
2629	Log2(("emInterpretBtx: val=%x\n", valpar1));
2630	/* Data read, emulate bit test instruction. */
2631	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2632
2633	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2634
2635	/* Update guest's eflags and finish. */
2636	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2637	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2638
2639	/* And write it back */
2640	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2641	if (RT_SUCCESS(rc))
2642	{
2643	/* All done! */
2644	*pcbSize = 1;
2645	return VINF_SUCCESS;
2646	}
2647	#ifdef IN_RC
2648	}
2649	}
2650	#endif
2651	return VERR_EM_INTERPRETER;
2652	}
2653
2654
2655	#ifndef VBOX_COMPARE_IEM_AND_EM
2656	/**
2657	* LOCK BTR/C/S Emulation.
2658	*/
2659	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2660	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2661	{
2662	void *pvParam1;
2663
2664	DISQPVPARAMVAL param1, param2;
2665	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2666	if(RT_FAILURE(rc))
2667	return VERR_EM_INTERPRETER;
2668
2669	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2670	if(RT_FAILURE(rc))
2671	return VERR_EM_INTERPRETER;
2672
2673	/* The destination is always a virtual address */
2674	if (param1.type != DISQPV_TYPE_ADDRESS)
2675	return VERR_EM_INTERPRETER;
2676
2677	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2678	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2679	uint64_t ValPar2 = param2.val.val64;
2680
2681	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2682	RTGCPTR GCPtrPar1 = param1.val.val64;
2683	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2684	ValPar2 &= 7;
2685
2686	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2687	#ifdef IN_RC
2688	Assert(TRPMHasTrap(pVCpu));
2689	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2690	#endif
2691
2692	PGMPAGEMAPLOCK Lock;
2693	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2694	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2695
2696	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2697
2698	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2699	RTGCUINTREG32 eflags = 0;
2700	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2701	PGMPhysReleasePageMappingLock(pVM, &Lock);
2702	if (RT_FAILURE(rc))
2703	{
2704	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2705	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2706	return VERR_EM_INTERPRETER;
2707	}
2708
2709	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2710
2711	/* Update guest's eflags and finish. */
2712	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2713	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2714
2715	*pcbSize = 1;
2716	return VINF_SUCCESS;
2717	}
2718	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2719
2720
2721	/**
2722	* MOV emulation.
2723	*/
2724	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2725	{
2726	NOREF(pvFault);
2727	DISQPVPARAMVAL param1, param2;
2728	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2729	if(RT_FAILURE(rc))
2730	return VERR_EM_INTERPRETER;
2731
2732	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2733	if(RT_FAILURE(rc))
2734	return VERR_EM_INTERPRETER;
2735
2736	if (param1.type == DISQPV_TYPE_ADDRESS)
2737	{
2738	RTGCPTR pDest;
2739	uint64_t val64;
2740
2741	switch(param1.type)
2742	{
2743	case DISQPV_TYPE_IMMEDIATE:
2744	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2745	return VERR_EM_INTERPRETER;
2746	/* fallthru */
2747
2748	case DISQPV_TYPE_ADDRESS:
2749	pDest = (RTGCPTR)param1.val.val64;
2750	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2751	break;
2752
2753	default:
2754	AssertFailed();
2755	return VERR_EM_INTERPRETER;
2756	}
2757
2758	switch(param2.type)
2759	{
2760	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2761	val64 = param2.val.val64;
2762	break;
2763
2764	default:
2765	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2766	return VERR_EM_INTERPRETER;
2767	}
2768	#ifdef LOG_ENABLED
2769	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2770	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2771	else
2772	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2773	#endif
2774
2775	Assert(param2.size <= 8 && param2.size > 0);
2776	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2777	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2778	if (RT_FAILURE(rc))
2779	return VERR_EM_INTERPRETER;
2780
2781	*pcbSize = param2.size;
2782	}
2783	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2784	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2785	else if ( param1.type == DISQPV_TYPE_REGISTER
2786	&& param2.type == DISQPV_TYPE_REGISTER)
2787	{
2788	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2789	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2790	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2791
2792	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2793	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2794
2795	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2796	switch (param1.size)
2797	{
2798	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2799	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2800	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2801	default:
2802	AssertFailed();
2803	return VERR_EM_INTERPRETER;
2804	}
2805	AssertRCReturn(rc, rc);
2806	}
2807	#endif
2808	else
2809	{ /* read fault */
2810	RTGCPTR pSrc;
2811	uint64_t val64;
2812
2813	/* Source */
2814	switch(param2.type)
2815	{
2816	case DISQPV_TYPE_IMMEDIATE:
2817	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2818	return VERR_EM_INTERPRETER;
2819	/* fallthru */
2820
2821	case DISQPV_TYPE_ADDRESS:
2822	pSrc = (RTGCPTR)param2.val.val64;
2823	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2824	break;
2825
2826	default:
2827	return VERR_EM_INTERPRETER;
2828	}
2829
2830	Assert(param1.size <= 8 && param1.size > 0);
2831	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2832	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2833	if (RT_FAILURE(rc))
2834	return VERR_EM_INTERPRETER;
2835
2836	/* Destination */
2837	switch(param1.type)
2838	{
2839	case DISQPV_TYPE_REGISTER:
2840	switch(param1.size)
2841	{
2842	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2843	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2844	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2845	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2846	default:
2847	return VERR_EM_INTERPRETER;
2848	}
2849	if (RT_FAILURE(rc))
2850	return rc;
2851	break;
2852
2853	default:
2854	return VERR_EM_INTERPRETER;
2855	}
2856	#ifdef LOG_ENABLED
2857	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2858	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2859	else
2860	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2861	#endif
2862	}
2863	return VINF_SUCCESS;
2864	}
2865
2866
2867	#ifndef IN_RC
2868	/**
2869	* [REP] STOSWD emulation
2870	*/
2871	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2872	{
2873	int rc;
2874	RTGCPTR GCDest, GCOffset;
2875	uint32_t cbSize;
2876	uint64_t cTransfers;
2877	int offIncrement;
2878	NOREF(pvFault);
2879
2880	/* Don't support any but these three prefix bytes. */
2881	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2882	return VERR_EM_INTERPRETER;
2883
2884	switch (pDis->uAddrMode)
2885	{
2886	case DISCPUMODE_16BIT:
2887	GCOffset = pRegFrame->di;
2888	cTransfers = pRegFrame->cx;
2889	break;
2890	case DISCPUMODE_32BIT:
2891	GCOffset = pRegFrame->edi;
2892	cTransfers = pRegFrame->ecx;
2893	break;
2894	case DISCPUMODE_64BIT:
2895	GCOffset = pRegFrame->rdi;
2896	cTransfers = pRegFrame->rcx;
2897	break;
2898	default:
2899	AssertFailed();
2900	return VERR_EM_INTERPRETER;
2901	}
2902
2903	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2904	switch (pDis->uOpMode)
2905	{
2906	case DISCPUMODE_16BIT:
2907	cbSize = 2;
2908	break;
2909	case DISCPUMODE_32BIT:
2910	cbSize = 4;
2911	break;
2912	case DISCPUMODE_64BIT:
2913	cbSize = 8;
2914	break;
2915	default:
2916	AssertFailed();
2917	return VERR_EM_INTERPRETER;
2918	}
2919
2920	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2921
2922	if (!(pDis->fPrefix & DISPREFIX_REP))
2923	{
2924	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2925
2926	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2927	if (RT_FAILURE(rc))
2928	return VERR_EM_INTERPRETER;
2929	Assert(rc == VINF_SUCCESS);
2930
2931	/* Update (e/r)di. */
2932	switch (pDis->uAddrMode)
2933	{
2934	case DISCPUMODE_16BIT:
2935	pRegFrame->di += offIncrement;
2936	break;
2937	case DISCPUMODE_32BIT:
2938	pRegFrame->edi += offIncrement;
2939	break;
2940	case DISCPUMODE_64BIT:
2941	pRegFrame->rdi += offIncrement;
2942	break;
2943	default:
2944	AssertFailed();
2945	return VERR_EM_INTERPRETER;
2946	}
2947
2948	}
2949	else
2950	{
2951	if (!cTransfers)
2952	return VINF_SUCCESS;
2953
2954	/*
2955	* Do not try emulate cross page stuff here because we don't know what might
2956	* be waiting for us on the subsequent pages. The caller has only asked us to
2957	* ignore access handlers fro the current page.
2958	* This also fends off big stores which would quickly kill PGMR0DynMap.
2959	*/
2960	if ( cbSize > PAGE_SIZE
2961	\|\| cTransfers > PAGE_SIZE
2962	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2963	{
2964	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2965	GCDest, cbSize, offIncrement, cTransfers));
2966	return VERR_EM_INTERPRETER;
2967	}
2968
2969	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2970	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2971	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2972	cTransfers * cbSize,
2973	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2974	if (rc != VINF_SUCCESS)
2975	{
2976	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2977	return VERR_EM_INTERPRETER;
2978	}
2979
2980	/* REP case */
2981	while (cTransfers)
2982	{
2983	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2984	if (RT_FAILURE(rc))
2985	{
2986	rc = VERR_EM_INTERPRETER;
2987	break;
2988	}
2989
2990	Assert(rc == VINF_SUCCESS);
2991	GCOffset += offIncrement;
2992	GCDest += offIncrement;
2993	cTransfers--;
2994	}
2995
2996	/* Update the registers. */
2997	switch (pDis->uAddrMode)
2998	{
2999	case DISCPUMODE_16BIT:
3000	pRegFrame->di = GCOffset;
3001	pRegFrame->cx = cTransfers;
3002	break;
3003	case DISCPUMODE_32BIT:
3004	pRegFrame->edi = GCOffset;
3005	pRegFrame->ecx = cTransfers;
3006	break;
3007	case DISCPUMODE_64BIT:
3008	pRegFrame->rdi = GCOffset;
3009	pRegFrame->rcx = cTransfers;
3010	break;
3011	default:
3012	AssertFailed();
3013	return VERR_EM_INTERPRETER;
3014	}
3015	}
3016
3017	*pcbSize = cbSize;
3018	return rc;
3019	}
3020	#endif /* !IN_RC */
3021
3022
3023	/**
3024	* [LOCK] CMPXCHG emulation.
3025	*/
3026	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3027	{
3028	DISQPVPARAMVAL param1, param2;
3029	NOREF(pvFault);
3030
3031	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0)
3032	Assert(pDis->Param1.cb <= 4);
3033	#endif
3034
3035	/* Source to make DISQueryParamVal read the register value - ugly hack */
3036	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3037	if(RT_FAILURE(rc))
3038	return VERR_EM_INTERPRETER;
3039
3040	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3041	if(RT_FAILURE(rc))
3042	return VERR_EM_INTERPRETER;
3043
3044	uint64_t valpar;
3045	switch(param2.type)
3046	{
3047	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3048	valpar = param2.val.val64;
3049	break;
3050
3051	default:
3052	return VERR_EM_INTERPRETER;
3053	}
3054
3055	PGMPAGEMAPLOCK Lock;
3056	RTGCPTR GCPtrPar1;
3057	void *pvParam1;
3058	uint64_t eflags;
3059
3060	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3061	switch(param1.type)
3062	{
3063	case DISQPV_TYPE_ADDRESS:
3064	GCPtrPar1 = param1.val.val64;
3065	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3066
3067	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3068	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3069	break;
3070
3071	default:
3072	return VERR_EM_INTERPRETER;
3073	}
3074
3075	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3076
3077	#ifndef VBOX_COMPARE_IEM_AND_EM
3078	if (pDis->fPrefix & DISPREFIX_LOCK)
3079	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3080	else
3081	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3082	#else /* VBOX_COMPARE_IEM_AND_EM */
3083	uint64_t u64;
3084	switch (pDis->Param2.cb)
3085	{
3086	case 1: u64 = (uint8_t )pvParam1; break;
3087	case 2: u64 = (uint16_t )pvParam1; break;
3088	case 4: u64 = (uint32_t )pvParam1; break;
3089	default:
3090	case 8: u64 = (uint64_t )pvParam1; break;
3091	}
3092	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3093	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3094	#endif /* VBOX_COMPARE_IEM_AND_EM */
3095
3096	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3097
3098	/* Update guest's eflags and finish. */
3099	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3100	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3101
3102	*pcbSize = param2.size;
3103	PGMPhysReleasePageMappingLock(pVM, &Lock);
3104	return VINF_SUCCESS;
3105	}
3106
3107
3108	/**
3109	* [LOCK] CMPXCHG8B emulation.
3110	*/
3111	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3112	{
3113	DISQPVPARAMVAL param1;
3114	NOREF(pvFault);
3115
3116	/* Source to make DISQueryParamVal read the register value - ugly hack */
3117	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3118	if(RT_FAILURE(rc))
3119	return VERR_EM_INTERPRETER;
3120
3121	RTGCPTR GCPtrPar1;
3122	void *pvParam1;
3123	uint64_t eflags;
3124	PGMPAGEMAPLOCK Lock;
3125
3126	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3127	switch(param1.type)
3128	{
3129	case DISQPV_TYPE_ADDRESS:
3130	GCPtrPar1 = param1.val.val64;
3131	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3132
3133	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3134	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3135	break;
3136
3137	default:
3138	return VERR_EM_INTERPRETER;
3139	}
3140
3141	LogFlow(("%s %RGv=%08x eax=%08x\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax));
3142
3143	#ifndef VBOX_COMPARE_IEM_AND_EM
3144	if (pDis->fPrefix & DISPREFIX_LOCK)
3145	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3146	else
3147	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3148	#else /* VBOX_COMPARE_IEM_AND_EM */
3149	uint64_t u64 = (uint64_t )pvParam1;
3150	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3151	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3152	#endif /* VBOX_COMPARE_IEM_AND_EM */
3153
3154	LogFlow(("%s %RGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pDis), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3155
3156	/* Update guest's eflags and finish; note that only ZF is affected. */
3157	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3158	\| (eflags & (X86_EFL_ZF));
3159
3160	*pcbSize = 8;
3161	PGMPhysReleasePageMappingLock(pVM, &Lock);
3162	return VINF_SUCCESS;
3163	}
3164
3165
3166	#ifdef IN_RC /** @todo test+enable for HM as well. */
3167	/**
3168	* [LOCK] XADD emulation.
3169	*/
3170	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3171	{
3172	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3173	DISQPVPARAMVAL param1;
3174	void *pvParamReg2;
3175	size_t cbParamReg2;
3176	NOREF(pvFault);
3177
3178	/* Source to make DISQueryParamVal read the register value - ugly hack */
3179	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3180	if(RT_FAILURE(rc))
3181	return VERR_EM_INTERPRETER;
3182
3183	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3184	Assert(cbParamReg2 <= 4);
3185	if(RT_FAILURE(rc))
3186	return VERR_EM_INTERPRETER;
3187
3188	#ifdef IN_RC
3189	if (TRPMHasTrap(pVCpu))
3190	{
3191	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3192	{
3193	#endif
3194	RTGCPTR GCPtrPar1;
3195	void *pvParam1;
3196	uint32_t eflags;
3197	PGMPAGEMAPLOCK Lock;
3198
3199	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3200	switch(param1.type)
3201	{
3202	case DISQPV_TYPE_ADDRESS:
3203	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3204	#ifdef IN_RC
3205	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3206	#endif
3207
3208	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3209	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3210	break;
3211
3212	default:
3213	return VERR_EM_INTERPRETER;
3214	}
3215
3216	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3217
3218	#ifndef VBOX_COMPARE_IEM_AND_EM
3219	if (pDis->fPrefix & DISPREFIX_LOCK)
3220	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3221	else
3222	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3223	#else /* VBOX_COMPARE_IEM_AND_EM */
3224	uint64_t u64;
3225	switch (cbParamReg2)
3226	{
3227	case 1: u64 = (uint8_t )pvParam1; break;
3228	case 2: u64 = (uint16_t )pvParam1; break;
3229	case 4: u64 = (uint32_t )pvParam1; break;
3230	default:
3231	case 8: u64 = (uint64_t )pvParam1; break;
3232	}
3233	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3234	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3235	#endif /* VBOX_COMPARE_IEM_AND_EM */
3236
3237	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3238
3239	/* Update guest's eflags and finish. */
3240	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3241	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3242
3243	*pcbSize = cbParamReg2;
3244	PGMPhysReleasePageMappingLock(pVM, &Lock);
3245	return VINF_SUCCESS;
3246	#ifdef IN_RC
3247	}
3248	}
3249
3250	return VERR_EM_INTERPRETER;
3251	#endif
3252	}
3253	#endif /* IN_RC */
3254
3255
3256	/**
3257	* WBINVD Emulation.
3258	*/
3259	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3260	{
3261	/* Nothing to do. */
3262	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3263	return VINF_SUCCESS;
3264	}
3265
3266
3267	/**
3268	* INVLPG Emulation.
3269	*/
3270	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3271	{
3272	DISQPVPARAMVAL param1;
3273	RTGCPTR addr;
3274	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3275
3276	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3277	if(RT_FAILURE(rc))
3278	return VERR_EM_INTERPRETER;
3279
3280	switch(param1.type)
3281	{
3282	case DISQPV_TYPE_IMMEDIATE:
3283	case DISQPV_TYPE_ADDRESS:
3284	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3285	return VERR_EM_INTERPRETER;
3286	addr = (RTGCPTR)param1.val.val64;
3287	break;
3288
3289	default:
3290	return VERR_EM_INTERPRETER;
3291	}
3292
3293	/** @todo is addr always a flat linear address or ds based
3294	* (in absence of segment override prefixes)????
3295	*/
3296	#ifdef IN_RC
3297	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3298	#endif
3299	rc = PGMInvalidatePage(pVCpu, addr);
3300	if ( rc == VINF_SUCCESS
3301	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3302	return VINF_SUCCESS;
3303	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3304	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3305	VERR_EM_INTERPRETER);
3306	return rc;
3307	}
3308
3309	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3310
3311	/**
3312	* CPUID Emulation.
3313	*/
3314	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3315	{
3316	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3317	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3318	return rc;
3319	}
3320
3321
3322	/**
3323	* CLTS Emulation.
3324	*/
3325	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3326	{
3327	NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3328	return EMInterpretCLTS(pVM, pVCpu);
3329	}
3330
3331
3332	/**
3333	* LMSW Emulation.
3334	*/
3335	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3336	{
3337	DISQPVPARAMVAL param1;
3338	uint32_t val;
3339	NOREF(pvFault); NOREF(pcbSize);
3340
3341	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3342	if(RT_FAILURE(rc))
3343	return VERR_EM_INTERPRETER;
3344
3345	switch(param1.type)
3346	{
3347	case DISQPV_TYPE_IMMEDIATE:
3348	case DISQPV_TYPE_ADDRESS:
3349	if(!(param1.flags & DISQPV_FLAG_16))
3350	return VERR_EM_INTERPRETER;
3351	val = param1.val.val32;
3352	break;
3353
3354	default:
3355	return VERR_EM_INTERPRETER;
3356	}
3357
3358	LogFlow(("emInterpretLmsw %x\n", val));
3359	return EMInterpretLMSW(pVM, pVCpu, pRegFrame, val);
3360	}
3361
3362	#ifdef EM_EMULATE_SMSW
3363	/**
3364	* SMSW Emulation.
3365	*/
3366	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3367	{
3368	NOREF(pvFault); NOREF(pcbSize);
3369	DISQPVPARAMVAL param1;
3370	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3371
3372	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3373	if(RT_FAILURE(rc))
3374	return VERR_EM_INTERPRETER;
3375
3376	switch(param1.type)
3377	{
3378	case DISQPV_TYPE_IMMEDIATE:
3379	if(param1.size != sizeof(uint16_t))
3380	return VERR_EM_INTERPRETER;
3381	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3382	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3383	break;
3384
3385	case DISQPV_TYPE_ADDRESS:
3386	{
3387	RTGCPTR pParam1;
3388
3389	/* Actually forced to 16 bits regardless of the operand size. */
3390	if(param1.size != sizeof(uint16_t))
3391	return VERR_EM_INTERPRETER;
3392
3393	pParam1 = (RTGCPTR)param1.val.val64;
3394	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3395	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3396
3397	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3398	if (RT_FAILURE(rc))
3399	{
3400	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3401	return VERR_EM_INTERPRETER;
3402	}
3403	break;
3404	}
3405
3406	default:
3407	return VERR_EM_INTERPRETER;
3408	}
3409
3410	LogFlow(("emInterpretSmsw %x\n", cr0));
3411	return rc;
3412	}
3413	#endif
3414
3415	/**
3416	* MOV CRx
3417	*/
3418	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3419	{
3420	NOREF(pvFault); NOREF(pcbSize);
3421	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3422	return EMInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3423
3424	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3425	return EMInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3426
3427	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3428	}
3429
3430
3431	/**
3432	* MOV DRx
3433	*/
3434	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3435	{
3436	int rc = VERR_EM_INTERPRETER;
3437	NOREF(pvFault); NOREF(pcbSize);
3438
3439	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3440	{
3441	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3442	}
3443	else
3444	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3445	{
3446	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3447	}
3448	else
3449	AssertMsgFailed(("Unexpected debug register move\n"));
3450
3451	return rc;
3452	}
3453
3454
3455	/**
3456	* LLDT Emulation.
3457	*/
3458	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3459	{
3460	DISQPVPARAMVAL param1;
3461	RTSEL sel;
3462	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3463
3464	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3465	if(RT_FAILURE(rc))
3466	return VERR_EM_INTERPRETER;
3467
3468	switch(param1.type)
3469	{
3470	case DISQPV_TYPE_ADDRESS:
3471	return VERR_EM_INTERPRETER; //feeling lazy right now
3472
3473	case DISQPV_TYPE_IMMEDIATE:
3474	if(!(param1.flags & DISQPV_FLAG_16))
3475	return VERR_EM_INTERPRETER;
3476	sel = (RTSEL)param1.val.val16;
3477	break;
3478
3479	default:
3480	return VERR_EM_INTERPRETER;
3481	}
3482
3483	#ifdef IN_RING0
3484	/* Only for the VT-x real-mode emulation case. */
3485	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3486	CPUMSetGuestLDTR(pVCpu, sel);
3487	return VINF_SUCCESS;
3488	#else
3489	if (sel == 0)
3490	{
3491	if (CPUMGetHyperLDTR(pVCpu) == 0)
3492	{
3493	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3494	return VINF_SUCCESS;
3495	}
3496	}
3497	//still feeling lazy
3498	return VERR_EM_INTERPRETER;
3499	#endif
3500	}
3501
3502	#ifdef IN_RING0
3503	/**
3504	* LIDT/LGDT Emulation.
3505	*/
3506	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3507	{
3508	DISQPVPARAMVAL param1;
3509	RTGCPTR pParam1;
3510	X86XDTR32 dtr32;
3511	NOREF(pvFault); NOREF(pcbSize);
3512
3513	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3514
3515	/* Only for the VT-x real-mode emulation case. */
3516	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3517
3518	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3519	if(RT_FAILURE(rc))
3520	return VERR_EM_INTERPRETER;
3521
3522	switch(param1.type)
3523	{
3524	case DISQPV_TYPE_ADDRESS:
3525	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3526	break;
3527
3528	default:
3529	return VERR_EM_INTERPRETER;
3530	}
3531
3532	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3533	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3534
3535	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3536	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3537
3538	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3539	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3540	else
3541	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3542
3543	return VINF_SUCCESS;
3544	}
3545	#endif
3546
3547
3548	#ifdef IN_RC
3549	/**
3550	* STI Emulation.
3551	*
3552	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3553	*/
3554	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3555	{
3556	NOREF(pcbSize);
3557	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3558
3559	if(!pGCState)
3560	{
3561	Assert(pGCState);
3562	return VERR_EM_INTERPRETER;
3563	}
3564	pGCState->uVMFlags \|= X86_EFL_IF;
3565
3566	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3567	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3568
3569	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3570	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3571
3572	return VINF_SUCCESS;
3573	}
3574	#endif /* IN_RC */
3575
3576
3577	/**
3578	* HLT Emulation.
3579	*/
3580	static VBOXSTRICTRC
3581	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3582	{
3583	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3584	return VINF_EM_HALT;
3585	}
3586
3587
3588	/**
3589	* RDTSC Emulation.
3590	*/
3591	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3592	{
3593	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3594	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3595	}
3596
3597	/**
3598	* RDPMC Emulation
3599	*/
3600	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3601	{
3602	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3603	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3604	}
3605
3606
3607	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3608	{
3609	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3610	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3611	}
3612
3613
3614	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3615	{
3616	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3617	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3618	}
3619
3620
3621	/**
3622	* RDMSR Emulation.
3623	*/
3624	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3625	{
3626	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3627	different, so we play safe by completely disassembling the instruction. */
3628	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3629	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3630	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3631	}
3632
3633
3634	/**
3635	* WRMSR Emulation.
3636	*/
3637	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3638	{
3639	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3640	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3641	}
3642
3643
3644	/**
3645	* Internal worker.
3646	* @copydoc emInterpretInstructionCPUOuter
3647	*/
3648	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3649	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3650	{
3651	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3652	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3653	Assert(pcbSize);
3654	*pcbSize = 0;
3655
3656	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3657	{
3658	/*
3659	* Only supervisor guest code!!
3660	* And no complicated prefixes.
3661	*/
3662	/* Get the current privilege level. */
3663	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3664	#ifdef VBOX_WITH_RAW_RING1
3665	if ( !EMIsRawRing1Enabled(pVM)
3666	\|\| cpl > 1
3667	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3668	)
3669	#endif
3670	{
3671	if ( cpl != 0
3672	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3673	{
3674	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3675	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3676	return VERR_EM_INTERPRETER;
3677	}
3678	}
3679	}
3680	else
3681	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3682
3683	#ifdef IN_RC
3684	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3685	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3686	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3687	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3688	&& pDis->pCurInstr->uOpcode != OP_XADD
3689	&& pDis->pCurInstr->uOpcode != OP_OR
3690	&& pDis->pCurInstr->uOpcode != OP_AND
3691	&& pDis->pCurInstr->uOpcode != OP_XOR
3692	&& pDis->pCurInstr->uOpcode != OP_BTR
3693	)
3694	)
3695	#else
3696	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3697	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3698	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3699	)
3700	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3701	&& pDis->pCurInstr->uOpcode != OP_OR
3702	&& pDis->pCurInstr->uOpcode != OP_AND
3703	&& pDis->pCurInstr->uOpcode != OP_XOR
3704	&& pDis->pCurInstr->uOpcode != OP_BTR
3705	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3706	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3707	)
3708	)
3709	#endif
3710	{
3711	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3712	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3713	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3714	return VERR_EM_INTERPRETER;
3715	}
3716
3717	#if HC_ARCH_BITS == 32
3718	/*
3719	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3720	* Whitelisted instructions are safe.
3721	*/
3722	if ( pDis->Param1.cb > 4
3723	&& CPUMIsGuestIn64BitCode(pVCpu))
3724	{
3725	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3726	if ( uOpCode != OP_STOSWD
3727	&& uOpCode != OP_MOV
3728	&& uOpCode != OP_CMPXCHG8B
3729	&& uOpCode != OP_XCHG
3730	&& uOpCode != OP_BTS
3731	&& uOpCode != OP_BTR
3732	&& uOpCode != OP_BTC
3733	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL_IN_R0
3734	&& uOpCode != OP_CMPXCHG /* solaris */
3735	&& uOpCode != OP_AND /* windows */
3736	&& uOpCode != OP_OR /* windows */
3737	&& uOpCode != OP_XOR /* because we can */
3738	&& uOpCode != OP_ADD /* windows (dripple) */
3739	&& uOpCode != OP_ADC /* because we can */
3740	&& uOpCode != OP_SUB /* because we can */
3741	/** @todo OP_BTS or is that a different kind of failure? */
3742	# endif
3743	)
3744	{
3745	# ifdef VBOX_WITH_STATISTICS
3746	switch (pDis->pCurInstr->uOpcode)
3747	{
3748	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3749	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3750	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3751	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3752	INTERPRET_FAILED_CASE(OP_INC,Inc);
3753	INTERPRET_FAILED_CASE(OP_POP,Pop);
3754	INTERPRET_FAILED_CASE(OP_OR, Or);
3755	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3756	INTERPRET_FAILED_CASE(OP_AND,And);
3757	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3758	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3759	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3760	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3761	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3762	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3763	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3764	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3765	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3766	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3767	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3768	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3769	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3770	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3771	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3772	INTERPRET_FAILED_CASE(OP_ADD,Add);
3773	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3774	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3775	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3776	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3777	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3778	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3779	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3780	INTERPRET_FAILED_CASE(OP_STI, Sti);
3781	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3782	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3783	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3784	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3785	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3786	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3787	# undef INTERPRET_FAILED_CASE
3788	default:
3789	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3790	break;
3791	}
3792	# endif /* VBOX_WITH_STATISTICS */
3793	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3794	return VERR_EM_INTERPRETER;
3795	}
3796	}
3797	#endif
3798
3799	VBOXSTRICTRC rc;
3800	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3801	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3802	#endif
3803	switch (pDis->pCurInstr->uOpcode)
3804	{
3805	/*
3806	* Macros for generating the right case statements.
3807	*/
3808	# ifndef VBOX_COMPARE_IEM_AND_EM
3809	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3810	case opcode:\
3811	if (pDis->fPrefix & DISPREFIX_LOCK) \
3812	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3813	else \
3814	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3815	if (RT_SUCCESS(rc)) \
3816	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3817	else \
3818	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3819	return rc
3820	# else /* VBOX_COMPARE_IEM_AND_EM */
3821	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3822	case opcode:\
3823	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3824	if (RT_SUCCESS(rc)) \
3825	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3826	else \
3827	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3828	return rc
3829	# endif /* VBOX_COMPARE_IEM_AND_EM */
3830
3831	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3832	case opcode:\
3833	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3834	if (RT_SUCCESS(rc)) \
3835	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3836	else \
3837	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3838	return rc
3839
3840	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3841	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3842	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3843	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3844
3845	#define INTERPRET_CASE(opcode, Instr) \
3846	case opcode:\
3847	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3848	if (RT_SUCCESS(rc)) \
3849	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3850	else \
3851	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3852	return rc
3853
3854	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3855	case opcode:\
3856	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3857	if (RT_SUCCESS(rc)) \
3858	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3859	else \
3860	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3861	return rc
3862
3863	#define INTERPRET_STAT_CASE(opcode, Instr) \
3864	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3865
3866	/*
3867	* The actual case statements.
3868	*/
3869	INTERPRET_CASE(OP_XCHG,Xchg);
3870	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3871	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3872	INTERPRET_CASE(OP_POP,Pop);
3873	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3874	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3875	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3876	INTERPRET_CASE(OP_MOV,Mov);
3877	#ifndef IN_RC
3878	INTERPRET_CASE(OP_STOSWD,StosWD);
3879	#endif
3880	INTERPRET_CASE(OP_INVLPG,InvlPg);
3881	INTERPRET_CASE(OP_CPUID,CpuId);
3882	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3883	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3884	#ifdef IN_RING0
3885	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3886	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3887	#endif
3888	INTERPRET_CASE(OP_LLDT,LLdt);
3889	INTERPRET_CASE(OP_LMSW,Lmsw);
3890	#ifdef EM_EMULATE_SMSW
3891	INTERPRET_CASE(OP_SMSW,Smsw);
3892	#endif
3893	INTERPRET_CASE(OP_CLTS,Clts);
3894	INTERPRET_CASE(OP_MONITOR, Monitor);
3895	INTERPRET_CASE(OP_MWAIT, MWait);
3896	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3897	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3898	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3899	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3900	INTERPRET_CASE(OP_ADC,Adc);
3901	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3902	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3903	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3904	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3905	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3906	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3907	#ifdef IN_RC
3908	INTERPRET_CASE(OP_STI,Sti);
3909	INTERPRET_CASE(OP_XADD, XAdd);
3910	INTERPRET_CASE(OP_IRET,Iret);
3911	#endif
3912	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3913	INTERPRET_CASE(OP_HLT,Hlt);
3914	INTERPRET_CASE(OP_WBINVD,WbInvd);
3915	#ifdef VBOX_WITH_STATISTICS
3916	# ifndef IN_RC
3917	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3918	# endif
3919	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3920	#endif
3921
3922	default:
3923	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3924	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3925	return VERR_EM_INTERPRETER;
3926
3927	#undef INTERPRET_CASE_EX_PARAM2
3928	#undef INTERPRET_STAT_CASE
3929	#undef INTERPRET_CASE_EX
3930	#undef INTERPRET_CASE
3931	} /* switch (opcode) */
3932	/* not reached */
3933	}
3934
3935	/**
3936	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3937	*
3938	* EIP is NOT updated!
3939	*
3940	* @returns VBox strict status code.
3941	* @retval VINF_* Scheduling instructions. When these are returned, it
3942	* starts to get a bit tricky to know whether code was
3943	* executed or not... We'll address this when it becomes a problem.
3944	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3945	* @retval VERR_* Fatal errors.
3946	*
3947	* @param pVCpu Pointer to the VMCPU.
3948	* @param pDis The disassembler cpu state for the instruction to be
3949	* interpreted.
3950	* @param pRegFrame The register frame. EIP is NOT changed!
3951	* @param pvFault The fault address (CR2).
3952	* @param pcbSize Size of the write (if applicable).
3953	* @param enmCodeType Code type (user/supervisor)
3954	*
3955	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3956	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3957	* to worry about e.g. invalid modrm combinations (!)
3958	*
3959	* @todo At this time we do NOT check if the instruction overwrites vital information.
3960	* Make sure this can't happen!! (will add some assertions/checks later)
3961	*/
3962	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3963	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3964	{
3965	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3966	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3967	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3968	if (RT_SUCCESS(rc))
3969	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3970	else
3971	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3972	return rc;
3973	}
3974
3975
3976	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 50590

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