EMAll.cpp@ 60852

Last change on this file since 60852 was 60804, checked in by vboxsync, 9 years ago
VMM: Introduced the new APIC update force-flag and relevant fixes, Win8.1 SMP boots now. VMM/HMVMXR0: Fixed the HLT exit to use instruction length and also keep the INHIBIT force-flag more in sync with the VT-x's guest-interruptibility state.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 142.1 KB

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1	/* $Id: EMAll.cpp 60804 2016-05-03 14:13:51Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/patm.h>
27	#include <VBox/vmm/csam.h>
28	#include <VBox/vmm/pgm.h>
29	#ifdef VBOX_WITH_IEM
30	# include <VBox/vmm/iem.h>
31	#endif
32	#include <VBox/vmm/iom.h>
33	#include <VBox/vmm/stam.h>
34	#include "EMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/vmm.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/tm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include "internal/pgm.h"
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50	#ifndef IN_RC
51	#undef VBOX_WITH_IEM
52	#endif
53	#ifdef VBOX_WITH_IEM
54	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
55	//# define VBOX_SAME_AS_EM
56	//# define VBOX_COMPARE_IEM_LAST
57	#endif
58
59	#ifdef VBOX_WITH_RAW_RING1
60	# define EM_EMULATE_SMSW
61	#endif
62
63
64	/*********************************************************************************************************************************
65	* Defined Constants And Macros *
66	*********************************************************************************************************************************/
67	/** @def EM_ASSERT_FAULT_RETURN
68	* Safety check.
69	*
70	* Could in theory misfire on a cross page boundary access...
71	*
72	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
73	* turns up an alias page instead of the original faulting one and annoying the
74	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
75	*/
76	#if 0
77	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
78	#else
79	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
80	#endif
81
82
83	/*********************************************************************************************************************************
84	* Internal Functions *
85	*********************************************************************************************************************************/
86	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
87	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
88	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
89	#endif
90
91
92	/*********************************************************************************************************************************
93	* Global Variables *
94	*********************************************************************************************************************************/
95	#ifdef VBOX_COMPARE_IEM_AND_EM
96	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
97	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
98	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
99	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
100	static uint32_t g_fIncomingFFs;
101	static CPUMCTX g_IncomingCtx;
102	static bool g_fIgnoreRaxRdx = false;
103
104	static uint32_t g_fEmFFs;
105	static CPUMCTX g_EmCtx;
106	static uint8_t g_abEmWrote[256];
107	static size_t g_cbEmWrote;
108
109	static uint32_t g_fIemFFs;
110	static CPUMCTX g_IemCtx;
111	extern uint8_t g_abIemWrote[256];
112	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
113	extern size_t g_cbIemWrote;
114	#else
115	static size_t g_cbIemWrote;
116	#endif
117	#endif
118
119
120	/**
121	* Get the current execution manager status.
122	*
123	* @returns Current status.
124	* @param pVCpu The cross context virtual CPU structure.
125	*/
126	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
127	{
128	return pVCpu->em.s.enmState;
129	}
130
131
132	/**
133	* Sets the current execution manager status. (use only when you know what you're doing!)
134	*
135	* @param pVCpu The cross context virtual CPU structure.
136	* @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
137	*/
138	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
139	{
140	/* Only allowed combination: */
141	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
142	pVCpu->em.s.enmState = enmNewState;
143	}
144
145
146	/**
147	* Sets the PC for which interrupts should be inhibited.
148	*
149	* @param pVCpu The cross context virtual CPU structure.
150	* @param PC The PC.
151	*/
152	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
153	{
154	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
155	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
156	}
157
158
159	/**
160	* Gets the PC for which interrupts should be inhibited.
161	*
162	* There are a few instructions which inhibits or delays interrupts
163	* for the instruction following them. These instructions are:
164	* - STI
165	* - MOV SS, r/m16
166	* - POP SS
167	*
168	* @returns The PC for which interrupts should be inhibited.
169	* @param pVCpu The cross context virtual CPU structure.
170	*
171	*/
172	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
173	{
174	return pVCpu->em.s.GCPtrInhibitInterrupts;
175	}
176
177
178	/**
179	* Prepare an MWAIT - essentials of the MONITOR instruction.
180	*
181	* @returns VINF_SUCCESS
182	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
183	* @param rax The content of RAX.
184	* @param rcx The content of RCX.
185	* @param rdx The content of RDX.
186	* @param GCPhys The physical address corresponding to rax.
187	*/
188	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
189	{
190	pVCpu->em.s.MWait.uMonitorRAX = rax;
191	pVCpu->em.s.MWait.uMonitorRCX = rcx;
192	pVCpu->em.s.MWait.uMonitorRDX = rdx;
193	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
194	/** @todo Make use of GCPhys. */
195	NOREF(GCPhys);
196	/** @todo Complete MONITOR implementation. */
197	return VINF_SUCCESS;
198	}
199
200
201	/**
202	* Performs an MWAIT.
203	*
204	* @returns VINF_SUCCESS
205	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
206	* @param rax The content of RAX.
207	* @param rcx The content of RCX.
208	*/
209	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
210	{
211	pVCpu->em.s.MWait.uMWaitRAX = rax;
212	pVCpu->em.s.MWait.uMWaitRCX = rcx;
213	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
214	if (rcx)
215	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
216	else
217	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
218	/** @todo not completely correct?? */
219	return VINF_EM_HALT;
220	}
221
222
223
224	/**
225	* Determine if we should continue execution in HM after encountering an mwait
226	* instruction.
227	*
228	* Clears MWAIT flags if returning @c true.
229	*
230	* @returns true if we should continue, false if we should halt.
231	* @param pVCpu The cross context virtual CPU structure.
232	* @param pCtx Current CPU context.
233	*/
234	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
235	{
236	if ( pCtx->eflags.Bits.u1IF
237	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
238	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
239	{
240	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
241	{
242	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
243	return true;
244	}
245	}
246
247	return false;
248	}
249
250
251	/**
252	* Determine if we should continue execution in HM after encountering a hlt
253	* instruction.
254	*
255	* @returns true if we should continue, false if we should halt.
256	* @param pVCpu The cross context virtual CPU structure.
257	* @param pCtx Current CPU context.
258	*/
259	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
260	{
261	if (pCtx->eflags.Bits.u1IF)
262	return !!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
263	return false;
264	}
265
266
267	/**
268	* Locks REM execution to a single VCPU.
269	*
270	* @param pVM The cross context VM structure.
271	*/
272	VMMDECL(void) EMRemLock(PVM pVM)
273	{
274	#ifdef VBOX_WITH_REM
275	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
276	return; /* early init */
277
278	Assert(!PGMIsLockOwner(pVM));
279	Assert(!IOMIsLockWriteOwner(pVM));
280	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
281	AssertRCSuccess(rc);
282	#endif
283	}
284
285
286	/**
287	* Unlocks REM execution
288	*
289	* @param pVM The cross context VM structure.
290	*/
291	VMMDECL(void) EMRemUnlock(PVM pVM)
292	{
293	#ifdef VBOX_WITH_REM
294	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
295	return; /* early init */
296
297	PDMCritSectLeave(&pVM->em.s.CritSectREM);
298	#endif
299	}
300
301
302	/**
303	* Check if this VCPU currently owns the REM lock.
304	*
305	* @returns bool owner/not owner
306	* @param pVM The cross context VM structure.
307	*/
308	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
309	{
310	#ifdef VBOX_WITH_REM
311	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
312	return true; /* early init */
313
314	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
315	#else
316	return true;
317	#endif
318	}
319
320
321	/**
322	* Try to acquire the REM lock.
323	*
324	* @returns VBox status code
325	* @param pVM The cross context VM structure.
326	*/
327	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
328	{
329	#ifdef VBOX_WITH_REM
330	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
331	return VINF_SUCCESS; /* early init */
332
333	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
334	#else
335	return VINF_SUCCESS;
336	#endif
337	}
338
339
340	/**
341	* @callback_method_impl{FNDISREADBYTES}
342	*/
343	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
344	{
345	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
346	#if defined(IN_RC) \|\| defined(IN_RING3)
347	PVM pVM = pVCpu->CTX_SUFF(pVM);
348	#endif
349	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
350	int rc;
351
352	/*
353	* Figure how much we can or must read.
354	*/
355	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
356	if (cbToRead > cbMaxRead)
357	cbToRead = cbMaxRead;
358	else if (cbToRead < cbMinRead)
359	cbToRead = cbMinRead;
360
361	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
362	/*
363	* We might be called upon to interpret an instruction in a patch.
364	*/
365	if (PATMIsPatchGCAddr(pVCpu->CTX_SUFF(pVM), uSrcAddr))
366	{
367	# ifdef IN_RC
368	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
369	# else
370	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVCpu->CTX_SUFF(pVM), uSrcAddr), cbToRead);
371	# endif
372	rc = VINF_SUCCESS;
373	}
374	else
375	#endif
376	{
377	# ifdef IN_RC
378	/*
379	* Try access it thru the shadow page tables first. Fall back on the
380	* slower PGM method if it fails because the TLB or page table was
381	* modified recently.
382	*/
383	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
384	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
385	{
386	cbToRead = cbMinRead;
387	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
388	}
389	if (rc == VERR_ACCESS_DENIED)
390	#endif
391	{
392	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
393	if (RT_FAILURE(rc))
394	{
395	if (cbToRead > cbMinRead)
396	{
397	cbToRead = cbMinRead;
398	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
399	}
400	if (RT_FAILURE(rc))
401	{
402	#ifndef IN_RC
403	/*
404	* If we fail to find the page via the guest's page tables
405	* we invalidate the page in the host TLB (pertaining to
406	* the guest in the NestedPaging case). See @bugref{6043}.
407	*/
408	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
409	{
410	HMInvalidatePage(pVCpu, uSrcAddr);
411	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
412	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
413	}
414	#endif
415	}
416	}
417	}
418	}
419
420	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
421	return rc;
422	}
423
424
425	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
426	{
427	NOREF(pVM);
428	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
429	}
430
431
432	/**
433	* Disassembles the current instruction.
434	*
435	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
436	* details.
437	*
438	* @param pVM The cross context VM structure.
439	* @param pVCpu The cross context virtual CPU structure.
440	* @param pDis Where to return the parsed instruction info.
441	* @param pcbInstr Where to return the instruction size. (optional)
442	*/
443	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
444	{
445	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
446	RTGCPTR GCPtrInstr;
447	#if 0
448	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
449	#else
450	/** @todo Get the CPU mode as well while we're at it! */
451	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
452	pCtxCore->rip, &GCPtrInstr);
453	#endif
454	if (RT_FAILURE(rc))
455	{
456	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
457	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
458	return rc;
459	}
460	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
461	}
462
463
464	/**
465	* Disassembles one instruction.
466	*
467	* This is used by internally by the interpreter and by trap/access handlers.
468	*
469	* @returns VBox status code.
470	*
471	* @param pVM The cross context VM structure.
472	* @param pVCpu The cross context virtual CPU structure.
473	* @param GCPtrInstr The flat address of the instruction.
474	* @param pCtxCore The context core (used to determine the cpu mode).
475	* @param pDis Where to return the parsed instruction info.
476	* @param pcbInstr Where to return the instruction size. (optional)
477	*/
478	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
479	PDISCPUSTATE pDis, unsigned *pcbInstr)
480	{
481	NOREF(pVM);
482	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
483	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
484	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
485	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
486	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
487	if (RT_SUCCESS(rc))
488	return VINF_SUCCESS;
489	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
490	return rc;
491	}
492
493
494	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
495	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
496	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
497	uint32_t cbEm, uint32_t cbIem)
498	{
499	/* Quick compare. */
500	if ( rcEm == rcIem
501	&& cbEm == cbIem
502	&& g_cbEmWrote == g_cbIemWrote
503	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
504	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
505	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
506	)
507	return;
508
509	/* Report exact differences. */
510	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
511	if (rcEm != rcIem)
512	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
513	else if (cbEm != cbIem)
514	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
515
516	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
517	{
518	if (g_cbIemWrote != g_cbEmWrote)
519	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
520	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
521	{
522	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
523	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
524	}
525
526	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
527	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
528	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
529
530	# define CHECK_FIELD(a_Field) \
531	do \
532	{ \
533	if (pEmCtx->a_Field != pIemCtx->a_Field) \
534	{ \
535	switch (sizeof(pEmCtx->a_Field)) \
536	{ \
537	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
538	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
539	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
540	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
541	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
542	} \
543	cDiffs++; \
544	} \
545	} while (0)
546
547	# define CHECK_BIT_FIELD(a_Field) \
548	do \
549	{ \
550	if (pEmCtx->a_Field != pIemCtx->a_Field) \
551	{ \
552	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
553	cDiffs++; \
554	} \
555	} while (0)
556
557	# define CHECK_SEL(a_Sel) \
558	do \
559	{ \
560	CHECK_FIELD(a_Sel.Sel); \
561	CHECK_FIELD(a_Sel.Attr.u); \
562	CHECK_FIELD(a_Sel.u64Base); \
563	CHECK_FIELD(a_Sel.u32Limit); \
564	CHECK_FIELD(a_Sel.fFlags); \
565	} while (0)
566
567	unsigned cDiffs = 0;
568	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
569	{
570	RTLogPrintf(" the FPU state differs\n");
571	cDiffs++;
572	CHECK_FIELD(fpu.FCW);
573	CHECK_FIELD(fpu.FSW);
574	CHECK_FIELD(fpu.FTW);
575	CHECK_FIELD(fpu.FOP);
576	CHECK_FIELD(fpu.FPUIP);
577	CHECK_FIELD(fpu.CS);
578	CHECK_FIELD(fpu.Rsrvd1);
579	CHECK_FIELD(fpu.FPUDP);
580	CHECK_FIELD(fpu.DS);
581	CHECK_FIELD(fpu.Rsrvd2);
582	CHECK_FIELD(fpu.MXCSR);
583	CHECK_FIELD(fpu.MXCSR_MASK);
584	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
585	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
586	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
587	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
588	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
589	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
590	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
591	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
592	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
593	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
594	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
595	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
596	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
597	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
598	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
599	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
600	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
601	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
602	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
603	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
604	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
605	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
606	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
607	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
608	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
609	CHECK_FIELD(fpu.au32RsrvdRest[i]);
610	}
611	CHECK_FIELD(rip);
612	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
613	{
614	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
615	CHECK_BIT_FIELD(rflags.Bits.u1CF);
616	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
617	CHECK_BIT_FIELD(rflags.Bits.u1PF);
618	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
619	CHECK_BIT_FIELD(rflags.Bits.u1AF);
620	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
621	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
622	CHECK_BIT_FIELD(rflags.Bits.u1SF);
623	CHECK_BIT_FIELD(rflags.Bits.u1TF);
624	CHECK_BIT_FIELD(rflags.Bits.u1IF);
625	CHECK_BIT_FIELD(rflags.Bits.u1DF);
626	CHECK_BIT_FIELD(rflags.Bits.u1OF);
627	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
628	CHECK_BIT_FIELD(rflags.Bits.u1NT);
629	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
630	CHECK_BIT_FIELD(rflags.Bits.u1RF);
631	CHECK_BIT_FIELD(rflags.Bits.u1VM);
632	CHECK_BIT_FIELD(rflags.Bits.u1AC);
633	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
634	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
635	CHECK_BIT_FIELD(rflags.Bits.u1ID);
636	}
637
638	if (!g_fIgnoreRaxRdx)
639	CHECK_FIELD(rax);
640	CHECK_FIELD(rcx);
641	if (!g_fIgnoreRaxRdx)
642	CHECK_FIELD(rdx);
643	CHECK_FIELD(rbx);
644	CHECK_FIELD(rsp);
645	CHECK_FIELD(rbp);
646	CHECK_FIELD(rsi);
647	CHECK_FIELD(rdi);
648	CHECK_FIELD(r8);
649	CHECK_FIELD(r9);
650	CHECK_FIELD(r10);
651	CHECK_FIELD(r11);
652	CHECK_FIELD(r12);
653	CHECK_FIELD(r13);
654	CHECK_SEL(cs);
655	CHECK_SEL(ss);
656	CHECK_SEL(ds);
657	CHECK_SEL(es);
658	CHECK_SEL(fs);
659	CHECK_SEL(gs);
660	CHECK_FIELD(cr0);
661	CHECK_FIELD(cr2);
662	CHECK_FIELD(cr3);
663	CHECK_FIELD(cr4);
664	CHECK_FIELD(dr[0]);
665	CHECK_FIELD(dr[1]);
666	CHECK_FIELD(dr[2]);
667	CHECK_FIELD(dr[3]);
668	CHECK_FIELD(dr[6]);
669	CHECK_FIELD(dr[7]);
670	CHECK_FIELD(gdtr.cbGdt);
671	CHECK_FIELD(gdtr.pGdt);
672	CHECK_FIELD(idtr.cbIdt);
673	CHECK_FIELD(idtr.pIdt);
674	CHECK_SEL(ldtr);
675	CHECK_SEL(tr);
676	CHECK_FIELD(SysEnter.cs);
677	CHECK_FIELD(SysEnter.eip);
678	CHECK_FIELD(SysEnter.esp);
679	CHECK_FIELD(msrEFER);
680	CHECK_FIELD(msrSTAR);
681	CHECK_FIELD(msrPAT);
682	CHECK_FIELD(msrLSTAR);
683	CHECK_FIELD(msrCSTAR);
684	CHECK_FIELD(msrSFMASK);
685	CHECK_FIELD(msrKERNELGSBASE);
686
687	# undef CHECK_FIELD
688	# undef CHECK_BIT_FIELD
689	}
690	}
691	#endif /* VBOX_COMPARE_IEM_AND_EM */
692
693
694	/**
695	* Interprets the current instruction.
696	*
697	* @returns VBox status code.
698	* @retval VINF_* Scheduling instructions.
699	* @retval VERR_EM_INTERPRETER Something we can't cope with.
700	* @retval VERR_* Fatal errors.
701	*
702	* @param pVCpu The cross context virtual CPU structure.
703	* @param pRegFrame The register frame.
704	* Updates the EIP if an instruction was executed successfully.
705	* @param pvFault The fault address (CR2).
706	*
707	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
708	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
709	* to worry about e.g. invalid modrm combinations (!)
710	*/
711	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
712	{
713	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
714	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
715	#ifdef VBOX_WITH_IEM
716	NOREF(pvFault);
717
718	# ifdef VBOX_COMPARE_IEM_AND_EM
719	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
720	g_IncomingCtx = *pCtx;
721	g_fIncomingFFs = pVCpu->fLocalForcedActions;
722	g_cbEmWrote = g_cbIemWrote = 0;
723
724	# ifdef VBOX_COMPARE_IEM_FIRST
725	/* IEM */
726	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
727	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
728	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
729	rcIem = VERR_EM_INTERPRETER;
730	g_IemCtx = *pCtx;
731	g_fIemFFs = pVCpu->fLocalForcedActions;
732	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
733	*pCtx = g_IncomingCtx;
734	# endif
735
736	/* EM */
737	RTGCPTR pbCode;
738	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
739	if (RT_SUCCESS(rcEm))
740	{
741	uint32_t cbOp;
742	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
743	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
744	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
745	if (RT_SUCCESS(rcEm))
746	{
747	Assert(cbOp == pDis->cbInstr);
748	uint32_t cbIgnored;
749	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
750	if (RT_SUCCESS(rcEm))
751	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
752
753	}
754	rcEm = VERR_EM_INTERPRETER;
755	}
756	else
757	rcEm = VERR_EM_INTERPRETER;
758	# ifdef VBOX_SAME_AS_EM
759	if (rcEm == VERR_EM_INTERPRETER)
760	{
761	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
762	return rcEm;
763	}
764	# endif
765	g_EmCtx = *pCtx;
766	g_fEmFFs = pVCpu->fLocalForcedActions;
767	VBOXSTRICTRC rc = rcEm;
768
769	# ifdef VBOX_COMPARE_IEM_LAST
770	/* IEM */
771	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
772	*pCtx = g_IncomingCtx;
773	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
774	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
775	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
776	rcIem = VERR_EM_INTERPRETER;
777	g_IemCtx = *pCtx;
778	g_fIemFFs = pVCpu->fLocalForcedActions;
779	rc = rcIem;
780	# endif
781
782	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
783	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
784	# endif
785
786	# else
787	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
788	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
789	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
790	rc = VERR_EM_INTERPRETER;
791	# endif
792	if (rc != VINF_SUCCESS)
793	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
794
795	return rc;
796	#else
797	RTGCPTR pbCode;
798	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
799	if (RT_SUCCESS(rc))
800	{
801	uint32_t cbOp;
802	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
803	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
804	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
805	if (RT_SUCCESS(rc))
806	{
807	Assert(cbOp == pDis->cbInstr);
808	uint32_t cbIgnored;
809	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
810	if (RT_SUCCESS(rc))
811	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
812
813	return rc;
814	}
815	}
816	return VERR_EM_INTERPRETER;
817	#endif
818	}
819
820
821	/**
822	* Interprets the current instruction.
823	*
824	* @returns VBox status code.
825	* @retval VINF_* Scheduling instructions.
826	* @retval VERR_EM_INTERPRETER Something we can't cope with.
827	* @retval VERR_* Fatal errors.
828	*
829	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
830	* @param pRegFrame The register frame.
831	* Updates the EIP if an instruction was executed successfully.
832	* @param pvFault The fault address (CR2).
833	* @param pcbWritten Size of the write (if applicable).
834	*
835	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
836	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
837	* to worry about e.g. invalid modrm combinations (!)
838	*/
839	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
840	{
841	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
842	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
843	#ifdef VBOX_WITH_IEM
844	NOREF(pvFault);
845
846	# ifdef VBOX_COMPARE_IEM_AND_EM
847	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
848	g_IncomingCtx = *pCtx;
849	g_fIncomingFFs = pVCpu->fLocalForcedActions;
850	g_cbEmWrote = g_cbIemWrote = 0;
851
852	# ifdef VBOX_COMPARE_IEM_FIRST
853	/* IEM */
854	uint32_t cbIemWritten = 0;
855	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
856	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
857	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
858	rcIem = VERR_EM_INTERPRETER;
859	g_IemCtx = *pCtx;
860	g_fIemFFs = pVCpu->fLocalForcedActions;
861	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
862	*pCtx = g_IncomingCtx;
863	# endif
864
865	/* EM */
866	uint32_t cbEmWritten = 0;
867	RTGCPTR pbCode;
868	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
869	if (RT_SUCCESS(rcEm))
870	{
871	uint32_t cbOp;
872	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
873	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
874	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
875	if (RT_SUCCESS(rcEm))
876	{
877	Assert(cbOp == pDis->cbInstr);
878	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
879	if (RT_SUCCESS(rcEm))
880	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
881
882	}
883	else
884	rcEm = VERR_EM_INTERPRETER;
885	}
886	else
887	rcEm = VERR_EM_INTERPRETER;
888	# ifdef VBOX_SAME_AS_EM
889	if (rcEm == VERR_EM_INTERPRETER)
890	{
891	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
892	return rcEm;
893	}
894	# endif
895	g_EmCtx = *pCtx;
896	g_fEmFFs = pVCpu->fLocalForcedActions;
897	*pcbWritten = cbEmWritten;
898	VBOXSTRICTRC rc = rcEm;
899
900	# ifdef VBOX_COMPARE_IEM_LAST
901	/* IEM */
902	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
903	*pCtx = g_IncomingCtx;
904	uint32_t cbIemWritten = 0;
905	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
906	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
907	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
908	rcIem = VERR_EM_INTERPRETER;
909	g_IemCtx = *pCtx;
910	g_fIemFFs = pVCpu->fLocalForcedActions;
911	*pcbWritten = cbIemWritten;
912	rc = rcIem;
913	# endif
914
915	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
916	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
917	# endif
918
919	# else
920	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
921	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
922	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
923	rc = VERR_EM_INTERPRETER;
924	# endif
925	if (rc != VINF_SUCCESS)
926	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
927
928	return rc;
929	#else
930	RTGCPTR pbCode;
931	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
932	if (RT_SUCCESS(rc))
933	{
934	uint32_t cbOp;
935	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
936	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
937	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
938	if (RT_SUCCESS(rc))
939	{
940	Assert(cbOp == pDis->cbInstr);
941	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
942	if (RT_SUCCESS(rc))
943	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
944
945	return rc;
946	}
947	}
948	return VERR_EM_INTERPRETER;
949	#endif
950	}
951
952
953	/**
954	* Interprets the current instruction using the supplied DISCPUSTATE structure.
955	*
956	* IP/EIP/RIP IS updated!
957	*
958	* @returns VBox strict status code.
959	* @retval VINF_* Scheduling instructions. When these are returned, it
960	* starts to get a bit tricky to know whether code was
961	* executed or not... We'll address this when it becomes a problem.
962	* @retval VERR_EM_INTERPRETER Something we can't cope with.
963	* @retval VERR_* Fatal errors.
964	*
965	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
966	* @param pDis The disassembler cpu state for the instruction to be
967	* interpreted.
968	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
969	* @param pvFault The fault address (CR2).
970	* @param enmCodeType Code type (user/supervisor)
971	*
972	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
973	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
974	* to worry about e.g. invalid modrm combinations (!)
975	*
976	* @todo At this time we do NOT check if the instruction overwrites vital information.
977	* Make sure this can't happen!! (will add some assertions/checks later)
978	*/
979	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
980	RTGCPTR pvFault, EMCODETYPE enmCodeType)
981	{
982	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
983	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
984	#ifdef VBOX_WITH_IEM
985	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
986
987	# ifdef VBOX_COMPARE_IEM_AND_EM
988	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
989	g_IncomingCtx = *pCtx;
990	g_fIncomingFFs = pVCpu->fLocalForcedActions;
991	g_cbEmWrote = g_cbIemWrote = 0;
992
993	# ifdef VBOX_COMPARE_IEM_FIRST
994	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
995	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
996	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
997	rcIem = VERR_EM_INTERPRETER;
998	g_IemCtx = *pCtx;
999	g_fIemFFs = pVCpu->fLocalForcedActions;
1000	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1001	*pCtx = g_IncomingCtx;
1002	# endif
1003
1004	/* EM */
1005	uint32_t cbIgnored;
1006	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1007	if (RT_SUCCESS(rcEm))
1008	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1009	# ifdef VBOX_SAME_AS_EM
1010	if (rcEm == VERR_EM_INTERPRETER)
1011	{
1012	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1013	return rcEm;
1014	}
1015	# endif
1016	g_EmCtx = *pCtx;
1017	g_fEmFFs = pVCpu->fLocalForcedActions;
1018	VBOXSTRICTRC rc = rcEm;
1019
1020	# ifdef VBOX_COMPARE_IEM_LAST
1021	/* IEM */
1022	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1023	*pCtx = g_IncomingCtx;
1024	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1025	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1026	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1027	rcIem = VERR_EM_INTERPRETER;
1028	g_IemCtx = *pCtx;
1029	g_fIemFFs = pVCpu->fLocalForcedActions;
1030	rc = rcIem;
1031	# endif
1032
1033	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1034	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1035	# endif
1036
1037	# else
1038	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1039	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1040	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1041	rc = VERR_EM_INTERPRETER;
1042	# endif
1043
1044	if (rc != VINF_SUCCESS)
1045	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1046
1047	return rc;
1048	#else
1049	uint32_t cbIgnored;
1050	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1051	if (RT_SUCCESS(rc))
1052	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1053	return rc;
1054	#endif
1055	}
1056
1057	#ifdef IN_RC
1058
1059	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1060	{
1061	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1062	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1063	return rc;
1064	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1065	}
1066
1067
1068	/**
1069	* Interpret IRET (currently only to V86 code) - PATM only.
1070	*
1071	* @returns VBox status code.
1072	* @param pVM The cross context VM structure.
1073	* @param pVCpu The cross context virtual CPU structure.
1074	* @param pRegFrame The register frame.
1075	*
1076	*/
1077	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1078	{
1079	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1080	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1081	int rc;
1082
1083	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1084	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1085	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1086	* this function. Fear that it may guru on us, thus not converted to
1087	* IEM. */
1088
1089	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1090	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1091	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1092	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1093	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1094
1095	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1096	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1097	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1098	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1099	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1100	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1101	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1102
1103	pRegFrame->eip = eip & 0xffff;
1104	pRegFrame->cs.Sel = cs;
1105
1106	/* Mask away all reserved bits */
1107	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1108	eflags &= uMask;
1109
1110	CPUMRawSetEFlags(pVCpu, eflags);
1111	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1112
1113	pRegFrame->esp = esp;
1114	pRegFrame->ss.Sel = ss;
1115	pRegFrame->ds.Sel = ds;
1116	pRegFrame->es.Sel = es;
1117	pRegFrame->fs.Sel = fs;
1118	pRegFrame->gs.Sel = gs;
1119
1120	return VINF_SUCCESS;
1121	}
1122
1123	/**
1124	* IRET Emulation.
1125	*/
1126	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1127	{
1128	#ifdef VBOX_WITH_RAW_RING1
1129	NOREF(pvFault); NOREF(pcbSize);
1130	if (EMIsRawRing1Enabled(pVM))
1131	{
1132	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1133	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1134	int rc;
1135	uint32_t cpl, rpl;
1136
1137	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1138	/* @todo: we don't verify all the edge cases that generate #GP faults */
1139
1140	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1141	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1142	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1143	* this function. Fear that it may guru on us, thus not converted to
1144	* IEM. */
1145
1146	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1147	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1148	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1149	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1150	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1151
1152	/* Deal with V86 above. */
1153	if (eflags & X86_EFL_VM)
1154	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1155
1156	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1157	rpl = cs & X86_SEL_RPL;
1158
1159	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1160	if (rpl != cpl)
1161	{
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1163	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1164	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1165	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1166	Log(("emInterpretIret: SS:ESP=%04x:%08x\n", ss, esp));
1167	pRegFrame->ss.Sel = ss;
1168	pRegFrame->esp = esp;
1169	}
1170	pRegFrame->cs.Sel = cs;
1171	pRegFrame->eip = eip;
1172
1173	/* Adjust CS & SS as required. */
1174	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1175
1176	/* Mask away all reserved bits */
1177	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1178	eflags &= uMask;
1179
1180	CPUMRawSetEFlags(pVCpu, eflags);
1181	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1182	return VINF_SUCCESS;
1183	}
1184	#else
1185	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1186	#endif
1187	return VERR_EM_INTERPRETER;
1188	}
1189
1190	#endif /* IN_RC */
1191
1192
1193
1194	/*
1195	*
1196	* Old interpreter primitives used by HM, move/eliminate later.
1197	* Old interpreter primitives used by HM, move/eliminate later.
1198	* Old interpreter primitives used by HM, move/eliminate later.
1199	* Old interpreter primitives used by HM, move/eliminate later.
1200	* Old interpreter primitives used by HM, move/eliminate later.
1201	*
1202	*/
1203
1204
1205	/**
1206	* Interpret CPUID given the parameters in the CPU context.
1207	*
1208	* @returns VBox status code.
1209	* @param pVM The cross context VM structure.
1210	* @param pVCpu The cross context virtual CPU structure.
1211	* @param pRegFrame The register frame.
1212	*
1213	*/
1214	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1215	{
1216	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1217	uint32_t iLeaf = pRegFrame->eax;
1218	uint32_t iSubLeaf = pRegFrame->ecx;
1219	NOREF(pVM);
1220
1221	/* cpuid clears the high dwords of the affected 64 bits registers. */
1222	pRegFrame->rax = 0;
1223	pRegFrame->rbx = 0;
1224	pRegFrame->rcx = 0;
1225	pRegFrame->rdx = 0;
1226
1227	/* Note: operates the same in 64 and non-64 bits mode. */
1228	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1229	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1230	return VINF_SUCCESS;
1231	}
1232
1233
1234	/**
1235	* Interpret RDTSC.
1236	*
1237	* @returns VBox status code.
1238	* @param pVM The cross context VM structure.
1239	* @param pVCpu The cross context virtual CPU structure.
1240	* @param pRegFrame The register frame.
1241	*
1242	*/
1243	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1244	{
1245	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1246	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1247
1248	if (uCR4 & X86_CR4_TSD)
1249	return VERR_EM_INTERPRETER; /* genuine #GP */
1250
1251	uint64_t uTicks = TMCpuTickGet(pVCpu);
1252
1253	/* Same behaviour in 32 & 64 bits mode */
1254	pRegFrame->rax = (uint32_t)uTicks;
1255	pRegFrame->rdx = (uTicks >> 32ULL);
1256	#ifdef VBOX_COMPARE_IEM_AND_EM
1257	g_fIgnoreRaxRdx = true;
1258	#endif
1259
1260	NOREF(pVM);
1261	return VINF_SUCCESS;
1262	}
1263
1264	/**
1265	* Interpret RDTSCP.
1266	*
1267	* @returns VBox status code.
1268	* @param pVM The cross context VM structure.
1269	* @param pVCpu The cross context virtual CPU structure.
1270	* @param pCtx The CPU context.
1271	*
1272	*/
1273	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1274	{
1275	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1276	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1277
1278	if (!CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1279	{
1280	AssertFailed();
1281	return VERR_EM_INTERPRETER; /* genuine #UD */
1282	}
1283
1284	if (uCR4 & X86_CR4_TSD)
1285	return VERR_EM_INTERPRETER; /* genuine #GP */
1286
1287	uint64_t uTicks = TMCpuTickGet(pVCpu);
1288
1289	/* Same behaviour in 32 & 64 bits mode */
1290	pCtx->rax = (uint32_t)uTicks;
1291	pCtx->rdx = (uTicks >> 32ULL);
1292	#ifdef VBOX_COMPARE_IEM_AND_EM
1293	g_fIgnoreRaxRdx = true;
1294	#endif
1295	/* Low dword of the TSC_AUX msr only. */
1296	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1297	pCtx->rcx &= UINT32_C(0xffffffff);
1298
1299	return VINF_SUCCESS;
1300	}
1301
1302	/**
1303	* Interpret RDPMC.
1304	*
1305	* @returns VBox status code.
1306	* @param pVM The cross context VM structure.
1307	* @param pVCpu The cross context virtual CPU structure.
1308	* @param pRegFrame The register frame.
1309	*
1310	*/
1311	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1312	{
1313	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1314	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1315
1316	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1317	if ( !(uCR4 & X86_CR4_PCE)
1318	&& CPUMGetGuestCPL(pVCpu) != 0)
1319	{
1320	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1321	return VERR_EM_INTERPRETER; /* genuine #GP */
1322	}
1323
1324	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1325	pRegFrame->rax = 0;
1326	pRegFrame->rdx = 0;
1327	/** @todo We should trigger a \#GP here if the CPU doesn't support the index in
1328	* ecx but see @bugref{3472}! */
1329
1330	NOREF(pVM);
1331	return VINF_SUCCESS;
1332	}
1333
1334
1335	/**
1336	* MWAIT Emulation.
1337	*/
1338	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1339	{
1340	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1341	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1342	NOREF(pVM);
1343
1344	/* Get the current privilege level. */
1345	cpl = CPUMGetGuestCPL(pVCpu);
1346	if (cpl != 0)
1347	return VERR_EM_INTERPRETER; /* supervisor only */
1348
1349	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1350	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1351	return VERR_EM_INTERPRETER; /* not supported */
1352
1353	/*
1354	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1355	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1356	*/
1357	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1358	if (pRegFrame->ecx > 1)
1359	{
1360	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1361	return VERR_EM_INTERPRETER; /* illegal value. */
1362	}
1363
1364	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1365	{
1366	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1367	return VERR_EM_INTERPRETER; /* illegal value. */
1368	}
1369
1370	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1371	}
1372
1373
1374	/**
1375	* MONITOR Emulation.
1376	*/
1377	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1378	{
1379	uint32_t u32Dummy, u32ExtFeatures, cpl;
1380	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1381	NOREF(pVM);
1382
1383	if (pRegFrame->ecx != 0)
1384	{
1385	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1386	return VERR_EM_INTERPRETER; /* illegal value. */
1387	}
1388
1389	/* Get the current privilege level. */
1390	cpl = CPUMGetGuestCPL(pVCpu);
1391	if (cpl != 0)
1392	return VERR_EM_INTERPRETER; /* supervisor only */
1393
1394	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1395	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1396	return VERR_EM_INTERPRETER; /* not supported */
1397
1398	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1399	return VINF_SUCCESS;
1400	}
1401
1402
1403	/* VT-x only: */
1404
1405	/**
1406	* Interpret INVLPG.
1407	*
1408	* @returns VBox status code.
1409	* @param pVM The cross context VM structure.
1410	* @param pVCpu The cross context virtual CPU structure.
1411	* @param pRegFrame The register frame.
1412	* @param pAddrGC Operand address.
1413	*
1414	*/
1415	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1416	{
1417	/** @todo is addr always a flat linear address or ds based
1418	* (in absence of segment override prefixes)????
1419	*/
1420	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1421	NOREF(pVM); NOREF(pRegFrame);
1422	#ifdef IN_RC
1423	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1424	#endif
1425	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1426	if ( rc == VINF_SUCCESS
1427	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1428	return VINF_SUCCESS;
1429	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1430	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1431	VERR_EM_INTERPRETER);
1432	return rc;
1433	}
1434
1435
1436	/**
1437	* Update CRx.
1438	*
1439	* @returns VBox status code.
1440	* @param pVM The cross context VM structure.
1441	* @param pVCpu The cross context virtual CPU structure.
1442	* @param pRegFrame The register frame.
1443	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
1444	* @param val New CRx value
1445	*
1446	*/
1447	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
1448	{
1449	uint64_t oldval;
1450	uint64_t msrEFER;
1451	uint32_t fValid;
1452	int rc, rc2;
1453	NOREF(pVM);
1454
1455	/** @todo Clean up this mess. */
1456	LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
1457	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1458	switch (DestRegCrx)
1459	{
1460	case DISCREG_CR0:
1461	oldval = CPUMGetGuestCR0(pVCpu);
1462	#ifdef IN_RC
1463	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1464	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
1465	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1466	return VERR_EM_INTERPRETER;
1467	#endif
1468	rc = VINF_SUCCESS;
1469	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1470	CPUMSetGuestCR0(pVCpu, val);
1471	#else
1472	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
1473	#endif
1474	val = CPUMGetGuestCR0(pVCpu);
1475	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1476	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1477	{
1478	/* global flush */
1479	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1480	AssertRCReturn(rc, rc);
1481	}
1482
1483	/* Deal with long mode enabling/disabling. */
1484	msrEFER = CPUMGetGuestEFER(pVCpu);
1485	if (msrEFER & MSR_K6_EFER_LME)
1486	{
1487	if ( !(oldval & X86_CR0_PG)
1488	&& (val & X86_CR0_PG))
1489	{
1490	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1491	if (pRegFrame->cs.Attr.n.u1Long)
1492	{
1493	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
1494	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1495	}
1496
1497	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1498	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
1499	{
1500	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
1501	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1502	}
1503	msrEFER \|= MSR_K6_EFER_LMA;
1504	}
1505	else
1506	if ( (oldval & X86_CR0_PG)
1507	&& !(val & X86_CR0_PG))
1508	{
1509	msrEFER &= ~MSR_K6_EFER_LMA;
1510	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
1511	}
1512	CPUMSetGuestEFER(pVCpu, msrEFER);
1513	}
1514	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1515	return rc2 == VINF_SUCCESS ? rc : rc2;
1516
1517	case DISCREG_CR2:
1518	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
1519	return VINF_SUCCESS;
1520
1521	case DISCREG_CR3:
1522	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1523	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
1524	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
1525	{
1526	/* flush */
1527	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
1528	AssertRC(rc);
1529	}
1530	return rc;
1531
1532	case DISCREG_CR4:
1533	oldval = CPUMGetGuestCR4(pVCpu);
1534	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
1535	val = CPUMGetGuestCR4(pVCpu);
1536
1537	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1538	msrEFER = CPUMGetGuestEFER(pVCpu);
1539	if ( (msrEFER & MSR_K6_EFER_LMA)
1540	&& (oldval & X86_CR4_PAE)
1541	&& !(val & X86_CR4_PAE))
1542	{
1543	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1544	}
1545
1546	/* From IEM iemCImpl_load_CrX. */
1547	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
1548	fValid = X86_CR4_VME \| X86_CR4_PVI
1549	\| X86_CR4_TSD \| X86_CR4_DE
1550	\| X86_CR4_PSE \| X86_CR4_PAE
1551	\| X86_CR4_MCE \| X86_CR4_PGE
1552	\| X86_CR4_PCE \| X86_CR4_OSFXSR
1553	\| X86_CR4_OSXMMEEXCPT;
1554	//if (xxx)
1555	// fValid \|= X86_CR4_VMXE;
1556	//if (xxx)
1557	// fValid \|= X86_CR4_OSXSAVE;
1558	if (val & ~(uint64_t)fValid)
1559	{
1560	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
1561	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
1562	}
1563
1564	rc = VINF_SUCCESS;
1565	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1566	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1567	{
1568	/* global flush */
1569	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
1570	AssertRCReturn(rc, rc);
1571	}
1572
1573	/* Feeling extremely lazy. */
1574	# ifdef IN_RC
1575	if ( (oldval & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1576	!= (val & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1577	{
1578	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
1579	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
1580	}
1581	# endif
1582	# ifdef VBOX_WITH_RAW_MODE
1583	if (((val ^ oldval) & X86_CR4_VME) && !HMIsEnabled(pVM))
1584	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1585	# endif
1586
1587	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
1588	return rc2 == VINF_SUCCESS ? rc : rc2;
1589
1590	case DISCREG_CR8:
1591	return PDMApicSetTPR(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1592
1593	default:
1594	AssertFailed();
1595	case DISCREG_CR1: /* illegal op */
1596	break;
1597	}
1598	return VERR_EM_INTERPRETER;
1599	}
1600
1601
1602	/**
1603	* Interpret CRx write.
1604	*
1605	* @returns VBox status code.
1606	* @param pVM The cross context VM structure.
1607	* @param pVCpu The cross context virtual CPU structure.
1608	* @param pRegFrame The register frame.
1609	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
1610	* @param SrcRegGen General purpose register index (USE_REG_E**))
1611	*
1612	*/
1613	static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1614	{
1615	uint64_t val;
1616	int rc;
1617	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1618
1619	if (CPUMIsGuestIn64BitCode(pVCpu))
1620	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
1621	else
1622	{
1623	uint32_t val32;
1624	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1625	val = val32;
1626	}
1627
1628	if (RT_SUCCESS(rc))
1629	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
1630
1631	return VERR_EM_INTERPRETER;
1632	}
1633
1634
1635	#ifdef LOG_ENABLED
1636	static const char *emMSRtoString(uint32_t uMsr)
1637	{
1638	switch (uMsr)
1639	{
1640	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1641	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1642	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1643	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1644	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1645	case MSR_K6_EFER: return "MSR_K6_EFER";
1646	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1647	case MSR_K6_STAR: return "MSR_K6_STAR";
1648	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1649	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1650	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1651	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1652	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1653	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1654	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1655	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1656	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1657	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1658	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1659	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1660	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1661	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1662	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1663	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1664	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1665	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1666	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1667	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1668	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1669	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1670	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1671	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1672	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1673	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1674	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1675	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1676	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1677	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1678	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1679	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1680	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1681	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1682	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1683	}
1684	return "Unknown MSR";
1685	}
1686	#endif /* LOG_ENABLED */
1687
1688
1689	/**
1690	* Interpret RDMSR
1691	*
1692	* @returns VBox status code.
1693	* @param pVM The cross context VM structure.
1694	* @param pVCpu The cross context virtual CPU structure.
1695	* @param pRegFrame The register frame.
1696	*/
1697	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1698	{
1699	NOREF(pVM);
1700
1701	/* Get the current privilege level. */
1702	if (CPUMGetGuestCPL(pVCpu) != 0)
1703	{
1704	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1705	return VERR_EM_INTERPRETER; /* supervisor only */
1706	}
1707
1708	uint64_t uValue;
1709	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1710	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1711	{
1712	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1713	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1714	return VERR_EM_INTERPRETER;
1715	}
1716	pRegFrame->rax = (uint32_t) uValue;
1717	pRegFrame->rdx = (uint32_t)(uValue >> 32);
1718	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1719	return VINF_SUCCESS;
1720	}
1721
1722
1723	/**
1724	* Interpret WRMSR
1725	*
1726	* @returns VBox status code.
1727	* @param pVM The cross context VM structure.
1728	* @param pVCpu The cross context virtual CPU structure.
1729	* @param pRegFrame The register frame.
1730	*/
1731	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1732	{
1733	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1734
1735	/* Check the current privilege level, this instruction is supervisor only. */
1736	if (CPUMGetGuestCPL(pVCpu) != 0)
1737	{
1738	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1739	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1740	}
1741
1742	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1743	if (rcStrict != VINF_SUCCESS)
1744	{
1745	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1746	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1747	return VERR_EM_INTERPRETER;
1748	}
1749	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1750	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1751	NOREF(pVM);
1752	return VINF_SUCCESS;
1753	}
1754
1755
1756	/**
1757	* Interpret CRx read.
1758	*
1759	* @returns VBox status code.
1760	* @param pVM The cross context VM structure.
1761	* @param pVCpu The cross context virtual CPU structure.
1762	* @param pRegFrame The register frame.
1763	* @param DestRegGen General purpose register index (USE_REG_E**))
1764	* @param SrcRegCrx CRx register index (DISUSE_REG_CR*)
1765	*
1766	*/
1767	static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1768	{
1769	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1770	uint64_t val64;
1771	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
1772	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1773	NOREF(pVM);
1774
1775	if (CPUMIsGuestIn64BitCode(pVCpu))
1776	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1777	else
1778	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1779
1780	if (RT_SUCCESS(rc))
1781	{
1782	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
1783	return VINF_SUCCESS;
1784	}
1785	return VERR_EM_INTERPRETER;
1786	}
1787
1788
1789	/**
1790	* Interpret DRx write.
1791	*
1792	* @returns VBox status code.
1793	* @param pVM The cross context VM structure.
1794	* @param pVCpu The cross context virtual CPU structure.
1795	* @param pRegFrame The register frame.
1796	* @param DestRegDrx DRx register index (USE_REG_DR*)
1797	* @param SrcRegGen General purpose register index (USE_REG_E**))
1798	*
1799	*/
1800	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1801	{
1802	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1803	uint64_t uNewDrX;
1804	int rc;
1805	NOREF(pVM);
1806
1807	if (CPUMIsGuestIn64BitCode(pVCpu))
1808	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1809	else
1810	{
1811	uint32_t val32;
1812	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1813	uNewDrX = val32;
1814	}
1815
1816	if (RT_SUCCESS(rc))
1817	{
1818	if (DestRegDrx == 6)
1819	{
1820	uNewDrX \|= X86_DR6_RA1_MASK;
1821	uNewDrX &= ~X86_DR6_RAZ_MASK;
1822	}
1823	else if (DestRegDrx == 7)
1824	{
1825	uNewDrX \|= X86_DR7_RA1_MASK;
1826	uNewDrX &= ~X86_DR7_RAZ_MASK;
1827	}
1828
1829	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1830	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1831	if (RT_SUCCESS(rc))
1832	return rc;
1833	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1834	}
1835	return VERR_EM_INTERPRETER;
1836	}
1837
1838
1839	/**
1840	* Interpret DRx read.
1841	*
1842	* @returns VBox status code.
1843	* @param pVM The cross context VM structure.
1844	* @param pVCpu The cross context virtual CPU structure.
1845	* @param pRegFrame The register frame.
1846	* @param DestRegGen General purpose register index (USE_REG_E**))
1847	* @param SrcRegDrx DRx register index (USE_REG_DR*)
1848	*/
1849	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1850	{
1851	uint64_t val64;
1852	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1853	NOREF(pVM);
1854
1855	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1856	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1857	if (CPUMIsGuestIn64BitCode(pVCpu))
1858	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1859	else
1860	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1861
1862	if (RT_SUCCESS(rc))
1863	return VINF_SUCCESS;
1864
1865	return VERR_EM_INTERPRETER;
1866	}
1867
1868
1869	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1870
1871
1872
1873
1874
1875
1876	/*
1877	*
1878	* The old interpreter.
1879	* The old interpreter.
1880	* The old interpreter.
1881	* The old interpreter.
1882	* The old interpreter.
1883	*
1884	*/
1885
1886	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1887	{
1888	#ifdef IN_RC
1889	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1890	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1891	return rc;
1892	/*
1893	* The page pool cache may end up here in some cases because it
1894	* flushed one of the shadow mappings used by the trapping
1895	* instruction and it either flushed the TLB or the CPU reused it.
1896	*/
1897	#else
1898	NOREF(pVM);
1899	#endif
1900	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1901	}
1902
1903
1904	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1905	{
1906	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1907	pages or write monitored pages. */
1908	NOREF(pVM);
1909	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1910	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1911	#else
1912	int rc = VINF_SUCCESS;
1913	#endif
1914	#ifdef VBOX_COMPARE_IEM_AND_EM
1915	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1916	g_cbEmWrote = cb;
1917	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1918	#endif
1919	return rc;
1920	}
1921
1922
1923	/** Convert sel:addr to a flat GC address. */
1924	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1925	{
1926	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1927	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1928	}
1929
1930
1931	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1932	/**
1933	* Get the mnemonic for the disassembled instruction.
1934	*
1935	* GC/R0 doesn't include the strings in the DIS tables because
1936	* of limited space.
1937	*/
1938	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1939	{
1940	switch (pDis->pCurInstr->uOpcode)
1941	{
1942	case OP_XCHG: return "Xchg";
1943	case OP_DEC: return "Dec";
1944	case OP_INC: return "Inc";
1945	case OP_POP: return "Pop";
1946	case OP_OR: return "Or";
1947	case OP_AND: return "And";
1948	case OP_MOV: return "Mov";
1949	case OP_INVLPG: return "InvlPg";
1950	case OP_CPUID: return "CpuId";
1951	case OP_MOV_CR: return "MovCRx";
1952	case OP_MOV_DR: return "MovDRx";
1953	case OP_LLDT: return "LLdt";
1954	case OP_LGDT: return "LGdt";
1955	case OP_LIDT: return "LIdt";
1956	case OP_CLTS: return "Clts";
1957	case OP_MONITOR: return "Monitor";
1958	case OP_MWAIT: return "MWait";
1959	case OP_RDMSR: return "Rdmsr";
1960	case OP_WRMSR: return "Wrmsr";
1961	case OP_ADD: return "Add";
1962	case OP_ADC: return "Adc";
1963	case OP_SUB: return "Sub";
1964	case OP_SBB: return "Sbb";
1965	case OP_RDTSC: return "Rdtsc";
1966	case OP_STI: return "Sti";
1967	case OP_CLI: return "Cli";
1968	case OP_XADD: return "XAdd";
1969	case OP_HLT: return "Hlt";
1970	case OP_IRET: return "Iret";
1971	case OP_MOVNTPS: return "MovNTPS";
1972	case OP_STOSWD: return "StosWD";
1973	case OP_WBINVD: return "WbInvd";
1974	case OP_XOR: return "Xor";
1975	case OP_BTR: return "Btr";
1976	case OP_BTS: return "Bts";
1977	case OP_BTC: return "Btc";
1978	case OP_LMSW: return "Lmsw";
1979	case OP_SMSW: return "Smsw";
1980	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1981	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1982
1983	default:
1984	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1985	return "???";
1986	}
1987	}
1988	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1989
1990
1991	/**
1992	* XCHG instruction emulation.
1993	*/
1994	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1995	{
1996	DISQPVPARAMVAL param1, param2;
1997	NOREF(pvFault);
1998
1999	/* Source to make DISQueryParamVal read the register value - ugly hack */
2000	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2001	if(RT_FAILURE(rc))
2002	return VERR_EM_INTERPRETER;
2003
2004	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2005	if(RT_FAILURE(rc))
2006	return VERR_EM_INTERPRETER;
2007
2008	#ifdef IN_RC
2009	if (TRPMHasTrap(pVCpu))
2010	{
2011	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2012	{
2013	#endif
2014	RTGCPTR pParam1 = 0, pParam2 = 0;
2015	uint64_t valpar1, valpar2;
2016
2017	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2018	switch(param1.type)
2019	{
2020	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2021	valpar1 = param1.val.val64;
2022	break;
2023
2024	case DISQPV_TYPE_ADDRESS:
2025	pParam1 = (RTGCPTR)param1.val.val64;
2026	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2027	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2028	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2029	if (RT_FAILURE(rc))
2030	{
2031	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2032	return VERR_EM_INTERPRETER;
2033	}
2034	break;
2035
2036	default:
2037	AssertFailed();
2038	return VERR_EM_INTERPRETER;
2039	}
2040
2041	switch(param2.type)
2042	{
2043	case DISQPV_TYPE_ADDRESS:
2044	pParam2 = (RTGCPTR)param2.val.val64;
2045	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
2046	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
2047	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
2048	if (RT_FAILURE(rc))
2049	{
2050	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2051	}
2052	break;
2053
2054	case DISQPV_TYPE_IMMEDIATE:
2055	valpar2 = param2.val.val64;
2056	break;
2057
2058	default:
2059	AssertFailed();
2060	return VERR_EM_INTERPRETER;
2061	}
2062
2063	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
2064	if (pParam1 == 0)
2065	{
2066	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2067	switch(param1.size)
2068	{
2069	case 1: //special case for AH etc
2070	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
2071	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
2072	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
2073	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
2074	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2075	}
2076	if (RT_FAILURE(rc))
2077	return VERR_EM_INTERPRETER;
2078	}
2079	else
2080	{
2081	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
2082	if (RT_FAILURE(rc))
2083	{
2084	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2085	return VERR_EM_INTERPRETER;
2086	}
2087	}
2088
2089	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
2090	if (pParam2 == 0)
2091	{
2092	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
2093	switch(param2.size)
2094	{
2095	case 1: //special case for AH etc
2096	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
2097	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
2098	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
2099	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
2100	default: AssertFailedReturn(VERR_EM_INTERPRETER);
2101	}
2102	if (RT_FAILURE(rc))
2103	return VERR_EM_INTERPRETER;
2104	}
2105	else
2106	{
2107	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
2108	if (RT_FAILURE(rc))
2109	{
2110	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2111	return VERR_EM_INTERPRETER;
2112	}
2113	}
2114
2115	*pcbSize = param2.size;
2116	return VINF_SUCCESS;
2117	#ifdef IN_RC
2118	}
2119	}
2120	return VERR_EM_INTERPRETER;
2121	#endif
2122	}
2123
2124
2125	/**
2126	* INC and DEC emulation.
2127	*/
2128	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2129	PFNEMULATEPARAM2 pfnEmulate)
2130	{
2131	DISQPVPARAMVAL param1;
2132	NOREF(pvFault);
2133
2134	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2135	if(RT_FAILURE(rc))
2136	return VERR_EM_INTERPRETER;
2137
2138	#ifdef IN_RC
2139	if (TRPMHasTrap(pVCpu))
2140	{
2141	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2142	{
2143	#endif
2144	RTGCPTR pParam1 = 0;
2145	uint64_t valpar1;
2146
2147	if (param1.type == DISQPV_TYPE_ADDRESS)
2148	{
2149	pParam1 = (RTGCPTR)param1.val.val64;
2150	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2151	#ifdef IN_RC
2152	/* Safety check (in theory it could cross a page boundary and fault there though) */
2153	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2154	#endif
2155	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2156	if (RT_FAILURE(rc))
2157	{
2158	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2159	return VERR_EM_INTERPRETER;
2160	}
2161	}
2162	else
2163	{
2164	AssertFailed();
2165	return VERR_EM_INTERPRETER;
2166	}
2167
2168	uint32_t eflags;
2169
2170	eflags = pfnEmulate(&valpar1, param1.size);
2171
2172	/* Write result back */
2173	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2174	if (RT_FAILURE(rc))
2175	{
2176	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2177	return VERR_EM_INTERPRETER;
2178	}
2179
2180	/* Update guest's eflags and finish. */
2181	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2182	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2183
2184	/* All done! */
2185	*pcbSize = param1.size;
2186	return VINF_SUCCESS;
2187	#ifdef IN_RC
2188	}
2189	}
2190	return VERR_EM_INTERPRETER;
2191	#endif
2192	}
2193
2194
2195	/**
2196	* POP Emulation.
2197	*/
2198	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2199	{
2200	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2201	DISQPVPARAMVAL param1;
2202	NOREF(pvFault);
2203
2204	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2205	if(RT_FAILURE(rc))
2206	return VERR_EM_INTERPRETER;
2207
2208	#ifdef IN_RC
2209	if (TRPMHasTrap(pVCpu))
2210	{
2211	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2212	{
2213	#endif
2214	RTGCPTR pParam1 = 0;
2215	uint32_t valpar1;
2216	RTGCPTR pStackVal;
2217
2218	/* Read stack value first */
2219	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2220	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2221
2222	/* Convert address; don't bother checking limits etc, as we only read here */
2223	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2224	if (pStackVal == 0)
2225	return VERR_EM_INTERPRETER;
2226
2227	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2228	if (RT_FAILURE(rc))
2229	{
2230	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2231	return VERR_EM_INTERPRETER;
2232	}
2233
2234	if (param1.type == DISQPV_TYPE_ADDRESS)
2235	{
2236	pParam1 = (RTGCPTR)param1.val.val64;
2237
2238	/* pop [esp+xx] uses esp after the actual pop! */
2239	AssertCompile(DISGREG_ESP == DISGREG_SP);
2240	if ( (pDis->Param1.fUse & DISUSE_BASE)
2241	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2242	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2243	)
2244	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2245
2246	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2247	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2248	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2249	if (RT_FAILURE(rc))
2250	{
2251	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2252	return VERR_EM_INTERPRETER;
2253	}
2254
2255	/* Update ESP as the last step */
2256	pRegFrame->esp += param1.size;
2257	}
2258	else
2259	{
2260	#ifndef DEBUG_bird // annoying assertion.
2261	AssertFailed();
2262	#endif
2263	return VERR_EM_INTERPRETER;
2264	}
2265
2266	/* All done! */
2267	*pcbSize = param1.size;
2268	return VINF_SUCCESS;
2269	#ifdef IN_RC
2270	}
2271	}
2272	return VERR_EM_INTERPRETER;
2273	#endif
2274	}
2275
2276
2277	/**
2278	* XOR/OR/AND Emulation.
2279	*/
2280	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2281	PFNEMULATEPARAM3 pfnEmulate)
2282	{
2283	DISQPVPARAMVAL param1, param2;
2284	NOREF(pvFault);
2285
2286	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2287	if(RT_FAILURE(rc))
2288	return VERR_EM_INTERPRETER;
2289
2290	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2291	if(RT_FAILURE(rc))
2292	return VERR_EM_INTERPRETER;
2293
2294	#ifdef IN_RC
2295	if (TRPMHasTrap(pVCpu))
2296	{
2297	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2298	{
2299	#endif
2300	RTGCPTR pParam1;
2301	uint64_t valpar1, valpar2;
2302
2303	if (pDis->Param1.cb != pDis->Param2.cb)
2304	{
2305	if (pDis->Param1.cb < pDis->Param2.cb)
2306	{
2307	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2308	return VERR_EM_INTERPRETER;
2309	}
2310	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2311	pDis->Param2.cb = pDis->Param1.cb;
2312	param2.size = param1.size;
2313	}
2314
2315	/* The destination is always a virtual address */
2316	if (param1.type == DISQPV_TYPE_ADDRESS)
2317	{
2318	pParam1 = (RTGCPTR)param1.val.val64;
2319	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2320	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2321	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2322	if (RT_FAILURE(rc))
2323	{
2324	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2325	return VERR_EM_INTERPRETER;
2326	}
2327	}
2328	else
2329	{
2330	AssertFailed();
2331	return VERR_EM_INTERPRETER;
2332	}
2333
2334	/* Register or immediate data */
2335	switch(param2.type)
2336	{
2337	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2338	valpar2 = param2.val.val64;
2339	break;
2340
2341	default:
2342	AssertFailed();
2343	return VERR_EM_INTERPRETER;
2344	}
2345
2346	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2347
2348	/* Data read, emulate instruction. */
2349	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2350
2351	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2352
2353	/* Update guest's eflags and finish. */
2354	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2355	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2356
2357	/* And write it back */
2358	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2359	if (RT_SUCCESS(rc))
2360	{
2361	/* All done! */
2362	*pcbSize = param2.size;
2363	return VINF_SUCCESS;
2364	}
2365	#ifdef IN_RC
2366	}
2367	}
2368	#endif
2369	return VERR_EM_INTERPRETER;
2370	}
2371
2372
2373	#ifndef VBOX_COMPARE_IEM_AND_EM
2374	/**
2375	* LOCK XOR/OR/AND Emulation.
2376	*/
2377	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2378	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2379	{
2380	void *pvParam1;
2381	DISQPVPARAMVAL param1, param2;
2382	NOREF(pvFault);
2383
2384	#if HC_ARCH_BITS == 32
2385	Assert(pDis->Param1.cb <= 4);
2386	#endif
2387
2388	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2389	if(RT_FAILURE(rc))
2390	return VERR_EM_INTERPRETER;
2391
2392	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2393	if(RT_FAILURE(rc))
2394	return VERR_EM_INTERPRETER;
2395
2396	if (pDis->Param1.cb != pDis->Param2.cb)
2397	{
2398	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2399	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2400	VERR_EM_INTERPRETER);
2401
2402	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2403	pDis->Param2.cb = pDis->Param1.cb;
2404	param2.size = param1.size;
2405	}
2406
2407	#ifdef IN_RC
2408	/* Safety check (in theory it could cross a page boundary and fault there though) */
2409	Assert( TRPMHasTrap(pVCpu)
2410	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2411	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2412	#endif
2413
2414	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2415	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2416	RTGCUINTREG ValPar2 = param2.val.val64;
2417
2418	/* The destination is always a virtual address */
2419	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2420
2421	RTGCPTR GCPtrPar1 = param1.val.val64;
2422	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2423	PGMPAGEMAPLOCK Lock;
2424	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2425	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2426
2427	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2428	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2429
2430	RTGCUINTREG32 eflags = 0;
2431	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2432	PGMPhysReleasePageMappingLock(pVM, &Lock);
2433	if (RT_FAILURE(rc))
2434	{
2435	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2436	return VERR_EM_INTERPRETER;
2437	}
2438
2439	/* Update guest's eflags and finish. */
2440	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2441	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2442
2443	*pcbSize = param2.size;
2444	return VINF_SUCCESS;
2445	}
2446	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2447
2448
2449	/**
2450	* ADD, ADC & SUB Emulation.
2451	*/
2452	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2453	PFNEMULATEPARAM3 pfnEmulate)
2454	{
2455	NOREF(pvFault);
2456	DISQPVPARAMVAL param1, param2;
2457	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2458	if(RT_FAILURE(rc))
2459	return VERR_EM_INTERPRETER;
2460
2461	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2462	if(RT_FAILURE(rc))
2463	return VERR_EM_INTERPRETER;
2464
2465	#ifdef IN_RC
2466	if (TRPMHasTrap(pVCpu))
2467	{
2468	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2469	{
2470	#endif
2471	RTGCPTR pParam1;
2472	uint64_t valpar1, valpar2;
2473
2474	if (pDis->Param1.cb != pDis->Param2.cb)
2475	{
2476	if (pDis->Param1.cb < pDis->Param2.cb)
2477	{
2478	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2479	return VERR_EM_INTERPRETER;
2480	}
2481	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2482	pDis->Param2.cb = pDis->Param1.cb;
2483	param2.size = param1.size;
2484	}
2485
2486	/* The destination is always a virtual address */
2487	if (param1.type == DISQPV_TYPE_ADDRESS)
2488	{
2489	pParam1 = (RTGCPTR)param1.val.val64;
2490	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2491	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2492	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2493	if (RT_FAILURE(rc))
2494	{
2495	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2496	return VERR_EM_INTERPRETER;
2497	}
2498	}
2499	else
2500	{
2501	#ifndef DEBUG_bird
2502	AssertFailed();
2503	#endif
2504	return VERR_EM_INTERPRETER;
2505	}
2506
2507	/* Register or immediate data */
2508	switch(param2.type)
2509	{
2510	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2511	valpar2 = param2.val.val64;
2512	break;
2513
2514	default:
2515	AssertFailed();
2516	return VERR_EM_INTERPRETER;
2517	}
2518
2519	/* Data read, emulate instruction. */
2520	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2521
2522	/* Update guest's eflags and finish. */
2523	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2524	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2525
2526	/* And write it back */
2527	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2528	if (RT_SUCCESS(rc))
2529	{
2530	/* All done! */
2531	*pcbSize = param2.size;
2532	return VINF_SUCCESS;
2533	}
2534	#ifdef IN_RC
2535	}
2536	}
2537	#endif
2538	return VERR_EM_INTERPRETER;
2539	}
2540
2541
2542	/**
2543	* ADC Emulation.
2544	*/
2545	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2546	{
2547	if (pRegFrame->eflags.Bits.u1CF)
2548	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2549	else
2550	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2551	}
2552
2553
2554	/**
2555	* BTR/C/S Emulation.
2556	*/
2557	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2558	PFNEMULATEPARAM2UINT32 pfnEmulate)
2559	{
2560	DISQPVPARAMVAL param1, param2;
2561	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2562	if(RT_FAILURE(rc))
2563	return VERR_EM_INTERPRETER;
2564
2565	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2566	if(RT_FAILURE(rc))
2567	return VERR_EM_INTERPRETER;
2568
2569	#ifdef IN_RC
2570	if (TRPMHasTrap(pVCpu))
2571	{
2572	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2573	{
2574	#endif
2575	RTGCPTR pParam1;
2576	uint64_t valpar1 = 0, valpar2;
2577	uint32_t eflags;
2578
2579	/* The destination is always a virtual address */
2580	if (param1.type != DISQPV_TYPE_ADDRESS)
2581	return VERR_EM_INTERPRETER;
2582
2583	pParam1 = (RTGCPTR)param1.val.val64;
2584	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2585
2586	/* Register or immediate data */
2587	switch(param2.type)
2588	{
2589	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2590	valpar2 = param2.val.val64;
2591	break;
2592
2593	default:
2594	AssertFailed();
2595	return VERR_EM_INTERPRETER;
2596	}
2597
2598	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2599	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2600	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); NOREF(pvFault);
2601	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2602	if (RT_FAILURE(rc))
2603	{
2604	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2605	return VERR_EM_INTERPRETER;
2606	}
2607
2608	Log2(("emInterpretBtx: val=%x\n", valpar1));
2609	/* Data read, emulate bit test instruction. */
2610	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2611
2612	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2613
2614	/* Update guest's eflags and finish. */
2615	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2616	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2617
2618	/* And write it back */
2619	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2620	if (RT_SUCCESS(rc))
2621	{
2622	/* All done! */
2623	*pcbSize = 1;
2624	return VINF_SUCCESS;
2625	}
2626	#ifdef IN_RC
2627	}
2628	}
2629	#endif
2630	return VERR_EM_INTERPRETER;
2631	}
2632
2633
2634	#ifndef VBOX_COMPARE_IEM_AND_EM
2635	/**
2636	* LOCK BTR/C/S Emulation.
2637	*/
2638	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2639	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2640	{
2641	void *pvParam1;
2642
2643	DISQPVPARAMVAL param1, param2;
2644	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2645	if(RT_FAILURE(rc))
2646	return VERR_EM_INTERPRETER;
2647
2648	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2649	if(RT_FAILURE(rc))
2650	return VERR_EM_INTERPRETER;
2651
2652	/* The destination is always a virtual address */
2653	if (param1.type != DISQPV_TYPE_ADDRESS)
2654	return VERR_EM_INTERPRETER;
2655
2656	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2657	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2658	uint64_t ValPar2 = param2.val.val64;
2659
2660	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2661	RTGCPTR GCPtrPar1 = param1.val.val64;
2662	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2663	ValPar2 &= 7;
2664
2665	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2666	#ifdef IN_RC
2667	Assert(TRPMHasTrap(pVCpu));
2668	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2669	#endif
2670
2671	PGMPAGEMAPLOCK Lock;
2672	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2673	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2674
2675	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2676	NOREF(pvFault);
2677
2678	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2679	RTGCUINTREG32 eflags = 0;
2680	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2681	PGMPhysReleasePageMappingLock(pVM, &Lock);
2682	if (RT_FAILURE(rc))
2683	{
2684	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2685	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2686	return VERR_EM_INTERPRETER;
2687	}
2688
2689	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2690
2691	/* Update guest's eflags and finish. */
2692	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2693	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2694
2695	*pcbSize = 1;
2696	return VINF_SUCCESS;
2697	}
2698	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2699
2700
2701	/**
2702	* MOV emulation.
2703	*/
2704	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2705	{
2706	NOREF(pvFault);
2707	DISQPVPARAMVAL param1, param2;
2708	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2709	if(RT_FAILURE(rc))
2710	return VERR_EM_INTERPRETER;
2711
2712	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2713	if(RT_FAILURE(rc))
2714	return VERR_EM_INTERPRETER;
2715
2716	/* If destination is a segment register, punt. We can't handle it here.
2717	* NB: Source can be a register and still trigger a #PF!
2718	*/
2719	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2720	return VERR_EM_INTERPRETER;
2721
2722	if (param1.type == DISQPV_TYPE_ADDRESS)
2723	{
2724	RTGCPTR pDest;
2725	uint64_t val64;
2726
2727	switch(param1.type)
2728	{
2729	case DISQPV_TYPE_IMMEDIATE:
2730	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2731	return VERR_EM_INTERPRETER;
2732	/* fallthru */
2733
2734	case DISQPV_TYPE_ADDRESS:
2735	pDest = (RTGCPTR)param1.val.val64;
2736	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2737	break;
2738
2739	default:
2740	AssertFailed();
2741	return VERR_EM_INTERPRETER;
2742	}
2743
2744	switch(param2.type)
2745	{
2746	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2747	val64 = param2.val.val64;
2748	break;
2749
2750	default:
2751	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2752	return VERR_EM_INTERPRETER;
2753	}
2754	#ifdef LOG_ENABLED
2755	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2756	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2757	else
2758	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2759	#endif
2760
2761	Assert(param2.size <= 8 && param2.size > 0);
2762	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2763	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2764	if (RT_FAILURE(rc))
2765	return VERR_EM_INTERPRETER;
2766
2767	*pcbSize = param2.size;
2768	}
2769	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2770	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2771	else if ( param1.type == DISQPV_TYPE_REGISTER
2772	&& param2.type == DISQPV_TYPE_REGISTER)
2773	{
2774	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2775	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2776	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2777
2778	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2779	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2780
2781	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2782	switch (param1.size)
2783	{
2784	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2785	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2786	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2787	default:
2788	AssertFailed();
2789	return VERR_EM_INTERPRETER;
2790	}
2791	AssertRCReturn(rc, rc);
2792	}
2793	#endif
2794	else
2795	{ /* read fault */
2796	RTGCPTR pSrc;
2797	uint64_t val64;
2798
2799	/* Source */
2800	switch(param2.type)
2801	{
2802	case DISQPV_TYPE_IMMEDIATE:
2803	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2804	return VERR_EM_INTERPRETER;
2805	/* fallthru */
2806
2807	case DISQPV_TYPE_ADDRESS:
2808	pSrc = (RTGCPTR)param2.val.val64;
2809	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2810	break;
2811
2812	default:
2813	return VERR_EM_INTERPRETER;
2814	}
2815
2816	Assert(param1.size <= 8 && param1.size > 0);
2817	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2818	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2819	if (RT_FAILURE(rc))
2820	return VERR_EM_INTERPRETER;
2821
2822	/* Destination */
2823	switch(param1.type)
2824	{
2825	case DISQPV_TYPE_REGISTER:
2826	switch(param1.size)
2827	{
2828	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2829	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2830	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2831	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2832	default:
2833	return VERR_EM_INTERPRETER;
2834	}
2835	if (RT_FAILURE(rc))
2836	return rc;
2837	break;
2838
2839	default:
2840	return VERR_EM_INTERPRETER;
2841	}
2842	#ifdef LOG_ENABLED
2843	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2844	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2845	else
2846	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2847	#endif
2848	}
2849	return VINF_SUCCESS;
2850	}
2851
2852
2853	#ifndef IN_RC
2854	/**
2855	* [REP] STOSWD emulation
2856	*/
2857	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2858	{
2859	int rc;
2860	RTGCPTR GCDest, GCOffset;
2861	uint32_t cbSize;
2862	uint64_t cTransfers;
2863	int offIncrement;
2864	NOREF(pvFault);
2865
2866	/* Don't support any but these three prefix bytes. */
2867	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2868	return VERR_EM_INTERPRETER;
2869
2870	switch (pDis->uAddrMode)
2871	{
2872	case DISCPUMODE_16BIT:
2873	GCOffset = pRegFrame->di;
2874	cTransfers = pRegFrame->cx;
2875	break;
2876	case DISCPUMODE_32BIT:
2877	GCOffset = pRegFrame->edi;
2878	cTransfers = pRegFrame->ecx;
2879	break;
2880	case DISCPUMODE_64BIT:
2881	GCOffset = pRegFrame->rdi;
2882	cTransfers = pRegFrame->rcx;
2883	break;
2884	default:
2885	AssertFailed();
2886	return VERR_EM_INTERPRETER;
2887	}
2888
2889	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2890	switch (pDis->uOpMode)
2891	{
2892	case DISCPUMODE_16BIT:
2893	cbSize = 2;
2894	break;
2895	case DISCPUMODE_32BIT:
2896	cbSize = 4;
2897	break;
2898	case DISCPUMODE_64BIT:
2899	cbSize = 8;
2900	break;
2901	default:
2902	AssertFailed();
2903	return VERR_EM_INTERPRETER;
2904	}
2905
2906	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2907
2908	if (!(pDis->fPrefix & DISPREFIX_REP))
2909	{
2910	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2911
2912	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2913	if (RT_FAILURE(rc))
2914	return VERR_EM_INTERPRETER;
2915	Assert(rc == VINF_SUCCESS);
2916
2917	/* Update (e/r)di. */
2918	switch (pDis->uAddrMode)
2919	{
2920	case DISCPUMODE_16BIT:
2921	pRegFrame->di += offIncrement;
2922	break;
2923	case DISCPUMODE_32BIT:
2924	pRegFrame->edi += offIncrement;
2925	break;
2926	case DISCPUMODE_64BIT:
2927	pRegFrame->rdi += offIncrement;
2928	break;
2929	default:
2930	AssertFailed();
2931	return VERR_EM_INTERPRETER;
2932	}
2933
2934	}
2935	else
2936	{
2937	if (!cTransfers)
2938	return VINF_SUCCESS;
2939
2940	/*
2941	* Do not try emulate cross page stuff here because we don't know what might
2942	* be waiting for us on the subsequent pages. The caller has only asked us to
2943	* ignore access handlers fro the current page.
2944	* This also fends off big stores which would quickly kill PGMR0DynMap.
2945	*/
2946	if ( cbSize > PAGE_SIZE
2947	\|\| cTransfers > PAGE_SIZE
2948	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2949	{
2950	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2951	GCDest, cbSize, offIncrement, cTransfers));
2952	return VERR_EM_INTERPRETER;
2953	}
2954
2955	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2956	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2957	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2958	cTransfers * cbSize,
2959	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2960	if (rc != VINF_SUCCESS)
2961	{
2962	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2963	return VERR_EM_INTERPRETER;
2964	}
2965
2966	/* REP case */
2967	while (cTransfers)
2968	{
2969	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2970	if (RT_FAILURE(rc))
2971	{
2972	rc = VERR_EM_INTERPRETER;
2973	break;
2974	}
2975
2976	Assert(rc == VINF_SUCCESS);
2977	GCOffset += offIncrement;
2978	GCDest += offIncrement;
2979	cTransfers--;
2980	}
2981
2982	/* Update the registers. */
2983	switch (pDis->uAddrMode)
2984	{
2985	case DISCPUMODE_16BIT:
2986	pRegFrame->di = GCOffset;
2987	pRegFrame->cx = cTransfers;
2988	break;
2989	case DISCPUMODE_32BIT:
2990	pRegFrame->edi = GCOffset;
2991	pRegFrame->ecx = cTransfers;
2992	break;
2993	case DISCPUMODE_64BIT:
2994	pRegFrame->rdi = GCOffset;
2995	pRegFrame->rcx = cTransfers;
2996	break;
2997	default:
2998	AssertFailed();
2999	return VERR_EM_INTERPRETER;
3000	}
3001	}
3002
3003	*pcbSize = cbSize;
3004	return rc;
3005	}
3006	#endif /* !IN_RC */
3007
3008
3009	/**
3010	* [LOCK] CMPXCHG emulation.
3011	*/
3012	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3013	{
3014	DISQPVPARAMVAL param1, param2;
3015	NOREF(pvFault);
3016
3017	#if HC_ARCH_BITS == 32
3018	Assert(pDis->Param1.cb <= 4);
3019	#endif
3020
3021	/* Source to make DISQueryParamVal read the register value - ugly hack */
3022	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3023	if(RT_FAILURE(rc))
3024	return VERR_EM_INTERPRETER;
3025
3026	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
3027	if(RT_FAILURE(rc))
3028	return VERR_EM_INTERPRETER;
3029
3030	uint64_t valpar;
3031	switch(param2.type)
3032	{
3033	case DISQPV_TYPE_IMMEDIATE: /* register actually */
3034	valpar = param2.val.val64;
3035	break;
3036
3037	default:
3038	return VERR_EM_INTERPRETER;
3039	}
3040
3041	PGMPAGEMAPLOCK Lock;
3042	RTGCPTR GCPtrPar1;
3043	void *pvParam1;
3044	uint64_t eflags;
3045
3046	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3047	switch(param1.type)
3048	{
3049	case DISQPV_TYPE_ADDRESS:
3050	GCPtrPar1 = param1.val.val64;
3051	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3052
3053	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3054	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3055	break;
3056
3057	default:
3058	return VERR_EM_INTERPRETER;
3059	}
3060
3061	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
3062
3063	#ifndef VBOX_COMPARE_IEM_AND_EM
3064	if (pDis->fPrefix & DISPREFIX_LOCK)
3065	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3066	else
3067	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
3068	#else /* VBOX_COMPARE_IEM_AND_EM */
3069	uint64_t u64;
3070	switch (pDis->Param2.cb)
3071	{
3072	case 1: u64 = (uint8_t )pvParam1; break;
3073	case 2: u64 = (uint16_t )pvParam1; break;
3074	case 4: u64 = (uint32_t )pvParam1; break;
3075	default:
3076	case 8: u64 = (uint64_t )pvParam1; break;
3077	}
3078	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
3079	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3080	#endif /* VBOX_COMPARE_IEM_AND_EM */
3081
3082	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
3083
3084	/* Update guest's eflags and finish. */
3085	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3086	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3087
3088	*pcbSize = param2.size;
3089	PGMPhysReleasePageMappingLock(pVM, &Lock);
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/**
3095	* [LOCK] CMPXCHG8B emulation.
3096	*/
3097	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3098	{
3099	DISQPVPARAMVAL param1;
3100	NOREF(pvFault);
3101
3102	/* Source to make DISQueryParamVal read the register value - ugly hack */
3103	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3104	if(RT_FAILURE(rc))
3105	return VERR_EM_INTERPRETER;
3106
3107	RTGCPTR GCPtrPar1;
3108	void *pvParam1;
3109	uint64_t eflags;
3110	PGMPAGEMAPLOCK Lock;
3111
3112	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
3113	switch(param1.type)
3114	{
3115	case DISQPV_TYPE_ADDRESS:
3116	GCPtrPar1 = param1.val.val64;
3117	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
3118
3119	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3120	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3121	break;
3122
3123	default:
3124	return VERR_EM_INTERPRETER;
3125	}
3126
3127	LogFlow(("%s %RGv=%p eax=%08x\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax));
3128
3129	#ifndef VBOX_COMPARE_IEM_AND_EM
3130	if (pDis->fPrefix & DISPREFIX_LOCK)
3131	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3132	else
3133	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3134	#else /* VBOX_COMPARE_IEM_AND_EM */
3135	uint64_t u64 = (uint64_t )pvParam1;
3136	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
3137	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
3138	#endif /* VBOX_COMPARE_IEM_AND_EM */
3139
3140	LogFlow(("%s %RGv=%p eax=%08x ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
3141
3142	/* Update guest's eflags and finish; note that only ZF is affected. */
3143	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
3144	\| (eflags & (X86_EFL_ZF));
3145
3146	*pcbSize = 8;
3147	PGMPhysReleasePageMappingLock(pVM, &Lock);
3148	return VINF_SUCCESS;
3149	}
3150
3151
3152	#ifdef IN_RC /** @todo test+enable for HM as well. */
3153	/**
3154	* [LOCK] XADD emulation.
3155	*/
3156	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3157	{
3158	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
3159	DISQPVPARAMVAL param1;
3160	void *pvParamReg2;
3161	size_t cbParamReg2;
3162	NOREF(pvFault);
3163
3164	/* Source to make DISQueryParamVal read the register value - ugly hack */
3165	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3166	if(RT_FAILURE(rc))
3167	return VERR_EM_INTERPRETER;
3168
3169	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3170	Assert(cbParamReg2 <= 4);
3171	if(RT_FAILURE(rc))
3172	return VERR_EM_INTERPRETER;
3173
3174	#ifdef IN_RC
3175	if (TRPMHasTrap(pVCpu))
3176	{
3177	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3178	{
3179	#endif
3180	RTGCPTR GCPtrPar1;
3181	void *pvParam1;
3182	uint32_t eflags;
3183	PGMPAGEMAPLOCK Lock;
3184
3185	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3186	switch(param1.type)
3187	{
3188	case DISQPV_TYPE_ADDRESS:
3189	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3190	#ifdef IN_RC
3191	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3192	#endif
3193
3194	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3195	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3196	break;
3197
3198	default:
3199	return VERR_EM_INTERPRETER;
3200	}
3201
3202	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3203
3204	#ifndef VBOX_COMPARE_IEM_AND_EM
3205	if (pDis->fPrefix & DISPREFIX_LOCK)
3206	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3207	else
3208	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3209	#else /* VBOX_COMPARE_IEM_AND_EM */
3210	uint64_t u64;
3211	switch (cbParamReg2)
3212	{
3213	case 1: u64 = (uint8_t )pvParam1; break;
3214	case 2: u64 = (uint16_t )pvParam1; break;
3215	case 4: u64 = (uint32_t )pvParam1; break;
3216	default:
3217	case 8: u64 = (uint64_t )pvParam1; break;
3218	}
3219	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3220	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3221	#endif /* VBOX_COMPARE_IEM_AND_EM */
3222
3223	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3224
3225	/* Update guest's eflags and finish. */
3226	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3227	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3228
3229	*pcbSize = cbParamReg2;
3230	PGMPhysReleasePageMappingLock(pVM, &Lock);
3231	return VINF_SUCCESS;
3232	#ifdef IN_RC
3233	}
3234	}
3235
3236	return VERR_EM_INTERPRETER;
3237	#endif
3238	}
3239	#endif /* IN_RC */
3240
3241
3242	/**
3243	* WBINVD Emulation.
3244	*/
3245	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3246	{
3247	/* Nothing to do. */
3248	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3249	return VINF_SUCCESS;
3250	}
3251
3252
3253	/**
3254	* INVLPG Emulation.
3255	*/
3256	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3257	{
3258	DISQPVPARAMVAL param1;
3259	RTGCPTR addr;
3260	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3261
3262	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3263	if(RT_FAILURE(rc))
3264	return VERR_EM_INTERPRETER;
3265
3266	switch(param1.type)
3267	{
3268	case DISQPV_TYPE_IMMEDIATE:
3269	case DISQPV_TYPE_ADDRESS:
3270	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3271	return VERR_EM_INTERPRETER;
3272	addr = (RTGCPTR)param1.val.val64;
3273	break;
3274
3275	default:
3276	return VERR_EM_INTERPRETER;
3277	}
3278
3279	/** @todo is addr always a flat linear address or ds based
3280	* (in absence of segment override prefixes)????
3281	*/
3282	#ifdef IN_RC
3283	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3284	#endif
3285	rc = PGMInvalidatePage(pVCpu, addr);
3286	if ( rc == VINF_SUCCESS
3287	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3288	return VINF_SUCCESS;
3289	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3290	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3291	VERR_EM_INTERPRETER);
3292	return rc;
3293	}
3294
3295	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3296
3297	/**
3298	* CPUID Emulation.
3299	*/
3300	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3301	{
3302	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3303	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3304	return rc;
3305	}
3306
3307
3308	/**
3309	* CLTS Emulation.
3310	*/
3311	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3312	{
3313	NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3314
3315	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3316	if (!(cr0 & X86_CR0_TS))
3317	return VINF_SUCCESS;
3318	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
3319	}
3320
3321
3322	/**
3323	* LMSW Emulation.
3324	*/
3325	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3326	{
3327	DISQPVPARAMVAL param1;
3328	uint32_t val;
3329	NOREF(pvFault); NOREF(pcbSize);
3330	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3331
3332	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3333	if(RT_FAILURE(rc))
3334	return VERR_EM_INTERPRETER;
3335
3336	switch(param1.type)
3337	{
3338	case DISQPV_TYPE_IMMEDIATE:
3339	case DISQPV_TYPE_ADDRESS:
3340	if(!(param1.flags & DISQPV_FLAG_16))
3341	return VERR_EM_INTERPRETER;
3342	val = param1.val.val32;
3343	break;
3344
3345	default:
3346	return VERR_EM_INTERPRETER;
3347	}
3348
3349	LogFlow(("emInterpretLmsw %x\n", val));
3350	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
3351
3352	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
3353	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
3354	\| (val & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
3355
3356	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
3357
3358	}
3359
3360	#ifdef EM_EMULATE_SMSW
3361	/**
3362	* SMSW Emulation.
3363	*/
3364	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3365	{
3366	NOREF(pvFault); NOREF(pcbSize);
3367	DISQPVPARAMVAL param1;
3368	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3369
3370	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3371	if(RT_FAILURE(rc))
3372	return VERR_EM_INTERPRETER;
3373
3374	switch(param1.type)
3375	{
3376	case DISQPV_TYPE_IMMEDIATE:
3377	if(param1.size != sizeof(uint16_t))
3378	return VERR_EM_INTERPRETER;
3379	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3380	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3381	break;
3382
3383	case DISQPV_TYPE_ADDRESS:
3384	{
3385	RTGCPTR pParam1;
3386
3387	/* Actually forced to 16 bits regardless of the operand size. */
3388	if(param1.size != sizeof(uint16_t))
3389	return VERR_EM_INTERPRETER;
3390
3391	pParam1 = (RTGCPTR)param1.val.val64;
3392	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3393	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3394
3395	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3396	if (RT_FAILURE(rc))
3397	{
3398	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3399	return VERR_EM_INTERPRETER;
3400	}
3401	break;
3402	}
3403
3404	default:
3405	return VERR_EM_INTERPRETER;
3406	}
3407
3408	LogFlow(("emInterpretSmsw %x\n", cr0));
3409	return rc;
3410	}
3411	#endif
3412
3413	/**
3414	* MOV CRx
3415	*/
3416	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3417	{
3418	NOREF(pvFault); NOREF(pcbSize);
3419	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3420	return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3421
3422	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3423	return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3424
3425	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3426	}
3427
3428
3429	/**
3430	* MOV DRx
3431	*/
3432	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3433	{
3434	int rc = VERR_EM_INTERPRETER;
3435	NOREF(pvFault); NOREF(pcbSize);
3436
3437	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3438	{
3439	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3440	}
3441	else
3442	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3443	{
3444	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3445	}
3446	else
3447	AssertMsgFailed(("Unexpected debug register move\n"));
3448
3449	return rc;
3450	}
3451
3452
3453	/**
3454	* LLDT Emulation.
3455	*/
3456	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3457	{
3458	DISQPVPARAMVAL param1;
3459	RTSEL sel;
3460	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3461
3462	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3463	if(RT_FAILURE(rc))
3464	return VERR_EM_INTERPRETER;
3465
3466	switch(param1.type)
3467	{
3468	case DISQPV_TYPE_ADDRESS:
3469	return VERR_EM_INTERPRETER; //feeling lazy right now
3470
3471	case DISQPV_TYPE_IMMEDIATE:
3472	if(!(param1.flags & DISQPV_FLAG_16))
3473	return VERR_EM_INTERPRETER;
3474	sel = (RTSEL)param1.val.val16;
3475	break;
3476
3477	default:
3478	return VERR_EM_INTERPRETER;
3479	}
3480
3481	#ifdef IN_RING0
3482	/* Only for the VT-x real-mode emulation case. */
3483	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3484	CPUMSetGuestLDTR(pVCpu, sel);
3485	return VINF_SUCCESS;
3486	#else
3487	if (sel == 0)
3488	{
3489	if (CPUMGetHyperLDTR(pVCpu) == 0)
3490	{
3491	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3492	return VINF_SUCCESS;
3493	}
3494	}
3495	//still feeling lazy
3496	return VERR_EM_INTERPRETER;
3497	#endif
3498	}
3499
3500	#ifdef IN_RING0
3501	/**
3502	* LIDT/LGDT Emulation.
3503	*/
3504	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3505	{
3506	DISQPVPARAMVAL param1;
3507	RTGCPTR pParam1;
3508	X86XDTR32 dtr32;
3509	NOREF(pvFault); NOREF(pcbSize);
3510
3511	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3512
3513	/* Only for the VT-x real-mode emulation case. */
3514	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3515
3516	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3517	if(RT_FAILURE(rc))
3518	return VERR_EM_INTERPRETER;
3519
3520	switch(param1.type)
3521	{
3522	case DISQPV_TYPE_ADDRESS:
3523	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3524	break;
3525
3526	default:
3527	return VERR_EM_INTERPRETER;
3528	}
3529
3530	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3531	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3532
3533	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3534	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3535
3536	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3537	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3538	else
3539	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3540
3541	return VINF_SUCCESS;
3542	}
3543	#endif
3544
3545
3546	#ifdef IN_RC
3547	/**
3548	* STI Emulation.
3549	*
3550	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3551	*/
3552	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3553	{
3554	NOREF(pcbSize);
3555	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3556
3557	if(!pGCState)
3558	{
3559	Assert(pGCState);
3560	return VERR_EM_INTERPRETER;
3561	}
3562	pGCState->uVMFlags \|= X86_EFL_IF;
3563
3564	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3565	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3566
3567	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3568	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3569
3570	return VINF_SUCCESS;
3571	}
3572	#endif /* IN_RC */
3573
3574
3575	/**
3576	* HLT Emulation.
3577	*/
3578	static VBOXSTRICTRC
3579	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3580	{
3581	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3582	return VINF_EM_HALT;
3583	}
3584
3585
3586	/**
3587	* RDTSC Emulation.
3588	*/
3589	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3590	{
3591	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3592	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3593	}
3594
3595	/**
3596	* RDPMC Emulation
3597	*/
3598	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3599	{
3600	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3601	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3602	}
3603
3604
3605	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3606	{
3607	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3608	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3609	}
3610
3611
3612	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3613	{
3614	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3615	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3616	}
3617
3618
3619	/**
3620	* RDMSR Emulation.
3621	*/
3622	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3623	{
3624	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3625	different, so we play safe by completely disassembling the instruction. */
3626	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3627	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3628	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3629	}
3630
3631
3632	/**
3633	* WRMSR Emulation.
3634	*/
3635	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3636	{
3637	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3638	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3639	}
3640
3641
3642	/**
3643	* Internal worker.
3644	* @copydoc emInterpretInstructionCPUOuter
3645	* @param pVM The cross context VM structure.
3646	*/
3647	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3648	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3649	{
3650	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3651	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3652	Assert(pcbSize);
3653	*pcbSize = 0;
3654
3655	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3656	{
3657	/*
3658	* Only supervisor guest code!!
3659	* And no complicated prefixes.
3660	*/
3661	/* Get the current privilege level. */
3662	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3663	#ifdef VBOX_WITH_RAW_RING1
3664	if ( !EMIsRawRing1Enabled(pVM)
3665	\|\| cpl > 1
3666	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3667	)
3668	#endif
3669	{
3670	if ( cpl != 0
3671	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3672	{
3673	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3674	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3675	return VERR_EM_INTERPRETER;
3676	}
3677	}
3678	}
3679	else
3680	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3681
3682	#ifdef IN_RC
3683	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3684	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3685	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3686	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3687	&& pDis->pCurInstr->uOpcode != OP_XADD
3688	&& pDis->pCurInstr->uOpcode != OP_OR
3689	&& pDis->pCurInstr->uOpcode != OP_AND
3690	&& pDis->pCurInstr->uOpcode != OP_XOR
3691	&& pDis->pCurInstr->uOpcode != OP_BTR
3692	)
3693	)
3694	#else
3695	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3696	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3697	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3698	)
3699	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3700	&& pDis->pCurInstr->uOpcode != OP_OR
3701	&& pDis->pCurInstr->uOpcode != OP_AND
3702	&& pDis->pCurInstr->uOpcode != OP_XOR
3703	&& pDis->pCurInstr->uOpcode != OP_BTR
3704	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3705	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3706	)
3707	)
3708	#endif
3709	{
3710	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3711	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3712	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3713	return VERR_EM_INTERPRETER;
3714	}
3715
3716	#if HC_ARCH_BITS == 32
3717	/*
3718	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3719	* Whitelisted instructions are safe.
3720	*/
3721	if ( pDis->Param1.cb > 4
3722	&& CPUMIsGuestIn64BitCode(pVCpu))
3723	{
3724	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3725	if ( uOpCode != OP_STOSWD
3726	&& uOpCode != OP_MOV
3727	&& uOpCode != OP_CMPXCHG8B
3728	&& uOpCode != OP_XCHG
3729	&& uOpCode != OP_BTS
3730	&& uOpCode != OP_BTR
3731	&& uOpCode != OP_BTC
3732	)
3733	{
3734	# ifdef VBOX_WITH_STATISTICS
3735	switch (pDis->pCurInstr->uOpcode)
3736	{
3737	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3738	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3739	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3740	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3741	INTERPRET_FAILED_CASE(OP_INC,Inc);
3742	INTERPRET_FAILED_CASE(OP_POP,Pop);
3743	INTERPRET_FAILED_CASE(OP_OR, Or);
3744	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3745	INTERPRET_FAILED_CASE(OP_AND,And);
3746	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3747	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3748	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3749	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3750	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3751	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3752	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3753	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3754	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3755	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3756	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3757	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3758	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3759	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3760	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3761	INTERPRET_FAILED_CASE(OP_ADD,Add);
3762	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3763	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3764	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3765	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3766	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3767	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3768	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3769	INTERPRET_FAILED_CASE(OP_STI, Sti);
3770	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3771	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3772	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3773	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3774	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3775	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3776	# undef INTERPRET_FAILED_CASE
3777	default:
3778	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3779	break;
3780	}
3781	# endif /* VBOX_WITH_STATISTICS */
3782	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3783	return VERR_EM_INTERPRETER;
3784	}
3785	}
3786	#endif
3787
3788	VBOXSTRICTRC rc;
3789	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3790	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3791	#endif
3792	switch (pDis->pCurInstr->uOpcode)
3793	{
3794	/*
3795	* Macros for generating the right case statements.
3796	*/
3797	# ifndef VBOX_COMPARE_IEM_AND_EM
3798	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3799	case opcode:\
3800	if (pDis->fPrefix & DISPREFIX_LOCK) \
3801	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3802	else \
3803	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3804	if (RT_SUCCESS(rc)) \
3805	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3806	else \
3807	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3808	return rc
3809	# else /* VBOX_COMPARE_IEM_AND_EM */
3810	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3811	case opcode:\
3812	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3813	if (RT_SUCCESS(rc)) \
3814	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3815	else \
3816	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3817	return rc
3818	# endif /* VBOX_COMPARE_IEM_AND_EM */
3819
3820	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3821	case opcode:\
3822	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3823	if (RT_SUCCESS(rc)) \
3824	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3825	else \
3826	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3827	return rc
3828
3829	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3830	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3831	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3832	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3833
3834	#define INTERPRET_CASE(opcode, Instr) \
3835	case opcode:\
3836	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3837	if (RT_SUCCESS(rc)) \
3838	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3839	else \
3840	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3841	return rc
3842
3843	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3844	case opcode:\
3845	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3846	if (RT_SUCCESS(rc)) \
3847	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3848	else \
3849	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3850	return rc
3851
3852	#define INTERPRET_STAT_CASE(opcode, Instr) \
3853	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3854
3855	/*
3856	* The actual case statements.
3857	*/
3858	INTERPRET_CASE(OP_XCHG,Xchg);
3859	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3860	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3861	INTERPRET_CASE(OP_POP,Pop);
3862	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3863	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3864	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3865	INTERPRET_CASE(OP_MOV,Mov);
3866	#ifndef IN_RC
3867	INTERPRET_CASE(OP_STOSWD,StosWD);
3868	#endif
3869	INTERPRET_CASE(OP_INVLPG,InvlPg);
3870	INTERPRET_CASE(OP_CPUID,CpuId);
3871	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3872	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3873	#ifdef IN_RING0
3874	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3875	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3876	#endif
3877	INTERPRET_CASE(OP_LLDT,LLdt);
3878	INTERPRET_CASE(OP_LMSW,Lmsw);
3879	#ifdef EM_EMULATE_SMSW
3880	INTERPRET_CASE(OP_SMSW,Smsw);
3881	#endif
3882	INTERPRET_CASE(OP_CLTS,Clts);
3883	INTERPRET_CASE(OP_MONITOR, Monitor);
3884	INTERPRET_CASE(OP_MWAIT, MWait);
3885	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3886	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3887	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3888	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3889	INTERPRET_CASE(OP_ADC,Adc);
3890	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3891	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3892	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3893	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3894	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3895	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3896	#ifdef IN_RC
3897	INTERPRET_CASE(OP_STI,Sti);
3898	INTERPRET_CASE(OP_XADD, XAdd);
3899	INTERPRET_CASE(OP_IRET,Iret);
3900	#endif
3901	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3902	INTERPRET_CASE(OP_HLT,Hlt);
3903	INTERPRET_CASE(OP_WBINVD,WbInvd);
3904	#ifdef VBOX_WITH_STATISTICS
3905	# ifndef IN_RC
3906	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3907	# endif
3908	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3909	#endif
3910
3911	default:
3912	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3913	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3914	return VERR_EM_INTERPRETER;
3915
3916	#undef INTERPRET_CASE_EX_PARAM2
3917	#undef INTERPRET_STAT_CASE
3918	#undef INTERPRET_CASE_EX
3919	#undef INTERPRET_CASE
3920	} /* switch (opcode) */
3921	/* not reached */
3922	}
3923
3924	/**
3925	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3926	*
3927	* EIP is NOT updated!
3928	*
3929	* @returns VBox strict status code.
3930	* @retval VINF_* Scheduling instructions. When these are returned, it
3931	* starts to get a bit tricky to know whether code was
3932	* executed or not... We'll address this when it becomes a problem.
3933	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3934	* @retval VERR_* Fatal errors.
3935	*
3936	* @param pVCpu The cross context virtual CPU structure.
3937	* @param pDis The disassembler cpu state for the instruction to be
3938	* interpreted.
3939	* @param pRegFrame The register frame. EIP is NOT changed!
3940	* @param pvFault The fault address (CR2).
3941	* @param pcbSize Size of the write (if applicable).
3942	* @param enmCodeType Code type (user/supervisor)
3943	*
3944	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
3945	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
3946	* to worry about e.g. invalid modrm combinations (!)
3947	*
3948	* @todo At this time we do NOT check if the instruction overwrites vital information.
3949	* Make sure this can't happen!! (will add some assertions/checks later)
3950	*/
3951	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3952	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3953	{
3954	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3955	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
3956	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
3957	if (RT_SUCCESS(rc))
3958	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3959	else
3960	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
3961	return rc;
3962	}
3963
3964
3965	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 60852

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