EMAll.cpp@ 71417

Last change on this file since 71417 was 71341, checked in by vboxsync, 7 years ago
VMM/EM: Todo comment and removed superfluous double negation in EMShouldContinueAfterHalt.
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1	/* $Id: EMAll.cpp 71341 2018-03-15 06:13:31Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_WITH_IEM
23	#define LOG_GROUP LOG_GROUP_EM
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/selm.h>
27	#include <VBox/vmm/patm.h>
28	#include <VBox/vmm/csam.h>
29	#include <VBox/vmm/pgm.h>
30	#ifdef VBOX_WITH_IEM
31	# include <VBox/vmm/iem.h>
32	#endif
33	#include <VBox/vmm/iom.h>
34	#include <VBox/vmm/stam.h>
35	#include "EMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/vmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/tm.h>
40	#include <VBox/vmm/pdmapi.h>
41	#include <VBox/param.h>
42	#include <VBox/err.h>
43	#include <VBox/dis.h>
44	#include <VBox/disopcode.h>
45	#include <VBox/log.h>
46	#include <iprt/assert.h>
47	#include <iprt/asm.h>
48	#include <iprt/string.h>
49
50	#ifdef VBOX_WITH_IEM
51	//# define VBOX_COMPARE_IEM_AND_EM /* debugging... */
52	//# define VBOX_SAME_AS_EM
53	//# define VBOX_COMPARE_IEM_LAST
54	#endif
55
56	#ifdef VBOX_WITH_RAW_RING1
57	# define EM_EMULATE_SMSW
58	#endif
59
60
61	/*********************************************************************************************************************************
62	* Defined Constants And Macros *
63	*********************************************************************************************************************************/
64	/** @def EM_ASSERT_FAULT_RETURN
65	* Safety check.
66	*
67	* Could in theory misfire on a cross page boundary access...
68	*
69	* Currently disabled because the CSAM (+ PATM) patch monitoring occasionally
70	* turns up an alias page instead of the original faulting one and annoying the
71	* heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
72	*/
73	#if 0
74	# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
75	#else
76	# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
77	#endif
78
79
80	/*********************************************************************************************************************************
81	* Internal Functions *
82	*********************************************************************************************************************************/
83	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
84	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
85	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize);
86	#endif
87
88
89	/*********************************************************************************************************************************
90	* Global Variables *
91	*********************************************************************************************************************************/
92	#ifdef VBOX_COMPARE_IEM_AND_EM
93	static const uint32_t g_fInterestingFFs = VMCPU_FF_TO_R3
94	\| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE \| VMCPU_FF_INHIBIT_INTERRUPTS
95	\| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT
96	\| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL;
97	static uint32_t g_fIncomingFFs;
98	static CPUMCTX g_IncomingCtx;
99	static bool g_fIgnoreRaxRdx = false;
100
101	static uint32_t g_fEmFFs;
102	static CPUMCTX g_EmCtx;
103	static uint8_t g_abEmWrote[256];
104	static size_t g_cbEmWrote;
105
106	static uint32_t g_fIemFFs;
107	static CPUMCTX g_IemCtx;
108	extern uint8_t g_abIemWrote[256];
109	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
110	extern size_t g_cbIemWrote;
111	#else
112	static size_t g_cbIemWrote;
113	#endif
114	#endif
115
116
117	/**
118	* Get the current execution manager status.
119	*
120	* @returns Current status.
121	* @param pVCpu The cross context virtual CPU structure.
122	*/
123	VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
124	{
125	return pVCpu->em.s.enmState;
126	}
127
128
129	/**
130	* Sets the current execution manager status. (use only when you know what you're doing!)
131	*
132	* @param pVCpu The cross context virtual CPU structure.
133	* @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
134	*/
135	VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
136	{
137	/* Only allowed combination: */
138	Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
139	pVCpu->em.s.enmState = enmNewState;
140	}
141
142
143	/**
144	* Sets the PC for which interrupts should be inhibited.
145	*
146	* @param pVCpu The cross context virtual CPU structure.
147	* @param PC The PC.
148	*/
149	VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
150	{
151	pVCpu->em.s.GCPtrInhibitInterrupts = PC;
152	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
153	}
154
155
156	/**
157	* Gets the PC for which interrupts should be inhibited.
158	*
159	* There are a few instructions which inhibits or delays interrupts
160	* for the instruction following them. These instructions are:
161	* - STI
162	* - MOV SS, r/m16
163	* - POP SS
164	*
165	* @returns The PC for which interrupts should be inhibited.
166	* @param pVCpu The cross context virtual CPU structure.
167	*
168	*/
169	VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
170	{
171	return pVCpu->em.s.GCPtrInhibitInterrupts;
172	}
173
174
175	/**
176	* Prepare an MWAIT - essentials of the MONITOR instruction.
177	*
178	* @returns VINF_SUCCESS
179	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
180	* @param rax The content of RAX.
181	* @param rcx The content of RCX.
182	* @param rdx The content of RDX.
183	* @param GCPhys The physical address corresponding to rax.
184	*/
185	VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
186	{
187	pVCpu->em.s.MWait.uMonitorRAX = rax;
188	pVCpu->em.s.MWait.uMonitorRCX = rcx;
189	pVCpu->em.s.MWait.uMonitorRDX = rdx;
190	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_MONITOR_ACTIVE;
191	/** @todo Make use of GCPhys. */
192	NOREF(GCPhys);
193	/** @todo Complete MONITOR implementation. */
194	return VINF_SUCCESS;
195	}
196
197
198	/**
199	* Checks if the monitor hardware is armed / active.
200	*
201	* @returns true if armed, false otherwise.
202	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
203	*/
204	VMM_INT_DECL(bool) EMMonitorIsArmed(PVMCPU pVCpu)
205	{
206	return RT_BOOL(pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_MONITOR_ACTIVE);
207	}
208
209
210	/**
211	* Performs an MWAIT.
212	*
213	* @returns VINF_SUCCESS
214	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
215	* @param rax The content of RAX.
216	* @param rcx The content of RCX.
217	*/
218	VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
219	{
220	pVCpu->em.s.MWait.uMWaitRAX = rax;
221	pVCpu->em.s.MWait.uMWaitRCX = rcx;
222	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_ACTIVE;
223	if (rcx)
224	pVCpu->em.s.MWait.fWait \|= EMMWAIT_FLAG_BREAKIRQIF0;
225	else
226	pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
227	/** @todo not completely correct?? */
228	return VINF_EM_HALT;
229	}
230
231
232
233	/**
234	* Determine if we should continue execution in HM after encountering an mwait
235	* instruction.
236	*
237	* Clears MWAIT flags if returning @c true.
238	*
239	* @returns true if we should continue, false if we should halt.
240	* @param pVCpu The cross context virtual CPU structure.
241	* @param pCtx Current CPU context.
242	*/
243	VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
244	{
245	if ( pCtx->eflags.Bits.u1IF
246	\|\| ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0))
247	== (EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0)) )
248	{
249	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
250	{
251	pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE \| EMMWAIT_FLAG_BREAKIRQIF0);
252	return true;
253	}
254	}
255
256	return false;
257	}
258
259
260	/**
261	* Determine if we should continue execution in HM after encountering a hlt
262	* instruction.
263	*
264	* @returns true if we should continue, false if we should halt.
265	* @param pVCpu The cross context virtual CPU structure.
266	* @param pCtx Current CPU context.
267	*/
268	VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
269	{
270	/** @todo Shouldn't we be checking GIF here? */
271	if (pCtx->eflags.Bits.u1IF)
272	return VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC));
273	return false;
274	}
275
276
277	/**
278	* Unhalts and wakes up the given CPU.
279	*
280	* This is an API for assisting the KVM hypercall API in implementing KICK_CPU.
281	* It sets VMCPU_FF_UNHALT for @a pVCpuDst and makes sure it is woken up. If
282	* the CPU isn't currently in a halt, the next HLT instruction it executes will
283	* be affected.
284	*
285	* @returns GVMMR0SchedWakeUpEx result or VINF_SUCCESS depending on context.
286	* @param pVM The cross context VM structure.
287	* @param pVCpuDst The cross context virtual CPU structure of the
288	* CPU to unhalt and wake up. This is usually not the
289	* same as the caller.
290	* @thread EMT
291	*/
292	VMM_INT_DECL(int) EMUnhaltAndWakeUp(PVM pVM, PVMCPU pVCpuDst)
293	{
294	/*
295	* Flag the current(/next) HLT to unhalt immediately.
296	*/
297	VMCPU_FF_SET(pVCpuDst, VMCPU_FF_UNHALT);
298
299	/*
300	* Wake up the EMT (technically should be abstracted by VMM/VMEmt, but
301	* just do it here for now).
302	*/
303	#ifdef IN_RING0
304	/* We might be here with preemption disabled or enabled (i.e. depending on
305	thread-context hooks being used), so don't try obtaining the GVMMR0 used
306	lock here. See @bugref{7270#c148}. */
307	int rc = GVMMR0SchedWakeUpNoGVMNoLock(pVM, pVCpuDst->idCpu);
308	AssertRC(rc);
309
310	#elif defined(IN_RING3)
311	int rc = SUPR3CallVMMR0(pVM->pVMR0, pVCpuDst->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL /* pvArg */);
312	AssertRC(rc);
313
314	#else
315	/* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
316	Assert(pVM->cCpus == 1); NOREF(pVM);
317	int rc = VINF_SUCCESS;
318	#endif
319	return rc;
320	}
321
322
323	/**
324	* Locks REM execution to a single VCPU.
325	*
326	* @param pVM The cross context VM structure.
327	*/
328	VMMDECL(void) EMRemLock(PVM pVM)
329	{
330	#ifdef VBOX_WITH_REM
331	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
332	return; /* early init */
333
334	Assert(!PGMIsLockOwner(pVM));
335	Assert(!IOMIsLockWriteOwner(pVM));
336	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
337	AssertRCSuccess(rc);
338	#else
339	RT_NOREF(pVM);
340	#endif
341	}
342
343
344	/**
345	* Unlocks REM execution
346	*
347	* @param pVM The cross context VM structure.
348	*/
349	VMMDECL(void) EMRemUnlock(PVM pVM)
350	{
351	#ifdef VBOX_WITH_REM
352	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
353	return; /* early init */
354
355	PDMCritSectLeave(&pVM->em.s.CritSectREM);
356	#else
357	RT_NOREF(pVM);
358	#endif
359	}
360
361
362	/**
363	* Check if this VCPU currently owns the REM lock.
364	*
365	* @returns bool owner/not owner
366	* @param pVM The cross context VM structure.
367	*/
368	VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
369	{
370	#ifdef VBOX_WITH_REM
371	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
372	return true; /* early init */
373
374	return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
375	#else
376	RT_NOREF(pVM);
377	return true;
378	#endif
379	}
380
381
382	/**
383	* Try to acquire the REM lock.
384	*
385	* @returns VBox status code
386	* @param pVM The cross context VM structure.
387	*/
388	VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
389	{
390	#ifdef VBOX_WITH_REM
391	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
392	return VINF_SUCCESS; /* early init */
393
394	return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
395	#else
396	RT_NOREF(pVM);
397	return VINF_SUCCESS;
398	#endif
399	}
400
401
402	/**
403	* @callback_method_impl{FNDISREADBYTES}
404	*/
405	static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
406	{
407	PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
408	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
409	PVM pVM = pVCpu->CTX_SUFF(pVM);
410	#endif
411	RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
412	int rc;
413
414	/*
415	* Figure how much we can or must read.
416	*/
417	size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
418	if (cbToRead > cbMaxRead)
419	cbToRead = cbMaxRead;
420	else if (cbToRead < cbMinRead)
421	cbToRead = cbMinRead;
422
423	#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) \|\| defined(IN_RING3))
424	/*
425	* We might be called upon to interpret an instruction in a patch.
426	*/
427	if (PATMIsPatchGCAddr(pVM, uSrcAddr))
428	{
429	# ifdef IN_RC
430	memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
431	# else
432	memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVM, uSrcAddr), cbToRead);
433	# endif
434	rc = VINF_SUCCESS;
435	}
436	else
437	#endif
438	{
439	# ifdef IN_RC
440	/*
441	* Try access it thru the shadow page tables first. Fall back on the
442	* slower PGM method if it fails because the TLB or page table was
443	* modified recently.
444	*/
445	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
446	if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
447	{
448	cbToRead = cbMinRead;
449	rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
450	}
451	if (rc == VERR_ACCESS_DENIED)
452	#endif
453	{
454	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
455	if (RT_FAILURE(rc))
456	{
457	if (cbToRead > cbMinRead)
458	{
459	cbToRead = cbMinRead;
460	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
461	}
462	if (RT_FAILURE(rc))
463	{
464	#ifndef IN_RC
465	/*
466	* If we fail to find the page via the guest's page tables
467	* we invalidate the page in the host TLB (pertaining to
468	* the guest in the NestedPaging case). See @bugref{6043}.
469	*/
470	if (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
471	{
472	HMInvalidatePage(pVCpu, uSrcAddr);
473	if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
474	HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
475	}
476	#endif
477	}
478	}
479	}
480	}
481
482	pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
483	return rc;
484	}
485
486
487	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
488	DECLINLINE(int) emDisCoreOne(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
489	{
490	NOREF(pVM);
491	return DISInstrWithReader(InstrGC, (DISCPUMODE)pDis->uCpuMode, emReadBytes, pVCpu, pDis, pOpsize);
492	}
493	#endif
494
495
496	/**
497	* Disassembles the current instruction.
498	*
499	* @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
500	* details.
501	*
502	* @param pVM The cross context VM structure.
503	* @param pVCpu The cross context virtual CPU structure.
504	* @param pDis Where to return the parsed instruction info.
505	* @param pcbInstr Where to return the instruction size. (optional)
506	*/
507	VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
508	{
509	PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
510	RTGCPTR GCPtrInstr;
511	#if 0
512	int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
513	#else
514	/** @todo Get the CPU mode as well while we're at it! */
515	int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
516	pCtxCore->rip, &GCPtrInstr);
517	#endif
518	if (RT_FAILURE(rc))
519	{
520	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
521	pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
522	return rc;
523	}
524	return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
525	}
526
527
528	/**
529	* Disassembles one instruction.
530	*
531	* This is used by internally by the interpreter and by trap/access handlers.
532	*
533	* @returns VBox status code.
534	*
535	* @param pVM The cross context VM structure.
536	* @param pVCpu The cross context virtual CPU structure.
537	* @param GCPtrInstr The flat address of the instruction.
538	* @param pCtxCore The context core (used to determine the cpu mode).
539	* @param pDis Where to return the parsed instruction info.
540	* @param pcbInstr Where to return the instruction size. (optional)
541	*/
542	VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
543	PDISCPUSTATE pDis, unsigned *pcbInstr)
544	{
545	NOREF(pVM);
546	Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
547	DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
548	/** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
549	* \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
550	int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
551	if (RT_SUCCESS(rc))
552	return VINF_SUCCESS;
553	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
554	return rc;
555	}
556
557
558	#if defined(VBOX_COMPARE_IEM_FIRST) \|\| defined(VBOX_COMPARE_IEM_LAST)
559	static void emCompareWithIem(PVMCPU pVCpu, PCCPUMCTX pEmCtx, PCCPUMCTX pIemCtx,
560	VBOXSTRICTRC rcEm, VBOXSTRICTRC rcIem,
561	uint32_t cbEm, uint32_t cbIem)
562	{
563	/* Quick compare. */
564	if ( rcEm == rcIem
565	&& cbEm == cbIem
566	&& g_cbEmWrote == g_cbIemWrote
567	&& memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote) == 0
568	&& memcmp(pIemCtx, pEmCtx, sizeof(*pIemCtx)) == 0
569	&& (g_fEmFFs & g_fInterestingFFs) == (g_fIemFFs & g_fInterestingFFs)
570	)
571	return;
572
573	/* Report exact differences. */
574	RTLogPrintf("! EM and IEM differs at %04x:%08RGv !\n", g_IncomingCtx.cs.Sel, g_IncomingCtx.rip);
575	if (rcEm != rcIem)
576	RTLogPrintf(" * rcIem=%Rrc rcEm=%Rrc\n", VBOXSTRICTRC_VAL(rcIem), VBOXSTRICTRC_VAL(rcEm));
577	else if (cbEm != cbIem)
578	RTLogPrintf(" * cbIem=%#x cbEm=%#x\n", cbIem, cbEm);
579
580	if (RT_SUCCESS(rcEm) && RT_SUCCESS(rcIem))
581	{
582	if (g_cbIemWrote != g_cbEmWrote)
583	RTLogPrintf("!! g_cbIemWrote=%#x g_cbEmWrote=%#x\n", g_cbIemWrote, g_cbEmWrote);
584	else if (memcmp(g_abIemWrote, g_abEmWrote, g_cbIemWrote))
585	{
586	RTLogPrintf("!! IemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
587	RTLogPrintf("!! EemWrote %.*Rhxs\n", RT_MIN(RT_MAX(1, g_cbIemWrote), 64), g_abIemWrote);
588	}
589
590	if ((g_fEmFFs & g_fInterestingFFs) != (g_fIemFFs & g_fInterestingFFs))
591	RTLogPrintf("!! g_fIemFFs=%#x g_fEmFFs=%#x (diff=%#x)\n", g_fIemFFs & g_fInterestingFFs,
592	g_fEmFFs & g_fInterestingFFs, (g_fIemFFs ^ g_fEmFFs) & g_fInterestingFFs);
593
594	# define CHECK_FIELD(a_Field) \
595	do \
596	{ \
597	if (pEmCtx->a_Field != pIemCtx->a_Field) \
598	{ \
599	switch (sizeof(pEmCtx->a_Field)) \
600	{ \
601	case 1: RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
602	case 2: RTLogPrintf("!! %8s differs - iem=%04x - em=%04x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
603	case 4: RTLogPrintf("!! %8s differs - iem=%08x - em=%08x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
604	case 8: RTLogPrintf("!! %8s differs - iem=%016llx - em=%016llx\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); break; \
605	default: RTLogPrintf("!! %8s differs\n", #a_Field); break; \
606	} \
607	cDiffs++; \
608	} \
609	} while (0)
610
611	# define CHECK_BIT_FIELD(a_Field) \
612	do \
613	{ \
614	if (pEmCtx->a_Field != pIemCtx->a_Field) \
615	{ \
616	RTLogPrintf("!! %8s differs - iem=%02x - em=%02x\n", #a_Field, pIemCtx->a_Field, pEmCtx->a_Field); \
617	cDiffs++; \
618	} \
619	} while (0)
620
621	# define CHECK_SEL(a_Sel) \
622	do \
623	{ \
624	CHECK_FIELD(a_Sel.Sel); \
625	CHECK_FIELD(a_Sel.Attr.u); \
626	CHECK_FIELD(a_Sel.u64Base); \
627	CHECK_FIELD(a_Sel.u32Limit); \
628	CHECK_FIELD(a_Sel.fFlags); \
629	} while (0)
630
631	unsigned cDiffs = 0;
632	if (memcmp(&pEmCtx->fpu, &pIemCtx->fpu, sizeof(pIemCtx->fpu)))
633	{
634	RTLogPrintf(" the FPU state differs\n");
635	cDiffs++;
636	CHECK_FIELD(fpu.FCW);
637	CHECK_FIELD(fpu.FSW);
638	CHECK_FIELD(fpu.FTW);
639	CHECK_FIELD(fpu.FOP);
640	CHECK_FIELD(fpu.FPUIP);
641	CHECK_FIELD(fpu.CS);
642	CHECK_FIELD(fpu.Rsrvd1);
643	CHECK_FIELD(fpu.FPUDP);
644	CHECK_FIELD(fpu.DS);
645	CHECK_FIELD(fpu.Rsrvd2);
646	CHECK_FIELD(fpu.MXCSR);
647	CHECK_FIELD(fpu.MXCSR_MASK);
648	CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
649	CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
650	CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
651	CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
652	CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
653	CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
654	CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
655	CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
656	CHECK_FIELD(fpu.aXMM[ 0].au64[0]); CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
657	CHECK_FIELD(fpu.aXMM[ 1].au64[0]); CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
658	CHECK_FIELD(fpu.aXMM[ 2].au64[0]); CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
659	CHECK_FIELD(fpu.aXMM[ 3].au64[0]); CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
660	CHECK_FIELD(fpu.aXMM[ 4].au64[0]); CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
661	CHECK_FIELD(fpu.aXMM[ 5].au64[0]); CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
662	CHECK_FIELD(fpu.aXMM[ 6].au64[0]); CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
663	CHECK_FIELD(fpu.aXMM[ 7].au64[0]); CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
664	CHECK_FIELD(fpu.aXMM[ 8].au64[0]); CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
665	CHECK_FIELD(fpu.aXMM[ 9].au64[0]); CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
666	CHECK_FIELD(fpu.aXMM[10].au64[0]); CHECK_FIELD(fpu.aXMM[10].au64[1]);
667	CHECK_FIELD(fpu.aXMM[11].au64[0]); CHECK_FIELD(fpu.aXMM[11].au64[1]);
668	CHECK_FIELD(fpu.aXMM[12].au64[0]); CHECK_FIELD(fpu.aXMM[12].au64[1]);
669	CHECK_FIELD(fpu.aXMM[13].au64[0]); CHECK_FIELD(fpu.aXMM[13].au64[1]);
670	CHECK_FIELD(fpu.aXMM[14].au64[0]); CHECK_FIELD(fpu.aXMM[14].au64[1]);
671	CHECK_FIELD(fpu.aXMM[15].au64[0]); CHECK_FIELD(fpu.aXMM[15].au64[1]);
672	for (unsigned i = 0; i < RT_ELEMENTS(pEmCtx->fpu.au32RsrvdRest); i++)
673	CHECK_FIELD(fpu.au32RsrvdRest[i]);
674	}
675	CHECK_FIELD(rip);
676	if (pEmCtx->rflags.u != pIemCtx->rflags.u)
677	{
678	RTLogPrintf("!! rflags differs - iem=%08llx em=%08llx\n", pIemCtx->rflags.u, pEmCtx->rflags.u);
679	CHECK_BIT_FIELD(rflags.Bits.u1CF);
680	CHECK_BIT_FIELD(rflags.Bits.u1Reserved0);
681	CHECK_BIT_FIELD(rflags.Bits.u1PF);
682	CHECK_BIT_FIELD(rflags.Bits.u1Reserved1);
683	CHECK_BIT_FIELD(rflags.Bits.u1AF);
684	CHECK_BIT_FIELD(rflags.Bits.u1Reserved2);
685	CHECK_BIT_FIELD(rflags.Bits.u1ZF);
686	CHECK_BIT_FIELD(rflags.Bits.u1SF);
687	CHECK_BIT_FIELD(rflags.Bits.u1TF);
688	CHECK_BIT_FIELD(rflags.Bits.u1IF);
689	CHECK_BIT_FIELD(rflags.Bits.u1DF);
690	CHECK_BIT_FIELD(rflags.Bits.u1OF);
691	CHECK_BIT_FIELD(rflags.Bits.u2IOPL);
692	CHECK_BIT_FIELD(rflags.Bits.u1NT);
693	CHECK_BIT_FIELD(rflags.Bits.u1Reserved3);
694	CHECK_BIT_FIELD(rflags.Bits.u1RF);
695	CHECK_BIT_FIELD(rflags.Bits.u1VM);
696	CHECK_BIT_FIELD(rflags.Bits.u1AC);
697	CHECK_BIT_FIELD(rflags.Bits.u1VIF);
698	CHECK_BIT_FIELD(rflags.Bits.u1VIP);
699	CHECK_BIT_FIELD(rflags.Bits.u1ID);
700	}
701
702	if (!g_fIgnoreRaxRdx)
703	CHECK_FIELD(rax);
704	CHECK_FIELD(rcx);
705	if (!g_fIgnoreRaxRdx)
706	CHECK_FIELD(rdx);
707	CHECK_FIELD(rbx);
708	CHECK_FIELD(rsp);
709	CHECK_FIELD(rbp);
710	CHECK_FIELD(rsi);
711	CHECK_FIELD(rdi);
712	CHECK_FIELD(r8);
713	CHECK_FIELD(r9);
714	CHECK_FIELD(r10);
715	CHECK_FIELD(r11);
716	CHECK_FIELD(r12);
717	CHECK_FIELD(r13);
718	CHECK_SEL(cs);
719	CHECK_SEL(ss);
720	CHECK_SEL(ds);
721	CHECK_SEL(es);
722	CHECK_SEL(fs);
723	CHECK_SEL(gs);
724	CHECK_FIELD(cr0);
725	CHECK_FIELD(cr2);
726	CHECK_FIELD(cr3);
727	CHECK_FIELD(cr4);
728	CHECK_FIELD(dr[0]);
729	CHECK_FIELD(dr[1]);
730	CHECK_FIELD(dr[2]);
731	CHECK_FIELD(dr[3]);
732	CHECK_FIELD(dr[6]);
733	CHECK_FIELD(dr[7]);
734	CHECK_FIELD(gdtr.cbGdt);
735	CHECK_FIELD(gdtr.pGdt);
736	CHECK_FIELD(idtr.cbIdt);
737	CHECK_FIELD(idtr.pIdt);
738	CHECK_SEL(ldtr);
739	CHECK_SEL(tr);
740	CHECK_FIELD(SysEnter.cs);
741	CHECK_FIELD(SysEnter.eip);
742	CHECK_FIELD(SysEnter.esp);
743	CHECK_FIELD(msrEFER);
744	CHECK_FIELD(msrSTAR);
745	CHECK_FIELD(msrPAT);
746	CHECK_FIELD(msrLSTAR);
747	CHECK_FIELD(msrCSTAR);
748	CHECK_FIELD(msrSFMASK);
749	CHECK_FIELD(msrKERNELGSBASE);
750
751	# undef CHECK_FIELD
752	# undef CHECK_BIT_FIELD
753	}
754	}
755	#endif /* VBOX_COMPARE_IEM_AND_EM */
756
757
758	/**
759	* Interprets the current instruction.
760	*
761	* @returns VBox status code.
762	* @retval VINF_* Scheduling instructions.
763	* @retval VERR_EM_INTERPRETER Something we can't cope with.
764	* @retval VERR_* Fatal errors.
765	*
766	* @param pVCpu The cross context virtual CPU structure.
767	* @param pRegFrame The register frame.
768	* Updates the EIP if an instruction was executed successfully.
769	* @param pvFault The fault address (CR2).
770	*
771	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
772	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
773	* to worry about e.g. invalid modrm combinations (!)
774	*/
775	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
776	{
777	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
778	LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
779	#ifdef VBOX_WITH_IEM
780	NOREF(pvFault);
781
782	# ifdef VBOX_COMPARE_IEM_AND_EM
783	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
784	g_IncomingCtx = *pCtx;
785	g_fIncomingFFs = pVCpu->fLocalForcedActions;
786	g_cbEmWrote = g_cbIemWrote = 0;
787
788	# ifdef VBOX_COMPARE_IEM_FIRST
789	/* IEM */
790	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
791	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
792	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
793	rcIem = VERR_EM_INTERPRETER;
794	g_IemCtx = *pCtx;
795	g_fIemFFs = pVCpu->fLocalForcedActions;
796	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
797	*pCtx = g_IncomingCtx;
798	# endif
799
800	/* EM */
801	RTGCPTR pbCode;
802	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
803	if (RT_SUCCESS(rcEm))
804	{
805	uint32_t cbOp;
806	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
807	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
808	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
809	if (RT_SUCCESS(rcEm))
810	{
811	Assert(cbOp == pDis->cbInstr);
812	uint32_t cbIgnored;
813	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
814	if (RT_SUCCESS(rcEm))
815	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
816
817	}
818	rcEm = VERR_EM_INTERPRETER;
819	}
820	else
821	rcEm = VERR_EM_INTERPRETER;
822	# ifdef VBOX_SAME_AS_EM
823	if (rcEm == VERR_EM_INTERPRETER)
824	{
825	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
826	return rcEm;
827	}
828	# endif
829	g_EmCtx = *pCtx;
830	g_fEmFFs = pVCpu->fLocalForcedActions;
831	VBOXSTRICTRC rc = rcEm;
832
833	# ifdef VBOX_COMPARE_IEM_LAST
834	/* IEM */
835	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
836	*pCtx = g_IncomingCtx;
837	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
838	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
839	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
840	rcIem = VERR_EM_INTERPRETER;
841	g_IemCtx = *pCtx;
842	g_fIemFFs = pVCpu->fLocalForcedActions;
843	rc = rcIem;
844	# endif
845
846	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
847	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
848	# endif
849
850	# else
851	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
852	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
853	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
854	rc = VERR_EM_INTERPRETER;
855	# endif
856	if (rc != VINF_SUCCESS)
857	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
858
859	return rc;
860	#else
861	RTGCPTR pbCode;
862	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
863	if (RT_SUCCESS(rc))
864	{
865	uint32_t cbOp;
866	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
867	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
868	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
869	if (RT_SUCCESS(rc))
870	{
871	Assert(cbOp == pDis->cbInstr);
872	uint32_t cbIgnored;
873	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbIgnored);
874	if (RT_SUCCESS(rc))
875	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
876
877	return rc;
878	}
879	}
880	return VERR_EM_INTERPRETER;
881	#endif
882	}
883
884
885	/**
886	* Interprets the current instruction.
887	*
888	* @returns VBox status code.
889	* @retval VINF_* Scheduling instructions.
890	* @retval VERR_EM_INTERPRETER Something we can't cope with.
891	* @retval VERR_* Fatal errors.
892	*
893	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
894	* @param pRegFrame The register frame.
895	* Updates the EIP if an instruction was executed successfully.
896	* @param pvFault The fault address (CR2).
897	* @param pcbWritten Size of the write (if applicable).
898	*
899	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
900	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
901	* to worry about e.g. invalid modrm combinations (!)
902	*/
903	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
904	{
905	LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
906	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
907	#ifdef VBOX_WITH_IEM
908	NOREF(pvFault);
909
910	# ifdef VBOX_COMPARE_IEM_AND_EM
911	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
912	g_IncomingCtx = *pCtx;
913	g_fIncomingFFs = pVCpu->fLocalForcedActions;
914	g_cbEmWrote = g_cbIemWrote = 0;
915
916	# ifdef VBOX_COMPARE_IEM_FIRST
917	/* IEM */
918	uint32_t cbIemWritten = 0;
919	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
920	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
921	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
922	rcIem = VERR_EM_INTERPRETER;
923	g_IemCtx = *pCtx;
924	g_fIemFFs = pVCpu->fLocalForcedActions;
925	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
926	*pCtx = g_IncomingCtx;
927	# endif
928
929	/* EM */
930	uint32_t cbEmWritten = 0;
931	RTGCPTR pbCode;
932	VBOXSTRICTRC rcEm = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
933	if (RT_SUCCESS(rcEm))
934	{
935	uint32_t cbOp;
936	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
937	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
938	rcEm = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
939	if (RT_SUCCESS(rcEm))
940	{
941	Assert(cbOp == pDis->cbInstr);
942	rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, &cbEmWritten);
943	if (RT_SUCCESS(rcEm))
944	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
945
946	}
947	else
948	rcEm = VERR_EM_INTERPRETER;
949	}
950	else
951	rcEm = VERR_EM_INTERPRETER;
952	# ifdef VBOX_SAME_AS_EM
953	if (rcEm == VERR_EM_INTERPRETER)
954	{
955	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
956	return rcEm;
957	}
958	# endif
959	g_EmCtx = *pCtx;
960	g_fEmFFs = pVCpu->fLocalForcedActions;
961	*pcbWritten = cbEmWritten;
962	VBOXSTRICTRC rc = rcEm;
963
964	# ifdef VBOX_COMPARE_IEM_LAST
965	/* IEM */
966	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
967	*pCtx = g_IncomingCtx;
968	uint32_t cbIemWritten = 0;
969	VBOXSTRICTRC rcIem = IEMExecOneBypassEx(pVCpu, pRegFrame, &cbIemWritten);
970	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
971	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
972	rcIem = VERR_EM_INTERPRETER;
973	g_IemCtx = *pCtx;
974	g_fIemFFs = pVCpu->fLocalForcedActions;
975	*pcbWritten = cbIemWritten;
976	rc = rcIem;
977	# endif
978
979	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
980	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, cbEmWritten, cbIemWritten);
981	# endif
982
983	# else
984	VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
985	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
986	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
987	rc = VERR_EM_INTERPRETER;
988	# endif
989	if (rc != VINF_SUCCESS)
990	Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
991
992	return rc;
993	#else
994	RTGCPTR pbCode;
995	VBOXSTRICTRC rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
996	if (RT_SUCCESS(rc))
997	{
998	uint32_t cbOp;
999	PDISCPUSTATE pDis = &pVCpu->em.s.DisState;
1000	pDis->uCpuMode = CPUMGetGuestDisMode(pVCpu);
1001	rc = emDisCoreOne(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, (RTGCUINTPTR)pbCode, &cbOp);
1002	if (RT_SUCCESS(rc))
1003	{
1004	Assert(cbOp == pDis->cbInstr);
1005	rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_SUPERVISOR, pcbWritten);
1006	if (RT_SUCCESS(rc))
1007	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
1008
1009	return rc;
1010	}
1011	}
1012	return VERR_EM_INTERPRETER;
1013	#endif
1014	}
1015
1016
1017	/**
1018	* Interprets the current instruction using the supplied DISCPUSTATE structure.
1019	*
1020	* IP/EIP/RIP IS updated!
1021	*
1022	* @returns VBox strict status code.
1023	* @retval VINF_* Scheduling instructions. When these are returned, it
1024	* starts to get a bit tricky to know whether code was
1025	* executed or not... We'll address this when it becomes a problem.
1026	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1027	* @retval VERR_* Fatal errors.
1028	*
1029	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1030	* @param pDis The disassembler cpu state for the instruction to be
1031	* interpreted.
1032	* @param pRegFrame The register frame. IP/EIP/RIP IS changed!
1033	* @param pvFault The fault address (CR2).
1034	* @param enmCodeType Code type (user/supervisor)
1035	*
1036	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1037	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1038	* to worry about e.g. invalid modrm combinations (!)
1039	*
1040	* @todo At this time we do NOT check if the instruction overwrites vital information.
1041	* Make sure this can't happen!! (will add some assertions/checks later)
1042	*/
1043	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
1044	RTGCPTR pvFault, EMCODETYPE enmCodeType)
1045	{
1046	LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1047	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1048	#ifdef VBOX_WITH_IEM
1049	NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
1050
1051	# ifdef VBOX_COMPARE_IEM_AND_EM
1052	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1053	g_IncomingCtx = *pCtx;
1054	g_fIncomingFFs = pVCpu->fLocalForcedActions;
1055	g_cbEmWrote = g_cbIemWrote = 0;
1056
1057	# ifdef VBOX_COMPARE_IEM_FIRST
1058	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1059	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1060	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1061	rcIem = VERR_EM_INTERPRETER;
1062	g_IemCtx = *pCtx;
1063	g_fIemFFs = pVCpu->fLocalForcedActions;
1064	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1065	*pCtx = g_IncomingCtx;
1066	# endif
1067
1068	/* EM */
1069	uint32_t cbIgnored;
1070	VBOXSTRICTRC rcEm = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1071	if (RT_SUCCESS(rcEm))
1072	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1073	# ifdef VBOX_SAME_AS_EM
1074	if (rcEm == VERR_EM_INTERPRETER)
1075	{
1076	Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rcEm)));
1077	return rcEm;
1078	}
1079	# endif
1080	g_EmCtx = *pCtx;
1081	g_fEmFFs = pVCpu->fLocalForcedActions;
1082	VBOXSTRICTRC rc = rcEm;
1083
1084	# ifdef VBOX_COMPARE_IEM_LAST
1085	/* IEM */
1086	pVCpu->fLocalForcedActions = (pVCpu->fLocalForcedActions & ~g_fInterestingFFs) \| (g_fIncomingFFs & g_fInterestingFFs);
1087	*pCtx = g_IncomingCtx;
1088	VBOXSTRICTRC rcIem = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1089	if (RT_UNLIKELY( rcIem == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1090	\|\| rcIem == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1091	rcIem = VERR_EM_INTERPRETER;
1092	g_IemCtx = *pCtx;
1093	g_fIemFFs = pVCpu->fLocalForcedActions;
1094	rc = rcIem;
1095	# endif
1096
1097	# if defined(VBOX_COMPARE_IEM_LAST) \|\| defined(VBOX_COMPARE_IEM_FIRST)
1098	emCompareWithIem(pVCpu, &g_EmCtx, &g_IemCtx, rcEm, rcIem, 0, 0);
1099	# endif
1100
1101	# else
1102	VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1103	if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1104	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1105	rc = VERR_EM_INTERPRETER;
1106	# endif
1107
1108	if (rc != VINF_SUCCESS)
1109	Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1110
1111	return rc;
1112	#else
1113	uint32_t cbIgnored;
1114	VBOXSTRICTRC rc = emInterpretInstructionCPUOuter(pVCpu, pDis, pRegFrame, pvFault, enmCodeType, &cbIgnored);
1115	if (RT_SUCCESS(rc))
1116	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
1117	return rc;
1118	#endif
1119	}
1120
1121	#ifdef IN_RC
1122
1123	DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1124	{
1125	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1126	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1127	return rc;
1128	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1129	}
1130
1131
1132	/**
1133	* Interpret IRET (currently only to V86 code) - PATM only.
1134	*
1135	* @returns VBox status code.
1136	* @param pVM The cross context VM structure.
1137	* @param pVCpu The cross context virtual CPU structure.
1138	* @param pRegFrame The register frame.
1139	*
1140	*/
1141	VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1142	{
1143	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1144	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1145	int rc;
1146
1147	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1148	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1149	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1150	* this function. Fear that it may guru on us, thus not converted to
1151	* IEM. */
1152
1153	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1154	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1155	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1156	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1157	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1158
1159	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1160	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1161	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1162	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1163	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1164	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1165	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1166
1167	pRegFrame->eip = eip & 0xffff;
1168	pRegFrame->cs.Sel = cs;
1169
1170	/* Mask away all reserved bits */
1171	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1172	eflags &= uMask;
1173
1174	CPUMRawSetEFlags(pVCpu, eflags);
1175	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1176
1177	pRegFrame->esp = esp;
1178	pRegFrame->ss.Sel = ss;
1179	pRegFrame->ds.Sel = ds;
1180	pRegFrame->es.Sel = es;
1181	pRegFrame->fs.Sel = fs;
1182	pRegFrame->gs.Sel = gs;
1183
1184	return VINF_SUCCESS;
1185	}
1186
1187	# ifndef VBOX_WITH_IEM
1188	/**
1189	* IRET Emulation.
1190	*/
1191	static int emInterpretIret(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1192	{
1193	#ifdef VBOX_WITH_RAW_RING1
1194	NOREF(pvFault); NOREF(pcbSize); NOREF(pDis);
1195	if (EMIsRawRing1Enabled(pVM))
1196	{
1197	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1198	RTGCUINTPTR eip, cs, esp, ss, eflags, uMask;
1199	int rc;
1200	uint32_t cpl, rpl;
1201
1202	/* We only execute 32-bits protected mode code in raw mode, so no need to bother to check for 16-bits code here. */
1203	/** @todo we don't verify all the edge cases that generate #GP faults */
1204
1205	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1206	Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1207	/** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1208	* this function. Fear that it may guru on us, thus not converted to
1209	* IEM. */
1210
1211	rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1212	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1213	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1214	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1215	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1216
1217	/* Deal with V86 above. */
1218	if (eflags & X86_EFL_VM)
1219	return EMInterpretIretV86ForPatm(pVM, pVCpu, pRegFrame);
1220
1221	cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
1222	rpl = cs & X86_SEL_RPL;
1223
1224	Log(("emInterpretIret: iret to CS:EIP=%04X:%08X eflags=%x\n", cs, eip, eflags));
1225	if (rpl != cpl)
1226	{
1227	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1228	rc \|= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1229	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1230	Log(("emInterpretIret: return to different privilege level (rpl=%d cpl=%d)\n", rpl, cpl));
1231	Log(("emInterpretIret: SS:ESP=%04x:%08x\n", ss, esp));
1232	pRegFrame->ss.Sel = ss;
1233	pRegFrame->esp = esp;
1234	}
1235	pRegFrame->cs.Sel = cs;
1236	pRegFrame->eip = eip;
1237
1238	/* Adjust CS & SS as required. */
1239	CPUMRCRecheckRawState(pVCpu, pRegFrame);
1240
1241	/* Mask away all reserved bits */
1242	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1243	eflags &= uMask;
1244
1245	CPUMRawSetEFlags(pVCpu, eflags);
1246	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1247	return VINF_SUCCESS;
1248	}
1249	#else
1250	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
1251	#endif
1252	return VERR_EM_INTERPRETER;
1253	}
1254	# endif /* !VBOX_WITH_IEM */
1255
1256	#endif /* IN_RC */
1257
1258
1259
1260	/*
1261	*
1262	* Old interpreter primitives used by HM, move/eliminate later.
1263	* Old interpreter primitives used by HM, move/eliminate later.
1264	* Old interpreter primitives used by HM, move/eliminate later.
1265	* Old interpreter primitives used by HM, move/eliminate later.
1266	* Old interpreter primitives used by HM, move/eliminate later.
1267	*
1268	*/
1269
1270
1271	/**
1272	* Interpret CPUID given the parameters in the CPU context.
1273	*
1274	* @returns VBox status code.
1275	* @param pVM The cross context VM structure.
1276	* @param pVCpu The cross context virtual CPU structure.
1277	* @param pRegFrame The register frame.
1278	*
1279	*/
1280	VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1281	{
1282	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1283	uint32_t iLeaf = pRegFrame->eax;
1284	uint32_t iSubLeaf = pRegFrame->ecx;
1285	NOREF(pVM);
1286
1287	/* cpuid clears the high dwords of the affected 64 bits registers. */
1288	pRegFrame->rax = 0;
1289	pRegFrame->rbx = 0;
1290	pRegFrame->rcx = 0;
1291	pRegFrame->rdx = 0;
1292
1293	/* Note: operates the same in 64 and non-64 bits mode. */
1294	CPUMGetGuestCpuId(pVCpu, iLeaf, iSubLeaf, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1295	Log(("Emulate: CPUID %x/%x -> %08x %08x %08x %08x\n", iLeaf, iSubLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1296	return VINF_SUCCESS;
1297	}
1298
1299
1300	/**
1301	* Interpret RDTSC.
1302	*
1303	* @returns VBox status code.
1304	* @param pVM The cross context VM structure.
1305	* @param pVCpu The cross context virtual CPU structure.
1306	* @param pRegFrame The register frame.
1307	*
1308	*/
1309	VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1310	{
1311	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1312	unsigned uCR4 = CPUMGetGuestCR4(pVCpu);
1313
1314	if (uCR4 & X86_CR4_TSD)
1315	return VERR_EM_INTERPRETER; /* genuine #GP */
1316
1317	uint64_t uTicks = TMCpuTickGet(pVCpu);
1318	#ifdef VBOX_WITH_NESTED_HWVIRT
1319	uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
1320	#endif
1321
1322	/* Same behaviour in 32 & 64 bits mode */
1323	pRegFrame->rax = RT_LO_U32(uTicks);
1324	pRegFrame->rdx = RT_HI_U32(uTicks);
1325	#ifdef VBOX_COMPARE_IEM_AND_EM
1326	g_fIgnoreRaxRdx = true;
1327	#endif
1328
1329	NOREF(pVM);
1330	return VINF_SUCCESS;
1331	}
1332
1333	/**
1334	* Interpret RDTSCP.
1335	*
1336	* @returns VBox status code.
1337	* @param pVM The cross context VM structure.
1338	* @param pVCpu The cross context virtual CPU structure.
1339	* @param pCtx The CPU context.
1340	*
1341	*/
1342	VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1343	{
1344	Assert(pCtx == CPUMQueryGuestCtxPtr(pVCpu));
1345	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1346
1347	if (!pVM->cpum.ro.GuestFeatures.fRdTscP)
1348	{
1349	AssertFailed();
1350	return VERR_EM_INTERPRETER; /* genuine #UD */
1351	}
1352
1353	if (uCR4 & X86_CR4_TSD)
1354	return VERR_EM_INTERPRETER; /* genuine #GP */
1355
1356	uint64_t uTicks = TMCpuTickGet(pVCpu);
1357	#ifdef VBOX_WITH_NESTED_HWVIRT
1358	uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
1359	#endif
1360
1361	/* Same behaviour in 32 & 64 bits mode */
1362	pCtx->rax = RT_LO_U32(uTicks);
1363	pCtx->rdx = RT_HI_U32(uTicks);
1364	#ifdef VBOX_COMPARE_IEM_AND_EM
1365	g_fIgnoreRaxRdx = true;
1366	#endif
1367	/* Low dword of the TSC_AUX msr only. */
1368	VBOXSTRICTRC rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx); Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1369	pCtx->rcx &= UINT32_C(0xffffffff);
1370
1371	return VINF_SUCCESS;
1372	}
1373
1374	/**
1375	* Interpret RDPMC.
1376	*
1377	* @returns VBox status code.
1378	* @param pVM The cross context VM structure.
1379	* @param pVCpu The cross context virtual CPU structure.
1380	* @param pRegFrame The register frame.
1381	*
1382	*/
1383	VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1384	{
1385	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1386	uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1387
1388	/* If X86_CR4_PCE is not set, then CPL must be zero. */
1389	if ( !(uCR4 & X86_CR4_PCE)
1390	&& CPUMGetGuestCPL(pVCpu) != 0)
1391	{
1392	Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1393	return VERR_EM_INTERPRETER; /* genuine #GP */
1394	}
1395
1396	/* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1397	pRegFrame->rax = 0;
1398	pRegFrame->rdx = 0;
1399	/** @todo We should trigger a \#GP here if the CPU doesn't support the index in
1400	* ecx but see @bugref{3472}! */
1401
1402	NOREF(pVM);
1403	return VINF_SUCCESS;
1404	}
1405
1406
1407	/**
1408	* MWAIT Emulation.
1409	*/
1410	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1411	{
1412	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1413	uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1414	NOREF(pVM);
1415
1416	/* Get the current privilege level. */
1417	cpl = CPUMGetGuestCPL(pVCpu);
1418	if (cpl != 0)
1419	return VERR_EM_INTERPRETER; /* supervisor only */
1420
1421	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1422	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1423	return VERR_EM_INTERPRETER; /* not supported */
1424
1425	/*
1426	* CPUID.05H.ECX[0] defines support for power management extensions (eax)
1427	* CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1428	*/
1429	CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1430	if (pRegFrame->ecx > 1)
1431	{
1432	Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1433	return VERR_EM_INTERPRETER; /* illegal value. */
1434	}
1435
1436	if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1437	{
1438	Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1439	return VERR_EM_INTERPRETER; /* illegal value. */
1440	}
1441
1442	return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1443	}
1444
1445
1446	/**
1447	* MONITOR Emulation.
1448	*/
1449	VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1450	{
1451	uint32_t u32Dummy, u32ExtFeatures, cpl;
1452	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1453	NOREF(pVM);
1454
1455	if (pRegFrame->ecx != 0)
1456	{
1457	Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1458	return VERR_EM_INTERPRETER; /* illegal value. */
1459	}
1460
1461	/* Get the current privilege level. */
1462	cpl = CPUMGetGuestCPL(pVCpu);
1463	if (cpl != 0)
1464	return VERR_EM_INTERPRETER; /* supervisor only */
1465
1466	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1467	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1468	return VERR_EM_INTERPRETER; /* not supported */
1469
1470	EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1471	return VINF_SUCCESS;
1472	}
1473
1474
1475	/* VT-x only: */
1476
1477	/**
1478	* Interpret INVLPG.
1479	*
1480	* @returns VBox status code.
1481	* @param pVM The cross context VM structure.
1482	* @param pVCpu The cross context virtual CPU structure.
1483	* @param pRegFrame The register frame.
1484	* @param pAddrGC Operand address.
1485	*
1486	*/
1487	VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1488	{
1489	/** @todo is addr always a flat linear address or ds based
1490	* (in absence of segment override prefixes)????
1491	*/
1492	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1493	NOREF(pVM); NOREF(pRegFrame);
1494	#ifdef IN_RC
1495	LogFlow(("RC: EMULATE: invlpg %RGv\n", pAddrGC));
1496	#endif
1497	VBOXSTRICTRC rc = PGMInvalidatePage(pVCpu, pAddrGC);
1498	if ( rc == VINF_SUCCESS
1499	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
1500	return VINF_SUCCESS;
1501	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
1502	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), pAddrGC),
1503	VERR_EM_INTERPRETER);
1504	return rc;
1505	}
1506
1507
1508	#ifdef LOG_ENABLED
1509	static const char *emMSRtoString(uint32_t uMsr)
1510	{
1511	switch (uMsr)
1512	{
1513	case MSR_IA32_APICBASE: return "MSR_IA32_APICBASE";
1514	case MSR_IA32_CR_PAT: return "MSR_IA32_CR_PAT";
1515	case MSR_IA32_SYSENTER_CS: return "MSR_IA32_SYSENTER_CS";
1516	case MSR_IA32_SYSENTER_EIP: return "MSR_IA32_SYSENTER_EIP";
1517	case MSR_IA32_SYSENTER_ESP: return "MSR_IA32_SYSENTER_ESP";
1518	case MSR_K6_EFER: return "MSR_K6_EFER";
1519	case MSR_K8_SF_MASK: return "MSR_K8_SF_MASK";
1520	case MSR_K6_STAR: return "MSR_K6_STAR";
1521	case MSR_K8_LSTAR: return "MSR_K8_LSTAR";
1522	case MSR_K8_CSTAR: return "MSR_K8_CSTAR";
1523	case MSR_K8_FS_BASE: return "MSR_K8_FS_BASE";
1524	case MSR_K8_GS_BASE: return "MSR_K8_GS_BASE";
1525	case MSR_K8_KERNEL_GS_BASE: return "MSR_K8_KERNEL_GS_BASE";
1526	case MSR_K8_TSC_AUX: return "MSR_K8_TSC_AUX";
1527	case MSR_IA32_BIOS_SIGN_ID: return "Unsupported MSR_IA32_BIOS_SIGN_ID";
1528	case MSR_IA32_PLATFORM_ID: return "Unsupported MSR_IA32_PLATFORM_ID";
1529	case MSR_IA32_BIOS_UPDT_TRIG: return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
1530	case MSR_IA32_TSC: return "MSR_IA32_TSC";
1531	case MSR_IA32_MISC_ENABLE: return "MSR_IA32_MISC_ENABLE";
1532	case MSR_IA32_MTRR_CAP: return "MSR_IA32_MTRR_CAP";
1533	case MSR_IA32_MCG_CAP: return "Unsupported MSR_IA32_MCG_CAP";
1534	case MSR_IA32_MCG_STATUS: return "Unsupported MSR_IA32_MCG_STATUS";
1535	case MSR_IA32_MCG_CTRL: return "Unsupported MSR_IA32_MCG_CTRL";
1536	case MSR_IA32_MTRR_DEF_TYPE: return "MSR_IA32_MTRR_DEF_TYPE";
1537	case MSR_K7_EVNTSEL0: return "Unsupported MSR_K7_EVNTSEL0";
1538	case MSR_K7_EVNTSEL1: return "Unsupported MSR_K7_EVNTSEL1";
1539	case MSR_K7_EVNTSEL2: return "Unsupported MSR_K7_EVNTSEL2";
1540	case MSR_K7_EVNTSEL3: return "Unsupported MSR_K7_EVNTSEL3";
1541	case MSR_IA32_MC0_CTL: return "Unsupported MSR_IA32_MC0_CTL";
1542	case MSR_IA32_MC0_STATUS: return "Unsupported MSR_IA32_MC0_STATUS";
1543	case MSR_IA32_PERFEVTSEL0: return "Unsupported MSR_IA32_PERFEVTSEL0";
1544	case MSR_IA32_PERFEVTSEL1: return "Unsupported MSR_IA32_PERFEVTSEL1";
1545	case MSR_IA32_PERF_STATUS: return "MSR_IA32_PERF_STATUS";
1546	case MSR_IA32_PLATFORM_INFO: return "MSR_IA32_PLATFORM_INFO";
1547	case MSR_IA32_PERF_CTL: return "Unsupported MSR_IA32_PERF_CTL";
1548	case MSR_K7_PERFCTR0: return "Unsupported MSR_K7_PERFCTR0";
1549	case MSR_K7_PERFCTR1: return "Unsupported MSR_K7_PERFCTR1";
1550	case MSR_K7_PERFCTR2: return "Unsupported MSR_K7_PERFCTR2";
1551	case MSR_K7_PERFCTR3: return "Unsupported MSR_K7_PERFCTR3";
1552	case MSR_IA32_PMC0: return "Unsupported MSR_IA32_PMC0";
1553	case MSR_IA32_PMC1: return "Unsupported MSR_IA32_PMC1";
1554	case MSR_IA32_PMC2: return "Unsupported MSR_IA32_PMC2";
1555	case MSR_IA32_PMC3: return "Unsupported MSR_IA32_PMC3";
1556	}
1557	return "Unknown MSR";
1558	}
1559	#endif /* LOG_ENABLED */
1560
1561
1562	/**
1563	* Interpret RDMSR
1564	*
1565	* @returns VBox status code.
1566	* @param pVM The cross context VM structure.
1567	* @param pVCpu The cross context virtual CPU structure.
1568	* @param pRegFrame The register frame.
1569	*/
1570	VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1571	{
1572	NOREF(pVM);
1573
1574	/* Get the current privilege level. */
1575	if (CPUMGetGuestCPL(pVCpu) != 0)
1576	{
1577	Log4(("EM: Refuse RDMSR: CPL != 0\n"));
1578	return VERR_EM_INTERPRETER; /* supervisor only */
1579	}
1580
1581	uint64_t uValue;
1582	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRegFrame->ecx, &uValue);
1583	if (RT_UNLIKELY(rcStrict != VINF_SUCCESS))
1584	{
1585	Log4(("EM: Refuse RDMSR: rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1586	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_READ);
1587	return VERR_EM_INTERPRETER;
1588	}
1589	pRegFrame->rax = RT_LO_U32(uValue);
1590	pRegFrame->rdx = RT_HI_U32(uValue);
1591	LogFlow(("EMInterpretRdmsr %s (%x) -> %RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, uValue));
1592	return VINF_SUCCESS;
1593	}
1594
1595
1596	/**
1597	* Interpret WRMSR
1598	*
1599	* @returns VBox status code.
1600	* @param pVM The cross context VM structure.
1601	* @param pVCpu The cross context virtual CPU structure.
1602	* @param pRegFrame The register frame.
1603	*/
1604	VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1605	{
1606	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1607
1608	/* Check the current privilege level, this instruction is supervisor only. */
1609	if (CPUMGetGuestCPL(pVCpu) != 0)
1610	{
1611	Log4(("EM: Refuse WRMSR: CPL != 0\n"));
1612	return VERR_EM_INTERPRETER; /** @todo raise \#GP(0) */
1613	}
1614
1615	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRegFrame->ecx, RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx));
1616	if (rcStrict != VINF_SUCCESS)
1617	{
1618	Log4(("EM: Refuse WRMSR: CPUMSetGuestMsr returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1619	Assert(rcStrict == VERR_CPUM_RAISE_GP_0 \|\| rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_CPUM_R3_MSR_WRITE);
1620	return VERR_EM_INTERPRETER;
1621	}
1622	LogFlow(("EMInterpretWrmsr %s (%x) val=%RX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx,
1623	RT_MAKE_U64(pRegFrame->eax, pRegFrame->edx)));
1624	NOREF(pVM);
1625	return VINF_SUCCESS;
1626	}
1627
1628
1629	/**
1630	* Interpret DRx write.
1631	*
1632	* @returns VBox status code.
1633	* @param pVM The cross context VM structure.
1634	* @param pVCpu The cross context virtual CPU structure.
1635	* @param pRegFrame The register frame.
1636	* @param DestRegDrx DRx register index (USE_REG_DR*)
1637	* @param SrcRegGen General purpose register index (USE_REG_E**))
1638	*
1639	*/
1640	VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1641	{
1642	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1643	uint64_t uNewDrX;
1644	int rc;
1645	NOREF(pVM);
1646
1647	if (CPUMIsGuestIn64BitCode(pVCpu))
1648	rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1649	else
1650	{
1651	uint32_t val32;
1652	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1653	uNewDrX = val32;
1654	}
1655
1656	if (RT_SUCCESS(rc))
1657	{
1658	if (DestRegDrx == 6)
1659	{
1660	uNewDrX \|= X86_DR6_RA1_MASK;
1661	uNewDrX &= ~X86_DR6_RAZ_MASK;
1662	}
1663	else if (DestRegDrx == 7)
1664	{
1665	uNewDrX \|= X86_DR7_RA1_MASK;
1666	uNewDrX &= ~X86_DR7_RAZ_MASK;
1667	}
1668
1669	/** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1670	rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1671	if (RT_SUCCESS(rc))
1672	return rc;
1673	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1674	}
1675	return VERR_EM_INTERPRETER;
1676	}
1677
1678
1679	/**
1680	* Interpret DRx read.
1681	*
1682	* @returns VBox status code.
1683	* @param pVM The cross context VM structure.
1684	* @param pVCpu The cross context virtual CPU structure.
1685	* @param pRegFrame The register frame.
1686	* @param DestRegGen General purpose register index (USE_REG_E**))
1687	* @param SrcRegDrx DRx register index (USE_REG_DR*)
1688	*/
1689	VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1690	{
1691	uint64_t val64;
1692	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1693	NOREF(pVM);
1694
1695	int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1696	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1697	if (CPUMIsGuestIn64BitCode(pVCpu))
1698	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1699	else
1700	rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1701
1702	if (RT_SUCCESS(rc))
1703	return VINF_SUCCESS;
1704
1705	return VERR_EM_INTERPRETER;
1706	}
1707
1708
1709	#if !defined(VBOX_WITH_IEM) \|\| defined(VBOX_COMPARE_IEM_AND_EM)
1710
1711
1712
1713
1714
1715
1716	/*
1717	*
1718	* The old interpreter.
1719	* The old interpreter.
1720	* The old interpreter.
1721	* The old interpreter.
1722	* The old interpreter.
1723	*
1724	*/
1725
1726	DECLINLINE(int) emRamRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1727	{
1728	#ifdef IN_RC
1729	int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1730	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1731	return rc;
1732	/*
1733	* The page pool cache may end up here in some cases because it
1734	* flushed one of the shadow mappings used by the trapping
1735	* instruction and it either flushed the TLB or the CPU reused it.
1736	*/
1737	#else
1738	NOREF(pVM);
1739	#endif
1740	return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /fMayTrap/ false);
1741	}
1742
1743
1744	DECLINLINE(int) emRamWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, uint32_t cb)
1745	{
1746	/* Don't use MMGCRamWrite here as it does not respect zero pages, shared
1747	pages or write monitored pages. */
1748	NOREF(pVM);
1749	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
1750	int rc = PGMPhysInterpretedWriteNoHandlers(pVCpu, pCtxCore, GCPtrDst, pvSrc, cb, /fMayTrap/ false);
1751	#else
1752	int rc = VINF_SUCCESS;
1753	#endif
1754	#ifdef VBOX_COMPARE_IEM_AND_EM
1755	Log(("EM Wrote: %RGv %.*Rhxs rc=%Rrc\n", GCPtrDst, RT_MAX(RT_MIN(cb, 64), 1), pvSrc, rc));
1756	g_cbEmWrote = cb;
1757	memcpy(g_abEmWrote, pvSrc, RT_MIN(cb, sizeof(g_abEmWrote)));
1758	#endif
1759	return rc;
1760	}
1761
1762
1763	/** Convert sel:addr to a flat GC address. */
1764	DECLINLINE(RTGCPTR) emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, PDISOPPARAM pParam, RTGCPTR pvAddr)
1765	{
1766	DISSELREG enmPrefixSeg = DISDetectSegReg(pDis, pParam);
1767	return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1768	}
1769
1770
1771	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
1772	/**
1773	* Get the mnemonic for the disassembled instruction.
1774	*
1775	* GC/R0 doesn't include the strings in the DIS tables because
1776	* of limited space.
1777	*/
1778	static const char *emGetMnemonic(PDISCPUSTATE pDis)
1779	{
1780	switch (pDis->pCurInstr->uOpcode)
1781	{
1782	case OP_XCHG: return "Xchg";
1783	case OP_DEC: return "Dec";
1784	case OP_INC: return "Inc";
1785	case OP_POP: return "Pop";
1786	case OP_OR: return "Or";
1787	case OP_AND: return "And";
1788	case OP_MOV: return "Mov";
1789	case OP_INVLPG: return "InvlPg";
1790	case OP_CPUID: return "CpuId";
1791	case OP_MOV_CR: return "MovCRx";
1792	case OP_MOV_DR: return "MovDRx";
1793	case OP_LLDT: return "LLdt";
1794	case OP_LGDT: return "LGdt";
1795	case OP_LIDT: return "LIdt";
1796	case OP_CLTS: return "Clts";
1797	case OP_MONITOR: return "Monitor";
1798	case OP_MWAIT: return "MWait";
1799	case OP_RDMSR: return "Rdmsr";
1800	case OP_WRMSR: return "Wrmsr";
1801	case OP_ADD: return "Add";
1802	case OP_ADC: return "Adc";
1803	case OP_SUB: return "Sub";
1804	case OP_SBB: return "Sbb";
1805	case OP_RDTSC: return "Rdtsc";
1806	case OP_STI: return "Sti";
1807	case OP_CLI: return "Cli";
1808	case OP_XADD: return "XAdd";
1809	case OP_HLT: return "Hlt";
1810	case OP_IRET: return "Iret";
1811	case OP_MOVNTPS: return "MovNTPS";
1812	case OP_STOSWD: return "StosWD";
1813	case OP_WBINVD: return "WbInvd";
1814	case OP_XOR: return "Xor";
1815	case OP_BTR: return "Btr";
1816	case OP_BTS: return "Bts";
1817	case OP_BTC: return "Btc";
1818	case OP_LMSW: return "Lmsw";
1819	case OP_SMSW: return "Smsw";
1820	case OP_CMPXCHG: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
1821	case OP_CMPXCHG8B: return pDis->fPrefix & DISPREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
1822
1823	default:
1824	Log(("Unknown opcode %d\n", pDis->pCurInstr->uOpcode));
1825	return "???";
1826	}
1827	}
1828	#endif /* VBOX_STRICT \|\| LOG_ENABLED */
1829
1830
1831	/**
1832	* XCHG instruction emulation.
1833	*/
1834	static int emInterpretXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1835	{
1836	DISQPVPARAMVAL param1, param2;
1837	NOREF(pvFault);
1838
1839	/* Source to make DISQueryParamVal read the register value - ugly hack */
1840	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
1841	if(RT_FAILURE(rc))
1842	return VERR_EM_INTERPRETER;
1843
1844	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
1845	if(RT_FAILURE(rc))
1846	return VERR_EM_INTERPRETER;
1847
1848	#ifdef IN_RC
1849	if (TRPMHasTrap(pVCpu))
1850	{
1851	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1852	{
1853	#endif
1854	RTGCPTR pParam1 = 0, pParam2 = 0;
1855	uint64_t valpar1, valpar2;
1856
1857	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
1858	switch(param1.type)
1859	{
1860	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
1861	valpar1 = param1.val.val64;
1862	break;
1863
1864	case DISQPV_TYPE_ADDRESS:
1865	pParam1 = (RTGCPTR)param1.val.val64;
1866	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
1867	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
1868	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
1869	if (RT_FAILURE(rc))
1870	{
1871	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1872	return VERR_EM_INTERPRETER;
1873	}
1874	break;
1875
1876	default:
1877	AssertFailed();
1878	return VERR_EM_INTERPRETER;
1879	}
1880
1881	switch(param2.type)
1882	{
1883	case DISQPV_TYPE_ADDRESS:
1884	pParam2 = (RTGCPTR)param2.val.val64;
1885	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pParam2);
1886	EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
1887	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar2, pParam2, param2.size);
1888	if (RT_FAILURE(rc))
1889	{
1890	AssertMsgFailed(("MMGCRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1891	}
1892	break;
1893
1894	case DISQPV_TYPE_IMMEDIATE:
1895	valpar2 = param2.val.val64;
1896	break;
1897
1898	default:
1899	AssertFailed();
1900	return VERR_EM_INTERPRETER;
1901	}
1902
1903	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
1904	if (pParam1 == 0)
1905	{
1906	Assert(param1.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
1907	switch(param1.size)
1908	{
1909	case 1: //special case for AH etc
1910	rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t )valpar2); break;
1911	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)valpar2); break;
1912	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)valpar2); break;
1913	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, valpar2); break;
1914	default: AssertFailedReturn(VERR_EM_INTERPRETER);
1915	}
1916	if (RT_FAILURE(rc))
1917	return VERR_EM_INTERPRETER;
1918	}
1919	else
1920	{
1921	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar2, param1.size);
1922	if (RT_FAILURE(rc))
1923	{
1924	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1925	return VERR_EM_INTERPRETER;
1926	}
1927	}
1928
1929	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
1930	if (pParam2 == 0)
1931	{
1932	Assert(param2.type == DISQPV_TYPE_IMMEDIATE); /* register actually */
1933	switch(param2.size)
1934	{
1935	case 1: //special case for AH etc
1936	rc = DISWriteReg8(pRegFrame, pDis->Param2.Base.idxGenReg, (uint8_t )valpar1); break;
1937	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param2.Base.idxGenReg, (uint16_t)valpar1); break;
1938	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param2.Base.idxGenReg, (uint32_t)valpar1); break;
1939	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param2.Base.idxGenReg, valpar1); break;
1940	default: AssertFailedReturn(VERR_EM_INTERPRETER);
1941	}
1942	if (RT_FAILURE(rc))
1943	return VERR_EM_INTERPRETER;
1944	}
1945	else
1946	{
1947	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam2, &valpar1, param2.size);
1948	if (RT_FAILURE(rc))
1949	{
1950	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1951	return VERR_EM_INTERPRETER;
1952	}
1953	}
1954
1955	*pcbSize = param2.size;
1956	return VINF_SUCCESS;
1957	#ifdef IN_RC
1958	}
1959	}
1960	return VERR_EM_INTERPRETER;
1961	#endif
1962	}
1963
1964
1965	/**
1966	* INC and DEC emulation.
1967	*/
1968	static int emInterpretIncDec(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
1969	PFNEMULATEPARAM2 pfnEmulate)
1970	{
1971	DISQPVPARAMVAL param1;
1972	NOREF(pvFault);
1973
1974	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
1975	if(RT_FAILURE(rc))
1976	return VERR_EM_INTERPRETER;
1977
1978	#ifdef IN_RC
1979	if (TRPMHasTrap(pVCpu))
1980	{
1981	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
1982	{
1983	#endif
1984	RTGCPTR pParam1 = 0;
1985	uint64_t valpar1;
1986
1987	if (param1.type == DISQPV_TYPE_ADDRESS)
1988	{
1989	pParam1 = (RTGCPTR)param1.val.val64;
1990	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
1991	#ifdef IN_RC
1992	/* Safety check (in theory it could cross a page boundary and fault there though) */
1993	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
1994	#endif
1995	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
1996	if (RT_FAILURE(rc))
1997	{
1998	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
1999	return VERR_EM_INTERPRETER;
2000	}
2001	}
2002	else
2003	{
2004	AssertFailed();
2005	return VERR_EM_INTERPRETER;
2006	}
2007
2008	uint32_t eflags;
2009
2010	eflags = pfnEmulate(&valpar1, param1.size);
2011
2012	/* Write result back */
2013	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2014	if (RT_FAILURE(rc))
2015	{
2016	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2017	return VERR_EM_INTERPRETER;
2018	}
2019
2020	/* Update guest's eflags and finish. */
2021	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2022	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2023
2024	/* All done! */
2025	*pcbSize = param1.size;
2026	return VINF_SUCCESS;
2027	#ifdef IN_RC
2028	}
2029	}
2030	return VERR_EM_INTERPRETER;
2031	#endif
2032	}
2033
2034
2035	/**
2036	* POP Emulation.
2037	*/
2038	static int emInterpretPop(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2039	{
2040	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2041	DISQPVPARAMVAL param1;
2042	NOREF(pvFault);
2043
2044	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2045	if(RT_FAILURE(rc))
2046	return VERR_EM_INTERPRETER;
2047
2048	#ifdef IN_RC
2049	if (TRPMHasTrap(pVCpu))
2050	{
2051	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2052	{
2053	#endif
2054	RTGCPTR pParam1 = 0;
2055	uint32_t valpar1;
2056	RTGCPTR pStackVal;
2057
2058	/* Read stack value first */
2059	if (CPUMGetGuestCodeBits(pVCpu) == 16)
2060	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
2061
2062	/* Convert address; don't bother checking limits etc, as we only read here */
2063	pStackVal = SELMToFlat(pVM, DISSELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
2064	if (pStackVal == 0)
2065	return VERR_EM_INTERPRETER;
2066
2067	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pStackVal, param1.size);
2068	if (RT_FAILURE(rc))
2069	{
2070	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2071	return VERR_EM_INTERPRETER;
2072	}
2073
2074	if (param1.type == DISQPV_TYPE_ADDRESS)
2075	{
2076	pParam1 = (RTGCPTR)param1.val.val64;
2077
2078	/* pop [esp+xx] uses esp after the actual pop! */
2079	AssertCompile(DISGREG_ESP == DISGREG_SP);
2080	if ( (pDis->Param1.fUse & DISUSE_BASE)
2081	&& (pDis->Param1.fUse & (DISUSE_REG_GEN16\|DISUSE_REG_GEN32))
2082	&& pDis->Param1.Base.idxGenReg == DISGREG_ESP
2083	)
2084	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
2085
2086	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2087	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
2088	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2089	if (RT_FAILURE(rc))
2090	{
2091	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2092	return VERR_EM_INTERPRETER;
2093	}
2094
2095	/* Update ESP as the last step */
2096	pRegFrame->esp += param1.size;
2097	}
2098	else
2099	{
2100	#ifndef DEBUG_bird // annoying assertion.
2101	AssertFailed();
2102	#endif
2103	return VERR_EM_INTERPRETER;
2104	}
2105
2106	/* All done! */
2107	*pcbSize = param1.size;
2108	return VINF_SUCCESS;
2109	#ifdef IN_RC
2110	}
2111	}
2112	return VERR_EM_INTERPRETER;
2113	#endif
2114	}
2115
2116
2117	/**
2118	* XOR/OR/AND Emulation.
2119	*/
2120	static int emInterpretOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2121	PFNEMULATEPARAM3 pfnEmulate)
2122	{
2123	DISQPVPARAMVAL param1, param2;
2124	NOREF(pvFault);
2125
2126	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2127	if(RT_FAILURE(rc))
2128	return VERR_EM_INTERPRETER;
2129
2130	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2131	if(RT_FAILURE(rc))
2132	return VERR_EM_INTERPRETER;
2133
2134	#ifdef IN_RC
2135	if (TRPMHasTrap(pVCpu))
2136	{
2137	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2138	{
2139	#endif
2140	RTGCPTR pParam1;
2141	uint64_t valpar1, valpar2;
2142
2143	if (pDis->Param1.cb != pDis->Param2.cb)
2144	{
2145	if (pDis->Param1.cb < pDis->Param2.cb)
2146	{
2147	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2148	return VERR_EM_INTERPRETER;
2149	}
2150	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2151	pDis->Param2.cb = pDis->Param1.cb;
2152	param2.size = param1.size;
2153	}
2154
2155	/* The destination is always a virtual address */
2156	if (param1.type == DISQPV_TYPE_ADDRESS)
2157	{
2158	pParam1 = (RTGCPTR)param1.val.val64;
2159	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2160	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2161	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2162	if (RT_FAILURE(rc))
2163	{
2164	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2165	return VERR_EM_INTERPRETER;
2166	}
2167	}
2168	else
2169	{
2170	AssertFailed();
2171	return VERR_EM_INTERPRETER;
2172	}
2173
2174	/* Register or immediate data */
2175	switch(param2.type)
2176	{
2177	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2178	valpar2 = param2.val.val64;
2179	break;
2180
2181	default:
2182	AssertFailed();
2183	return VERR_EM_INTERPRETER;
2184	}
2185
2186	LogFlow(("emInterpretOrXorAnd %s %RGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pDis), pParam1, valpar1, valpar2, param2.size, param1.size));
2187
2188	/* Data read, emulate instruction. */
2189	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2190
2191	LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pDis), valpar1));
2192
2193	/* Update guest's eflags and finish. */
2194	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2195	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2196
2197	/* And write it back */
2198	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2199	if (RT_SUCCESS(rc))
2200	{
2201	/* All done! */
2202	*pcbSize = param2.size;
2203	return VINF_SUCCESS;
2204	}
2205	#ifdef IN_RC
2206	}
2207	}
2208	#endif
2209	return VERR_EM_INTERPRETER;
2210	}
2211
2212
2213	#ifndef VBOX_COMPARE_IEM_AND_EM
2214	/**
2215	* LOCK XOR/OR/AND Emulation.
2216	*/
2217	static int emInterpretLockOrXorAnd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2218	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
2219	{
2220	void *pvParam1;
2221	DISQPVPARAMVAL param1, param2;
2222	NOREF(pvFault);
2223
2224	#if HC_ARCH_BITS == 32
2225	Assert(pDis->Param1.cb <= 4);
2226	#endif
2227
2228	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2229	if(RT_FAILURE(rc))
2230	return VERR_EM_INTERPRETER;
2231
2232	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2233	if(RT_FAILURE(rc))
2234	return VERR_EM_INTERPRETER;
2235
2236	if (pDis->Param1.cb != pDis->Param2.cb)
2237	{
2238	AssertMsgReturn(pDis->Param1.cb >= pDis->Param2.cb, /* should never happen! */
2239	("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb),
2240	VERR_EM_INTERPRETER);
2241
2242	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2243	pDis->Param2.cb = pDis->Param1.cb;
2244	param2.size = param1.size;
2245	}
2246
2247	#ifdef IN_RC
2248	/* Safety check (in theory it could cross a page boundary and fault there though) */
2249	Assert( TRPMHasTrap(pVCpu)
2250	&& (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW));
2251	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
2252	#endif
2253
2254	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2255	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2256	RTGCUINTREG ValPar2 = param2.val.val64;
2257
2258	/* The destination is always a virtual address */
2259	AssertReturn(param1.type == DISQPV_TYPE_ADDRESS, VERR_EM_INTERPRETER);
2260
2261	RTGCPTR GCPtrPar1 = param1.val.val64;
2262	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2263	PGMPAGEMAPLOCK Lock;
2264	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2265	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2266
2267	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2268	Log2(("%s %RGv imm%d=%RX64\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2269
2270	RTGCUINTREG32 eflags = 0;
2271	rc = pfnEmulate(pvParam1, ValPar2, pDis->Param2.cb, &eflags);
2272	PGMPhysReleasePageMappingLock(pVM, &Lock);
2273	if (RT_FAILURE(rc))
2274	{
2275	Log(("%s %RGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2276	return VERR_EM_INTERPRETER;
2277	}
2278
2279	/* Update guest's eflags and finish. */
2280	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2281	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2282
2283	*pcbSize = param2.size;
2284	return VINF_SUCCESS;
2285	}
2286	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2287
2288
2289	/**
2290	* ADD, ADC & SUB Emulation.
2291	*/
2292	static int emInterpretAddSub(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2293	PFNEMULATEPARAM3 pfnEmulate)
2294	{
2295	NOREF(pvFault);
2296	DISQPVPARAMVAL param1, param2;
2297	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2298	if(RT_FAILURE(rc))
2299	return VERR_EM_INTERPRETER;
2300
2301	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2302	if(RT_FAILURE(rc))
2303	return VERR_EM_INTERPRETER;
2304
2305	#ifdef IN_RC
2306	if (TRPMHasTrap(pVCpu))
2307	{
2308	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2309	{
2310	#endif
2311	RTGCPTR pParam1;
2312	uint64_t valpar1, valpar2;
2313
2314	if (pDis->Param1.cb != pDis->Param2.cb)
2315	{
2316	if (pDis->Param1.cb < pDis->Param2.cb)
2317	{
2318	AssertMsgFailed(("%s at %RGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip, pDis->Param1.cb, pDis->Param2.cb)); /* should never happen! */
2319	return VERR_EM_INTERPRETER;
2320	}
2321	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
2322	pDis->Param2.cb = pDis->Param1.cb;
2323	param2.size = param1.size;
2324	}
2325
2326	/* The destination is always a virtual address */
2327	if (param1.type == DISQPV_TYPE_ADDRESS)
2328	{
2329	pParam1 = (RTGCPTR)param1.val.val64;
2330	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2331	EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
2332	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, param1.size);
2333	if (RT_FAILURE(rc))
2334	{
2335	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2336	return VERR_EM_INTERPRETER;
2337	}
2338	}
2339	else
2340	{
2341	#ifndef DEBUG_bird
2342	AssertFailed();
2343	#endif
2344	return VERR_EM_INTERPRETER;
2345	}
2346
2347	/* Register or immediate data */
2348	switch(param2.type)
2349	{
2350	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2351	valpar2 = param2.val.val64;
2352	break;
2353
2354	default:
2355	AssertFailed();
2356	return VERR_EM_INTERPRETER;
2357	}
2358
2359	/* Data read, emulate instruction. */
2360	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
2361
2362	/* Update guest's eflags and finish. */
2363	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2364	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2365
2366	/* And write it back */
2367	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, param1.size);
2368	if (RT_SUCCESS(rc))
2369	{
2370	/* All done! */
2371	*pcbSize = param2.size;
2372	return VINF_SUCCESS;
2373	}
2374	#ifdef IN_RC
2375	}
2376	}
2377	#endif
2378	return VERR_EM_INTERPRETER;
2379	}
2380
2381
2382	/**
2383	* ADC Emulation.
2384	*/
2385	static int emInterpretAdc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2386	{
2387	if (pRegFrame->eflags.Bits.u1CF)
2388	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
2389	else
2390	return emInterpretAddSub(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
2391	}
2392
2393
2394	/**
2395	* BTR/C/S Emulation.
2396	*/
2397	static int emInterpretBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
2398	PFNEMULATEPARAM2UINT32 pfnEmulate)
2399	{
2400	DISQPVPARAMVAL param1, param2;
2401	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2402	if(RT_FAILURE(rc))
2403	return VERR_EM_INTERPRETER;
2404
2405	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2406	if(RT_FAILURE(rc))
2407	return VERR_EM_INTERPRETER;
2408
2409	#ifdef IN_RC
2410	if (TRPMHasTrap(pVCpu))
2411	{
2412	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
2413	{
2414	#endif
2415	RTGCPTR pParam1;
2416	uint64_t valpar1 = 0, valpar2;
2417	uint32_t eflags;
2418
2419	/* The destination is always a virtual address */
2420	if (param1.type != DISQPV_TYPE_ADDRESS)
2421	return VERR_EM_INTERPRETER;
2422
2423	pParam1 = (RTGCPTR)param1.val.val64;
2424	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
2425
2426	/* Register or immediate data */
2427	switch(param2.type)
2428	{
2429	case DISQPV_TYPE_IMMEDIATE: /* both immediate data and register (ugly) */
2430	valpar2 = param2.val.val64;
2431	break;
2432
2433	default:
2434	AssertFailed();
2435	return VERR_EM_INTERPRETER;
2436	}
2437
2438	Log2(("emInterpret%s: pvFault=%RGv pParam1=%RGv val2=%x\n", emGetMnemonic(pDis), pvFault, pParam1, valpar2));
2439	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
2440	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER); NOREF(pvFault);
2441	rc = emRamRead(pVM, pVCpu, pRegFrame, &valpar1, pParam1, 1);
2442	if (RT_FAILURE(rc))
2443	{
2444	AssertMsgFailed(("emRamRead %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
2445	return VERR_EM_INTERPRETER;
2446	}
2447
2448	Log2(("emInterpretBtx: val=%x\n", valpar1));
2449	/* Data read, emulate bit test instruction. */
2450	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
2451
2452	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
2453
2454	/* Update guest's eflags and finish. */
2455	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2456	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2457
2458	/* And write it back */
2459	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &valpar1, 1);
2460	if (RT_SUCCESS(rc))
2461	{
2462	/* All done! */
2463	*pcbSize = 1;
2464	return VINF_SUCCESS;
2465	}
2466	#ifdef IN_RC
2467	}
2468	}
2469	#endif
2470	return VERR_EM_INTERPRETER;
2471	}
2472
2473
2474	#ifndef VBOX_COMPARE_IEM_AND_EM
2475	/**
2476	* LOCK BTR/C/S Emulation.
2477	*/
2478	static int emInterpretLockBitTest(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
2479	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
2480	{
2481	void *pvParam1;
2482
2483	DISQPVPARAMVAL param1, param2;
2484	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2485	if(RT_FAILURE(rc))
2486	return VERR_EM_INTERPRETER;
2487
2488	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2489	if(RT_FAILURE(rc))
2490	return VERR_EM_INTERPRETER;
2491
2492	/* The destination is always a virtual address */
2493	if (param1.type != DISQPV_TYPE_ADDRESS)
2494	return VERR_EM_INTERPRETER;
2495
2496	/* Register and immediate data == DISQPV_TYPE_IMMEDIATE */
2497	AssertReturn(param2.type == DISQPV_TYPE_IMMEDIATE, VERR_EM_INTERPRETER);
2498	uint64_t ValPar2 = param2.val.val64;
2499
2500	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
2501	RTGCPTR GCPtrPar1 = param1.val.val64;
2502	GCPtrPar1 = (GCPtrPar1 + ValPar2 / 8);
2503	ValPar2 &= 7;
2504
2505	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2506	#ifdef IN_RC
2507	Assert(TRPMHasTrap(pVCpu));
2508	EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
2509	#endif
2510
2511	PGMPAGEMAPLOCK Lock;
2512	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2513	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2514
2515	Log2(("emInterpretLockBitTest %s: pvFault=%RGv GCPtrPar1=%RGv imm=%RX64\n", emGetMnemonic(pDis), pvFault, GCPtrPar1, ValPar2));
2516	NOREF(pvFault);
2517
2518	/* Try emulate it with a one-shot #PF handler in place. (RC) */
2519	RTGCUINTREG32 eflags = 0;
2520	rc = pfnEmulate(pvParam1, ValPar2, &eflags);
2521	PGMPhysReleasePageMappingLock(pVM, &Lock);
2522	if (RT_FAILURE(rc))
2523	{
2524	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RX64 -> emulation failed due to page fault!\n",
2525	emGetMnemonic(pDis), GCPtrPar1, pDis->Param2.cb*8, ValPar2));
2526	return VERR_EM_INTERPRETER;
2527	}
2528
2529	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RX64 CF=%d\n", emGetMnemonic(pDis), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
2530
2531	/* Update guest's eflags and finish. */
2532	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2533	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2534
2535	*pcbSize = 1;
2536	return VINF_SUCCESS;
2537	}
2538	#endif /* !VBOX_COMPARE_IEM_AND_EM */
2539
2540
2541	/**
2542	* MOV emulation.
2543	*/
2544	static int emInterpretMov(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2545	{
2546	NOREF(pvFault);
2547	DISQPVPARAMVAL param1, param2;
2548	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_DST);
2549	if(RT_FAILURE(rc))
2550	return VERR_EM_INTERPRETER;
2551
2552	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2553	if(RT_FAILURE(rc))
2554	return VERR_EM_INTERPRETER;
2555
2556	/* If destination is a segment register, punt. We can't handle it here.
2557	* NB: Source can be a register and still trigger a #PF!
2558	*/
2559	if (RT_UNLIKELY(pDis->Param1.fUse == DISUSE_REG_SEG))
2560	return VERR_EM_INTERPRETER;
2561
2562	if (param1.type == DISQPV_TYPE_ADDRESS)
2563	{
2564	RTGCPTR pDest;
2565	uint64_t val64;
2566
2567	switch(param1.type)
2568	{
2569	case DISQPV_TYPE_IMMEDIATE:
2570	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2571	return VERR_EM_INTERPRETER;
2572	RT_FALL_THRU();
2573
2574	case DISQPV_TYPE_ADDRESS:
2575	pDest = (RTGCPTR)param1.val.val64;
2576	pDest = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pDest);
2577	break;
2578
2579	default:
2580	AssertFailed();
2581	return VERR_EM_INTERPRETER;
2582	}
2583
2584	switch(param2.type)
2585	{
2586	case DISQPV_TYPE_IMMEDIATE: /* register type is translated to this one too */
2587	val64 = param2.val.val64;
2588	break;
2589
2590	default:
2591	Log(("emInterpretMov: unexpected type=%d rip=%RGv\n", param2.type, (RTGCPTR)pRegFrame->rip));
2592	return VERR_EM_INTERPRETER;
2593	}
2594	#ifdef LOG_ENABLED
2595	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2596	LogFlow(("EMInterpretInstruction at %RGv: OP_MOV %RGv <- %RX64 (%d) &val64=%RHv\n", (RTGCPTR)pRegFrame->rip, pDest, val64, param2.size, &val64));
2597	else
2598	LogFlow(("EMInterpretInstruction at %08RX64: OP_MOV %RGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
2599	#endif
2600
2601	Assert(param2.size <= 8 && param2.size > 0);
2602	EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
2603	rc = emRamWrite(pVM, pVCpu, pRegFrame, pDest, &val64, param2.size);
2604	if (RT_FAILURE(rc))
2605	return VERR_EM_INTERPRETER;
2606
2607	*pcbSize = param2.size;
2608	}
2609	#if defined(IN_RC) && defined(VBOX_WITH_RAW_RING1)
2610	/* mov xx, cs instruction is dangerous in raw mode and replaced by an 'int3' by csam/patm. */
2611	else if ( param1.type == DISQPV_TYPE_REGISTER
2612	&& param2.type == DISQPV_TYPE_REGISTER)
2613	{
2614	AssertReturn((pDis->Param1.fUse & (DISUSE_REG_GEN8\|DISUSE_REG_GEN16\|DISUSE_REG_GEN32)), VERR_EM_INTERPRETER);
2615	AssertReturn(pDis->Param2.fUse == DISUSE_REG_SEG, VERR_EM_INTERPRETER);
2616	AssertReturn(pDis->Param2.Base.idxSegReg == DISSELREG_CS, VERR_EM_INTERPRETER);
2617
2618	uint32_t u32Cpl = CPUMRCGetGuestCPL(pVCpu, pRegFrame);
2619	uint32_t uValCS = (pRegFrame->cs.Sel & ~X86_SEL_RPL) \| u32Cpl;
2620
2621	Log(("EMInterpretInstruction: OP_MOV cs=%x->%x\n", pRegFrame->cs.Sel, uValCS));
2622	switch (param1.size)
2623	{
2624	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) uValCS); break;
2625	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)uValCS); break;
2626	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)uValCS); break;
2627	default:
2628	AssertFailed();
2629	return VERR_EM_INTERPRETER;
2630	}
2631	AssertRCReturn(rc, rc);
2632	}
2633	#endif
2634	else
2635	{ /* read fault */
2636	RTGCPTR pSrc;
2637	uint64_t val64;
2638
2639	/* Source */
2640	switch(param2.type)
2641	{
2642	case DISQPV_TYPE_IMMEDIATE:
2643	if(!(param2.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
2644	return VERR_EM_INTERPRETER;
2645	RT_FALL_THRU();
2646
2647	case DISQPV_TYPE_ADDRESS:
2648	pSrc = (RTGCPTR)param2.val.val64;
2649	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param2, pSrc);
2650	break;
2651
2652	default:
2653	return VERR_EM_INTERPRETER;
2654	}
2655
2656	Assert(param1.size <= 8 && param1.size > 0);
2657	EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
2658	rc = emRamRead(pVM, pVCpu, pRegFrame, &val64, pSrc, param1.size);
2659	if (RT_FAILURE(rc))
2660	return VERR_EM_INTERPRETER;
2661
2662	/* Destination */
2663	switch(param1.type)
2664	{
2665	case DISQPV_TYPE_REGISTER:
2666	switch(param1.size)
2667	{
2668	case 1: rc = DISWriteReg8(pRegFrame, pDis->Param1.Base.idxGenReg, (uint8_t) val64); break;
2669	case 2: rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, (uint16_t)val64); break;
2670	case 4: rc = DISWriteReg32(pRegFrame, pDis->Param1.Base.idxGenReg, (uint32_t)val64); break;
2671	case 8: rc = DISWriteReg64(pRegFrame, pDis->Param1.Base.idxGenReg, val64); break;
2672	default:
2673	return VERR_EM_INTERPRETER;
2674	}
2675	if (RT_FAILURE(rc))
2676	return rc;
2677	break;
2678
2679	default:
2680	return VERR_EM_INTERPRETER;
2681	}
2682	#ifdef LOG_ENABLED
2683	if (pDis->uCpuMode == DISCPUMODE_64BIT)
2684	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
2685	else
2686	LogFlow(("EMInterpretInstruction: OP_MOV %RGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
2687	#endif
2688	}
2689	return VINF_SUCCESS;
2690	}
2691
2692
2693	#ifndef IN_RC
2694	/**
2695	* [REP] STOSWD emulation
2696	*/
2697	static int emInterpretStosWD(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2698	{
2699	int rc;
2700	RTGCPTR GCDest, GCOffset;
2701	uint32_t cbSize;
2702	uint64_t cTransfers;
2703	int offIncrement;
2704	NOREF(pvFault);
2705
2706	/* Don't support any but these three prefix bytes. */
2707	if ((pDis->fPrefix & ~(DISPREFIX_ADDRSIZE\|DISPREFIX_OPSIZE\|DISPREFIX_REP\|DISPREFIX_REX)))
2708	return VERR_EM_INTERPRETER;
2709
2710	switch (pDis->uAddrMode)
2711	{
2712	case DISCPUMODE_16BIT:
2713	GCOffset = pRegFrame->di;
2714	cTransfers = pRegFrame->cx;
2715	break;
2716	case DISCPUMODE_32BIT:
2717	GCOffset = pRegFrame->edi;
2718	cTransfers = pRegFrame->ecx;
2719	break;
2720	case DISCPUMODE_64BIT:
2721	GCOffset = pRegFrame->rdi;
2722	cTransfers = pRegFrame->rcx;
2723	break;
2724	default:
2725	AssertFailed();
2726	return VERR_EM_INTERPRETER;
2727	}
2728
2729	GCDest = SELMToFlat(pVM, DISSELREG_ES, pRegFrame, GCOffset);
2730	switch (pDis->uOpMode)
2731	{
2732	case DISCPUMODE_16BIT:
2733	cbSize = 2;
2734	break;
2735	case DISCPUMODE_32BIT:
2736	cbSize = 4;
2737	break;
2738	case DISCPUMODE_64BIT:
2739	cbSize = 8;
2740	break;
2741	default:
2742	AssertFailed();
2743	return VERR_EM_INTERPRETER;
2744	}
2745
2746	offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
2747
2748	if (!(pDis->fPrefix & DISPREFIX_REP))
2749	{
2750	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize));
2751
2752	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2753	if (RT_FAILURE(rc))
2754	return VERR_EM_INTERPRETER;
2755	Assert(rc == VINF_SUCCESS);
2756
2757	/* Update (e/r)di. */
2758	switch (pDis->uAddrMode)
2759	{
2760	case DISCPUMODE_16BIT:
2761	pRegFrame->di += offIncrement;
2762	break;
2763	case DISCPUMODE_32BIT:
2764	pRegFrame->edi += offIncrement;
2765	break;
2766	case DISCPUMODE_64BIT:
2767	pRegFrame->rdi += offIncrement;
2768	break;
2769	default:
2770	AssertFailed();
2771	return VERR_EM_INTERPRETER;
2772	}
2773
2774	}
2775	else
2776	{
2777	if (!cTransfers)
2778	return VINF_SUCCESS;
2779
2780	/*
2781	* Do not try emulate cross page stuff here because we don't know what might
2782	* be waiting for us on the subsequent pages. The caller has only asked us to
2783	* ignore access handlers fro the current page.
2784	* This also fends off big stores which would quickly kill PGMR0DynMap.
2785	*/
2786	if ( cbSize > PAGE_SIZE
2787	\|\| cTransfers > PAGE_SIZE
2788	\|\| (GCDest >> PAGE_SHIFT) != ((GCDest + offIncrement * cTransfers) >> PAGE_SHIFT))
2789	{
2790	Log(("STOSWD is crosses pages, chicken out to the recompiler; GCDest=%RGv cbSize=%#x offIncrement=%d cTransfers=%#x\n",
2791	GCDest, cbSize, offIncrement, cTransfers));
2792	return VERR_EM_INTERPRETER;
2793	}
2794
2795	LogFlow(("emInterpretStosWD dest=%04X:%RGv (%RGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es.Sel, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
2796	/* Access verification first; we currently can't recover properly from traps inside this instruction */
2797	rc = PGMVerifyAccess(pVCpu, GCDest - ((offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize)),
2798	cTransfers * cbSize,
2799	X86_PTE_RW \| (CPUMGetGuestCPL(pVCpu) == 3 ? X86_PTE_US : 0));
2800	if (rc != VINF_SUCCESS)
2801	{
2802	Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
2803	return VERR_EM_INTERPRETER;
2804	}
2805
2806	/* REP case */
2807	while (cTransfers)
2808	{
2809	rc = emRamWrite(pVM, pVCpu, pRegFrame, GCDest, &pRegFrame->rax, cbSize);
2810	if (RT_FAILURE(rc))
2811	{
2812	rc = VERR_EM_INTERPRETER;
2813	break;
2814	}
2815
2816	Assert(rc == VINF_SUCCESS);
2817	GCOffset += offIncrement;
2818	GCDest += offIncrement;
2819	cTransfers--;
2820	}
2821
2822	/* Update the registers. */
2823	switch (pDis->uAddrMode)
2824	{
2825	case DISCPUMODE_16BIT:
2826	pRegFrame->di = GCOffset;
2827	pRegFrame->cx = cTransfers;
2828	break;
2829	case DISCPUMODE_32BIT:
2830	pRegFrame->edi = GCOffset;
2831	pRegFrame->ecx = cTransfers;
2832	break;
2833	case DISCPUMODE_64BIT:
2834	pRegFrame->rdi = GCOffset;
2835	pRegFrame->rcx = cTransfers;
2836	break;
2837	default:
2838	AssertFailed();
2839	return VERR_EM_INTERPRETER;
2840	}
2841	}
2842
2843	*pcbSize = cbSize;
2844	return rc;
2845	}
2846	#endif /* !IN_RC */
2847
2848
2849	/**
2850	* [LOCK] CMPXCHG emulation.
2851	*/
2852	static int emInterpretCmpXchg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2853	{
2854	DISQPVPARAMVAL param1, param2;
2855	NOREF(pvFault);
2856
2857	#if HC_ARCH_BITS == 32
2858	Assert(pDis->Param1.cb <= 4);
2859	#endif
2860
2861	/* Source to make DISQueryParamVal read the register value - ugly hack */
2862	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2863	if(RT_FAILURE(rc))
2864	return VERR_EM_INTERPRETER;
2865
2866	rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param2, &param2, DISQPVWHICH_SRC);
2867	if(RT_FAILURE(rc))
2868	return VERR_EM_INTERPRETER;
2869
2870	uint64_t valpar;
2871	switch(param2.type)
2872	{
2873	case DISQPV_TYPE_IMMEDIATE: /* register actually */
2874	valpar = param2.val.val64;
2875	break;
2876
2877	default:
2878	return VERR_EM_INTERPRETER;
2879	}
2880
2881	PGMPAGEMAPLOCK Lock;
2882	RTGCPTR GCPtrPar1;
2883	void *pvParam1;
2884	uint64_t eflags;
2885
2886	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
2887	switch(param1.type)
2888	{
2889	case DISQPV_TYPE_ADDRESS:
2890	GCPtrPar1 = param1.val.val64;
2891	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2892
2893	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2894	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2895	break;
2896
2897	default:
2898	return VERR_EM_INTERPRETER;
2899	}
2900
2901	LogFlow(("%s %RGv rax=%RX64 %RX64\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar));
2902
2903	#ifndef VBOX_COMPARE_IEM_AND_EM
2904	if (pDis->fPrefix & DISPREFIX_LOCK)
2905	eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
2906	else
2907	eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pDis->Param2.cb);
2908	#else /* VBOX_COMPARE_IEM_AND_EM */
2909	uint64_t u64;
2910	switch (pDis->Param2.cb)
2911	{
2912	case 1: u64 = (uint8_t )pvParam1; break;
2913	case 2: u64 = (uint16_t )pvParam1; break;
2914	case 4: u64 = (uint32_t )pvParam1; break;
2915	default:
2916	case 8: u64 = (uint64_t )pvParam1; break;
2917	}
2918	eflags = EMEmulateCmpXchg(&u64, &pRegFrame->rax, valpar, pDis->Param2.cb);
2919	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
2920	#endif /* VBOX_COMPARE_IEM_AND_EM */
2921
2922	LogFlow(("%s %RGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
2923
2924	/* Update guest's eflags and finish. */
2925	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
2926	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
2927
2928	*pcbSize = param2.size;
2929	PGMPhysReleasePageMappingLock(pVM, &Lock);
2930	return VINF_SUCCESS;
2931	}
2932
2933
2934	/**
2935	* [LOCK] CMPXCHG8B emulation.
2936	*/
2937	static int emInterpretCmpXchg8b(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2938	{
2939	DISQPVPARAMVAL param1;
2940	NOREF(pvFault);
2941
2942	/* Source to make DISQueryParamVal read the register value - ugly hack */
2943	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
2944	if(RT_FAILURE(rc))
2945	return VERR_EM_INTERPRETER;
2946
2947	RTGCPTR GCPtrPar1;
2948	void *pvParam1;
2949	uint64_t eflags;
2950	PGMPAGEMAPLOCK Lock;
2951
2952	AssertReturn(pDis->Param1.cb == 8, VERR_EM_INTERPRETER);
2953	switch(param1.type)
2954	{
2955	case DISQPV_TYPE_ADDRESS:
2956	GCPtrPar1 = param1.val.val64;
2957	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, GCPtrPar1);
2958
2959	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
2960	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2961	break;
2962
2963	default:
2964	return VERR_EM_INTERPRETER;
2965	}
2966
2967	LogFlow(("%s %RGv=%p eax=%08x\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax));
2968
2969	#ifndef VBOX_COMPARE_IEM_AND_EM
2970	if (pDis->fPrefix & DISPREFIX_LOCK)
2971	eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2972	else
2973	eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2974	#else /* VBOX_COMPARE_IEM_AND_EM */
2975	uint64_t u64 = (uint64_t )pvParam1;
2976	eflags = EMEmulateCmpXchg8b(&u64, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
2977	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, sizeof(u64)); AssertRCSuccess(rc2);
2978	#endif /* VBOX_COMPARE_IEM_AND_EM */
2979
2980	LogFlow(("%s %RGv=%p eax=%08x ZF=%d\n", emGetMnemonic(pDis), GCPtrPar1, pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
2981
2982	/* Update guest's eflags and finish; note that only ZF is affected. */
2983	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
2984	\| (eflags & (X86_EFL_ZF));
2985
2986	*pcbSize = 8;
2987	PGMPhysReleasePageMappingLock(pVM, &Lock);
2988	return VINF_SUCCESS;
2989	}
2990
2991
2992	#ifdef IN_RC /** @todo test+enable for HM as well. */
2993	/**
2994	* [LOCK] XADD emulation.
2995	*/
2996	static int emInterpretXAdd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2997	{
2998	Assert(pDis->uCpuMode != DISCPUMODE_64BIT); /** @todo check */
2999	DISQPVPARAMVAL param1;
3000	void *pvParamReg2;
3001	size_t cbParamReg2;
3002	NOREF(pvFault);
3003
3004	/* Source to make DISQueryParamVal read the register value - ugly hack */
3005	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3006	if(RT_FAILURE(rc))
3007	return VERR_EM_INTERPRETER;
3008
3009	rc = DISQueryParamRegPtr(pRegFrame, pDis, &pDis->Param2, &pvParamReg2, &cbParamReg2);
3010	Assert(cbParamReg2 <= 4);
3011	if(RT_FAILURE(rc))
3012	return VERR_EM_INTERPRETER;
3013
3014	#ifdef IN_RC
3015	if (TRPMHasTrap(pVCpu))
3016	{
3017	if (TRPMGetErrorCode(pVCpu) & X86_TRAP_PF_RW)
3018	{
3019	#endif
3020	RTGCPTR GCPtrPar1;
3021	void *pvParam1;
3022	uint32_t eflags;
3023	PGMPAGEMAPLOCK Lock;
3024
3025	AssertReturn(pDis->Param1.cb == pDis->Param2.cb, VERR_EM_INTERPRETER);
3026	switch(param1.type)
3027	{
3028	case DISQPV_TYPE_ADDRESS:
3029	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, (RTRCUINTPTR)param1.val.val64);
3030	#ifdef IN_RC
3031	EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
3032	#endif
3033
3034	rc = PGMPhysGCPtr2CCPtr(pVCpu, GCPtrPar1, &pvParam1, &Lock);
3035	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3036	break;
3037
3038	default:
3039	return VERR_EM_INTERPRETER;
3040	}
3041
3042	LogFlow(("XAdd %RGv=%p reg=%08llx\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2));
3043
3044	#ifndef VBOX_COMPARE_IEM_AND_EM
3045	if (pDis->fPrefix & DISPREFIX_LOCK)
3046	eflags = EMEmulateLockXAdd(pvParam1, pvParamReg2, cbParamReg2);
3047	else
3048	eflags = EMEmulateXAdd(pvParam1, pvParamReg2, cbParamReg2);
3049	#else /* VBOX_COMPARE_IEM_AND_EM */
3050	uint64_t u64;
3051	switch (cbParamReg2)
3052	{
3053	case 1: u64 = (uint8_t )pvParam1; break;
3054	case 2: u64 = (uint16_t )pvParam1; break;
3055	case 4: u64 = (uint32_t )pvParam1; break;
3056	default:
3057	case 8: u64 = (uint64_t )pvParam1; break;
3058	}
3059	eflags = EMEmulateXAdd(&u64, pvParamReg2, cbParamReg2);
3060	int rc2 = emRamWrite(pVM, pVCpu, pRegFrame, GCPtrPar1, &u64, pDis->Param2.cb); AssertRCSuccess(rc2);
3061	#endif /* VBOX_COMPARE_IEM_AND_EM */
3062
3063	LogFlow(("XAdd %RGv=%p reg=%08llx ZF=%d\n", GCPtrPar1, pvParam1, (uint64_t )pvParamReg2, !!(eflags & X86_EFL_ZF) ));
3064
3065	/* Update guest's eflags and finish. */
3066	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
3067	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
3068
3069	*pcbSize = cbParamReg2;
3070	PGMPhysReleasePageMappingLock(pVM, &Lock);
3071	return VINF_SUCCESS;
3072	#ifdef IN_RC
3073	}
3074	}
3075
3076	return VERR_EM_INTERPRETER;
3077	#endif
3078	}
3079	#endif /* IN_RC */
3080
3081
3082	/**
3083	* WBINVD Emulation.
3084	*/
3085	static int emInterpretWbInvd(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3086	{
3087	/* Nothing to do. */
3088	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3089	return VINF_SUCCESS;
3090	}
3091
3092
3093	/**
3094	* INVLPG Emulation.
3095	*/
3096	static VBOXSTRICTRC emInterpretInvlPg(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3097	{
3098	DISQPVPARAMVAL param1;
3099	RTGCPTR addr;
3100	NOREF(pvFault); NOREF(pVM); NOREF(pcbSize);
3101
3102	VBOXSTRICTRC rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3103	if(RT_FAILURE(rc))
3104	return VERR_EM_INTERPRETER;
3105
3106	switch(param1.type)
3107	{
3108	case DISQPV_TYPE_IMMEDIATE:
3109	case DISQPV_TYPE_ADDRESS:
3110	if(!(param1.flags & (DISQPV_FLAG_32\|DISQPV_FLAG_64)))
3111	return VERR_EM_INTERPRETER;
3112	addr = (RTGCPTR)param1.val.val64;
3113	break;
3114
3115	default:
3116	return VERR_EM_INTERPRETER;
3117	}
3118
3119	/** @todo is addr always a flat linear address or ds based
3120	* (in absence of segment override prefixes)????
3121	*/
3122	#ifdef IN_RC
3123	LogFlow(("RC: EMULATE: invlpg %RGv\n", addr));
3124	#endif
3125	rc = PGMInvalidatePage(pVCpu, addr);
3126	if ( rc == VINF_SUCCESS
3127	\|\| rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
3128	return VINF_SUCCESS;
3129	AssertMsgReturn(rc == VINF_EM_RAW_EMULATE_INSTR,
3130	("%Rrc addr=%RGv\n", VBOXSTRICTRC_VAL(rc), addr),
3131	VERR_EM_INTERPRETER);
3132	return rc;
3133	}
3134
3135	/** @todo change all these EMInterpretXXX methods to VBOXSTRICTRC. */
3136
3137	/**
3138	* CPUID Emulation.
3139	*/
3140	static int emInterpretCpuId(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3141	{
3142	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3143	int rc = EMInterpretCpuId(pVM, pVCpu, pRegFrame);
3144	return rc;
3145	}
3146
3147
3148	/**
3149	* CLTS Emulation.
3150	*/
3151	static int emInterpretClts(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3152	{
3153	NOREF(pVM); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3154
3155	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3156	if (!(cr0 & X86_CR0_TS))
3157	return VINF_SUCCESS;
3158	return CPUMSetGuestCR0(pVCpu, cr0 & ~X86_CR0_TS);
3159	}
3160
3161
3162	/**
3163	* Update CRx.
3164	*
3165	* @returns VBox status code.
3166	* @param pVM The cross context VM structure.
3167	* @param pVCpu The cross context virtual CPU structure.
3168	* @param pRegFrame The register frame.
3169	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
3170	* @param val New CRx value
3171	*
3172	*/
3173	static int emUpdateCRx(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
3174	{
3175	uint64_t oldval;
3176	uint64_t msrEFER;
3177	uint32_t fValid;
3178	int rc, rc2;
3179	NOREF(pVM);
3180
3181	/** @todo Clean up this mess. */
3182	LogFlow(("emInterpretCRxWrite at %RGv CR%d <- %RX64\n", (RTGCPTR)pRegFrame->rip, DestRegCrx, val));
3183	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3184	switch (DestRegCrx)
3185	{
3186	case DISCREG_CR0:
3187	oldval = CPUMGetGuestCR0(pVCpu);
3188	#ifdef IN_RC
3189	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
3190	if ( (val & (X86_CR0_WP \| X86_CR0_AM))
3191	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
3192	return VERR_EM_INTERPRETER;
3193	#endif
3194	rc = VINF_SUCCESS;
3195	#if !defined(VBOX_COMPARE_IEM_AND_EM) \|\| !defined(VBOX_COMPARE_IEM_LAST)
3196	CPUMSetGuestCR0(pVCpu, val);
3197	#else
3198	CPUMQueryGuestCtxPtr(pVCpu)->cr0 = val \| X86_CR0_ET;
3199	#endif
3200	val = CPUMGetGuestCR0(pVCpu);
3201	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
3202	!= (val & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
3203	{
3204	/* global flush */
3205	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
3206	AssertRCReturn(rc, rc);
3207	}
3208
3209	/* Deal with long mode enabling/disabling. */
3210	msrEFER = CPUMGetGuestEFER(pVCpu);
3211	if (msrEFER & MSR_K6_EFER_LME)
3212	{
3213	if ( !(oldval & X86_CR0_PG)
3214	&& (val & X86_CR0_PG))
3215	{
3216	/* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
3217	if (pRegFrame->cs.Attr.n.u1Long)
3218	{
3219	AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
3220	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
3221	}
3222
3223	/* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
3224	if (!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PAE))
3225	{
3226	AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
3227	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
3228	}
3229	msrEFER \|= MSR_K6_EFER_LMA;
3230	}
3231	else
3232	if ( (oldval & X86_CR0_PG)
3233	&& !(val & X86_CR0_PG))
3234	{
3235	msrEFER &= ~MSR_K6_EFER_LMA;
3236	/** @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
3237	}
3238	CPUMSetGuestEFER(pVCpu, msrEFER);
3239	}
3240	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
3241	return rc2 == VINF_SUCCESS ? rc : rc2;
3242
3243	case DISCREG_CR2:
3244	rc = CPUMSetGuestCR2(pVCpu, val); AssertRC(rc);
3245	return VINF_SUCCESS;
3246
3247	case DISCREG_CR3:
3248	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
3249	rc = CPUMSetGuestCR3(pVCpu, val); AssertRC(rc);
3250	if (CPUMGetGuestCR0(pVCpu) & X86_CR0_PG)
3251	{
3252	/* flush */
3253	rc = PGMFlushTLB(pVCpu, val, !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE));
3254	AssertRC(rc);
3255	}
3256	return rc;
3257
3258	case DISCREG_CR4:
3259	oldval = CPUMGetGuestCR4(pVCpu);
3260	rc = CPUMSetGuestCR4(pVCpu, val); AssertRC(rc);
3261	val = CPUMGetGuestCR4(pVCpu);
3262
3263	/* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
3264	msrEFER = CPUMGetGuestEFER(pVCpu);
3265	if ( (msrEFER & MSR_K6_EFER_LMA)
3266	&& (oldval & X86_CR4_PAE)
3267	&& !(val & X86_CR4_PAE))
3268	{
3269	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
3270	}
3271
3272	/* From IEM iemCImpl_load_CrX. */
3273	/** @todo Check guest CPUID bits for determining corresponding valid bits. */
3274	fValid = X86_CR4_VME \| X86_CR4_PVI
3275	\| X86_CR4_TSD \| X86_CR4_DE
3276	\| X86_CR4_PSE \| X86_CR4_PAE
3277	\| X86_CR4_MCE \| X86_CR4_PGE
3278	\| X86_CR4_PCE \| X86_CR4_OSFXSR
3279	\| X86_CR4_OSXMMEEXCPT;
3280	//if (xxx)
3281	// fValid \|= X86_CR4_VMXE;
3282	//if (xxx)
3283	// fValid \|= X86_CR4_OSXSAVE;
3284	if (val & ~(uint64_t)fValid)
3285	{
3286	Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", val, val & ~(uint64_t)fValid));
3287	return VERR_EM_INTERPRETER; /** @todo generate \#GP(0) */
3288	}
3289
3290	rc = VINF_SUCCESS;
3291	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
3292	!= (val & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
3293	{
3294	/* global flush */
3295	rc = PGMFlushTLB(pVCpu, CPUMGetGuestCR3(pVCpu), true /* global */);
3296	AssertRCReturn(rc, rc);
3297	}
3298
3299	/* Feeling extremely lazy. */
3300	# ifdef IN_RC
3301	if ( (oldval & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
3302	!= (val & (X86_CR4_OSFXSR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
3303	{
3304	Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
3305	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
3306	}
3307	# endif
3308	# ifdef VBOX_WITH_RAW_MODE
3309	if (((val ^ oldval) & X86_CR4_VME) && VM_IS_RAW_MODE_ENABLED(pVM))
3310	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
3311	# endif
3312
3313	rc2 = PGMChangeMode(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR4(pVCpu), CPUMGetGuestEFER(pVCpu));
3314	return rc2 == VINF_SUCCESS ? rc : rc2;
3315
3316	case DISCREG_CR8:
3317	return APICSetTpr(pVCpu, val << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
3318
3319	default:
3320	AssertFailed();
3321	case DISCREG_CR1: /* illegal op */
3322	break;
3323	}
3324	return VERR_EM_INTERPRETER;
3325	}
3326
3327
3328	/**
3329	* LMSW Emulation.
3330	*/
3331	static int emInterpretLmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3332	{
3333	DISQPVPARAMVAL param1;
3334	uint32_t val;
3335	NOREF(pvFault); NOREF(pcbSize);
3336	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3337
3338	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3339	if(RT_FAILURE(rc))
3340	return VERR_EM_INTERPRETER;
3341
3342	switch(param1.type)
3343	{
3344	case DISQPV_TYPE_IMMEDIATE:
3345	case DISQPV_TYPE_ADDRESS:
3346	if(!(param1.flags & DISQPV_FLAG_16))
3347	return VERR_EM_INTERPRETER;
3348	val = param1.val.val32;
3349	break;
3350
3351	default:
3352	return VERR_EM_INTERPRETER;
3353	}
3354
3355	LogFlow(("emInterpretLmsw %x\n", val));
3356	uint64_t OldCr0 = CPUMGetGuestCR0(pVCpu);
3357
3358	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
3359	uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
3360	\| (val & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
3361
3362	return emUpdateCRx(pVM, pVCpu, pRegFrame, DISCREG_CR0, NewCr0);
3363
3364	}
3365
3366	#ifdef EM_EMULATE_SMSW
3367	/**
3368	* SMSW Emulation.
3369	*/
3370	static int emInterpretSmsw(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3371	{
3372	NOREF(pvFault); NOREF(pcbSize);
3373	DISQPVPARAMVAL param1;
3374	uint64_t cr0 = CPUMGetGuestCR0(pVCpu);
3375
3376	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3377	if(RT_FAILURE(rc))
3378	return VERR_EM_INTERPRETER;
3379
3380	switch(param1.type)
3381	{
3382	case DISQPV_TYPE_IMMEDIATE:
3383	if(param1.size != sizeof(uint16_t))
3384	return VERR_EM_INTERPRETER;
3385	LogFlow(("emInterpretSmsw %d <- cr0 (%x)\n", pDis->Param1.Base.idxGenReg, cr0));
3386	rc = DISWriteReg16(pRegFrame, pDis->Param1.Base.idxGenReg, cr0);
3387	break;
3388
3389	case DISQPV_TYPE_ADDRESS:
3390	{
3391	RTGCPTR pParam1;
3392
3393	/* Actually forced to 16 bits regardless of the operand size. */
3394	if(param1.size != sizeof(uint16_t))
3395	return VERR_EM_INTERPRETER;
3396
3397	pParam1 = (RTGCPTR)param1.val.val64;
3398	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, pParam1);
3399	LogFlow(("emInterpretSmsw %RGv <- cr0 (%x)\n", pParam1, cr0));
3400
3401	rc = emRamWrite(pVM, pVCpu, pRegFrame, pParam1, &cr0, sizeof(uint16_t));
3402	if (RT_FAILURE(rc))
3403	{
3404	AssertMsgFailed(("emRamWrite %RGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3405	return VERR_EM_INTERPRETER;
3406	}
3407	break;
3408	}
3409
3410	default:
3411	return VERR_EM_INTERPRETER;
3412	}
3413
3414	LogFlow(("emInterpretSmsw %x\n", cr0));
3415	return rc;
3416	}
3417	#endif
3418
3419
3420	/**
3421	* Interpret CRx read.
3422	*
3423	* @returns VBox status code.
3424	* @param pVM The cross context VM structure.
3425	* @param pVCpu The cross context virtual CPU structure.
3426	* @param pRegFrame The register frame.
3427	* @param DestRegGen General purpose register index (USE_REG_E**))
3428	* @param SrcRegCrx CRx register index (DISUSE_REG_CR*)
3429	*
3430	*/
3431	static int emInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
3432	{
3433	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3434	uint64_t val64;
3435	int rc = CPUMGetGuestCRx(pVCpu, SrcRegCrx, &val64);
3436	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
3437	NOREF(pVM);
3438
3439	if (CPUMIsGuestIn64BitCode(pVCpu))
3440	rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
3441	else
3442	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
3443
3444	if (RT_SUCCESS(rc))
3445	{
3446	LogFlow(("MOV_CR: gen32=%d CR=%d val=%RX64\n", DestRegGen, SrcRegCrx, val64));
3447	return VINF_SUCCESS;
3448	}
3449	return VERR_EM_INTERPRETER;
3450	}
3451
3452
3453	/**
3454	* Interpret CRx write.
3455	*
3456	* @returns VBox status code.
3457	* @param pVM The cross context VM structure.
3458	* @param pVCpu The cross context virtual CPU structure.
3459	* @param pRegFrame The register frame.
3460	* @param DestRegCrx CRx register index (DISUSE_REG_CR*)
3461	* @param SrcRegGen General purpose register index (USE_REG_E**))
3462	*
3463	*/
3464	static int emInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
3465	{
3466	uint64_t val;
3467	int rc;
3468	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3469
3470	if (CPUMIsGuestIn64BitCode(pVCpu))
3471	rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
3472	else
3473	{
3474	uint32_t val32;
3475	rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
3476	val = val32;
3477	}
3478
3479	if (RT_SUCCESS(rc))
3480	return emUpdateCRx(pVM, pVCpu, pRegFrame, DestRegCrx, val);
3481
3482	return VERR_EM_INTERPRETER;
3483	}
3484
3485
3486	/**
3487	* MOV CRx
3488	*/
3489	static int emInterpretMovCRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3490	{
3491	NOREF(pvFault); NOREF(pcbSize);
3492	if ((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_CR)
3493	return emInterpretCRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxCtrlReg);
3494
3495	if (pDis->Param1.fUse == DISUSE_REG_CR && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3496	return emInterpretCRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxCtrlReg, pDis->Param2.Base.idxGenReg);
3497
3498	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
3499	}
3500
3501
3502	/**
3503	* MOV DRx
3504	*/
3505	static int emInterpretMovDRx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3506	{
3507	int rc = VERR_EM_INTERPRETER;
3508	NOREF(pvFault); NOREF(pcbSize);
3509
3510	if((pDis->Param1.fUse == DISUSE_REG_GEN32 \|\| pDis->Param1.fUse == DISUSE_REG_GEN64) && pDis->Param2.fUse == DISUSE_REG_DBG)
3511	{
3512	rc = EMInterpretDRxRead(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxGenReg, pDis->Param2.Base.idxDbgReg);
3513	}
3514	else
3515	if(pDis->Param1.fUse == DISUSE_REG_DBG && (pDis->Param2.fUse == DISUSE_REG_GEN32 \|\| pDis->Param2.fUse == DISUSE_REG_GEN64))
3516	{
3517	rc = EMInterpretDRxWrite(pVM, pVCpu, pRegFrame, pDis->Param1.Base.idxDbgReg, pDis->Param2.Base.idxGenReg);
3518	}
3519	else
3520	AssertMsgFailed(("Unexpected debug register move\n"));
3521
3522	return rc;
3523	}
3524
3525
3526	/**
3527	* LLDT Emulation.
3528	*/
3529	static int emInterpretLLdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3530	{
3531	DISQPVPARAMVAL param1;
3532	RTSEL sel;
3533	NOREF(pVM); NOREF(pvFault); NOREF(pcbSize);
3534
3535	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3536	if(RT_FAILURE(rc))
3537	return VERR_EM_INTERPRETER;
3538
3539	switch(param1.type)
3540	{
3541	case DISQPV_TYPE_ADDRESS:
3542	return VERR_EM_INTERPRETER; //feeling lazy right now
3543
3544	case DISQPV_TYPE_IMMEDIATE:
3545	if(!(param1.flags & DISQPV_FLAG_16))
3546	return VERR_EM_INTERPRETER;
3547	sel = (RTSEL)param1.val.val16;
3548	break;
3549
3550	default:
3551	return VERR_EM_INTERPRETER;
3552	}
3553
3554	#ifdef IN_RING0
3555	/* Only for the VT-x real-mode emulation case. */
3556	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3557	CPUMSetGuestLDTR(pVCpu, sel);
3558	return VINF_SUCCESS;
3559	#else
3560	if (sel == 0)
3561	{
3562	if (CPUMGetHyperLDTR(pVCpu) == 0)
3563	{
3564	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
3565	return VINF_SUCCESS;
3566	}
3567	}
3568	//still feeling lazy
3569	return VERR_EM_INTERPRETER;
3570	#endif
3571	}
3572
3573	#ifdef IN_RING0
3574	/**
3575	* LIDT/LGDT Emulation.
3576	*/
3577	static int emInterpretLIGdt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3578	{
3579	DISQPVPARAMVAL param1;
3580	RTGCPTR pParam1;
3581	X86XDTR32 dtr32;
3582	NOREF(pvFault); NOREF(pcbSize);
3583
3584	Log(("Emulate %s at %RGv\n", emGetMnemonic(pDis), (RTGCPTR)pRegFrame->rip));
3585
3586	/* Only for the VT-x real-mode emulation case. */
3587	AssertReturn(CPUMIsGuestInRealMode(pVCpu), VERR_EM_INTERPRETER);
3588
3589	int rc = DISQueryParamVal(pRegFrame, pDis, &pDis->Param1, &param1, DISQPVWHICH_SRC);
3590	if(RT_FAILURE(rc))
3591	return VERR_EM_INTERPRETER;
3592
3593	switch(param1.type)
3594	{
3595	case DISQPV_TYPE_ADDRESS:
3596	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pDis, &pDis->Param1, param1.val.val16);
3597	break;
3598
3599	default:
3600	return VERR_EM_INTERPRETER;
3601	}
3602
3603	rc = emRamRead(pVM, pVCpu, pRegFrame, &dtr32, pParam1, sizeof(dtr32));
3604	AssertRCReturn(rc, VERR_EM_INTERPRETER);
3605
3606	if (!(pDis->fPrefix & DISPREFIX_OPSIZE))
3607	dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
3608
3609	if (pDis->pCurInstr->uOpcode == OP_LIDT)
3610	CPUMSetGuestIDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3611	else
3612	CPUMSetGuestGDTR(pVCpu, dtr32.uAddr, dtr32.cb);
3613
3614	return VINF_SUCCESS;
3615	}
3616	#endif
3617
3618
3619	#ifdef IN_RC
3620	/**
3621	* STI Emulation.
3622	*
3623	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
3624	*/
3625	static int emInterpretSti(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3626	{
3627	NOREF(pcbSize);
3628	PPATMGCSTATE pGCState = PATMGetGCState(pVM);
3629
3630	if(!pGCState)
3631	{
3632	Assert(pGCState);
3633	return VERR_EM_INTERPRETER;
3634	}
3635	pGCState->uVMFlags \|= X86_EFL_IF;
3636
3637	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
3638	Assert(pvFault == SELMToFlat(pVM, DISSELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
3639
3640	pVCpu->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pDis->cbInstr;
3641	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3642
3643	return VINF_SUCCESS;
3644	}
3645	#endif /* IN_RC */
3646
3647
3648	/**
3649	* HLT Emulation.
3650	*/
3651	static VBOXSTRICTRC
3652	emInterpretHlt(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3653	{
3654	NOREF(pVM); NOREF(pVCpu); NOREF(pDis); NOREF(pRegFrame); NOREF(pvFault); NOREF(pcbSize);
3655	return VINF_EM_HALT;
3656	}
3657
3658
3659	/**
3660	* RDTSC Emulation.
3661	*/
3662	static int emInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3663	{
3664	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3665	return EMInterpretRdtsc(pVM, pVCpu, pRegFrame);
3666	}
3667
3668	/**
3669	* RDPMC Emulation
3670	*/
3671	static int emInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3672	{
3673	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3674	return EMInterpretRdpmc(pVM, pVCpu, pRegFrame);
3675	}
3676
3677
3678	static int emInterpretMonitor(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3679	{
3680	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3681	return EMInterpretMonitor(pVM, pVCpu, pRegFrame);
3682	}
3683
3684
3685	static VBOXSTRICTRC emInterpretMWait(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3686	{
3687	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3688	return EMInterpretMWait(pVM, pVCpu, pRegFrame);
3689	}
3690
3691
3692	/**
3693	* RDMSR Emulation.
3694	*/
3695	static int emInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3696	{
3697	/* Note: The Intel manual claims there's a REX version of RDMSR that's slightly
3698	different, so we play safe by completely disassembling the instruction. */
3699	Assert(!(pDis->fPrefix & DISPREFIX_REX));
3700	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3701	return EMInterpretRdmsr(pVM, pVCpu, pRegFrame);
3702	}
3703
3704
3705	/**
3706	* WRMSR Emulation.
3707	*/
3708	static int emInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3709	{
3710	NOREF(pDis); NOREF(pvFault); NOREF(pcbSize);
3711	return EMInterpretWrmsr(pVM, pVCpu, pRegFrame);
3712	}
3713
3714
3715	/**
3716	* Internal worker.
3717	* @copydoc emInterpretInstructionCPUOuter
3718	* @param pVM The cross context VM structure.
3719	*/
3720	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
3721	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
3722	{
3723	Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
3724	Assert(enmCodeType == EMCODETYPE_SUPERVISOR \|\| enmCodeType == EMCODETYPE_ALL);
3725	Assert(pcbSize);
3726	*pcbSize = 0;
3727
3728	if (enmCodeType == EMCODETYPE_SUPERVISOR)
3729	{
3730	/*
3731	* Only supervisor guest code!!
3732	* And no complicated prefixes.
3733	*/
3734	/* Get the current privilege level. */
3735	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
3736	#ifdef VBOX_WITH_RAW_RING1
3737	if ( !EMIsRawRing1Enabled(pVM)
3738	\|\| cpl > 1
3739	\|\| pRegFrame->eflags.Bits.u2IOPL > cpl
3740	)
3741	#endif
3742	{
3743	if ( cpl != 0
3744	&& pDis->pCurInstr->uOpcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
3745	{
3746	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
3747	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
3748	return VERR_EM_INTERPRETER;
3749	}
3750	}
3751	}
3752	else
3753	Log2(("emInterpretInstructionCPU allowed to interpret user-level code!!\n"));
3754
3755	#ifdef IN_RC
3756	if ( (pDis->fPrefix & (DISPREFIX_REPNE \| DISPREFIX_REP))
3757	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3758	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3759	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3760	&& pDis->pCurInstr->uOpcode != OP_XADD
3761	&& pDis->pCurInstr->uOpcode != OP_OR
3762	&& pDis->pCurInstr->uOpcode != OP_AND
3763	&& pDis->pCurInstr->uOpcode != OP_XOR
3764	&& pDis->pCurInstr->uOpcode != OP_BTR
3765	)
3766	)
3767	#else
3768	if ( (pDis->fPrefix & DISPREFIX_REPNE)
3769	\|\| ( (pDis->fPrefix & DISPREFIX_REP)
3770	&& pDis->pCurInstr->uOpcode != OP_STOSWD
3771	)
3772	\|\| ( (pDis->fPrefix & DISPREFIX_LOCK)
3773	&& pDis->pCurInstr->uOpcode != OP_OR
3774	&& pDis->pCurInstr->uOpcode != OP_AND
3775	&& pDis->pCurInstr->uOpcode != OP_XOR
3776	&& pDis->pCurInstr->uOpcode != OP_BTR
3777	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG
3778	&& pDis->pCurInstr->uOpcode != OP_CMPXCHG8B
3779	)
3780	)
3781	#endif
3782	{
3783	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
3784	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
3785	Log4(("EM: Refuse %u on REP/REPNE/LOCK prefix grounds\n", pDis->pCurInstr->uOpcode));
3786	return VERR_EM_INTERPRETER;
3787	}
3788
3789	#if HC_ARCH_BITS == 32
3790	/*
3791	* Unable to emulate most >4 bytes accesses in 32 bits mode.
3792	* Whitelisted instructions are safe.
3793	*/
3794	if ( pDis->Param1.cb > 4
3795	&& CPUMIsGuestIn64BitCode(pVCpu))
3796	{
3797	uint32_t uOpCode = pDis->pCurInstr->uOpcode;
3798	if ( uOpCode != OP_STOSWD
3799	&& uOpCode != OP_MOV
3800	&& uOpCode != OP_CMPXCHG8B
3801	&& uOpCode != OP_XCHG
3802	&& uOpCode != OP_BTS
3803	&& uOpCode != OP_BTR
3804	&& uOpCode != OP_BTC
3805	)
3806	{
3807	# ifdef VBOX_WITH_STATISTICS
3808	switch (pDis->pCurInstr->uOpcode)
3809	{
3810	# define INTERPRET_FAILED_CASE(opcode, Instr) \
3811	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); break;
3812	INTERPRET_FAILED_CASE(OP_XCHG,Xchg);
3813	INTERPRET_FAILED_CASE(OP_DEC,Dec);
3814	INTERPRET_FAILED_CASE(OP_INC,Inc);
3815	INTERPRET_FAILED_CASE(OP_POP,Pop);
3816	INTERPRET_FAILED_CASE(OP_OR, Or);
3817	INTERPRET_FAILED_CASE(OP_XOR,Xor);
3818	INTERPRET_FAILED_CASE(OP_AND,And);
3819	INTERPRET_FAILED_CASE(OP_MOV,Mov);
3820	INTERPRET_FAILED_CASE(OP_STOSWD,StosWD);
3821	INTERPRET_FAILED_CASE(OP_INVLPG,InvlPg);
3822	INTERPRET_FAILED_CASE(OP_CPUID,CpuId);
3823	INTERPRET_FAILED_CASE(OP_MOV_CR,MovCRx);
3824	INTERPRET_FAILED_CASE(OP_MOV_DR,MovDRx);
3825	INTERPRET_FAILED_CASE(OP_LLDT,LLdt);
3826	INTERPRET_FAILED_CASE(OP_LIDT,LIdt);
3827	INTERPRET_FAILED_CASE(OP_LGDT,LGdt);
3828	INTERPRET_FAILED_CASE(OP_LMSW,Lmsw);
3829	INTERPRET_FAILED_CASE(OP_CLTS,Clts);
3830	INTERPRET_FAILED_CASE(OP_MONITOR,Monitor);
3831	INTERPRET_FAILED_CASE(OP_MWAIT,MWait);
3832	INTERPRET_FAILED_CASE(OP_RDMSR,Rdmsr);
3833	INTERPRET_FAILED_CASE(OP_WRMSR,Wrmsr);
3834	INTERPRET_FAILED_CASE(OP_ADD,Add);
3835	INTERPRET_FAILED_CASE(OP_SUB,Sub);
3836	INTERPRET_FAILED_CASE(OP_ADC,Adc);
3837	INTERPRET_FAILED_CASE(OP_BTR,Btr);
3838	INTERPRET_FAILED_CASE(OP_BTS,Bts);
3839	INTERPRET_FAILED_CASE(OP_BTC,Btc);
3840	INTERPRET_FAILED_CASE(OP_RDTSC,Rdtsc);
3841	INTERPRET_FAILED_CASE(OP_CMPXCHG, CmpXchg);
3842	INTERPRET_FAILED_CASE(OP_STI, Sti);
3843	INTERPRET_FAILED_CASE(OP_XADD,XAdd);
3844	INTERPRET_FAILED_CASE(OP_CMPXCHG8B,CmpXchg8b);
3845	INTERPRET_FAILED_CASE(OP_HLT, Hlt);
3846	INTERPRET_FAILED_CASE(OP_IRET,Iret);
3847	INTERPRET_FAILED_CASE(OP_WBINVD,WbInvd);
3848	INTERPRET_FAILED_CASE(OP_MOVNTPS,MovNTPS);
3849	# undef INTERPRET_FAILED_CASE
3850	default:
3851	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3852	break;
3853	}
3854	# endif /* VBOX_WITH_STATISTICS */
3855	Log4(("EM: Refuse %u on grounds of accessing %u bytes\n", pDis->pCurInstr->uOpcode, pDis->Param1.cb));
3856	return VERR_EM_INTERPRETER;
3857	}
3858	}
3859	#endif
3860
3861	VBOXSTRICTRC rc;
3862	#if (defined(VBOX_STRICT) \|\| defined(LOG_ENABLED))
3863	LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pDis)));
3864	#endif
3865	switch (pDis->pCurInstr->uOpcode)
3866	{
3867	/*
3868	* Macros for generating the right case statements.
3869	*/
3870	# ifndef VBOX_COMPARE_IEM_AND_EM
3871	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3872	case opcode:\
3873	if (pDis->fPrefix & DISPREFIX_LOCK) \
3874	rc = emInterpretLock##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
3875	else \
3876	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3877	if (RT_SUCCESS(rc)) \
3878	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3879	else \
3880	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3881	return rc
3882	# else /* VBOX_COMPARE_IEM_AND_EM */
3883	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3884	case opcode:\
3885	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3886	if (RT_SUCCESS(rc)) \
3887	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3888	else \
3889	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3890	return rc
3891	# endif /* VBOX_COMPARE_IEM_AND_EM */
3892
3893	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
3894	case opcode:\
3895	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize, pfnEmulate); \
3896	if (RT_SUCCESS(rc)) \
3897	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3898	else \
3899	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3900	return rc
3901
3902	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
3903	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
3904	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
3905	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
3906
3907	#define INTERPRET_CASE(opcode, Instr) \
3908	case opcode:\
3909	rc = emInterpret##Instr(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3910	if (RT_SUCCESS(rc)) \
3911	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3912	else \
3913	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3914	return rc
3915
3916	#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
3917	case opcode:\
3918	rc = emInterpret##InstrFn(pVM, pVCpu, pDis, pRegFrame, pvFault, pcbSize); \
3919	if (RT_SUCCESS(rc)) \
3920	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
3921	else \
3922	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3923	return rc
3924
3925	#define INTERPRET_STAT_CASE(opcode, Instr) \
3926	case opcode: STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
3927
3928	/*
3929	* The actual case statements.
3930	*/
3931	INTERPRET_CASE(OP_XCHG,Xchg);
3932	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
3933	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
3934	INTERPRET_CASE(OP_POP,Pop);
3935	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
3936	INTERPRET_CASE_EX_LOCK_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor, EMEmulateLockXor);
3937	INTERPRET_CASE_EX_LOCK_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd, EMEmulateLockAnd);
3938	INTERPRET_CASE(OP_MOV,Mov);
3939	#ifndef IN_RC
3940	INTERPRET_CASE(OP_STOSWD,StosWD);
3941	#endif
3942	INTERPRET_CASE(OP_INVLPG,InvlPg);
3943	INTERPRET_CASE(OP_CPUID,CpuId);
3944	INTERPRET_CASE(OP_MOV_CR,MovCRx);
3945	INTERPRET_CASE(OP_MOV_DR,MovDRx);
3946	#ifdef IN_RING0
3947	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
3948	INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
3949	#endif
3950	INTERPRET_CASE(OP_LLDT,LLdt);
3951	INTERPRET_CASE(OP_LMSW,Lmsw);
3952	#ifdef EM_EMULATE_SMSW
3953	INTERPRET_CASE(OP_SMSW,Smsw);
3954	#endif
3955	INTERPRET_CASE(OP_CLTS,Clts);
3956	INTERPRET_CASE(OP_MONITOR, Monitor);
3957	INTERPRET_CASE(OP_MWAIT, MWait);
3958	INTERPRET_CASE(OP_RDMSR, Rdmsr);
3959	INTERPRET_CASE(OP_WRMSR, Wrmsr);
3960	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
3961	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
3962	INTERPRET_CASE(OP_ADC,Adc);
3963	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
3964	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
3965	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
3966	INTERPRET_CASE(OP_RDPMC,Rdpmc);
3967	INTERPRET_CASE(OP_RDTSC,Rdtsc);
3968	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
3969	#ifdef IN_RC
3970	INTERPRET_CASE(OP_STI,Sti);
3971	INTERPRET_CASE(OP_XADD, XAdd);
3972	INTERPRET_CASE(OP_IRET,Iret);
3973	#endif
3974	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
3975	INTERPRET_CASE(OP_HLT,Hlt);
3976	INTERPRET_CASE(OP_WBINVD,WbInvd);
3977	#ifdef VBOX_WITH_STATISTICS
3978	# ifndef IN_RC
3979	INTERPRET_STAT_CASE(OP_XADD, XAdd);
3980	# endif
3981	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
3982	#endif
3983
3984	default:
3985	Log3(("emInterpretInstructionCPU: opcode=%d\n", pDis->pCurInstr->uOpcode));
3986	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
3987	return VERR_EM_INTERPRETER;
3988
3989	#undef INTERPRET_CASE_EX_PARAM2
3990	#undef INTERPRET_STAT_CASE
3991	#undef INTERPRET_CASE_EX
3992	#undef INTERPRET_CASE
3993	} /* switch (opcode) */
3994	/* not reached */
3995	}
3996
3997	/**
3998	* Interprets the current instruction using the supplied DISCPUSTATE structure.
3999	*
4000	* EIP is NOT updated!
4001	*
4002	* @returns VBox strict status code.
4003	* @retval VINF_* Scheduling instructions. When these are returned, it
4004	* starts to get a bit tricky to know whether code was
4005	* executed or not... We'll address this when it becomes a problem.
4006	* @retval VERR_EM_INTERPRETER Something we can't cope with.
4007	* @retval VERR_* Fatal errors.
4008	*
4009	* @param pVCpu The cross context virtual CPU structure.
4010	* @param pDis The disassembler cpu state for the instruction to be
4011	* interpreted.
4012	* @param pRegFrame The register frame. EIP is NOT changed!
4013	* @param pvFault The fault address (CR2).
4014	* @param pcbSize Size of the write (if applicable).
4015	* @param enmCodeType Code type (user/supervisor)
4016	*
4017	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
4018	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
4019	* to worry about e.g. invalid modrm combinations (!)
4020	*
4021	* @todo At this time we do NOT check if the instruction overwrites vital information.
4022	* Make sure this can't happen!! (will add some assertions/checks later)
4023	*/
4024	DECLINLINE(VBOXSTRICTRC) emInterpretInstructionCPUOuter(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
4025	RTGCPTR pvFault, EMCODETYPE enmCodeType, uint32_t *pcbSize)
4026	{
4027	STAM_PROFILE_START(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
4028	VBOXSTRICTRC rc = emInterpretInstructionCPU(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, pRegFrame, pvFault, enmCodeType, pcbSize);
4029	STAM_PROFILE_STOP(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
4030	if (RT_SUCCESS(rc))
4031	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
4032	else
4033	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
4034	return rc;
4035	}
4036
4037
4038	#endif /* !VBOX_WITH_IEM */

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 71417

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