VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 75819

Last change on this file since 75819 was 75646, checked in by vboxsync, 6 years ago

VMM: HLT/MWAIT optimizations for busy guests: don't go back to ring-3 just to call GVMMR0SchedHalt(), do the first call in ring-0. This saves a reduces interrupt latency for some workloads. bugref:9172
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File size: 54.8 KB
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1/* $Id: EMAll.cpp 75646 2018-11-21 15:38:10Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor(/Manager) - All contexts
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/selm.h>
26#include <VBox/vmm/patm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/iem.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/hm.h>
31#include <VBox/vmm/pdmapi.h>
32#include <VBox/vmm/vmm.h>
33#include <VBox/vmm/stam.h>
34#include "EMInternal.h"
35#include <VBox/vmm/vm.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/dis.h>
39#include <VBox/disopcode.h>
40#include <VBox/log.h>
41#include <iprt/assert.h>
42#include <iprt/string.h>
43
44
45
46
47/**
48 * Get the current execution manager status.
49 *
50 * @returns Current status.
51 * @param pVCpu The cross context virtual CPU structure.
52 */
53VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
54{
55 return pVCpu->em.s.enmState;
56}
57
58
59/**
60 * Sets the current execution manager status. (use only when you know what you're doing!)
61 *
62 * @param pVCpu The cross context virtual CPU structure.
63 * @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
64 */
65VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
66{
67 /* Only allowed combination: */
68 Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
69 pVCpu->em.s.enmState = enmNewState;
70}
71
72
73/**
74 * Sets the PC for which interrupts should be inhibited.
75 *
76 * @param pVCpu The cross context virtual CPU structure.
77 * @param PC The PC.
78 */
79VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
80{
81 pVCpu->em.s.GCPtrInhibitInterrupts = PC;
82 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
83}
84
85
86/**
87 * Gets the PC for which interrupts should be inhibited.
88 *
89 * There are a few instructions which inhibits or delays interrupts
90 * for the instruction following them. These instructions are:
91 * - STI
92 * - MOV SS, r/m16
93 * - POP SS
94 *
95 * @returns The PC for which interrupts should be inhibited.
96 * @param pVCpu The cross context virtual CPU structure.
97 *
98 */
99VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
100{
101 return pVCpu->em.s.GCPtrInhibitInterrupts;
102}
103
104
105/**
106 * Checks if interrupt inhibiting is enabled for the current instruction.
107 *
108 * @returns true if interrupts are inhibited, false if not.
109 * @param pVCpu The cross context virtual CPU structure.
110 */
111VMMDECL(bool) EMIsInhibitInterruptsActive(PVMCPU pVCpu)
112{
113 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
114 return false;
115 if (pVCpu->em.s.GCPtrInhibitInterrupts == CPUMGetGuestRIP(pVCpu))
116 return true;
117 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
118 return false;
119}
120
121
122/**
123 * Enables / disable hypercall instructions.
124 *
125 * This interface is used by GIM to tell the execution monitors whether the
126 * hypercall instruction (VMMCALL & VMCALL) are allowed or should \#UD.
127 *
128 * @param pVCpu The cross context virtual CPU structure this applies to.
129 * @param fEnabled Whether hypercall instructions are enabled (true) or not.
130 */
131VMMDECL(void) EMSetHypercallInstructionsEnabled(PVMCPU pVCpu, bool fEnabled)
132{
133 pVCpu->em.s.fHypercallEnabled = fEnabled;
134}
135
136
137/**
138 * Checks if hypercall instructions (VMMCALL & VMCALL) are enabled or not.
139 *
140 * @returns true if enabled, false if not.
141 * @param pVCpu The cross context virtual CPU structure.
142 *
143 * @note If this call becomes a performance factor, we can make the data
144 * field available thru a read-only view in VMCPU. See VM::cpum.ro.
145 */
146VMMDECL(bool) EMAreHypercallInstructionsEnabled(PVMCPU pVCpu)
147{
148 return pVCpu->em.s.fHypercallEnabled;
149}
150
151
152/**
153 * Prepare an MWAIT - essentials of the MONITOR instruction.
154 *
155 * @returns VINF_SUCCESS
156 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
157 * @param rax The content of RAX.
158 * @param rcx The content of RCX.
159 * @param rdx The content of RDX.
160 * @param GCPhys The physical address corresponding to rax.
161 */
162VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
163{
164 pVCpu->em.s.MWait.uMonitorRAX = rax;
165 pVCpu->em.s.MWait.uMonitorRCX = rcx;
166 pVCpu->em.s.MWait.uMonitorRDX = rdx;
167 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_MONITOR_ACTIVE;
168 /** @todo Make use of GCPhys. */
169 NOREF(GCPhys);
170 /** @todo Complete MONITOR implementation. */
171 return VINF_SUCCESS;
172}
173
174
175/**
176 * Checks if the monitor hardware is armed / active.
177 *
178 * @returns true if armed, false otherwise.
179 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
180 */
181VMM_INT_DECL(bool) EMMonitorIsArmed(PVMCPU pVCpu)
182{
183 return RT_BOOL(pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_MONITOR_ACTIVE);
184}
185
186
187/**
188 * Checks if we're in a MWAIT.
189 *
190 * @retval 1 if regular,
191 * @retval > 1 if MWAIT with EMMWAIT_FLAG_BREAKIRQIF0
192 * @retval 0 if not armed
193 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
194 */
195VMM_INT_DECL(unsigned) EMMonitorWaitIsActive(PVMCPU pVCpu)
196{
197 uint32_t fWait = pVCpu->em.s.MWait.fWait;
198 AssertCompile(EMMWAIT_FLAG_ACTIVE == 1);
199 AssertCompile(EMMWAIT_FLAG_BREAKIRQIF0 == 2);
200 AssertCompile((EMMWAIT_FLAG_ACTIVE << 1) == EMMWAIT_FLAG_BREAKIRQIF0);
201 return fWait & (EMMWAIT_FLAG_ACTIVE | ((fWait & EMMWAIT_FLAG_ACTIVE) << 1));
202}
203
204
205/**
206 * Performs an MWAIT.
207 *
208 * @returns VINF_SUCCESS
209 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
210 * @param rax The content of RAX.
211 * @param rcx The content of RCX.
212 */
213VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
214{
215 pVCpu->em.s.MWait.uMWaitRAX = rax;
216 pVCpu->em.s.MWait.uMWaitRCX = rcx;
217 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_ACTIVE;
218 if (rcx)
219 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_BREAKIRQIF0;
220 else
221 pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
222 /** @todo not completely correct?? */
223 return VINF_EM_HALT;
224}
225
226
227/**
228 * Clears any address-range monitoring that is active.
229 *
230 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
231 */
232VMM_INT_DECL(void) EMMonitorWaitClear(PVMCPU pVCpu)
233{
234 LogFlowFunc(("Clearing MWAIT\n"));
235 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
236}
237
238
239/**
240 * Determine if we should continue execution in HM after encountering an mwait
241 * instruction.
242 *
243 * Clears MWAIT flags if returning @c true.
244 *
245 * @returns true if we should continue, false if we should halt.
246 * @param pVCpu The cross context virtual CPU structure.
247 * @param pCtx Current CPU context.
248 */
249VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
250{
251 if ( pCtx->eflags.Bits.u1IF
252 || ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
253 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) )
254 {
255 if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)))
256 {
257 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
258 return true;
259 }
260 }
261
262 return false;
263}
264
265
266/**
267 * Determine if we should continue execution in HM after encountering a hlt
268 * instruction.
269 *
270 * @returns true if we should continue, false if we should halt.
271 * @param pVCpu The cross context virtual CPU structure.
272 * @param pCtx Current CPU context.
273 */
274VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
275{
276 /** @todo Shouldn't we be checking GIF here? */
277 if (pCtx->eflags.Bits.u1IF)
278 return VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC));
279 return false;
280}
281
282
283/**
284 * Unhalts and wakes up the given CPU.
285 *
286 * This is an API for assisting the KVM hypercall API in implementing KICK_CPU.
287 * It sets VMCPU_FF_UNHALT for @a pVCpuDst and makes sure it is woken up. If
288 * the CPU isn't currently in a halt, the next HLT instruction it executes will
289 * be affected.
290 *
291 * @returns GVMMR0SchedWakeUpEx result or VINF_SUCCESS depending on context.
292 * @param pVM The cross context VM structure.
293 * @param pVCpuDst The cross context virtual CPU structure of the
294 * CPU to unhalt and wake up. This is usually not the
295 * same as the caller.
296 * @thread EMT
297 */
298VMM_INT_DECL(int) EMUnhaltAndWakeUp(PVM pVM, PVMCPU pVCpuDst)
299{
300 /*
301 * Flag the current(/next) HLT to unhalt immediately.
302 */
303 VMCPU_FF_SET(pVCpuDst, VMCPU_FF_UNHALT);
304
305 /*
306 * Wake up the EMT (technically should be abstracted by VMM/VMEmt, but
307 * just do it here for now).
308 */
309#ifdef IN_RING0
310 /* We might be here with preemption disabled or enabled (i.e. depending on
311 thread-context hooks being used), so don't try obtaining the GVMMR0 used
312 lock here. See @bugref{7270#c148}. */
313 int rc = GVMMR0SchedWakeUpNoGVMNoLock(pVM, pVCpuDst->idCpu);
314 AssertRC(rc);
315
316#elif defined(IN_RING3)
317 int rc = SUPR3CallVMMR0(pVM->pVMR0, pVCpuDst->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL /* pvArg */);
318 AssertRC(rc);
319
320#else
321 /* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
322 Assert(pVM->cCpus == 1); NOREF(pVM);
323 int rc = VINF_SUCCESS;
324#endif
325 return rc;
326}
327
328#ifndef IN_RING3
329
330/**
331 * Makes an I/O port write pending for ring-3 processing.
332 *
333 * @returns VINF_EM_PENDING_R3_IOPORT_READ
334 * @param pVCpu The cross context virtual CPU structure.
335 * @param uPort The I/O port.
336 * @param cbInstr The instruction length (for RIP updating).
337 * @param cbValue The write size.
338 * @param uValue The value being written.
339 * @sa emR3ExecutePendingIoPortWrite
340 *
341 * @note Must not be used when I/O port breakpoints are pending or when single stepping.
342 */
343VMMRZ_INT_DECL(VBOXSTRICTRC)
344EMRZSetPendingIoPortWrite(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue, uint32_t uValue)
345{
346 Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
347 pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
348 pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
349 pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
350 pVCpu->em.s.PendingIoPortAccess.uValue = uValue;
351 return VINF_EM_PENDING_R3_IOPORT_WRITE;
352}
353
354
355/**
356 * Makes an I/O port read pending for ring-3 processing.
357 *
358 * @returns VINF_EM_PENDING_R3_IOPORT_READ
359 * @param pVCpu The cross context virtual CPU structure.
360 * @param uPort The I/O port.
361 * @param cbInstr The instruction length (for RIP updating).
362 * @param cbValue The read size.
363 * @sa emR3ExecutePendingIoPortRead
364 *
365 * @note Must not be used when I/O port breakpoints are pending or when single stepping.
366 */
367VMMRZ_INT_DECL(VBOXSTRICTRC)
368EMRZSetPendingIoPortRead(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue)
369{
370 Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
371 pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
372 pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
373 pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
374 pVCpu->em.s.PendingIoPortAccess.uValue = UINT32_C(0x52454144); /* 'READ' */
375 return VINF_EM_PENDING_R3_IOPORT_READ;
376}
377
378#endif /* IN_RING3 */
379
380
381/**
382 * Worker for EMHistoryExec that checks for ring-3 returns and flags
383 * continuation of the EMHistoryExec run there.
384 */
385DECL_FORCE_INLINE(void) emHistoryExecSetContinueExitRecIdx(PVMCPU pVCpu, VBOXSTRICTRC rcStrict, PCEMEXITREC pExitRec)
386{
387 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
388#ifdef IN_RING3
389 RT_NOREF_PV(rcStrict); RT_NOREF_PV(pExitRec);
390#else
391 switch (VBOXSTRICTRC_VAL(rcStrict))
392 {
393 case VINF_SUCCESS:
394 default:
395 break;
396
397 /*
398 * Only status codes that EMHandleRCTmpl.h will resume EMHistoryExec with.
399 */
400 case VINF_IOM_R3_IOPORT_READ: /* -> emR3ExecuteIOInstruction */
401 case VINF_IOM_R3_IOPORT_WRITE: /* -> emR3ExecuteIOInstruction */
402 case VINF_IOM_R3_IOPORT_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
403 case VINF_IOM_R3_MMIO_READ: /* -> emR3ExecuteInstruction */
404 case VINF_IOM_R3_MMIO_WRITE: /* -> emR3ExecuteInstruction */
405 case VINF_IOM_R3_MMIO_READ_WRITE: /* -> emR3ExecuteInstruction */
406 case VINF_IOM_R3_MMIO_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
407 case VINF_CPUM_R3_MSR_READ: /* -> emR3ExecuteInstruction */
408 case VINF_CPUM_R3_MSR_WRITE: /* -> emR3ExecuteInstruction */
409 case VINF_GIM_R3_HYPERCALL: /* -> emR3ExecuteInstruction */
410 pVCpu->em.s.idxContinueExitRec = (uint16_t)(pExitRec - &pVCpu->em.s.aExitRecords[0]);
411 break;
412 }
413#endif /* !IN_RING3 */
414}
415
416#ifndef IN_RC
417
418/**
419 * Execute using history.
420 *
421 * This function will be called when EMHistoryAddExit() and friends returns a
422 * non-NULL result. This happens in response to probing or when probing has
423 * uncovered adjacent exits which can more effectively be reached by using IEM
424 * than restarting execution using the main execution engine and fielding an
425 * regular exit.
426 *
427 * @returns VBox strict status code, see IEMExecForExits.
428 * @param pVCpu The cross context virtual CPU structure.
429 * @param pExitRec The exit record return by a previous history add
430 * or update call.
431 * @param fWillExit Flags indicating to IEM what will cause exits, TBD.
432 */
433VMM_INT_DECL(VBOXSTRICTRC) EMHistoryExec(PVMCPU pVCpu, PCEMEXITREC pExitRec, uint32_t fWillExit)
434{
435 Assert(pExitRec);
436 VMCPU_ASSERT_EMT(pVCpu);
437 IEMEXECFOREXITSTATS ExecStats;
438 switch (pExitRec->enmAction)
439 {
440 /*
441 * Executes multiple instruction stopping only when we've gone a given
442 * number without perceived exits.
443 */
444 case EMEXITACTION_EXEC_WITH_MAX:
445 {
446 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryExec, a);
447 LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %RX64, max %u\n", pExitRec->uFlatPC, pExitRec->cMaxInstructionsWithoutExit));
448 VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
449 pExitRec->cMaxInstructionsWithoutExit /* cMinInstructions*/,
450 pVCpu->em.s.cHistoryExecMaxInstructions,
451 pExitRec->cMaxInstructionsWithoutExit,
452 &ExecStats);
453 LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
454 VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
455 emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRec);
456
457 /* Ignore instructions IEM doesn't know about. */
458 if ( ( rcStrict != VERR_IEM_INSTR_NOT_IMPLEMENTED
459 && rcStrict != VERR_IEM_ASPECT_NOT_IMPLEMENTED)
460 || ExecStats.cInstructions == 0)
461 { /* likely */ }
462 else
463 rcStrict = VINF_SUCCESS;
464
465 if (ExecStats.cExits > 1)
466 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecSavedExits, ExecStats.cExits - 1);
467 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecInstructions, ExecStats.cInstructions);
468 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryExec, a);
469 return rcStrict;
470 }
471
472 /*
473 * Probe a exit for close by exits.
474 */
475 case EMEXITACTION_EXEC_PROBE:
476 {
477 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryProbe, b);
478 LogFlow(("EMHistoryExec/EXEC_PROBE: %RX64\n", pExitRec->uFlatPC));
479 PEMEXITREC pExitRecUnconst = (PEMEXITREC)pExitRec;
480 VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
481 pVCpu->em.s.cHistoryProbeMinInstructions,
482 pVCpu->em.s.cHistoryExecMaxInstructions,
483 pVCpu->em.s.cHistoryProbeMaxInstructionsWithoutExit,
484 &ExecStats);
485 LogFlow(("EMHistoryExec/EXEC_PROBE: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
486 VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
487 emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRecUnconst);
488 if ( ExecStats.cExits >= 2
489 && RT_SUCCESS(rcStrict))
490 {
491 Assert(ExecStats.cMaxExitDistance > 0 && ExecStats.cMaxExitDistance <= 32);
492 pExitRecUnconst->cMaxInstructionsWithoutExit = ExecStats.cMaxExitDistance;
493 pExitRecUnconst->enmAction = EMEXITACTION_EXEC_WITH_MAX;
494 LogFlow(("EMHistoryExec/EXEC_PROBE: -> EXEC_WITH_MAX %u\n", ExecStats.cMaxExitDistance));
495 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedExecWithMax);
496 }
497#ifndef IN_RING3
498 else if ( pVCpu->em.s.idxContinueExitRec != UINT16_MAX
499 && RT_SUCCESS(rcStrict))
500 {
501 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedToRing3);
502 LogFlow(("EMHistoryExec/EXEC_PROBE: -> ring-3\n"));
503 }
504#endif
505 else
506 {
507 pExitRecUnconst->enmAction = EMEXITACTION_NORMAL_PROBED;
508 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
509 LogFlow(("EMHistoryExec/EXEC_PROBE: -> PROBED\n"));
510 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedNormal);
511 if ( rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED
512 || rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
513 rcStrict = VINF_SUCCESS;
514 }
515 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryProbeInstructions, ExecStats.cInstructions);
516 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryProbe, b);
517 return rcStrict;
518 }
519
520 /* We shouldn't ever see these here! */
521 case EMEXITACTION_FREE_RECORD:
522 case EMEXITACTION_NORMAL:
523 case EMEXITACTION_NORMAL_PROBED:
524 break;
525
526 /* No default case, want compiler warnings. */
527 }
528 AssertLogRelFailedReturn(VERR_EM_INTERNAL_ERROR);
529}
530
531
532/**
533 * Worker for emHistoryAddOrUpdateRecord.
534 */
535DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInit(PEMEXITREC pExitRec, uint64_t uFlatPC, uint32_t uFlagsAndType, uint64_t uExitNo)
536{
537 pExitRec->uFlatPC = uFlatPC;
538 pExitRec->uFlagsAndType = uFlagsAndType;
539 pExitRec->enmAction = EMEXITACTION_NORMAL;
540 pExitRec->bUnused = 0;
541 pExitRec->cMaxInstructionsWithoutExit = 64;
542 pExitRec->uLastExitNo = uExitNo;
543 pExitRec->cHits = 1;
544 return NULL;
545}
546
547
548/**
549 * Worker for emHistoryAddOrUpdateRecord.
550 */
551DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitNew(PVMCPU pVCpu, PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
552 PEMEXITREC pExitRec, uint64_t uFlatPC,
553 uint32_t uFlagsAndType, uint64_t uExitNo)
554{
555 pHistEntry->idxSlot = (uint32_t)idxSlot;
556 pVCpu->em.s.cExitRecordUsed++;
557 LogFlow(("emHistoryRecordInitNew: [%#x] = %#07x %016RX64; (%u of %u used)\n", idxSlot, uFlagsAndType, uFlatPC,
558 pVCpu->em.s.cExitRecordUsed, RT_ELEMENTS(pVCpu->em.s.aExitRecords) ));
559 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
560}
561
562
563/**
564 * Worker for emHistoryAddOrUpdateRecord.
565 */
566DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitReplacement(PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
567 PEMEXITREC pExitRec, uint64_t uFlatPC,
568 uint32_t uFlagsAndType, uint64_t uExitNo)
569{
570 pHistEntry->idxSlot = (uint32_t)idxSlot;
571 LogFlow(("emHistoryRecordInitReplacement: [%#x] = %#07x %016RX64 replacing %#07x %016RX64 with %u hits, %u exits old\n",
572 idxSlot, uFlagsAndType, uFlatPC, pExitRec->uFlagsAndType, pExitRec->uFlatPC, pExitRec->cHits,
573 uExitNo - pExitRec->uLastExitNo));
574 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
575}
576
577
578/**
579 * Adds or updates the EMEXITREC for this PC/type and decide on an action.
580 *
581 * @returns Pointer to an exit record if special action should be taken using
582 * EMHistoryExec(). Take normal exit action when NULL.
583 *
584 * @param pVCpu The cross context virtual CPU structure.
585 * @param uFlagsAndType Combined flags and type, EMEXIT_F_KIND_EM set and
586 * both EMEXIT_F_CS_EIP and EMEXIT_F_UNFLATTENED_PC are clear.
587 * @param uFlatPC The flattened program counter.
588 * @param pHistEntry The exit history entry.
589 * @param uExitNo The current exit number.
590 */
591static PCEMEXITREC emHistoryAddOrUpdateRecord(PVMCPU pVCpu, uint64_t uFlagsAndType, uint64_t uFlatPC,
592 PEMEXITENTRY pHistEntry, uint64_t uExitNo)
593{
594# ifdef IN_RING0
595 /* Disregard the hm flag. */
596 uFlagsAndType &= ~EMEXIT_F_HM;
597# endif
598
599 /*
600 * Work the hash table.
601 */
602 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitRecords) == 1024);
603# define EM_EXIT_RECORDS_IDX_MASK 0x3ff
604 uintptr_t idxSlot = ((uintptr_t)uFlatPC >> 1) & EM_EXIT_RECORDS_IDX_MASK;
605 PEMEXITREC pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
606 if (pExitRec->uFlatPC == uFlatPC)
607 {
608 Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
609 pHistEntry->idxSlot = (uint32_t)idxSlot;
610 if (pExitRec->uFlagsAndType == uFlagsAndType)
611 {
612 pExitRec->uLastExitNo = uExitNo;
613 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[0]);
614 }
615 else
616 {
617 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[0]);
618 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
619 }
620 }
621 else if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
622 {
623 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[0]);
624 return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
625 }
626 else
627 {
628 /*
629 * Collision. We calculate a new hash for stepping away from the first,
630 * doing up to 8 steps away before replacing the least recently used record.
631 */
632 uintptr_t idxOldest = idxSlot;
633 uint64_t uOldestExitNo = pExitRec->uLastExitNo;
634 unsigned iOldestStep = 0;
635 unsigned iStep = 1;
636 uintptr_t const idxAdd = (uintptr_t)(uFlatPC >> 11) & (EM_EXIT_RECORDS_IDX_MASK / 4);
637 for (;;)
638 {
639 Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
640 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecNew) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
641 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
642 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecTypeChanged) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
643
644 /* Step to the next slot. */
645 idxSlot += idxAdd;
646 idxSlot &= EM_EXIT_RECORDS_IDX_MASK;
647 pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
648
649 /* Does it match? */
650 if (pExitRec->uFlatPC == uFlatPC)
651 {
652 Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
653 pHistEntry->idxSlot = (uint32_t)idxSlot;
654 if (pExitRec->uFlagsAndType == uFlagsAndType)
655 {
656 pExitRec->uLastExitNo = uExitNo;
657 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[iStep]);
658 break;
659 }
660 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[iStep]);
661 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
662 }
663
664 /* Is it free? */
665 if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
666 {
667 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[iStep]);
668 return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
669 }
670
671 /* Is it the least recently used one? */
672 if (pExitRec->uLastExitNo < uOldestExitNo)
673 {
674 uOldestExitNo = pExitRec->uLastExitNo;
675 idxOldest = idxSlot;
676 iOldestStep = iStep;
677 }
678
679 /* Next iteration? */
680 iStep++;
681 Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced));
682 if (RT_LIKELY(iStep < 8 + 1))
683 { /* likely */ }
684 else
685 {
686 /* Replace the least recently used slot. */
687 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecReplaced[iOldestStep]);
688 pExitRec = &pVCpu->em.s.aExitRecords[idxOldest];
689 return emHistoryRecordInitReplacement(pHistEntry, idxOldest, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
690 }
691 }
692 }
693
694 /*
695 * Found an existing record.
696 */
697 switch (pExitRec->enmAction)
698 {
699 case EMEXITACTION_NORMAL:
700 {
701 uint64_t const cHits = ++pExitRec->cHits;
702 if (cHits < 256)
703 return NULL;
704 LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> EXEC_PROBE\n", idxSlot, uFlagsAndType, uFlatPC));
705 pExitRec->enmAction = EMEXITACTION_EXEC_PROBE;
706 return pExitRec;
707 }
708
709 case EMEXITACTION_NORMAL_PROBED:
710 pExitRec->cHits += 1;
711 return NULL;
712
713 default:
714 pExitRec->cHits += 1;
715 return pExitRec;
716
717 /* This will happen if the caller ignores or cannot serve the probe
718 request (forced to ring-3, whatever). We retry this 256 times. */
719 case EMEXITACTION_EXEC_PROBE:
720 {
721 uint64_t const cHits = ++pExitRec->cHits;
722 if (cHits < 512)
723 return pExitRec;
724 pExitRec->enmAction = EMEXITACTION_NORMAL_PROBED;
725 LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> PROBED\n", idxSlot, uFlagsAndType, uFlatPC));
726 return NULL;
727 }
728 }
729}
730
731#endif /* !IN_RC */
732
733/**
734 * Adds an exit to the history for this CPU.
735 *
736 * @returns Pointer to an exit record if special action should be taken using
737 * EMHistoryExec(). Take normal exit action when NULL.
738 *
739 * @param pVCpu The cross context virtual CPU structure.
740 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
741 * @param uFlatPC The flattened program counter (RIP). UINT64_MAX if not available.
742 * @param uTimestamp The TSC value for the exit, 0 if not available.
743 * @thread EMT(pVCpu)
744 */
745VMM_INT_DECL(PCEMEXITREC) EMHistoryAddExit(PVMCPU pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC, uint64_t uTimestamp)
746{
747 VMCPU_ASSERT_EMT(pVCpu);
748
749 /*
750 * Add the exit history entry.
751 */
752 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
753 uint64_t uExitNo = pVCpu->em.s.iNextExit++;
754 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
755 pHistEntry->uFlatPC = uFlatPC;
756 pHistEntry->uTimestamp = uTimestamp;
757 pHistEntry->uFlagsAndType = uFlagsAndType;
758 pHistEntry->idxSlot = UINT32_MAX;
759
760#ifndef IN_RC
761 /*
762 * If common exit type, we will insert/update the exit into the exit record hash table.
763 */
764 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
765# ifdef IN_RING0
766 && pVCpu->em.s.fExitOptimizationEnabledR0
767 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
768# else
769 && pVCpu->em.s.fExitOptimizationEnabled
770# endif
771 && uFlatPC != UINT64_MAX
772 )
773 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
774#endif
775 return NULL;
776}
777
778
779#ifdef IN_RC
780/**
781 * Special raw-mode interface for adding an exit to the history.
782 *
783 * Currently this is only for recording, not optimizing, so no return value. If
784 * we start seriously caring about raw-mode again, we may extend it.
785 *
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
788 * @param uCs The CS.
789 * @param uEip The EIP.
790 * @param uTimestamp The TSC value for the exit, 0 if not available.
791 * @thread EMT(0)
792 */
793VMMRC_INT_DECL(void) EMRCHistoryAddExitCsEip(PVMCPU pVCpu, uint32_t uFlagsAndType, uint16_t uCs, uint32_t uEip, uint64_t uTimestamp)
794{
795 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
796 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)(pVCpu->em.s.iNextExit++) & 0xff];
797 pHistEntry->uFlatPC = ((uint64_t)uCs << 32) | uEip;
798 pHistEntry->uTimestamp = uTimestamp;
799 pHistEntry->uFlagsAndType = uFlagsAndType | EMEXIT_F_CS_EIP;
800 pHistEntry->idxSlot = UINT32_MAX;
801}
802#endif
803
804
805#ifdef IN_RING0
806/**
807 * Interface that VT-x uses to supply the PC of an exit when CS:RIP is being read.
808 *
809 * @param pVCpu The cross context virtual CPU structure.
810 * @param uFlatPC The flattened program counter (RIP).
811 * @param fFlattened Set if RIP was subjected to CS.BASE, clear if not.
812 */
813VMMR0_INT_DECL(void) EMR0HistoryUpdatePC(PVMCPU pVCpu, uint64_t uFlatPC, bool fFlattened)
814{
815 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
816 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
817 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
818 pHistEntry->uFlatPC = uFlatPC;
819 if (fFlattened)
820 pHistEntry->uFlagsAndType &= ~EMEXIT_F_UNFLATTENED_PC;
821 else
822 pHistEntry->uFlagsAndType |= EMEXIT_F_UNFLATTENED_PC;
823}
824#endif
825
826
827/**
828 * Interface for convering a engine specific exit to a generic one and get guidance.
829 *
830 * @returns Pointer to an exit record if special action should be taken using
831 * EMHistoryExec(). Take normal exit action when NULL.
832 *
833 * @param pVCpu The cross context virtual CPU structure.
834 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
835 * @thread EMT(pVCpu)
836 */
837VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndType(PVMCPU pVCpu, uint32_t uFlagsAndType)
838{
839 VMCPU_ASSERT_EMT(pVCpu);
840
841 /*
842 * Do the updating.
843 */
844 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
845 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
846 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
847 pHistEntry->uFlagsAndType = uFlagsAndType | (pHistEntry->uFlagsAndType & (EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC));
848
849#ifndef IN_RC
850 /*
851 * If common exit type, we will insert/update the exit into the exit record hash table.
852 */
853 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
854# ifdef IN_RING0
855 && pVCpu->em.s.fExitOptimizationEnabledR0
856 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
857# else
858 && pVCpu->em.s.fExitOptimizationEnabled
859# endif
860 && pHistEntry->uFlatPC != UINT64_MAX
861 )
862 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, pHistEntry->uFlatPC, pHistEntry, uExitNo);
863#endif
864 return NULL;
865}
866
867
868/**
869 * Interface for convering a engine specific exit to a generic one and get
870 * guidance, supplying flattened PC too.
871 *
872 * @returns Pointer to an exit record if special action should be taken using
873 * EMHistoryExec(). Take normal exit action when NULL.
874 *
875 * @param pVCpu The cross context virtual CPU structure.
876 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
877 * @param uFlatPC The flattened program counter (RIP).
878 * @thread EMT(pVCpu)
879 */
880VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndTypeAndPC(PVMCPU pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC)
881{
882 VMCPU_ASSERT_EMT(pVCpu);
883 Assert(uFlatPC != UINT64_MAX);
884
885 /*
886 * Do the updating.
887 */
888 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
889 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
890 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
891 pHistEntry->uFlagsAndType = uFlagsAndType;
892 pHistEntry->uFlatPC = uFlatPC;
893
894#ifndef IN_RC
895 /*
896 * If common exit type, we will insert/update the exit into the exit record hash table.
897 */
898 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
899# ifdef IN_RING0
900 && pVCpu->em.s.fExitOptimizationEnabledR0
901 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
902# else
903 && pVCpu->em.s.fExitOptimizationEnabled
904# endif
905 )
906 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
907#endif
908 return NULL;
909}
910
911
912/**
913 * Locks REM execution to a single VCPU.
914 *
915 * @param pVM The cross context VM structure.
916 */
917VMMDECL(void) EMRemLock(PVM pVM)
918{
919#ifdef VBOX_WITH_REM
920 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
921 return; /* early init */
922
923 Assert(!PGMIsLockOwner(pVM));
924 Assert(!IOMIsLockWriteOwner(pVM));
925 int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
926 AssertRCSuccess(rc);
927#else
928 RT_NOREF(pVM);
929#endif
930}
931
932
933/**
934 * Unlocks REM execution
935 *
936 * @param pVM The cross context VM structure.
937 */
938VMMDECL(void) EMRemUnlock(PVM pVM)
939{
940#ifdef VBOX_WITH_REM
941 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
942 return; /* early init */
943
944 PDMCritSectLeave(&pVM->em.s.CritSectREM);
945#else
946 RT_NOREF(pVM);
947#endif
948}
949
950
951/**
952 * Check if this VCPU currently owns the REM lock.
953 *
954 * @returns bool owner/not owner
955 * @param pVM The cross context VM structure.
956 */
957VMMDECL(bool) EMRemIsLockOwner(PVM pVM)
958{
959#ifdef VBOX_WITH_REM
960 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
961 return true; /* early init */
962
963 return PDMCritSectIsOwner(&pVM->em.s.CritSectREM);
964#else
965 RT_NOREF(pVM);
966 return true;
967#endif
968}
969
970
971/**
972 * Try to acquire the REM lock.
973 *
974 * @returns VBox status code
975 * @param pVM The cross context VM structure.
976 */
977VMM_INT_DECL(int) EMRemTryLock(PVM pVM)
978{
979#ifdef VBOX_WITH_REM
980 if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
981 return VINF_SUCCESS; /* early init */
982
983 return PDMCritSectTryEnter(&pVM->em.s.CritSectREM);
984#else
985 RT_NOREF(pVM);
986 return VINF_SUCCESS;
987#endif
988}
989
990
991/**
992 * @callback_method_impl{FNDISREADBYTES}
993 */
994static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
995{
996 PVMCPU pVCpu = (PVMCPU)pDis->pvUser;
997#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) || defined(IN_RING3))
998 PVM pVM = pVCpu->CTX_SUFF(pVM);
999#endif
1000 RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
1001 int rc;
1002
1003 /*
1004 * Figure how much we can or must read.
1005 */
1006 size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
1007 if (cbToRead > cbMaxRead)
1008 cbToRead = cbMaxRead;
1009 else if (cbToRead < cbMinRead)
1010 cbToRead = cbMinRead;
1011
1012#if defined(VBOX_WITH_RAW_MODE) && (defined(IN_RC) || defined(IN_RING3))
1013 /*
1014 * We might be called upon to interpret an instruction in a patch.
1015 */
1016 if (PATMIsPatchGCAddr(pVM, uSrcAddr))
1017 {
1018# ifdef IN_RC
1019 memcpy(&pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
1020# else
1021 memcpy(&pDis->abInstr[offInstr], PATMR3GCPtrToHCPtr(pVM, uSrcAddr), cbToRead);
1022# endif
1023 rc = VINF_SUCCESS;
1024 }
1025 else
1026#endif
1027 {
1028# ifdef IN_RC
1029 /*
1030 * Try access it thru the shadow page tables first. Fall back on the
1031 * slower PGM method if it fails because the TLB or page table was
1032 * modified recently.
1033 */
1034 rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
1035 if (rc == VERR_ACCESS_DENIED && cbToRead > cbMinRead)
1036 {
1037 cbToRead = cbMinRead;
1038 rc = MMGCRamRead(pVCpu->pVMRC, &pDis->abInstr[offInstr], (void *)(uintptr_t)uSrcAddr, cbToRead);
1039 }
1040 if (rc == VERR_ACCESS_DENIED)
1041#endif
1042 {
1043 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
1044 if (RT_FAILURE(rc))
1045 {
1046 if (cbToRead > cbMinRead)
1047 {
1048 cbToRead = cbMinRead;
1049 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
1050 }
1051 if (RT_FAILURE(rc))
1052 {
1053#ifndef IN_RC
1054 /*
1055 * If we fail to find the page via the guest's page tables
1056 * we invalidate the page in the host TLB (pertaining to
1057 * the guest in the NestedPaging case). See @bugref{6043}.
1058 */
1059 if (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1060 {
1061 HMInvalidatePage(pVCpu, uSrcAddr);
1062 if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
1063 HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
1064 }
1065#endif
1066 }
1067 }
1068 }
1069 }
1070
1071 pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
1072 return rc;
1073}
1074
1075
1076
1077/**
1078 * Disassembles the current instruction.
1079 *
1080 * @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
1081 * details.
1082 *
1083 * @param pVM The cross context VM structure.
1084 * @param pVCpu The cross context virtual CPU structure.
1085 * @param pDis Where to return the parsed instruction info.
1086 * @param pcbInstr Where to return the instruction size. (optional)
1087 */
1088VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
1089{
1090 PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
1091 RTGCPTR GCPtrInstr;
1092#if 0
1093 int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
1094#else
1095/** @todo Get the CPU mode as well while we're at it! */
1096 int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
1097 pCtxCore->rip, &GCPtrInstr);
1098#endif
1099 if (RT_FAILURE(rc))
1100 {
1101 Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
1102 pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
1103 return rc;
1104 }
1105 return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
1106}
1107
1108
1109/**
1110 * Disassembles one instruction.
1111 *
1112 * This is used by internally by the interpreter and by trap/access handlers.
1113 *
1114 * @returns VBox status code.
1115 *
1116 * @param pVM The cross context VM structure.
1117 * @param pVCpu The cross context virtual CPU structure.
1118 * @param GCPtrInstr The flat address of the instruction.
1119 * @param pCtxCore The context core (used to determine the cpu mode).
1120 * @param pDis Where to return the parsed instruction info.
1121 * @param pcbInstr Where to return the instruction size. (optional)
1122 */
1123VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
1124 PDISCPUSTATE pDis, unsigned *pcbInstr)
1125{
1126 NOREF(pVM);
1127 Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
1128 DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
1129 /** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
1130 * \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
1131 int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
1132 if (RT_SUCCESS(rc))
1133 return VINF_SUCCESS;
1134 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
1135 return rc;
1136}
1137
1138
1139/**
1140 * Interprets the current instruction.
1141 *
1142 * @returns VBox status code.
1143 * @retval VINF_* Scheduling instructions.
1144 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1145 * @retval VERR_* Fatal errors.
1146 *
1147 * @param pVCpu The cross context virtual CPU structure.
1148 * @param pRegFrame The register frame.
1149 * Updates the EIP if an instruction was executed successfully.
1150 * @param pvFault The fault address (CR2).
1151 *
1152 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1153 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1154 * to worry about e.g. invalid modrm combinations (!)
1155 */
1156VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1157{
1158 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1159 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1160 NOREF(pvFault);
1161
1162 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
1163 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1164 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1165 rc = VERR_EM_INTERPRETER;
1166 if (rc != VINF_SUCCESS)
1167 Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1168
1169 return rc;
1170}
1171
1172
1173/**
1174 * Interprets the current instruction.
1175 *
1176 * @returns VBox status code.
1177 * @retval VINF_* Scheduling instructions.
1178 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1179 * @retval VERR_* Fatal errors.
1180 *
1181 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1182 * @param pRegFrame The register frame.
1183 * Updates the EIP if an instruction was executed successfully.
1184 * @param pvFault The fault address (CR2).
1185 * @param pcbWritten Size of the write (if applicable).
1186 *
1187 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1188 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1189 * to worry about e.g. invalid modrm combinations (!)
1190 */
1191VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
1192{
1193 LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1194 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1195 NOREF(pvFault);
1196
1197 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
1198 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1199 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1200 rc = VERR_EM_INTERPRETER;
1201 if (rc != VINF_SUCCESS)
1202 Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1203
1204 return rc;
1205}
1206
1207
1208/**
1209 * Interprets the current instruction using the supplied DISCPUSTATE structure.
1210 *
1211 * IP/EIP/RIP *IS* updated!
1212 *
1213 * @returns VBox strict status code.
1214 * @retval VINF_* Scheduling instructions. When these are returned, it
1215 * starts to get a bit tricky to know whether code was
1216 * executed or not... We'll address this when it becomes a problem.
1217 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1218 * @retval VERR_* Fatal errors.
1219 *
1220 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1221 * @param pDis The disassembler cpu state for the instruction to be
1222 * interpreted.
1223 * @param pRegFrame The register frame. IP/EIP/RIP *IS* changed!
1224 * @param pvFault The fault address (CR2).
1225 * @param enmCodeType Code type (user/supervisor)
1226 *
1227 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1228 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1229 * to worry about e.g. invalid modrm combinations (!)
1230 *
1231 * @todo At this time we do NOT check if the instruction overwrites vital information.
1232 * Make sure this can't happen!! (will add some assertions/checks later)
1233 */
1234VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
1235 RTGCPTR pvFault, EMCODETYPE enmCodeType)
1236{
1237 LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1238 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1239 NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
1240
1241 VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1242 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1243 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1244 rc = VERR_EM_INTERPRETER;
1245
1246 if (rc != VINF_SUCCESS)
1247 Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1248
1249 return rc;
1250}
1251
1252#ifdef IN_RC
1253
1254DECLINLINE(int) emRCStackRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, uint32_t cb)
1255{
1256 int rc = MMGCRamRead(pVM, pvDst, (void *)(uintptr_t)GCPtrSrc, cb);
1257 if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
1258 return rc;
1259 return PGMPhysInterpretedReadNoHandlers(pVCpu, pCtxCore, pvDst, GCPtrSrc, cb, /*fMayTrap*/ false);
1260}
1261
1262
1263/**
1264 * Interpret IRET (currently only to V86 code) - PATM only.
1265 *
1266 * @returns VBox status code.
1267 * @param pVM The cross context VM structure.
1268 * @param pVCpu The cross context virtual CPU structure.
1269 * @param pRegFrame The register frame.
1270 *
1271 */
1272VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1273{
1274 RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1275 RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1276 int rc;
1277
1278 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1279 Assert(!CPUMIsGuestIn64BitCode(pVCpu));
1280 /** @todo Rainy day: Test what happens when VERR_EM_INTERPRETER is returned by
1281 * this function. Fear that it may guru on us, thus not converted to
1282 * IEM. */
1283
1284 rc = emRCStackRead(pVM, pVCpu, pRegFrame, &eip, (RTGCPTR)pIretStack , 4);
1285 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &cs, (RTGCPTR)(pIretStack + 4), 4);
1286 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1287 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1288 AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1289
1290 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &esp, (RTGCPTR)(pIretStack + 12), 4);
1291 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &ss, (RTGCPTR)(pIretStack + 16), 4);
1292 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &es, (RTGCPTR)(pIretStack + 20), 4);
1293 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &ds, (RTGCPTR)(pIretStack + 24), 4);
1294 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &fs, (RTGCPTR)(pIretStack + 28), 4);
1295 rc |= emRCStackRead(pVM, pVCpu, pRegFrame, &gs, (RTGCPTR)(pIretStack + 32), 4);
1296 AssertRCReturn(rc, VERR_EM_INTERPRETER);
1297
1298 pRegFrame->eip = eip & 0xffff;
1299 pRegFrame->cs.Sel = cs;
1300
1301 /* Mask away all reserved bits */
1302 uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
1303 eflags &= uMask;
1304
1305 CPUMRawSetEFlags(pVCpu, eflags);
1306 Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
1307
1308 pRegFrame->esp = esp;
1309 pRegFrame->ss.Sel = ss;
1310 pRegFrame->ds.Sel = ds;
1311 pRegFrame->es.Sel = es;
1312 pRegFrame->fs.Sel = fs;
1313 pRegFrame->gs.Sel = gs;
1314
1315 return VINF_SUCCESS;
1316}
1317
1318
1319#endif /* IN_RC */
1320
1321
1322
1323/*
1324 *
1325 * Old interpreter primitives used by HM, move/eliminate later.
1326 * Old interpreter primitives used by HM, move/eliminate later.
1327 * Old interpreter primitives used by HM, move/eliminate later.
1328 * Old interpreter primitives used by HM, move/eliminate later.
1329 * Old interpreter primitives used by HM, move/eliminate later.
1330 *
1331 */
1332
1333
1334/**
1335 * Interpret RDPMC.
1336 *
1337 * @returns VBox status code.
1338 * @param pVM The cross context VM structure.
1339 * @param pVCpu The cross context virtual CPU structure.
1340 * @param pRegFrame The register frame.
1341 *
1342 */
1343VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1344{
1345 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1346 uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1347
1348 /* If X86_CR4_PCE is not set, then CPL must be zero. */
1349 if ( !(uCR4 & X86_CR4_PCE)
1350 && CPUMGetGuestCPL(pVCpu) != 0)
1351 {
1352 Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1353 return VERR_EM_INTERPRETER; /* genuine #GP */
1354 }
1355
1356 /* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1357 pRegFrame->rax = 0;
1358 pRegFrame->rdx = 0;
1359 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
1360 * ecx but see @bugref{3472}! */
1361
1362 NOREF(pVM);
1363 return VINF_SUCCESS;
1364}
1365
1366
1367/**
1368 * MWAIT Emulation.
1369 */
1370VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1371{
1372 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1373 uint32_t u32Dummy, u32ExtFeatures, cpl, u32MWaitFeatures;
1374 NOREF(pVM);
1375
1376 /* Get the current privilege level. */
1377 cpl = CPUMGetGuestCPL(pVCpu);
1378 if (cpl != 0)
1379 return VERR_EM_INTERPRETER; /* supervisor only */
1380
1381 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1382 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1383 return VERR_EM_INTERPRETER; /* not supported */
1384
1385 /*
1386 * CPUID.05H.ECX[0] defines support for power management extensions (eax)
1387 * CPUID.05H.ECX[1] defines support for interrupts as break events for mwait even when IF=0
1388 */
1389 CPUMGetGuestCpuId(pVCpu, 5, 0, &u32Dummy, &u32Dummy, &u32MWaitFeatures, &u32Dummy);
1390 if (pRegFrame->ecx > 1)
1391 {
1392 Log(("EMInterpretMWait: unexpected ecx value %x -> recompiler\n", pRegFrame->ecx));
1393 return VERR_EM_INTERPRETER; /* illegal value. */
1394 }
1395
1396 if (pRegFrame->ecx && !(u32MWaitFeatures & X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
1397 {
1398 Log(("EMInterpretMWait: unsupported X86_CPUID_MWAIT_ECX_BREAKIRQIF0 -> recompiler\n"));
1399 return VERR_EM_INTERPRETER; /* illegal value. */
1400 }
1401
1402 return EMMonitorWaitPerform(pVCpu, pRegFrame->rax, pRegFrame->rcx);
1403}
1404
1405
1406/**
1407 * MONITOR Emulation.
1408 */
1409VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1410{
1411 uint32_t u32Dummy, u32ExtFeatures, cpl;
1412 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1413 NOREF(pVM);
1414
1415 if (pRegFrame->ecx != 0)
1416 {
1417 Log(("emInterpretMonitor: unexpected ecx=%x -> recompiler!!\n", pRegFrame->ecx));
1418 return VERR_EM_INTERPRETER; /* illegal value. */
1419 }
1420
1421 /* Get the current privilege level. */
1422 cpl = CPUMGetGuestCPL(pVCpu);
1423 if (cpl != 0)
1424 return VERR_EM_INTERPRETER; /* supervisor only */
1425
1426 CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
1427 if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
1428 return VERR_EM_INTERPRETER; /* not supported */
1429
1430 EMMonitorWaitPrepare(pVCpu, pRegFrame->rax, pRegFrame->rcx, pRegFrame->rdx, NIL_RTGCPHYS);
1431 return VINF_SUCCESS;
1432}
1433
1434
1435/* VT-x only: */
1436
1437/**
1438 * Interpret DRx write.
1439 *
1440 * @returns VBox status code.
1441 * @param pVM The cross context VM structure.
1442 * @param pVCpu The cross context virtual CPU structure.
1443 * @param pRegFrame The register frame.
1444 * @param DestRegDrx DRx register index (USE_REG_DR*)
1445 * @param SrcRegGen General purpose register index (USE_REG_E**))
1446 *
1447 */
1448VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1449{
1450 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1451 uint64_t uNewDrX;
1452 int rc;
1453 NOREF(pVM);
1454
1455 if (CPUMIsGuestIn64BitCode(pVCpu))
1456 rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1457 else
1458 {
1459 uint32_t val32;
1460 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1461 uNewDrX = val32;
1462 }
1463
1464 if (RT_SUCCESS(rc))
1465 {
1466 if (DestRegDrx == 6)
1467 {
1468 uNewDrX |= X86_DR6_RA1_MASK;
1469 uNewDrX &= ~X86_DR6_RAZ_MASK;
1470 }
1471 else if (DestRegDrx == 7)
1472 {
1473 uNewDrX |= X86_DR7_RA1_MASK;
1474 uNewDrX &= ~X86_DR7_RAZ_MASK;
1475 }
1476
1477 /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1478 rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1479 if (RT_SUCCESS(rc))
1480 return rc;
1481 AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1482 }
1483 return VERR_EM_INTERPRETER;
1484}
1485
1486
1487/**
1488 * Interpret DRx read.
1489 *
1490 * @returns VBox status code.
1491 * @param pVM The cross context VM structure.
1492 * @param pVCpu The cross context virtual CPU structure.
1493 * @param pRegFrame The register frame.
1494 * @param DestRegGen General purpose register index (USE_REG_E**))
1495 * @param SrcRegDrx DRx register index (USE_REG_DR*)
1496 */
1497VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1498{
1499 uint64_t val64;
1500 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1501 NOREF(pVM);
1502
1503 int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1504 AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1505 if (CPUMIsGuestIn64BitCode(pVCpu))
1506 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1507 else
1508 rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1509
1510 if (RT_SUCCESS(rc))
1511 return VINF_SUCCESS;
1512
1513 return VERR_EM_INTERPRETER;
1514}
1515
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