EMAll.cpp@ 8213

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1	/* $Id: EMAll.cpp 8191 2008-04-19 20:32:53Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor(/Manager) - All contexts
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_EM
27	#include <VBox/em.h>
28	#include <VBox/mm.h>
29	#include <VBox/selm.h>
30	#include <VBox/patm.h>
31	#include <VBox/csam.h>
32	#include <VBox/pgm.h>
33	#include <VBox/iom.h>
34	#include <VBox/stam.h>
35	#include "EMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/hwaccm.h>
38	#include <VBox/tm.h>
39
40	#include <VBox/param.h>
41	#include <VBox/err.h>
42	#include <VBox/dis.h>
43	#include <VBox/disopcode.h>
44	#include <VBox/log.h>
45	#include <iprt/assert.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48
49
50	/*******************************************************************************
51	* Structures and Typedefs *
52	*******************************************************************************/
53	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2_UINT32(uint32_t *pu32Param1, uint32_t val2);
54	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(uint32_t *pu32Param1, size_t val2);
55	typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(uint32_t *pu32Param1, uint32_t val2, size_t val3);
56	typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(RTGCPTR GCPtrParam1, RTGCUINTREG Val2, uint32_t *pf);
57	typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
58	typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(RTGCPTR GCPtrParam1, RTGCUINTREG Val2, size_t cb, uint32_t *pf);
59	typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
60
61
62	/*******************************************************************************
63	* Internal Functions *
64	*******************************************************************************/
65	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
66
67
68	/**
69	* Get the current execution manager status.
70	*
71	* @returns Current status.
72	*/
73	EMDECL(EMSTATE) EMGetState(PVM pVM)
74	{
75	return pVM->em.s.enmState;
76	}
77
78
79	#ifndef IN_GC
80	/**
81	* Read callback for disassembly function; supports reading bytes that cross a page boundary
82	*
83	* @returns VBox status code.
84	* @param pSrc GC source pointer
85	* @param pDest HC destination pointer
86	* @param size Number of bytes to read
87	* @param dwUserdata Callback specific user data (pCpu)
88	*
89	*/
90	DECLCALLBACK(int) EMReadBytes(RTHCUINTPTR pSrc, uint8_t pDest, unsigned size, void pvUserdata)
91	{
92	DISCPUSTATE pCpu = (DISCPUSTATE )pvUserdata;
93	PVM pVM = (PVM)pCpu->apvUserData[0];
94	#ifdef IN_RING0
95	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, size);
96	AssertRC(rc);
97	#else
98	if (!PATMIsPatchGCAddr(pVM, pSrc))
99	{
100	int rc = PGMPhysReadGCPtr(pVM, pDest, pSrc, size);
101	AssertRC(rc);
102	}
103	else
104	{
105	for (uint32_t i = 0; i < size; i++)
106	{
107	uint8_t opcode;
108	if (VBOX_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
109	{
110	*(pDest+i) = opcode;
111	}
112	}
113	}
114	#endif /* IN_RING0 */
115	return VINF_SUCCESS;
116	}
117
118	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
119	{
120	return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
121	}
122
123	#else
124
125	DECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE pCpu, RTGCUINTPTR InstrGC, uint32_t pOpsize)
126	{
127	return DISCoreOne(pCpu, InstrGC, pOpsize);
128	}
129
130	#endif
131
132
133	/**
134	* Disassembles one instruction.
135	*
136	* @param pVM The VM handle.
137	* @param pCtxCore The context core (used for both the mode and instruction).
138	* @param pCpu Where to return the parsed instruction info.
139	* @param pcbInstr Where to return the instruction size. (optional)
140	*/
141	EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
142	{
143	RTGCPTR GCPtrInstr;
144	int rc = SELMValidateAndConvertCSAddr(pVM, pCtxCore->eflags, pCtxCore->ss, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid, (RTGCPTR)pCtxCore->eip, &GCPtrInstr);
145	if (VBOX_FAILURE(rc))
146	{
147	Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RX32 (cpl=%d) - rc=%Vrc !!\n",
148	pCtxCore->cs, pCtxCore->eip, pCtxCore->ss & X86_SEL_RPL, rc));
149	return rc;
150	}
151	return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
152	}
153
154
155	/**
156	* Disassembles one instruction.
157	*
158	* This is used by internally by the interpreter and by trap/access handlers.
159	*
160	* @param pVM The VM handle.
161	* @param GCPtrInstr The flat address of the instruction.
162	* @param pCtxCore The context core (used to determin the cpu mode).
163	* @param pCpu Where to return the parsed instruction info.
164	* @param pcbInstr Where to return the instruction size. (optional)
165	*/
166	EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
167	{
168	int rc = DISCoreOneEx(GCPtrInstr, SELMIsSelector32Bit(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid) ? CPUMODE_32BIT : CPUMODE_16BIT,
169	#ifdef IN_GC
170	NULL, NULL,
171	#else
172	EMReadBytes, pVM,
173	#endif
174	pCpu, pcbInstr);
175	if (VBOX_SUCCESS(rc))
176	return VINF_SUCCESS;
177	AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Vrc\n", GCPtrInstr, rc));
178	return VERR_INTERNAL_ERROR;
179	}
180
181
182	/**
183	* Interprets the current instruction.
184	*
185	* @returns VBox status code.
186	* @retval VINF_* Scheduling instructions.
187	* @retval VERR_EM_INTERPRETER Something we can't cope with.
188	* @retval VERR_* Fatal errors.
189	*
190	* @param pVM The VM handle.
191	* @param pRegFrame The register frame.
192	* Updates the EIP if an instruction was executed successfully.
193	* @param pvFault The fault address (CR2).
194	* @param pcbSize Size of the write (if applicable).
195	*
196	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
197	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
198	* to worry about e.g. invalid modrm combinations (!)
199	*/
200	EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
201	{
202	RTGCPTR pbCode;
203	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
204	if (VBOX_SUCCESS(rc))
205	{
206	uint32_t cbOp;
207	DISCPUSTATE Cpu;
208	Cpu.mode = SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid) ? CPUMODE_32BIT : CPUMODE_16BIT;
209	rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
210	if (VBOX_SUCCESS(rc))
211	{
212	Assert(cbOp == Cpu.opsize);
213	rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
214	if (VBOX_SUCCESS(rc))
215	{
216	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
217	}
218	return rc;
219	}
220	}
221	return VERR_EM_INTERPRETER;
222	}
223
224	/**
225	* Interprets the current instruction using the supplied DISCPUSTATE structure.
226	*
227	* EIP is NOT updated!
228	*
229	* @returns VBox status code.
230	* @retval VINF_* Scheduling instructions. When these are returned, it
231	* starts to get a bit tricky to know whether code was
232	* executed or not... We'll address this when it becomes a problem.
233	* @retval VERR_EM_INTERPRETER Something we can't cope with.
234	* @retval VERR_* Fatal errors.
235	*
236	* @param pVM The VM handle.
237	* @param pCpu The disassembler cpu state for the instruction to be interpreted.
238	* @param pRegFrame The register frame. EIP is NOT changed!
239	* @param pvFault The fault address (CR2).
240	* @param pcbSize Size of the write (if applicable).
241	*
242	* @remark Invalid opcode exceptions have a higher priority than GP (see Intel
243	* Architecture System Developers Manual, Vol 3, 5.5) so we don't need
244	* to worry about e.g. invalid modrm combinations (!)
245	*
246	* @todo At this time we do NOT check if the instruction overwrites vital information.
247	* Make sure this can't happen!! (will add some assertions/checks later)
248	*/
249	EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
250	{
251	STAM_PROFILE_START(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
252	int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
253	STAM_PROFILE_STOP(&CTXMID(pVM->em.s.CTXSUFF(pStats)->Stat,Emulate), a);
254	if (VBOX_SUCCESS(rc))
255	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretSucceeded));
256	else
257	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,InterpretFailed));
258	return rc;
259	}
260
261
262	/**
263	* Interpret a port I/O instruction.
264	*
265	* @returns VBox status code suitable for scheduling.
266	* @param pVM The VM handle.
267	* @param pCtxCore The context core. This will be updated on successful return.
268	* @param pCpu The instruction to interpret.
269	* @param cbOp The size of the instruction.
270	* @remark This may raise exceptions.
271	*/
272	EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
273	{
274	/*
275	* Hand it on to IOM.
276	*/
277	#ifdef IN_GC
278	int rc = IOMGCIOPortHandler(pVM, pCtxCore, pCpu);
279	if (IOM_SUCCESS(rc))
280	pCtxCore->eip += cbOp;
281	return rc;
282	#else
283	AssertReleaseMsgFailed(("not implemented\n"));
284	return VERR_NOT_IMPLEMENTED;
285	#endif
286	}
287
288
289	DECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
290	{
291	#ifdef IN_GC
292	int rc = MMGCRamRead(pVM, pDest, GCSrc, cb);
293	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
294	return rc;
295	/*
296	* The page pool cache may end up here in some cases because it
297	* flushed one of the shadow mappings used by the trapping
298	* instruction and it either flushed the TLB or the CPU reused it.
299	*/
300	RTGCPHYS GCPhys;
301	rc = PGMPhysGCPtr2GCPhys(pVM, GCSrc, &GCPhys);
302	AssertRCReturn(rc, rc);
303	PGMPhysRead(pVM, GCPhys, pDest, cb);
304	return VINF_SUCCESS;
305	#else
306	return PGMPhysReadGCPtrSafe(pVM, pDest, GCSrc, cb);
307	#endif
308	}
309
310	DECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
311	{
312	#ifdef IN_GC
313	int rc = MMGCRamWrite(pVM, GCDest, pSrc, cb);
314	if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
315	return rc;
316	/*
317	* The page pool cache may end up here in some cases because it
318	* flushed one of the shadow mappings used by the trapping
319	* instruction and it either flushed the TLB or the CPU reused it.
320	* We want to play safe here, verifying that we've got write
321	* access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
322	*/
323	uint64_t fFlags;
324	RTGCPHYS GCPhys;
325	rc = PGMGstGetPage(pVM, GCDest, &fFlags, &GCPhys);
326	if (RT_FAILURE(rc))
327	return rc;
328	if ( !(fFlags & X86_PTE_RW)
329	&& (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
330	return VERR_ACCESS_DENIED;
331
332	PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
333	return VINF_SUCCESS;
334
335	#else
336	return PGMPhysWriteGCPtrSafe(pVM, GCDest, pSrc, cb);
337	#endif
338	}
339
340	/* Convert sel:addr to a flat GC address */
341	static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
342	{
343	int prefix_seg, rc;
344	RTSEL sel;
345	CPUMSELREGHID *pSelHidReg;
346
347	prefix_seg = DISDetectSegReg(pCpu, pParam);
348	rc = DISFetchRegSegEx(pRegFrame, prefix_seg, &sel, &pSelHidReg);
349	if (VBOX_FAILURE(rc))
350	return pvAddr;
351
352	return SELMToFlat(pVM, pRegFrame->eflags, sel, pSelHidReg, pvAddr);
353	}
354
355	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
356	# ifdef IN_GC
357	/**
358	* Get the mnemonic for the disassembled instruction.
359	*
360	* GC/R0 doesn't include the strings in the DIS tables because
361	* of limited space.
362	*/
363	static const char *emGetMnemonic(PDISCPUSTATE pCpu)
364	{
365	switch (pCpu->pCurInstr->opcode)
366	{
367	case OP_XOR: return "Xor";
368	case OP_OR: return "Or";
369	case OP_AND: return "And";
370	case OP_BTR: return "Btr";
371	case OP_BTS: return "Bts";
372	default:
373	AssertMsgFailed(("%d\n", pCpu->pCurInstr->opcode));
374	return "???";
375	}
376	}
377	# endif
378	#endif
379
380	/**
381	* XCHG instruction emulation.
382	*/
383	static int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
384	{
385	OP_PARAMVAL param1, param2;
386
387	/* Source to make DISQueryParamVal read the register value - ugly hack */
388	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
389	if(VBOX_FAILURE(rc))
390	return VERR_EM_INTERPRETER;
391
392	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
393	if(VBOX_FAILURE(rc))
394	return VERR_EM_INTERPRETER;
395
396	#ifdef IN_GC
397	if (TRPMHasTrap(pVM))
398	{
399	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
400	{
401	#endif
402	RTGCPTR pParam1 = 0, pParam2 = 0;
403	uint32_t valpar1, valpar2;
404
405	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
406	switch(param1.type)
407	{
408	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
409	valpar1 = param1.val.val32;
410	break;
411
412	case PARMTYPE_ADDRESS:
413	pParam1 = (RTGCPTR)param1.val.val32;
414	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
415	#ifdef IN_GC
416	/* Safety check (in theory it could cross a page boundary and fault there though) */
417	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
418	#endif
419	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
420	if (VBOX_FAILURE(rc))
421	{
422	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
423	return VERR_EM_INTERPRETER;
424	}
425	break;
426
427	default:
428	AssertFailed();
429	return VERR_EM_INTERPRETER;
430	}
431
432	switch(param2.type)
433	{
434	case PARMTYPE_ADDRESS:
435	pParam2 = (RTGCPTR)param2.val.val32;
436	pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
437	#ifdef IN_GC
438	/* Safety check (in theory it could cross a page boundary and fault there though) */
439	AssertReturn(pParam2 == pvFault, VERR_EM_INTERPRETER);
440	#endif
441	rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
442	if (VBOX_FAILURE(rc))
443	{
444	AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
445	}
446	break;
447
448	case PARMTYPE_IMMEDIATE:
449	valpar2 = param2.val.val32;
450	break;
451
452	default:
453	AssertFailed();
454	return VERR_EM_INTERPRETER;
455	}
456
457	/* Write value of parameter 2 to parameter 1 (reg or memory address) */
458	if (pParam1 == 0)
459	{
460	Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
461	switch(param1.size)
462	{
463	case 1: //special case for AH etc
464	rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen8, (uint8_t)valpar2); break;
465	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen32, (uint16_t)valpar2); break;
466	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen32, valpar2); break;
467	default: AssertFailedReturn(VERR_EM_INTERPRETER);
468	}
469	if (VBOX_FAILURE(rc))
470	return VERR_EM_INTERPRETER;
471	}
472	else
473	{
474	rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
475	if (VBOX_FAILURE(rc))
476	{
477	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
478	return VERR_EM_INTERPRETER;
479	}
480	}
481
482	/* Write value of parameter 1 to parameter 2 (reg or memory address) */
483	if (pParam2 == 0)
484	{
485	Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
486	switch(param2.size)
487	{
488	case 1: //special case for AH etc
489	rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen8, (uint8_t)valpar1); break;
490	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen32, (uint16_t)valpar1); break;
491	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen32, valpar1); break;
492	default: AssertFailedReturn(VERR_EM_INTERPRETER);
493	}
494	if (VBOX_FAILURE(rc))
495	return VERR_EM_INTERPRETER;
496	}
497	else
498	{
499	rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
500	if (VBOX_FAILURE(rc))
501	{
502	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
503	return VERR_EM_INTERPRETER;
504	}
505	}
506
507	*pcbSize = param2.size;
508	return VINF_SUCCESS;
509	#ifdef IN_GC
510	}
511	}
512	#endif
513	return VERR_EM_INTERPRETER;
514	}
515
516	/**
517	* INC and DEC emulation.
518	*/
519	static int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
520	PFN_EMULATE_PARAM2 pfnEmulate)
521	{
522	OP_PARAMVAL param1;
523
524	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
525	if(VBOX_FAILURE(rc))
526	return VERR_EM_INTERPRETER;
527
528	#ifdef IN_GC
529	if (TRPMHasTrap(pVM))
530	{
531	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
532	{
533	#endif
534	RTGCPTR pParam1 = 0;
535	uint32_t valpar1;
536
537	if (param1.type == PARMTYPE_ADDRESS)
538	{
539	pParam1 = (RTGCPTR)param1.val.val32;
540	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
541	#ifdef IN_GC
542	/* Safety check (in theory it could cross a page boundary and fault there though) */
543	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
544	#endif
545	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
546	if (VBOX_FAILURE(rc))
547	{
548	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
549	return VERR_EM_INTERPRETER;
550	}
551	}
552	else
553	{
554	AssertFailed();
555	return VERR_EM_INTERPRETER;
556	}
557
558	uint32_t eflags;
559
560	eflags = pfnEmulate(&valpar1, param1.size);
561
562	/* Write result back */
563	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
564	if (VBOX_FAILURE(rc))
565	{
566	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
567	return VERR_EM_INTERPRETER;
568	}
569
570	/* Update guest's eflags and finish. */
571	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
572	\| (eflags & (X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
573
574	/* All done! */
575	*pcbSize = param1.size;
576	return VINF_SUCCESS;
577	#ifdef IN_GC
578	}
579	}
580	#endif
581	return VERR_EM_INTERPRETER;
582	}
583
584	/**
585	* POP Emulation.
586	*/
587	static int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
588	{
589	OP_PARAMVAL param1;
590	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
591	if(VBOX_FAILURE(rc))
592	return VERR_EM_INTERPRETER;
593
594	#ifdef IN_GC
595	if (TRPMHasTrap(pVM))
596	{
597	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
598	{
599	#endif
600	RTGCPTR pParam1 = 0;
601	uint32_t valpar1;
602	RTGCPTR pStackVal;
603
604	/* Read stack value first */
605	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == false)
606	return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
607
608	/* Convert address; don't bother checking limits etc, as we only read here */
609	pStackVal = SELMToFlat(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid, (RTGCPTR)pRegFrame->esp);
610	if (pStackVal == 0)
611	return VERR_EM_INTERPRETER;
612
613	rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
614	if (VBOX_FAILURE(rc))
615	{
616	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
617	return VERR_EM_INTERPRETER;
618	}
619
620	if (param1.type == PARMTYPE_ADDRESS)
621	{
622	pParam1 = (RTGCPTR)param1.val.val32;
623
624	/* pop [esp+xx] uses esp after the actual pop! */
625	AssertCompile(USE_REG_ESP == USE_REG_SP);
626	if ( (pCpu->param1.flags & USE_BASE)
627	&& (pCpu->param1.flags & (USE_REG_GEN16\|USE_REG_GEN32))
628	&& pCpu->param1.base.reg_gen32 == USE_REG_ESP
629	)
630	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
631
632	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
633
634	#ifdef IN_GC
635	/* Safety check (in theory it could cross a page boundary and fault there though) */
636	AssertMsgReturn(pParam1 == pvFault \|\| (RTGCPTR)pRegFrame->esp == pvFault, ("%VGv != %VGv ss:esp=%04X:%VGv\n", pParam1, pvFault, pRegFrame->ss, pRegFrame->esp), VERR_EM_INTERPRETER);
637	#endif
638	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
639	if (VBOX_FAILURE(rc))
640	{
641	AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
642	return VERR_EM_INTERPRETER;
643	}
644
645	/* Update ESP as the last step */
646	pRegFrame->esp += param1.size;
647	}
648	else
649	{
650	#ifndef DEBUG_bird // annoying assertion.
651	AssertFailed();
652	#endif
653	return VERR_EM_INTERPRETER;
654	}
655
656	/* All done! */
657	*pcbSize = param1.size;
658	return VINF_SUCCESS;
659	#ifdef IN_GC
660	}
661	}
662	#endif
663	return VERR_EM_INTERPRETER;
664	}
665
666
667	/**
668	* XOR/OR/AND Emulation.
669	*/
670	static int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
671	PFN_EMULATE_PARAM3 pfnEmulate)
672	{
673	OP_PARAMVAL param1, param2;
674	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
675	if(VBOX_FAILURE(rc))
676	return VERR_EM_INTERPRETER;
677
678	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
679	if(VBOX_FAILURE(rc))
680	return VERR_EM_INTERPRETER;
681
682	#ifdef DEBUG
683	const char *pszInstr;
684
685	if (pCpu->pCurInstr->opcode == OP_XOR)
686	pszInstr = "Xor";
687	else
688	if (pCpu->pCurInstr->opcode == OP_OR)
689	pszInstr = "Or";
690	else
691	if (pCpu->pCurInstr->opcode == OP_AND)
692	pszInstr = "And";
693	#endif
694
695	#ifdef IN_GC
696	if (TRPMHasTrap(pVM))
697	{
698	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
699	{
700	#endif
701	RTGCPTR pParam1;
702	uint32_t valpar1, valpar2;
703
704	if (pCpu->param1.size != pCpu->param2.size)
705	{
706	if (pCpu->param1.size < pCpu->param2.size)
707	{
708	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->eip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
709	return VERR_EM_INTERPRETER;
710	}
711	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
712	pCpu->param2.size = pCpu->param1.size;
713	param2.size = param1.size;
714	}
715
716	/* The destination is always a virtual address */
717	if (param1.type == PARMTYPE_ADDRESS)
718	{
719	pParam1 = (RTGCPTR)param1.val.val32;
720	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
721
722	#ifdef IN_GC
723	/* Safety check (in theory it could cross a page boundary and fault there though) */
724	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv, pParam1=%VGv pvFault=%VGv\n", pRegFrame->eip, pParam1, pvFault), VERR_EM_INTERPRETER);
725	#endif
726	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
727	if (VBOX_FAILURE(rc))
728	{
729	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
730	return VERR_EM_INTERPRETER;
731	}
732	}
733	else
734	{
735	AssertFailed();
736	return VERR_EM_INTERPRETER;
737	}
738
739	/* Register or immediate data */
740	switch(param2.type)
741	{
742	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
743	valpar2 = param2.val.val32;
744	break;
745
746	default:
747	AssertFailed();
748	return VERR_EM_INTERPRETER;
749	}
750
751	/* Data read, emulate instruction. */
752	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
753
754	/* Update guest's eflags and finish. */
755	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
756	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
757
758	/* And write it back */
759	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
760	if (VBOX_SUCCESS(rc))
761	{
762	/* All done! */
763	*pcbSize = param2.size;
764	return VINF_SUCCESS;
765	}
766	#ifdef IN_GC
767	}
768	}
769	#endif
770	return VERR_EM_INTERPRETER;
771	}
772
773	#ifdef IN_GC
774	/**
775	* LOCK XOR/OR/AND Emulation.
776	*/
777	static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
778	uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
779	{
780	OP_PARAMVAL param1, param2;
781	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
782	if(VBOX_FAILURE(rc))
783	return VERR_EM_INTERPRETER;
784
785	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
786	if(VBOX_FAILURE(rc))
787	return VERR_EM_INTERPRETER;
788
789	if (pCpu->param1.size != pCpu->param2.size)
790	{
791	AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
792	("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->eip, pCpu->param1.size, pCpu->param2.size),
793	VERR_EM_INTERPRETER);
794
795	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
796	pCpu->param2.size = pCpu->param1.size;
797	param2.size = param1.size;
798	}
799
800	/* The destination is always a virtual address */
801	AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
802	RTGCPTR GCPtrPar1 = (RTGCPTR)param1.val.val32;
803	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
804
805	# ifdef IN_GC
806	/* Safety check (in theory it could cross a page boundary and fault there though) */
807	Assert( TRPMHasTrap(pVM)
808	&& (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW));
809	AssertMsgReturn(GCPtrPar1 == pvFault, ("eip=%VGv, GCPtrPar1=%VGv pvFault=%VGv\n", pRegFrame->eip, GCPtrPar1, pvFault), VERR_EM_INTERPRETER);
810	# endif
811
812	/* Register and immediate data == PARMTYPE_IMMEDIATE */
813	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
814	RTGCUINTREG ValPar2 = param2.val.val32;
815
816	/* Try emulate it with a one-shot #PF handler in place. */
817	Log2(("%s %RGv imm%d=%RGr\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
818
819	RTGCUINTREG eflags = 0;
820	MMGCRamRegisterTrapHandler(pVM);
821	rc = pfnEmulate(GCPtrPar1, ValPar2, pCpu->param2.size, &eflags);
822	MMGCRamDeregisterTrapHandler(pVM);
823
824	if (RT_FAILURE(rc))
825	{
826	Log(("%s %RGv imm%d=%RGr -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
827	return VERR_EM_INTERPRETER;
828	}
829
830	/* Update guest's eflags and finish. */
831	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
832	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
833
834	*pcbSize = param2.size;
835	return VINF_SUCCESS;
836	}
837	#endif
838
839	/**
840	* ADD, ADC & SUB Emulation.
841	*/
842	static int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
843	PFN_EMULATE_PARAM3 pfnEmulate)
844	{
845	OP_PARAMVAL param1, param2;
846	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
847	if(VBOX_FAILURE(rc))
848	return VERR_EM_INTERPRETER;
849
850	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
851	if(VBOX_FAILURE(rc))
852	return VERR_EM_INTERPRETER;
853
854	#ifdef DEBUG
855	const char *pszInstr;
856
857	if (pCpu->pCurInstr->opcode == OP_SUB)
858	pszInstr = "Sub";
859	else
860	if (pCpu->pCurInstr->opcode == OP_ADD)
861	pszInstr = "Add";
862	else
863	if (pCpu->pCurInstr->opcode == OP_ADC)
864	pszInstr = "Adc";
865	#endif
866
867	#ifdef IN_GC
868	if (TRPMHasTrap(pVM))
869	{
870	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
871	{
872	#endif
873	RTGCPTR pParam1;
874	uint32_t valpar1, valpar2;
875
876	if (pCpu->param1.size != pCpu->param2.size)
877	{
878	if (pCpu->param1.size < pCpu->param2.size)
879	{
880	AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", pszInstr, pRegFrame->eip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
881	return VERR_EM_INTERPRETER;
882	}
883	/* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
884	pCpu->param2.size = pCpu->param1.size;
885	param2.size = param1.size;
886	}
887
888	/* The destination is always a virtual address */
889	if (param1.type == PARMTYPE_ADDRESS)
890	{
891	pParam1 = (RTGCPTR)param1.val.val32;
892	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
893
894	#ifdef IN_GC
895	/* Safety check (in theory it could cross a page boundary and fault there though) */
896	AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
897	#endif
898	rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
899	if (VBOX_FAILURE(rc))
900	{
901	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
902	return VERR_EM_INTERPRETER;
903	}
904	}
905	else
906	{
907	#ifndef DEBUG_bird
908	AssertFailed();
909	#endif
910	return VERR_EM_INTERPRETER;
911	}
912
913	/* Register or immediate data */
914	switch(param2.type)
915	{
916	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
917	valpar2 = param2.val.val32;
918	break;
919
920	default:
921	AssertFailed();
922	return VERR_EM_INTERPRETER;
923	}
924
925	/* Data read, emulate instruction. */
926	uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
927
928	/* Update guest's eflags and finish. */
929	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
930	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
931
932	/* And write it back */
933	rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
934	if (VBOX_SUCCESS(rc))
935	{
936	/* All done! */
937	*pcbSize = param2.size;
938	return VINF_SUCCESS;
939	}
940	#ifdef IN_GC
941	}
942	}
943	#endif
944	return VERR_EM_INTERPRETER;
945	}
946
947	/**
948	* ADC Emulation.
949	*/
950	static int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
951	{
952	if (pRegFrame->eflags.Bits.u1CF)
953	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
954	else
955	return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
956	}
957
958	/**
959	* BTR/C/S Emulation.
960	*/
961	static int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
962	PFN_EMULATE_PARAM2_UINT32 pfnEmulate)
963	{
964	OP_PARAMVAL param1, param2;
965	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
966	if(VBOX_FAILURE(rc))
967	return VERR_EM_INTERPRETER;
968
969	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
970	if(VBOX_FAILURE(rc))
971	return VERR_EM_INTERPRETER;
972
973	#ifdef LOG_ENABLED
974	const char *pszInstr;
975
976	if (pCpu->pCurInstr->opcode == OP_BTR)
977	pszInstr = "Btr";
978	else
979	if (pCpu->pCurInstr->opcode == OP_BTS)
980	pszInstr = "Bts";
981	else
982	if (pCpu->pCurInstr->opcode == OP_BTC)
983	pszInstr = "Btc";
984	#endif
985
986	#ifdef IN_GC
987	if (TRPMHasTrap(pVM))
988	{
989	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
990	{
991	#endif
992	RTGCPTR pParam1;
993	uint32_t valpar1 = 0, valpar2;
994	uint32_t eflags;
995
996	/* The destination is always a virtual address */
997	if (param1.type != PARMTYPE_ADDRESS)
998	return VERR_EM_INTERPRETER;
999
1000	pParam1 = (RTGCPTR)param1.val.val32;
1001	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1002
1003	/* Register or immediate data */
1004	switch(param2.type)
1005	{
1006	case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
1007	valpar2 = param2.val.val32;
1008	break;
1009
1010	default:
1011	AssertFailed();
1012	return VERR_EM_INTERPRETER;
1013	}
1014
1015	Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", pszInstr, pvFault, pParam1, valpar2));
1016	pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
1017	#ifdef IN_GC
1018	/* Safety check. */
1019	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, ("pParam1=%VGv pvFault=%VGv\n", pParam1, pvFault), VERR_EM_INTERPRETER);
1020	#endif
1021	rc = emRamRead(pVM, &valpar1, pParam1, 1);
1022	if (VBOX_FAILURE(rc))
1023	{
1024	AssertMsgFailed(("emRamRead %VGv size=%d failed with %Vrc\n", pParam1, param1.size, rc));
1025	return VERR_EM_INTERPRETER;
1026	}
1027
1028	Log2(("emInterpretBtx: val=%x\n", valpar1));
1029	/* Data read, emulate bit test instruction. */
1030	eflags = pfnEmulate(&valpar1, valpar2 & 0x7);
1031
1032	Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
1033
1034	/* Update guest's eflags and finish. */
1035	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1036	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1037
1038	/* And write it back */
1039	rc = emRamWrite(pVM, pParam1, &valpar1, 1);
1040	if (VBOX_SUCCESS(rc))
1041	{
1042	/* All done! */
1043	*pcbSize = 1;
1044	return VINF_SUCCESS;
1045	}
1046	#ifdef IN_GC
1047	}
1048	}
1049	#endif
1050	return VERR_EM_INTERPRETER;
1051	}
1052
1053	#ifdef IN_GC
1054	/**
1055	* LOCK BTR/C/S Emulation.
1056	*/
1057	static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
1058	uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
1059	{
1060	OP_PARAMVAL param1, param2;
1061	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1062	if(VBOX_FAILURE(rc))
1063	return VERR_EM_INTERPRETER;
1064
1065	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1066	if(VBOX_FAILURE(rc))
1067	return VERR_EM_INTERPRETER;
1068
1069	/* The destination is always a virtual address */
1070	if (param1.type != PARMTYPE_ADDRESS)
1071	return VERR_EM_INTERPRETER;
1072
1073	RTGCPTR GCPtrPar1 = (RTGCPTR)param1.val.val32;
1074	GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1075
1076	/* Register and immediate data == PARMTYPE_IMMEDIATE */
1077	AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
1078	RTGCUINTREG ValPar2 = param2.val.val32;
1079
1080	Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%RGv imm=%RGr\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1081
1082	/* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1083	GCPtrPar1 = (RTGCPTR)((RTGCUINTPTR)GCPtrPar1 + ValPar2 / 8);
1084	ValPar2 &= 7;
1085	# ifdef IN_GC
1086	Assert(TRPMHasTrap(pVM));
1087	AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
1088	("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
1089	VERR_EM_INTERPRETER);
1090	# endif
1091
1092	/* Try emulate it with a one-shot #PF handler in place. */
1093	RTGCUINTREG eflags = 0;
1094	MMGCRamRegisterTrapHandler(pVM);
1095	rc = pfnEmulate(GCPtrPar1, ValPar2, &eflags);
1096	MMGCRamDeregisterTrapHandler(pVM);
1097
1098	if (RT_FAILURE(rc))
1099	{
1100	Log(("emInterpretLockBitTest %s: %RGv imm%d=%RGr -> emulation failed due to page fault!\n",
1101	emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
1102	return VERR_EM_INTERPRETER;
1103	}
1104
1105	Log2(("emInterpretLockBitTest %s: GCPtrPar1=%RGv imm=%RGr CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
1106
1107	/* Update guest's eflags and finish. */
1108	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1109	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1110
1111	*pcbSize = 1;
1112	return VINF_SUCCESS;
1113	}
1114	#endif /* IN_GC */
1115
1116	/**
1117	* MOV emulation.
1118	*/
1119	static int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1120	{
1121	OP_PARAMVAL param1, param2;
1122	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_DEST);
1123	if(VBOX_FAILURE(rc))
1124	return VERR_EM_INTERPRETER;
1125
1126	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1127	if(VBOX_FAILURE(rc))
1128	return VERR_EM_INTERPRETER;
1129
1130	#ifdef IN_GC
1131	if (TRPMHasTrap(pVM))
1132	{
1133	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1134	{
1135	#else
1136	/** @todo Make this the default and don't rely on TRPM information. */
1137	if (param1.type == PARMTYPE_ADDRESS)
1138	{
1139	#endif
1140	RTGCPTR pDest;
1141	uint32_t val32;
1142
1143	switch(param1.type)
1144	{
1145	case PARMTYPE_IMMEDIATE:
1146	if(!(param1.flags & PARAM_VAL32))
1147	return VERR_EM_INTERPRETER;
1148	/* fallthru */
1149
1150	case PARMTYPE_ADDRESS:
1151	pDest = (RTGCPTR)param1.val.val32;
1152	pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
1153	break;
1154
1155	default:
1156	AssertFailed();
1157	return VERR_EM_INTERPRETER;
1158	}
1159
1160	switch(param2.type)
1161	{
1162	case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
1163	val32 = param2.val.val32;
1164	break;
1165
1166	default:
1167	Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->eip));
1168	return VERR_EM_INTERPRETER;
1169	}
1170	LogFlow(("EMInterpretInstruction at %08x: OP_MOV %08X <- %08X (%d) &val32=%08x\n", pRegFrame->eip, pDest, val32, param2.size, &val32));
1171
1172	Assert(param2.size <= 4 && param2.size > 0);
1173
1174	#if 0 /* CSAM/PATM translates aliases which causes this to incorrectly trigger. See #2609 and #1498. */
1175	#ifdef IN_GC
1176	/* Safety check (in theory it could cross a page boundary and fault there though) */
1177	AssertMsgReturn(pDest == pvFault, ("eip=%VGv pDest=%VGv pvFault=%VGv\n", pRegFrame->eip, pDest, pvFault), VERR_EM_INTERPRETER);
1178	#endif
1179	#endif
1180	rc = emRamWrite(pVM, pDest, &val32, param2.size);
1181	if (VBOX_FAILURE(rc))
1182	return VERR_EM_INTERPRETER;
1183
1184	*pcbSize = param2.size;
1185	}
1186	else
1187	{ /* read fault */
1188	RTGCPTR pSrc;
1189	uint32_t val32;
1190
1191	/* Source */
1192	switch(param2.type)
1193	{
1194	case PARMTYPE_IMMEDIATE:
1195	if(!(param2.flags & PARAM_VAL32))
1196	return VERR_EM_INTERPRETER;
1197	/* fallthru */
1198
1199	case PARMTYPE_ADDRESS:
1200	pSrc = (RTGCPTR)param2.val.val32;
1201	pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
1202	break;
1203
1204	default:
1205	return VERR_EM_INTERPRETER;
1206	}
1207
1208	Assert(param1.size <= 4 && param1.size > 0);
1209	#ifdef IN_GC
1210	/* Safety check (in theory it could cross a page boundary and fault there though) */
1211	AssertReturn(pSrc == pvFault, VERR_EM_INTERPRETER);
1212	#endif
1213	rc = emRamRead(pVM, &val32, pSrc, param1.size);
1214	if (VBOX_FAILURE(rc))
1215	return VERR_EM_INTERPRETER;
1216
1217	/* Destination */
1218	switch(param1.type)
1219	{
1220	case PARMTYPE_REGISTER:
1221	switch(param1.size)
1222	{
1223	case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen8, (uint8_t)val32); break;
1224	case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen16, (uint16_t)val32); break;
1225	case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen32, val32); break;
1226	default:
1227	return VERR_EM_INTERPRETER;
1228	}
1229	if (VBOX_FAILURE(rc))
1230	return rc;
1231	break;
1232
1233	default:
1234	return VERR_EM_INTERPRETER;
1235	}
1236	LogFlow(("EMInterpretInstruction: OP_MOV %08X -> %08X (%d)\n", pSrc, val32, param1.size));
1237	}
1238	return VINF_SUCCESS;
1239	#ifdef IN_GC
1240	}
1241	#endif
1242	return VERR_EM_INTERPRETER;
1243	}
1244
1245	/*
1246	* [LOCK] CMPXCHG emulation.
1247	*/
1248	#ifdef IN_GC
1249	static int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1250	{
1251	OP_PARAMVAL param1, param2;
1252
1253	#ifdef LOG_ENABLED
1254	const char *pszInstr;
1255
1256	if (pCpu->prefix & PREFIX_LOCK)
1257	pszInstr = "Lock CmpXchg";
1258	else
1259	pszInstr = "CmpXchg";
1260	#endif
1261
1262	/* Source to make DISQueryParamVal read the register value - ugly hack */
1263	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1264	if(VBOX_FAILURE(rc))
1265	return VERR_EM_INTERPRETER;
1266
1267	rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, &param2, PARAM_SOURCE);
1268	if(VBOX_FAILURE(rc))
1269	return VERR_EM_INTERPRETER;
1270
1271	if (TRPMHasTrap(pVM))
1272	{
1273	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1274	{
1275	RTGCPTR pParam1;
1276	uint32_t valpar, eflags;
1277	#ifdef VBOX_STRICT
1278	uint32_t valpar1 = 0; /// @todo used uninitialized...
1279	#endif
1280
1281	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1282	switch(param1.type)
1283	{
1284	case PARMTYPE_ADDRESS:
1285	pParam1 = (RTGCPTR)param1.val.val32;
1286	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1287
1288	/* Safety check (in theory it could cross a page boundary and fault there though) */
1289	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv pParam1=%VGv pvFault=%VGv\n", pRegFrame->eip, pParam1, pvFault), VERR_EM_INTERPRETER);
1290	break;
1291
1292	default:
1293	return VERR_EM_INTERPRETER;
1294	}
1295
1296	switch(param2.type)
1297	{
1298	case PARMTYPE_IMMEDIATE: /* register actually */
1299	valpar = param2.val.val32;
1300	break;
1301
1302	default:
1303	return VERR_EM_INTERPRETER;
1304	}
1305
1306	LogFlow(("%s %VGv=%08x eax=%08x %08x\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1307
1308	MMGCRamRegisterTrapHandler(pVM);
1309	if (pCpu->prefix & PREFIX_LOCK)
1310	rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1311	else
1312	rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
1313	MMGCRamDeregisterTrapHandler(pVM);
1314
1315	if (VBOX_FAILURE(rc))
1316	{
1317	Log(("%s %VGv=%08x eax=%08x %08x -> emulation failed due to page fault!\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar));
1318	return VERR_EM_INTERPRETER;
1319	}
1320
1321	LogFlow(("%s %VGv=%08x eax=%08x %08x ZF=%d\n", pszInstr, pParam1, valpar1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
1322
1323	/* Update guest's eflags and finish. */
1324	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1325	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1326
1327	*pcbSize = param2.size;
1328	return VINF_SUCCESS;
1329	}
1330	}
1331	return VERR_EM_INTERPRETER;
1332	}
1333
1334	/*
1335	* [LOCK] CMPXCHG8B emulation.
1336	*/
1337	static int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1338	{
1339	OP_PARAMVAL param1;
1340
1341	#ifdef LOG_ENABLED
1342	const char *pszInstr;
1343
1344	if (pCpu->prefix & PREFIX_LOCK)
1345	pszInstr = "Lock CmpXchg8b";
1346	else
1347	pszInstr = "CmpXchg8b";
1348	#endif
1349
1350	/* Source to make DISQueryParamVal read the register value - ugly hack */
1351	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1352	if(VBOX_FAILURE(rc))
1353	return VERR_EM_INTERPRETER;
1354
1355	if (TRPMHasTrap(pVM))
1356	{
1357	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1358	{
1359	RTGCPTR pParam1;
1360	uint32_t eflags;
1361
1362	AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
1363	switch(param1.type)
1364	{
1365	case PARMTYPE_ADDRESS:
1366	pParam1 = (RTGCPTR)param1.val.val32;
1367	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1368
1369	/* Safety check (in theory it could cross a page boundary and fault there though) */
1370	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv pParam1=%VGv pvFault=%VGv\n", pRegFrame->eip, pParam1, pvFault), VERR_EM_INTERPRETER);
1371	break;
1372
1373	default:
1374	return VERR_EM_INTERPRETER;
1375	}
1376
1377	LogFlow(("%s %VGv=%08x eax=%08x\n", pszInstr, pParam1, pRegFrame->eax));
1378
1379	MMGCRamRegisterTrapHandler(pVM);
1380	if (pCpu->prefix & PREFIX_LOCK)
1381	rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1382	else
1383	rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
1384	MMGCRamDeregisterTrapHandler(pVM);
1385
1386	if (VBOX_FAILURE(rc))
1387	{
1388	Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", pszInstr, pParam1, pRegFrame->eax));
1389	return VERR_EM_INTERPRETER;
1390	}
1391
1392	LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", pszInstr, pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
1393
1394	/* Update guest's eflags and finish. */
1395	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1396	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1397
1398	*pcbSize = 8;
1399	return VINF_SUCCESS;
1400	}
1401	}
1402	return VERR_EM_INTERPRETER;
1403	}
1404	#endif
1405
1406	/*
1407	* [LOCK] XADD emulation.
1408	*/
1409	#ifdef IN_GC
1410	static int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1411	{
1412	OP_PARAMVAL param1;
1413	uint32_t *pParamReg2;
1414	size_t cbSizeParamReg2;
1415
1416	/* Source to make DISQueryParamVal read the register value - ugly hack */
1417	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1418	if(VBOX_FAILURE(rc))
1419	return VERR_EM_INTERPRETER;
1420
1421	rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
1422	Assert(cbSizeParamReg2 <= 4);
1423	if(VBOX_FAILURE(rc))
1424	return VERR_EM_INTERPRETER;
1425
1426	if (TRPMHasTrap(pVM))
1427	{
1428	if (TRPMGetErrorCode(pVM) & X86_TRAP_PF_RW)
1429	{
1430	RTGCPTR pParam1;
1431	uint32_t eflags;
1432	#ifdef VBOX_STRICT
1433	uint32_t valpar1 = 0; /// @todo used uninitialized...
1434	#endif
1435
1436	AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
1437	switch(param1.type)
1438	{
1439	case PARMTYPE_ADDRESS:
1440	pParam1 = (RTGCPTR)param1.val.val32;
1441	pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
1442
1443	/* Safety check (in theory it could cross a page boundary and fault there though) */
1444	AssertMsgReturn(pParam1 == pvFault, ("eip=%VGv pParam1=%VGv pvFault=%VGv\n", pRegFrame->eip, pParam1, pvFault), VERR_EM_INTERPRETER);
1445	break;
1446
1447	default:
1448	return VERR_EM_INTERPRETER;
1449	}
1450
1451	LogFlow(("XAdd %VGv=%08x reg=%08x\n", pParam1, *pParamReg2));
1452
1453	MMGCRamRegisterTrapHandler(pVM);
1454	if (pCpu->prefix & PREFIX_LOCK)
1455	rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1456	else
1457	rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
1458	MMGCRamDeregisterTrapHandler(pVM);
1459
1460	if (VBOX_FAILURE(rc))
1461	{
1462	Log(("XAdd %VGv=%08x reg=%08x -> emulation failed due to page fault!\n", pParam1, valpar1, *pParamReg2));
1463	return VERR_EM_INTERPRETER;
1464	}
1465
1466	LogFlow(("XAdd %VGv=%08x reg=%08x ZF=%d\n", pParam1, valpar1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
1467
1468	/* Update guest's eflags and finish. */
1469	pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF))
1470	\| (eflags & (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF));
1471
1472	*pcbSize = cbSizeParamReg2;
1473	return VINF_SUCCESS;
1474	}
1475	}
1476	return VERR_EM_INTERPRETER;
1477	}
1478	#endif
1479
1480	/**
1481	* Interpret IRET (currently only to V86 code)
1482	*
1483	* @returns VBox status code.
1484	* @param pVM The VM handle.
1485	* @param pRegFrame The register frame.
1486	*
1487	*/
1488	EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
1489	{
1490	RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
1491	RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
1492	int rc;
1493
1494	rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
1495	rc \|= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
1496	rc \|= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
1497	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1498	AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
1499
1500	rc \|= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
1501	rc \|= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
1502	rc \|= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
1503	rc \|= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
1504	rc \|= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
1505	rc \|= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
1506	AssertRCReturn(rc, VERR_EM_INTERPRETER);
1507
1508	pRegFrame->eip = eip & 0xffff;
1509	pRegFrame->cs = cs;
1510
1511	/* Mask away all reserved bits */
1512	uMask = X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_RF \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP \| X86_EFL_ID;
1513	eflags &= uMask;
1514
1515	#ifndef IN_RING0
1516	CPUMRawSetEFlags(pVM, pRegFrame, eflags);
1517	#endif
1518	Assert((pRegFrame->eflags.u32 & (X86_EFL_IF\|X86_EFL_IOPL)) == X86_EFL_IF);
1519
1520	pRegFrame->esp = esp;
1521	pRegFrame->ss = ss;
1522	pRegFrame->ds = ds;
1523	pRegFrame->es = es;
1524	pRegFrame->fs = fs;
1525	pRegFrame->gs = gs;
1526
1527	return VINF_SUCCESS;
1528	}
1529
1530
1531	/**
1532	* IRET Emulation.
1533	*/
1534	static int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1535	{
1536	/* only allow direct calls to EMInterpretIret for now */
1537	return VERR_EM_INTERPRETER;
1538	}
1539
1540	/**
1541	* INVLPG Emulation.
1542	*/
1543
1544	/**
1545	* Interpret INVLPG
1546	*
1547	* @returns VBox status code.
1548	* @param pVM The VM handle.
1549	* @param pRegFrame The register frame.
1550	* @param pAddrGC Operand address
1551	*
1552	*/
1553	EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
1554	{
1555	int rc;
1556
1557	/** @todo is addr always a flat linear address or ds based
1558	* (in absence of segment override prefixes)????
1559	*/
1560	#ifdef IN_GC
1561	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1562	LogFlow(("GC: EMULATE: invlpg %08X\n", pAddrGC));
1563	rc = PGMGCInvalidatePage(pVM, pAddrGC);
1564	#else
1565	rc = PGMInvalidatePage(pVM, pAddrGC);
1566	#endif
1567	if (VBOX_SUCCESS(rc))
1568	return VINF_SUCCESS;
1569	Log(("PGMInvalidatePage %VGv returned %VGv (%d)\n", pAddrGC, rc, rc));
1570	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1571	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1572	return VERR_EM_INTERPRETER;
1573	}
1574
1575	static int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1576	{
1577	OP_PARAMVAL param1;
1578	RTGCPTR addr;
1579
1580	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1581	if(VBOX_FAILURE(rc))
1582	return VERR_EM_INTERPRETER;
1583
1584	switch(param1.type)
1585	{
1586	case PARMTYPE_IMMEDIATE:
1587	case PARMTYPE_ADDRESS:
1588	if(!(param1.flags & PARAM_VAL32))
1589	return VERR_EM_INTERPRETER;
1590	addr = (RTGCPTR)param1.val.val32;
1591	break;
1592
1593	default:
1594	return VERR_EM_INTERPRETER;
1595	}
1596
1597	/** @todo is addr always a flat linear address or ds based
1598	* (in absence of segment override prefixes)????
1599	*/
1600	#ifdef IN_GC
1601	// Note: we could also use PGMFlushPage here, but it currently doesn't always use invlpg!!!!!!!!!!
1602	LogFlow(("GC: EMULATE: invlpg %08X\n", addr));
1603	rc = PGMGCInvalidatePage(pVM, addr);
1604	#else
1605	rc = PGMInvalidatePage(pVM, addr);
1606	#endif
1607	if (VBOX_SUCCESS(rc))
1608	return VINF_SUCCESS;
1609	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1610	return VERR_EM_INTERPRETER;
1611	}
1612
1613	/**
1614	* CPUID Emulation.
1615	*/
1616
1617	/**
1618	* Interpret CPUID given the parameters in the CPU context
1619	*
1620	* @returns VBox status code.
1621	* @param pVM The VM handle.
1622	* @param pRegFrame The register frame.
1623	*
1624	*/
1625	EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
1626	{
1627	CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
1628	return VINF_SUCCESS;
1629	}
1630
1631	static int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1632	{
1633	uint32_t iLeaf = pRegFrame->eax; NOREF(iLeaf);
1634
1635	int rc = EMInterpretCpuId(pVM, pRegFrame);
1636	Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
1637	return rc;
1638	}
1639
1640	/**
1641	* MOV CRx Emulation.
1642	*/
1643
1644	/**
1645	* Interpret CRx read
1646	*
1647	* @returns VBox status code.
1648	* @param pVM The VM handle.
1649	* @param pRegFrame The register frame.
1650	* @param DestRegGen General purpose register index (USE_REG_E**))
1651	* @param SrcRegCRx CRx register index (USE_REG_CR*)
1652	*
1653	*/
1654	EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1655	{
1656	uint64_t val64;
1657
1658	int rc = CPUMGetGuestCRx(pVM, SrcRegCrx, &val64);
1659	AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1660	/** @todo AMD64 */
1661	rc = DISWriteReg32(pRegFrame, DestRegGen, val64);
1662	if(VBOX_SUCCESS(rc))
1663	{
1664	LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
1665	return VINF_SUCCESS;
1666	}
1667	return VERR_EM_INTERPRETER;
1668	}
1669
1670
1671	/**
1672	* Interpret LMSW
1673	*
1674	* @returns VBox status code.
1675	* @param pVM The VM handle.
1676	* @param u16Data LMSW source data.
1677	*
1678	*/
1679	EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data)
1680	{
1681	uint32_t OldCr0 = CPUMGetGuestCR0(pVM);
1682
1683	/* don't use this path to go into protected mode! */
1684	Assert(OldCr0 & X86_CR0_PE);
1685	if (!(OldCr0 & X86_CR0_PE))
1686	return VERR_EM_INTERPRETER;
1687
1688	/* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
1689	uint32_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
1690	\| (u16Data & (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS));
1691
1692	#ifdef IN_GC
1693	/* Need to change the hyper CR0? Doing it the lazy way then. */
1694	if ( (OldCr0 & (X86_CR0_AM \| X86_CR0_WP))
1695	!= (NewCr0 & (X86_CR0_AM \| X86_CR0_WP)))
1696	{
1697	Log(("EMInterpretLMSW: CR0: %#x->%#x => R3\n", OldCr0, NewCr0));
1698	VM_FF_SET(pVM, VM_FF_TO_R3);
1699	}
1700	#endif
1701
1702	return CPUMSetGuestCR0(pVM, NewCr0);
1703	}
1704
1705
1706	/**
1707	* Interpret CLTS
1708	*
1709	* @returns VBox status code.
1710	* @param pVM The VM handle.
1711	*
1712	*/
1713	EMDECL(int) EMInterpretCLTS(PVM pVM)
1714	{
1715	uint32_t cr0 = CPUMGetGuestCR0(pVM);
1716	if (!(cr0 & X86_CR0_TS))
1717	return VINF_SUCCESS;
1718	return CPUMSetGuestCR0(pVM, cr0 & ~X86_CR0_TS);
1719	}
1720
1721	static int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1722	{
1723	return EMInterpretCLTS(pVM);
1724	}
1725
1726	/**
1727	* Interpret CRx write
1728	*
1729	* @returns VBox status code.
1730	* @param pVM The VM handle.
1731	* @param pRegFrame The register frame.
1732	* @param DestRegCRx CRx register index (USE_REG_CR*)
1733	* @param SrcRegGen General purpose register index (USE_REG_E**))
1734	*
1735	*/
1736	EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
1737	{
1738	uint32_t val32;
1739	uint32_t oldval;
1740	/** @todo Clean up this mess. */
1741
1742	/** @todo AMD64 */
1743	int rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1744	if (VBOX_SUCCESS(rc))
1745	{
1746	switch (DestRegCrx)
1747	{
1748	case USE_REG_CR0:
1749	oldval = CPUMGetGuestCR0(pVM);
1750	#ifdef IN_GC
1751	/* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
1752	if ( (val32 & (X86_CR0_WP \| X86_CR0_AM))
1753	!= (oldval & (X86_CR0_WP \| X86_CR0_AM)))
1754	return VERR_EM_INTERPRETER;
1755	#endif
1756	CPUMSetGuestCR0(pVM, val32);
1757	val32 = CPUMGetGuestCR0(pVM);
1758	if ( (oldval & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE))
1759	!= (val32 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)))
1760	{
1761	/* global flush */
1762	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1763	AssertRCReturn(rc, rc);
1764	}
1765	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
1766
1767	case USE_REG_CR2:
1768	rc = CPUMSetGuestCR2(pVM, val32); AssertRC(rc);
1769	return VINF_SUCCESS;
1770
1771	case USE_REG_CR3:
1772	/* Reloading the current CR3 means the guest just wants to flush the TLBs */
1773	rc = CPUMSetGuestCR3(pVM, val32); AssertRC(rc);
1774	if (CPUMGetGuestCR0(pVM) & X86_CR0_PG)
1775	{
1776	/* flush */
1777	rc = PGMFlushTLB(pVM, val32, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
1778	AssertRCReturn(rc, rc);
1779	}
1780	return VINF_SUCCESS;
1781
1782	case USE_REG_CR4:
1783	oldval = CPUMGetGuestCR4(pVM);
1784	rc = CPUMSetGuestCR4(pVM, val32); AssertRC(rc);
1785	val32 = CPUMGetGuestCR4(pVM);
1786	if ( (oldval & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE))
1787	!= (val32 & (X86_CR4_PGE\|X86_CR4_PAE\|X86_CR4_PSE)))
1788	{
1789	/* global flush */
1790	rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
1791	AssertRCReturn(rc, rc);
1792	}
1793	# ifdef IN_GC
1794	/* Feeling extremely lazy. */
1795	if ( (oldval & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME))
1796	!= (val32 & (X86_CR4_OSFSXR\|X86_CR4_OSXMMEEXCPT\|X86_CR4_PCE\|X86_CR4_MCE\|X86_CR4_PAE\|X86_CR4_DE\|X86_CR4_TSD\|X86_CR4_PVI\|X86_CR4_VME)))
1797	{
1798	Log(("emInterpretMovCRx: CR4: %#x->%#x => R3\n", oldval, val32));
1799	VM_FF_SET(pVM, VM_FF_TO_R3);
1800	}
1801	# endif
1802	return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
1803
1804	default:
1805	AssertFailed();
1806	case USE_REG_CR1: /* illegal op */
1807	break;
1808	}
1809	}
1810	return VERR_EM_INTERPRETER;
1811	}
1812
1813	static int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1814	{
1815	if (pCpu->param1.flags == USE_REG_GEN32 && pCpu->param2.flags == USE_REG_CR)
1816	return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen32, pCpu->param2.base.reg_ctrl);
1817	if (pCpu->param1.flags == USE_REG_CR && pCpu->param2.flags == USE_REG_GEN32)
1818	return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen32);
1819	AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
1820	return VERR_EM_INTERPRETER;
1821	}
1822
1823	/**
1824	* MOV DRx
1825	*/
1826
1827	/**
1828	* Interpret DRx write
1829	*
1830	* @returns VBox status code.
1831	* @param pVM The VM handle.
1832	* @param pRegFrame The register frame.
1833	* @param DestRegDRx DRx register index (USE_REG_DR*)
1834	* @param SrcRegGen General purpose register index (USE_REG_E**))
1835	*
1836	*/
1837	EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1838	{
1839	uint32_t val32;
1840
1841	int rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1842	if (VBOX_SUCCESS(rc))
1843	{
1844	rc = CPUMSetGuestDRx(pVM, DestRegDrx, val32);
1845	if (VBOX_SUCCESS(rc))
1846	return rc;
1847	AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1848	}
1849	return VERR_EM_INTERPRETER;
1850	}
1851
1852	/**
1853	* Interpret DRx read
1854	*
1855	* @returns VBox status code.
1856	* @param pVM The VM handle.
1857	* @param pRegFrame The register frame.
1858	* @param DestRegGen General purpose register index (USE_REG_E**))
1859	* @param SrcRegDRx DRx register index (USE_REG_DR*)
1860	*
1861	*/
1862	EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1863	{
1864	uint32_t val32;
1865
1866	int rc = CPUMGetGuestDRx(pVM, SrcRegDrx, &val32);
1867	AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1868	rc = DISWriteReg32(pRegFrame, DestRegGen, val32);
1869	if (VBOX_SUCCESS(rc))
1870	return VINF_SUCCESS;
1871	return VERR_EM_INTERPRETER;
1872	}
1873
1874	static int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1875	{
1876	int rc = VERR_EM_INTERPRETER;
1877
1878	if(pCpu->param1.flags == USE_REG_GEN32 && pCpu->param2.flags == USE_REG_DBG)
1879	{
1880	rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen32, pCpu->param2.base.reg_dbg);
1881	}
1882	else
1883	if(pCpu->param1.flags == USE_REG_DBG && pCpu->param2.flags == USE_REG_GEN32)
1884	{
1885	rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen32);
1886	}
1887	else
1888	AssertMsgFailed(("Unexpected debug register move\n"));
1889	return rc;
1890	}
1891
1892	/**
1893	* LLDT Emulation.
1894	*/
1895	static int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1896	{
1897	OP_PARAMVAL param1;
1898	RTSEL sel;
1899
1900	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1901	if(VBOX_FAILURE(rc))
1902	return VERR_EM_INTERPRETER;
1903
1904	switch(param1.type)
1905	{
1906	case PARMTYPE_ADDRESS:
1907	return VERR_EM_INTERPRETER; //feeling lazy right now
1908
1909	case PARMTYPE_IMMEDIATE:
1910	if(!(param1.flags & PARAM_VAL16))
1911	return VERR_EM_INTERPRETER;
1912	sel = (RTSEL)param1.val.val16;
1913	break;
1914
1915	default:
1916	return VERR_EM_INTERPRETER;
1917	}
1918
1919	if (sel == 0)
1920	{
1921	if (CPUMGetHyperLDTR(pVM) == 0)
1922	{
1923	// this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
1924	return VINF_SUCCESS;
1925	}
1926	}
1927	//still feeling lazy
1928	return VERR_EM_INTERPRETER;
1929	}
1930
1931	#ifdef IN_GC
1932	/**
1933	* STI Emulation.
1934	*
1935	* @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
1936	*/
1937	static int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1938	{
1939	PPATMGCSTATE pGCState = PATMQueryGCState(pVM);
1940
1941	if(!pGCState)
1942	{
1943	Assert(pGCState);
1944	return VERR_EM_INTERPRETER;
1945	}
1946	pGCState->uVMFlags \|= X86_EFL_IF;
1947
1948	Assert(pRegFrame->eflags.u32 & X86_EFL_IF);
1949	Assert(pvFault == SELMToFlat(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip));
1950
1951	pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
1952	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
1953
1954	return VINF_SUCCESS;
1955	}
1956	#endif /* IN_GC */
1957
1958
1959	/**
1960	* HLT Emulation.
1961	*/
1962	static int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1963	{
1964	return VINF_EM_HALT;
1965	}
1966
1967
1968	/**
1969	* RDTSC Emulation.
1970	*/
1971
1972	/**
1973	* Interpret RDTSC
1974	*
1975	* @returns VBox status code.
1976	* @param pVM The VM handle.
1977	* @param pRegFrame The register frame.
1978	*
1979	*/
1980	EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
1981	{
1982	unsigned uCR4 = CPUMGetGuestCR4(pVM);
1983
1984	if (uCR4 & X86_CR4_TSD)
1985	return VERR_EM_INTERPRETER; /* genuine #GP */
1986
1987	uint64_t uTicks = TMCpuTickGet(pVM);
1988
1989	pRegFrame->eax = uTicks;
1990	pRegFrame->edx = (uTicks >> 32ULL);
1991
1992	return VINF_SUCCESS;
1993	}
1994
1995	static int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1996	{
1997	return EMInterpretRdtsc(pVM, pRegFrame);
1998	}
1999
2000	/**
2001	* MONITOR Emulation.
2002	*/
2003	static int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2004	{
2005	uint32_t u32Dummy, u32ExtFeatures, cpl;
2006
2007	if (pRegFrame->ecx != 0)
2008	return VERR_EM_INTERPRETER; /* illegal value. */
2009
2010	/* Get the current privilege level. */
2011	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2012	if (cpl != 0)
2013	return VERR_EM_INTERPRETER; /* supervisor only */
2014
2015	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2016	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2017	return VERR_EM_INTERPRETER; /* not supported */
2018
2019	return VINF_SUCCESS;
2020	}
2021
2022
2023	/**
2024	* MWAIT Emulation.
2025	*/
2026	static int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2027	{
2028	uint32_t u32Dummy, u32ExtFeatures, cpl;
2029
2030	if (pRegFrame->ecx != 0)
2031	return VERR_EM_INTERPRETER; /* illegal value. */
2032
2033	/* Get the current privilege level. */
2034	cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2035	if (cpl != 0)
2036	return VERR_EM_INTERPRETER; /* supervisor only */
2037
2038	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
2039	if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
2040	return VERR_EM_INTERPRETER; /* not supported */
2041
2042	/** @todo not completely correct */
2043	return VINF_EM_HALT;
2044	}
2045
2046
2047	/**
2048	* Internal worker.
2049	* @copydoc EMInterpretInstructionCPU
2050	*/
2051	DECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
2052	{
2053	Assert(pcbSize);
2054	*pcbSize = 0;
2055
2056	/*
2057	* Only supervisor guest code!!
2058	* And no complicated prefixes.
2059	*/
2060	/* Get the current privilege level. */
2061	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
2062	if ( cpl != 0
2063	&& pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
2064	{
2065	Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
2066	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedUserMode));
2067	return VERR_EM_INTERPRETER;
2068	}
2069
2070	#ifdef IN_GC
2071	if ( (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP))
2072	\|\| ( (pCpu->prefix & PREFIX_LOCK)
2073	&& pCpu->pCurInstr->opcode != OP_CMPXCHG
2074	&& pCpu->pCurInstr->opcode != OP_CMPXCHG8B
2075	&& pCpu->pCurInstr->opcode != OP_XADD
2076	&& pCpu->pCurInstr->opcode != OP_OR
2077	&& pCpu->pCurInstr->opcode != OP_BTR
2078	)
2079	)
2080	#else
2081	if (pCpu->prefix & (PREFIX_REPNE \| PREFIX_REP \| PREFIX_LOCK))
2082	#endif
2083	{
2084	//Log(("EMInterpretInstruction: wrong prefix!!\n"));
2085	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedPrefix));
2086	return VERR_EM_INTERPRETER;
2087	}
2088
2089	int rc;
2090	switch (pCpu->pCurInstr->opcode)
2091	{
2092	#ifdef IN_GC
2093	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2094	case opcode:\
2095	if (pCpu->prefix & PREFIX_LOCK) \
2096	rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
2097	else \
2098	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2099	if (VBOX_SUCCESS(rc)) \
2100	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2101	else \
2102	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2103	return rc
2104	#else
2105	# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2106	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2107	#endif
2108	#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
2109	case opcode:\
2110	rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
2111	if (VBOX_SUCCESS(rc)) \
2112	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2113	else \
2114	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2115	return rc
2116
2117	#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
2118	INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
2119	#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
2120	INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
2121
2122	#define INTERPRET_CASE(opcode, Instr) \
2123	case opcode:\
2124	rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
2125	if (VBOX_SUCCESS(rc)) \
2126	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Instr)); \
2127	else \
2128	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); \
2129	return rc
2130	#define INTERPRET_STAT_CASE(opcode, Instr) \
2131	case opcode: STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
2132
2133	INTERPRET_CASE(OP_XCHG,Xchg);
2134	INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
2135	INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
2136	INTERPRET_CASE(OP_POP,Pop);
2137	INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
2138	INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
2139	INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
2140	INTERPRET_CASE(OP_MOV,Mov);
2141	INTERPRET_CASE(OP_INVLPG,InvlPg);
2142	INTERPRET_CASE(OP_CPUID,CpuId);
2143	INTERPRET_CASE(OP_MOV_CR,MovCRx);
2144	INTERPRET_CASE(OP_MOV_DR,MovDRx);
2145	INTERPRET_CASE(OP_LLDT,LLdt);
2146	INTERPRET_CASE(OP_CLTS,Clts);
2147	INTERPRET_CASE(OP_MONITOR, Monitor);
2148	INTERPRET_CASE(OP_MWAIT, MWait);
2149	INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
2150	INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
2151	INTERPRET_CASE(OP_ADC,Adc);
2152	INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
2153	INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
2154	INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
2155	INTERPRET_CASE(OP_RDTSC,Rdtsc);
2156	#ifdef IN_GC
2157	INTERPRET_CASE(OP_STI,Sti);
2158	INTERPRET_CASE(OP_CMPXCHG, CmpXchg);
2159	INTERPRET_CASE(OP_CMPXCHG8B, CmpXchg8b);
2160	INTERPRET_CASE(OP_XADD, XAdd);
2161	#endif
2162	INTERPRET_CASE(OP_HLT,Hlt);
2163	INTERPRET_CASE(OP_IRET,Iret);
2164	#ifdef VBOX_WITH_STATISTICS
2165	#ifndef IN_GC
2166	INTERPRET_STAT_CASE(OP_CMPXCHG,CmpXchg);
2167	INTERPRET_STAT_CASE(OP_CMPXCHG8B, CmpXchg8b);
2168	INTERPRET_STAT_CASE(OP_XADD, XAdd);
2169	#endif
2170	INTERPRET_STAT_CASE(OP_MOVNTPS,MovNTPS);
2171	INTERPRET_STAT_CASE(OP_STOSWD,StosWD);
2172	INTERPRET_STAT_CASE(OP_WBINVD,WbInvd);
2173	#endif
2174	default:
2175	Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
2176	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->CTXMID(Stat,FailedMisc));
2177	return VERR_EM_INTERPRETER;
2178	#undef INTERPRET_CASE_EX_PARAM2
2179	#undef INTERPRET_STAT_CASE
2180	#undef INTERPRET_CASE_EX
2181	#undef INTERPRET_CASE
2182	}
2183	AssertFailed();
2184	return VERR_INTERNAL_ERROR;
2185	}
2186
2187
2188	/**
2189	* Sets the PC for which interrupts should be inhibited.
2190	*
2191	* @param pVM The VM handle.
2192	* @param PC The PC.
2193	*/
2194	EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
2195	{
2196	pVM->em.s.GCPtrInhibitInterrupts = PC;
2197	VM_FF_SET(pVM, VM_FF_INHIBIT_INTERRUPTS);
2198	}
2199
2200
2201	/**
2202	* Gets the PC for which interrupts should be inhibited.
2203	*
2204	* There are a few instructions which inhibits or delays interrupts
2205	* for the instruction following them. These instructions are:
2206	* - STI
2207	* - MOV SS, r/m16
2208	* - POP SS
2209	*
2210	* @returns The PC for which interrupts should be inhibited.
2211	* @param pVM VM handle.
2212	*
2213	*/
2214	EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM)
2215	{
2216	return pVM->em.s.GCPtrInhibitInterrupts;
2217	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 8213

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