VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/EMAll.cpp@ 82968

Last change on this file since 82968 was 82968, checked in by vboxsync, 5 years ago

Copyright year updates by scm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 46.1 KB
Line 
1/* $Id: EMAll.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor(/Manager) - All contexts
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/selm.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/iem.h>
28#include <VBox/vmm/iom.h>
29#include <VBox/vmm/hm.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/vmm/vmm.h>
32#include <VBox/vmm/stam.h>
33#include "EMInternal.h"
34#include <VBox/vmm/vmcc.h>
35#include <VBox/param.h>
36#include <VBox/err.h>
37#include <VBox/dis.h>
38#include <VBox/disopcode.h>
39#include <VBox/log.h>
40#include <iprt/assert.h>
41#include <iprt/string.h>
42
43
44
45
46/**
47 * Get the current execution manager status.
48 *
49 * @returns Current status.
50 * @param pVCpu The cross context virtual CPU structure.
51 */
52VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu)
53{
54 return pVCpu->em.s.enmState;
55}
56
57
58/**
59 * Sets the current execution manager status. (use only when you know what you're doing!)
60 *
61 * @param pVCpu The cross context virtual CPU structure.
62 * @param enmNewState The new state, EMSTATE_WAIT_SIPI or EMSTATE_HALTED.
63 */
64VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState)
65{
66 /* Only allowed combination: */
67 Assert(pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI && enmNewState == EMSTATE_HALTED);
68 pVCpu->em.s.enmState = enmNewState;
69}
70
71
72/**
73 * Sets the PC for which interrupts should be inhibited.
74 *
75 * @param pVCpu The cross context virtual CPU structure.
76 * @param PC The PC.
77 */
78VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC)
79{
80 pVCpu->em.s.GCPtrInhibitInterrupts = PC;
81 VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
82}
83
84
85/**
86 * Gets the PC for which interrupts should be inhibited.
87 *
88 * There are a few instructions which inhibits or delays interrupts
89 * for the instruction following them. These instructions are:
90 * - STI
91 * - MOV SS, r/m16
92 * - POP SS
93 *
94 * @returns The PC for which interrupts should be inhibited.
95 * @param pVCpu The cross context virtual CPU structure.
96 *
97 */
98VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu)
99{
100 return pVCpu->em.s.GCPtrInhibitInterrupts;
101}
102
103
104/**
105 * Checks if interrupt inhibiting is enabled for the current instruction.
106 *
107 * @returns true if interrupts are inhibited, false if not.
108 * @param pVCpu The cross context virtual CPU structure.
109 */
110VMMDECL(bool) EMIsInhibitInterruptsActive(PVMCPU pVCpu)
111{
112 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
113 return false;
114 if (pVCpu->em.s.GCPtrInhibitInterrupts == CPUMGetGuestRIP(pVCpu))
115 return true;
116 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
117 return false;
118}
119
120
121/**
122 * Enables / disable hypercall instructions.
123 *
124 * This interface is used by GIM to tell the execution monitors whether the
125 * hypercall instruction (VMMCALL & VMCALL) are allowed or should \#UD.
126 *
127 * @param pVCpu The cross context virtual CPU structure this applies to.
128 * @param fEnabled Whether hypercall instructions are enabled (true) or not.
129 */
130VMMDECL(void) EMSetHypercallInstructionsEnabled(PVMCPU pVCpu, bool fEnabled)
131{
132 pVCpu->em.s.fHypercallEnabled = fEnabled;
133}
134
135
136/**
137 * Checks if hypercall instructions (VMMCALL & VMCALL) are enabled or not.
138 *
139 * @returns true if enabled, false if not.
140 * @param pVCpu The cross context virtual CPU structure.
141 *
142 * @note If this call becomes a performance factor, we can make the data
143 * field available thru a read-only view in VMCPU. See VM::cpum.ro.
144 */
145VMMDECL(bool) EMAreHypercallInstructionsEnabled(PVMCPU pVCpu)
146{
147 return pVCpu->em.s.fHypercallEnabled;
148}
149
150
151/**
152 * Prepare an MWAIT - essentials of the MONITOR instruction.
153 *
154 * @returns VINF_SUCCESS
155 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
156 * @param rax The content of RAX.
157 * @param rcx The content of RCX.
158 * @param rdx The content of RDX.
159 * @param GCPhys The physical address corresponding to rax.
160 */
161VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys)
162{
163 pVCpu->em.s.MWait.uMonitorRAX = rax;
164 pVCpu->em.s.MWait.uMonitorRCX = rcx;
165 pVCpu->em.s.MWait.uMonitorRDX = rdx;
166 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_MONITOR_ACTIVE;
167 /** @todo Make use of GCPhys. */
168 NOREF(GCPhys);
169 /** @todo Complete MONITOR implementation. */
170 return VINF_SUCCESS;
171}
172
173
174/**
175 * Checks if the monitor hardware is armed / active.
176 *
177 * @returns true if armed, false otherwise.
178 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
179 */
180VMM_INT_DECL(bool) EMMonitorIsArmed(PVMCPU pVCpu)
181{
182 return RT_BOOL(pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_MONITOR_ACTIVE);
183}
184
185
186/**
187 * Checks if we're in a MWAIT.
188 *
189 * @retval 1 if regular,
190 * @retval > 1 if MWAIT with EMMWAIT_FLAG_BREAKIRQIF0
191 * @retval 0 if not armed
192 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
193 */
194VMM_INT_DECL(unsigned) EMMonitorWaitIsActive(PVMCPU pVCpu)
195{
196 uint32_t fWait = pVCpu->em.s.MWait.fWait;
197 AssertCompile(EMMWAIT_FLAG_ACTIVE == 1);
198 AssertCompile(EMMWAIT_FLAG_BREAKIRQIF0 == 2);
199 AssertCompile((EMMWAIT_FLAG_ACTIVE << 1) == EMMWAIT_FLAG_BREAKIRQIF0);
200 return fWait & (EMMWAIT_FLAG_ACTIVE | ((fWait & EMMWAIT_FLAG_ACTIVE) << 1));
201}
202
203
204/**
205 * Performs an MWAIT.
206 *
207 * @returns VINF_SUCCESS
208 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
209 * @param rax The content of RAX.
210 * @param rcx The content of RCX.
211 */
212VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx)
213{
214 pVCpu->em.s.MWait.uMWaitRAX = rax;
215 pVCpu->em.s.MWait.uMWaitRCX = rcx;
216 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_ACTIVE;
217 if (rcx)
218 pVCpu->em.s.MWait.fWait |= EMMWAIT_FLAG_BREAKIRQIF0;
219 else
220 pVCpu->em.s.MWait.fWait &= ~EMMWAIT_FLAG_BREAKIRQIF0;
221 /** @todo not completely correct?? */
222 return VINF_EM_HALT;
223}
224
225
226/**
227 * Clears any address-range monitoring that is active.
228 *
229 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
230 */
231VMM_INT_DECL(void) EMMonitorWaitClear(PVMCPU pVCpu)
232{
233 LogFlowFunc(("Clearing MWAIT\n"));
234 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
235}
236
237
238/**
239 * Determine if we should continue execution in HM after encountering an mwait
240 * instruction.
241 *
242 * Clears MWAIT flags if returning @c true.
243 *
244 * @returns true if we should continue, false if we should halt.
245 * @param pVCpu The cross context virtual CPU structure.
246 * @param pCtx Current CPU context.
247 */
248VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx)
249{
250 if (CPUMGetGuestGif(pCtx))
251 {
252 if ( CPUMIsGuestPhysIntrEnabled(pVCpu)
253 || ( CPUMIsGuestInNestedHwvirtMode(pCtx)
254 && CPUMIsGuestVirtIntrEnabled(pVCpu))
255 || ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
256 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) )
257 {
258 if (VMCPU_FF_IS_ANY_SET(pVCpu, ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
259 | VMCPU_FF_INTERRUPT_NESTED_GUEST)))
260 {
261 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
262 return true;
263 }
264 }
265 }
266
267 return false;
268}
269
270
271/**
272 * Determine if we should continue execution in HM after encountering a hlt
273 * instruction.
274 *
275 * @returns true if we should continue, false if we should halt.
276 * @param pVCpu The cross context virtual CPU structure.
277 * @param pCtx Current CPU context.
278 */
279VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx)
280{
281 if (CPUMGetGuestGif(pCtx))
282 {
283 if (CPUMIsGuestPhysIntrEnabled(pVCpu))
284 return VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC));
285
286 if ( CPUMIsGuestInNestedHwvirtMode(pCtx)
287 && CPUMIsGuestVirtIntrEnabled(pVCpu))
288 return VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
289 }
290 return false;
291}
292
293
294/**
295 * Unhalts and wakes up the given CPU.
296 *
297 * This is an API for assisting the KVM hypercall API in implementing KICK_CPU.
298 * It sets VMCPU_FF_UNHALT for @a pVCpuDst and makes sure it is woken up. If
299 * the CPU isn't currently in a halt, the next HLT instruction it executes will
300 * be affected.
301 *
302 * @returns GVMMR0SchedWakeUpEx result or VINF_SUCCESS depending on context.
303 * @param pVM The cross context VM structure.
304 * @param pVCpuDst The cross context virtual CPU structure of the
305 * CPU to unhalt and wake up. This is usually not the
306 * same as the caller.
307 * @thread EMT
308 */
309VMM_INT_DECL(int) EMUnhaltAndWakeUp(PVMCC pVM, PVMCPUCC pVCpuDst)
310{
311 /*
312 * Flag the current(/next) HLT to unhalt immediately.
313 */
314 VMCPU_FF_SET(pVCpuDst, VMCPU_FF_UNHALT);
315
316 /*
317 * Wake up the EMT (technically should be abstracted by VMM/VMEmt, but
318 * just do it here for now).
319 */
320#ifdef IN_RING0
321 /* We might be here with preemption disabled or enabled (i.e. depending on
322 thread-context hooks being used), so don't try obtaining the GVMMR0 used
323 lock here. See @bugref{7270#c148}. */
324 int rc = GVMMR0SchedWakeUpNoGVMNoLock(pVM, pVCpuDst->idCpu);
325 AssertRC(rc);
326
327#elif defined(IN_RING3)
328 int rc = SUPR3CallVMMR0(VMCC_GET_VMR0_FOR_CALL(pVM), pVCpuDst->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL /* pvArg */);
329 AssertRC(rc);
330
331#else
332 /* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
333 Assert(pVM->cCpus == 1); NOREF(pVM);
334 int rc = VINF_SUCCESS;
335#endif
336 return rc;
337}
338
339#ifndef IN_RING3
340
341/**
342 * Makes an I/O port write pending for ring-3 processing.
343 *
344 * @returns VINF_EM_PENDING_R3_IOPORT_READ
345 * @param pVCpu The cross context virtual CPU structure.
346 * @param uPort The I/O port.
347 * @param cbInstr The instruction length (for RIP updating).
348 * @param cbValue The write size.
349 * @param uValue The value being written.
350 * @sa emR3ExecutePendingIoPortWrite
351 *
352 * @note Must not be used when I/O port breakpoints are pending or when single stepping.
353 */
354VMMRZ_INT_DECL(VBOXSTRICTRC)
355EMRZSetPendingIoPortWrite(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue, uint32_t uValue)
356{
357 Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
358 pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
359 pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
360 pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
361 pVCpu->em.s.PendingIoPortAccess.uValue = uValue;
362 return VINF_EM_PENDING_R3_IOPORT_WRITE;
363}
364
365
366/**
367 * Makes an I/O port read pending for ring-3 processing.
368 *
369 * @returns VINF_EM_PENDING_R3_IOPORT_READ
370 * @param pVCpu The cross context virtual CPU structure.
371 * @param uPort The I/O port.
372 * @param cbInstr The instruction length (for RIP updating).
373 * @param cbValue The read size.
374 * @sa emR3ExecutePendingIoPortRead
375 *
376 * @note Must not be used when I/O port breakpoints are pending or when single stepping.
377 */
378VMMRZ_INT_DECL(VBOXSTRICTRC)
379EMRZSetPendingIoPortRead(PVMCPU pVCpu, RTIOPORT uPort, uint8_t cbInstr, uint8_t cbValue)
380{
381 Assert(pVCpu->em.s.PendingIoPortAccess.cbValue == 0);
382 pVCpu->em.s.PendingIoPortAccess.uPort = uPort;
383 pVCpu->em.s.PendingIoPortAccess.cbValue = cbValue;
384 pVCpu->em.s.PendingIoPortAccess.cbInstr = cbInstr;
385 pVCpu->em.s.PendingIoPortAccess.uValue = UINT32_C(0x52454144); /* 'READ' */
386 return VINF_EM_PENDING_R3_IOPORT_READ;
387}
388
389#endif /* IN_RING3 */
390
391
392/**
393 * Worker for EMHistoryExec that checks for ring-3 returns and flags
394 * continuation of the EMHistoryExec run there.
395 */
396DECL_FORCE_INLINE(void) emHistoryExecSetContinueExitRecIdx(PVMCPU pVCpu, VBOXSTRICTRC rcStrict, PCEMEXITREC pExitRec)
397{
398 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
399#ifdef IN_RING3
400 RT_NOREF_PV(rcStrict); RT_NOREF_PV(pExitRec);
401#else
402 switch (VBOXSTRICTRC_VAL(rcStrict))
403 {
404 case VINF_SUCCESS:
405 default:
406 break;
407
408 /*
409 * Only status codes that EMHandleRCTmpl.h will resume EMHistoryExec with.
410 */
411 case VINF_IOM_R3_IOPORT_READ: /* -> emR3ExecuteIOInstruction */
412 case VINF_IOM_R3_IOPORT_WRITE: /* -> emR3ExecuteIOInstruction */
413 case VINF_IOM_R3_IOPORT_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
414 case VINF_IOM_R3_MMIO_READ: /* -> emR3ExecuteInstruction */
415 case VINF_IOM_R3_MMIO_WRITE: /* -> emR3ExecuteInstruction */
416 case VINF_IOM_R3_MMIO_READ_WRITE: /* -> emR3ExecuteInstruction */
417 case VINF_IOM_R3_MMIO_COMMIT_WRITE: /* -> VMCPU_FF_IOM -> VINF_EM_RESUME_R3_HISTORY_EXEC -> emR3ExecuteIOInstruction */
418 case VINF_CPUM_R3_MSR_READ: /* -> emR3ExecuteInstruction */
419 case VINF_CPUM_R3_MSR_WRITE: /* -> emR3ExecuteInstruction */
420 case VINF_GIM_R3_HYPERCALL: /* -> emR3ExecuteInstruction */
421 pVCpu->em.s.idxContinueExitRec = (uint16_t)(pExitRec - &pVCpu->em.s.aExitRecords[0]);
422 break;
423 }
424#endif /* !IN_RING3 */
425}
426
427
428/**
429 * Execute using history.
430 *
431 * This function will be called when EMHistoryAddExit() and friends returns a
432 * non-NULL result. This happens in response to probing or when probing has
433 * uncovered adjacent exits which can more effectively be reached by using IEM
434 * than restarting execution using the main execution engine and fielding an
435 * regular exit.
436 *
437 * @returns VBox strict status code, see IEMExecForExits.
438 * @param pVCpu The cross context virtual CPU structure.
439 * @param pExitRec The exit record return by a previous history add
440 * or update call.
441 * @param fWillExit Flags indicating to IEM what will cause exits, TBD.
442 */
443VMM_INT_DECL(VBOXSTRICTRC) EMHistoryExec(PVMCPUCC pVCpu, PCEMEXITREC pExitRec, uint32_t fWillExit)
444{
445 Assert(pExitRec);
446 VMCPU_ASSERT_EMT(pVCpu);
447 IEMEXECFOREXITSTATS ExecStats;
448 switch (pExitRec->enmAction)
449 {
450 /*
451 * Executes multiple instruction stopping only when we've gone a given
452 * number without perceived exits.
453 */
454 case EMEXITACTION_EXEC_WITH_MAX:
455 {
456 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryExec, a);
457 LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %RX64, max %u\n", pExitRec->uFlatPC, pExitRec->cMaxInstructionsWithoutExit));
458 VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
459 pExitRec->cMaxInstructionsWithoutExit /* cMinInstructions*/,
460 pVCpu->em.s.cHistoryExecMaxInstructions,
461 pExitRec->cMaxInstructionsWithoutExit,
462 &ExecStats);
463 LogFlow(("EMHistoryExec/EXEC_WITH_MAX: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
464 VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
465 emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRec);
466
467 /* Ignore instructions IEM doesn't know about. */
468 if ( ( rcStrict != VERR_IEM_INSTR_NOT_IMPLEMENTED
469 && rcStrict != VERR_IEM_ASPECT_NOT_IMPLEMENTED)
470 || ExecStats.cInstructions == 0)
471 { /* likely */ }
472 else
473 rcStrict = VINF_SUCCESS;
474
475 if (ExecStats.cExits > 1)
476 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecSavedExits, ExecStats.cExits - 1);
477 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryExecInstructions, ExecStats.cInstructions);
478 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryExec, a);
479 return rcStrict;
480 }
481
482 /*
483 * Probe a exit for close by exits.
484 */
485 case EMEXITACTION_EXEC_PROBE:
486 {
487 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHistoryProbe, b);
488 LogFlow(("EMHistoryExec/EXEC_PROBE: %RX64\n", pExitRec->uFlatPC));
489 PEMEXITREC pExitRecUnconst = (PEMEXITREC)pExitRec;
490 VBOXSTRICTRC rcStrict = IEMExecForExits(pVCpu, fWillExit,
491 pVCpu->em.s.cHistoryProbeMinInstructions,
492 pVCpu->em.s.cHistoryExecMaxInstructions,
493 pVCpu->em.s.cHistoryProbeMaxInstructionsWithoutExit,
494 &ExecStats);
495 LogFlow(("EMHistoryExec/EXEC_PROBE: %Rrc cExits=%u cMaxExitDistance=%u cInstructions=%u\n",
496 VBOXSTRICTRC_VAL(rcStrict), ExecStats.cExits, ExecStats.cMaxExitDistance, ExecStats.cInstructions));
497 emHistoryExecSetContinueExitRecIdx(pVCpu, rcStrict, pExitRecUnconst);
498 if ( ExecStats.cExits >= 2
499 && RT_SUCCESS(rcStrict))
500 {
501 Assert(ExecStats.cMaxExitDistance > 0 && ExecStats.cMaxExitDistance <= 32);
502 pExitRecUnconst->cMaxInstructionsWithoutExit = ExecStats.cMaxExitDistance;
503 pExitRecUnconst->enmAction = EMEXITACTION_EXEC_WITH_MAX;
504 LogFlow(("EMHistoryExec/EXEC_PROBE: -> EXEC_WITH_MAX %u\n", ExecStats.cMaxExitDistance));
505 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedExecWithMax);
506 }
507#ifndef IN_RING3
508 else if ( pVCpu->em.s.idxContinueExitRec != UINT16_MAX
509 && RT_SUCCESS(rcStrict))
510 {
511 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedToRing3);
512 LogFlow(("EMHistoryExec/EXEC_PROBE: -> ring-3\n"));
513 }
514#endif
515 else
516 {
517 pExitRecUnconst->enmAction = EMEXITACTION_NORMAL_PROBED;
518 pVCpu->em.s.idxContinueExitRec = UINT16_MAX;
519 LogFlow(("EMHistoryExec/EXEC_PROBE: -> PROBED\n"));
520 STAM_REL_COUNTER_INC(&pVCpu->em.s.StatHistoryProbedNormal);
521 if ( rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED
522 || rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
523 rcStrict = VINF_SUCCESS;
524 }
525 STAM_REL_COUNTER_ADD(&pVCpu->em.s.StatHistoryProbeInstructions, ExecStats.cInstructions);
526 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHistoryProbe, b);
527 return rcStrict;
528 }
529
530 /* We shouldn't ever see these here! */
531 case EMEXITACTION_FREE_RECORD:
532 case EMEXITACTION_NORMAL:
533 case EMEXITACTION_NORMAL_PROBED:
534 break;
535
536 /* No default case, want compiler warnings. */
537 }
538 AssertLogRelFailedReturn(VERR_EM_INTERNAL_ERROR);
539}
540
541
542/**
543 * Worker for emHistoryAddOrUpdateRecord.
544 */
545DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInit(PEMEXITREC pExitRec, uint64_t uFlatPC, uint32_t uFlagsAndType, uint64_t uExitNo)
546{
547 pExitRec->uFlatPC = uFlatPC;
548 pExitRec->uFlagsAndType = uFlagsAndType;
549 pExitRec->enmAction = EMEXITACTION_NORMAL;
550 pExitRec->bUnused = 0;
551 pExitRec->cMaxInstructionsWithoutExit = 64;
552 pExitRec->uLastExitNo = uExitNo;
553 pExitRec->cHits = 1;
554 return NULL;
555}
556
557
558/**
559 * Worker for emHistoryAddOrUpdateRecord.
560 */
561DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitNew(PVMCPU pVCpu, PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
562 PEMEXITREC pExitRec, uint64_t uFlatPC,
563 uint32_t uFlagsAndType, uint64_t uExitNo)
564{
565 pHistEntry->idxSlot = (uint32_t)idxSlot;
566 pVCpu->em.s.cExitRecordUsed++;
567 LogFlow(("emHistoryRecordInitNew: [%#x] = %#07x %016RX64; (%u of %u used)\n", idxSlot, uFlagsAndType, uFlatPC,
568 pVCpu->em.s.cExitRecordUsed, RT_ELEMENTS(pVCpu->em.s.aExitRecords) ));
569 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
570}
571
572
573/**
574 * Worker for emHistoryAddOrUpdateRecord.
575 */
576DECL_FORCE_INLINE(PCEMEXITREC) emHistoryRecordInitReplacement(PEMEXITENTRY pHistEntry, uintptr_t idxSlot,
577 PEMEXITREC pExitRec, uint64_t uFlatPC,
578 uint32_t uFlagsAndType, uint64_t uExitNo)
579{
580 pHistEntry->idxSlot = (uint32_t)idxSlot;
581 LogFlow(("emHistoryRecordInitReplacement: [%#x] = %#07x %016RX64 replacing %#07x %016RX64 with %u hits, %u exits old\n",
582 idxSlot, uFlagsAndType, uFlatPC, pExitRec->uFlagsAndType, pExitRec->uFlatPC, pExitRec->cHits,
583 uExitNo - pExitRec->uLastExitNo));
584 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
585}
586
587
588/**
589 * Adds or updates the EMEXITREC for this PC/type and decide on an action.
590 *
591 * @returns Pointer to an exit record if special action should be taken using
592 * EMHistoryExec(). Take normal exit action when NULL.
593 *
594 * @param pVCpu The cross context virtual CPU structure.
595 * @param uFlagsAndType Combined flags and type, EMEXIT_F_KIND_EM set and
596 * both EMEXIT_F_CS_EIP and EMEXIT_F_UNFLATTENED_PC are clear.
597 * @param uFlatPC The flattened program counter.
598 * @param pHistEntry The exit history entry.
599 * @param uExitNo The current exit number.
600 */
601static PCEMEXITREC emHistoryAddOrUpdateRecord(PVMCPU pVCpu, uint64_t uFlagsAndType, uint64_t uFlatPC,
602 PEMEXITENTRY pHistEntry, uint64_t uExitNo)
603{
604# ifdef IN_RING0
605 /* Disregard the hm flag. */
606 uFlagsAndType &= ~EMEXIT_F_HM;
607# endif
608
609 /*
610 * Work the hash table.
611 */
612 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitRecords) == 1024);
613# define EM_EXIT_RECORDS_IDX_MASK 0x3ff
614 uintptr_t idxSlot = ((uintptr_t)uFlatPC >> 1) & EM_EXIT_RECORDS_IDX_MASK;
615 PEMEXITREC pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
616 if (pExitRec->uFlatPC == uFlatPC)
617 {
618 Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
619 pHistEntry->idxSlot = (uint32_t)idxSlot;
620 if (pExitRec->uFlagsAndType == uFlagsAndType)
621 {
622 pExitRec->uLastExitNo = uExitNo;
623 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[0]);
624 }
625 else
626 {
627 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[0]);
628 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
629 }
630 }
631 else if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
632 {
633 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[0]);
634 return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
635 }
636 else
637 {
638 /*
639 * Collision. We calculate a new hash for stepping away from the first,
640 * doing up to 8 steps away before replacing the least recently used record.
641 */
642 uintptr_t idxOldest = idxSlot;
643 uint64_t uOldestExitNo = pExitRec->uLastExitNo;
644 unsigned iOldestStep = 0;
645 unsigned iStep = 1;
646 uintptr_t const idxAdd = (uintptr_t)(uFlatPC >> 11) & (EM_EXIT_RECORDS_IDX_MASK / 4);
647 for (;;)
648 {
649 Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
650 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecNew) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
651 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
652 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecTypeChanged) == RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecHits));
653
654 /* Step to the next slot. */
655 idxSlot += idxAdd;
656 idxSlot &= EM_EXIT_RECORDS_IDX_MASK;
657 pExitRec = &pVCpu->em.s.aExitRecords[idxSlot];
658
659 /* Does it match? */
660 if (pExitRec->uFlatPC == uFlatPC)
661 {
662 Assert(pExitRec->enmAction != EMEXITACTION_FREE_RECORD);
663 pHistEntry->idxSlot = (uint32_t)idxSlot;
664 if (pExitRec->uFlagsAndType == uFlagsAndType)
665 {
666 pExitRec->uLastExitNo = uExitNo;
667 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecHits[iStep]);
668 break;
669 }
670 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecTypeChanged[iStep]);
671 return emHistoryRecordInit(pExitRec, uFlatPC, uFlagsAndType, uExitNo);
672 }
673
674 /* Is it free? */
675 if (pExitRec->enmAction == EMEXITACTION_FREE_RECORD)
676 {
677 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecNew[iStep]);
678 return emHistoryRecordInitNew(pVCpu, pHistEntry, idxSlot, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
679 }
680
681 /* Is it the least recently used one? */
682 if (pExitRec->uLastExitNo < uOldestExitNo)
683 {
684 uOldestExitNo = pExitRec->uLastExitNo;
685 idxOldest = idxSlot;
686 iOldestStep = iStep;
687 }
688
689 /* Next iteration? */
690 iStep++;
691 Assert(iStep < RT_ELEMENTS(pVCpu->em.s.aStatHistoryRecReplaced));
692 if (RT_LIKELY(iStep < 8 + 1))
693 { /* likely */ }
694 else
695 {
696 /* Replace the least recently used slot. */
697 STAM_REL_COUNTER_INC(&pVCpu->em.s.aStatHistoryRecReplaced[iOldestStep]);
698 pExitRec = &pVCpu->em.s.aExitRecords[idxOldest];
699 return emHistoryRecordInitReplacement(pHistEntry, idxOldest, pExitRec, uFlatPC, uFlagsAndType, uExitNo);
700 }
701 }
702 }
703
704 /*
705 * Found an existing record.
706 */
707 switch (pExitRec->enmAction)
708 {
709 case EMEXITACTION_NORMAL:
710 {
711 uint64_t const cHits = ++pExitRec->cHits;
712 if (cHits < 256)
713 return NULL;
714 LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> EXEC_PROBE\n", idxSlot, uFlagsAndType, uFlatPC));
715 pExitRec->enmAction = EMEXITACTION_EXEC_PROBE;
716 return pExitRec;
717 }
718
719 case EMEXITACTION_NORMAL_PROBED:
720 pExitRec->cHits += 1;
721 return NULL;
722
723 default:
724 pExitRec->cHits += 1;
725 return pExitRec;
726
727 /* This will happen if the caller ignores or cannot serve the probe
728 request (forced to ring-3, whatever). We retry this 256 times. */
729 case EMEXITACTION_EXEC_PROBE:
730 {
731 uint64_t const cHits = ++pExitRec->cHits;
732 if (cHits < 512)
733 return pExitRec;
734 pExitRec->enmAction = EMEXITACTION_NORMAL_PROBED;
735 LogFlow(("emHistoryAddOrUpdateRecord: [%#x] %#07x %16RX64: -> PROBED\n", idxSlot, uFlagsAndType, uFlatPC));
736 return NULL;
737 }
738 }
739}
740
741
742/**
743 * Adds an exit to the history for this CPU.
744 *
745 * @returns Pointer to an exit record if special action should be taken using
746 * EMHistoryExec(). Take normal exit action when NULL.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
750 * @param uFlatPC The flattened program counter (RIP). UINT64_MAX if not available.
751 * @param uTimestamp The TSC value for the exit, 0 if not available.
752 * @thread EMT(pVCpu)
753 */
754VMM_INT_DECL(PCEMEXITREC) EMHistoryAddExit(PVMCPUCC pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC, uint64_t uTimestamp)
755{
756 VMCPU_ASSERT_EMT(pVCpu);
757
758 /*
759 * Add the exit history entry.
760 */
761 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
762 uint64_t uExitNo = pVCpu->em.s.iNextExit++;
763 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
764 pHistEntry->uFlatPC = uFlatPC;
765 pHistEntry->uTimestamp = uTimestamp;
766 pHistEntry->uFlagsAndType = uFlagsAndType;
767 pHistEntry->idxSlot = UINT32_MAX;
768
769 /*
770 * If common exit type, we will insert/update the exit into the exit record hash table.
771 */
772 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
773#ifdef IN_RING0
774 && pVCpu->em.s.fExitOptimizationEnabledR0
775 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
776#else
777 && pVCpu->em.s.fExitOptimizationEnabled
778#endif
779 && uFlatPC != UINT64_MAX
780 )
781 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
782 return NULL;
783}
784
785
786#ifdef IN_RING0
787/**
788 * Interface that VT-x uses to supply the PC of an exit when CS:RIP is being read.
789 *
790 * @param pVCpu The cross context virtual CPU structure.
791 * @param uFlatPC The flattened program counter (RIP).
792 * @param fFlattened Set if RIP was subjected to CS.BASE, clear if not.
793 */
794VMMR0_INT_DECL(void) EMR0HistoryUpdatePC(PVMCPU pVCpu, uint64_t uFlatPC, bool fFlattened)
795{
796 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
797 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
798 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
799 pHistEntry->uFlatPC = uFlatPC;
800 if (fFlattened)
801 pHistEntry->uFlagsAndType &= ~EMEXIT_F_UNFLATTENED_PC;
802 else
803 pHistEntry->uFlagsAndType |= EMEXIT_F_UNFLATTENED_PC;
804}
805#endif
806
807
808/**
809 * Interface for convering a engine specific exit to a generic one and get guidance.
810 *
811 * @returns Pointer to an exit record if special action should be taken using
812 * EMHistoryExec(). Take normal exit action when NULL.
813 *
814 * @param pVCpu The cross context virtual CPU structure.
815 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
816 * @thread EMT(pVCpu)
817 */
818VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndType(PVMCPUCC pVCpu, uint32_t uFlagsAndType)
819{
820 VMCPU_ASSERT_EMT(pVCpu);
821
822 /*
823 * Do the updating.
824 */
825 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
826 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
827 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
828 pHistEntry->uFlagsAndType = uFlagsAndType | (pHistEntry->uFlagsAndType & (EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC));
829
830 /*
831 * If common exit type, we will insert/update the exit into the exit record hash table.
832 */
833 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
834#ifdef IN_RING0
835 && pVCpu->em.s.fExitOptimizationEnabledR0
836 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
837#else
838 && pVCpu->em.s.fExitOptimizationEnabled
839#endif
840 && pHistEntry->uFlatPC != UINT64_MAX
841 )
842 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, pHistEntry->uFlatPC, pHistEntry, uExitNo);
843 return NULL;
844}
845
846
847/**
848 * Interface for convering a engine specific exit to a generic one and get
849 * guidance, supplying flattened PC too.
850 *
851 * @returns Pointer to an exit record if special action should be taken using
852 * EMHistoryExec(). Take normal exit action when NULL.
853 *
854 * @param pVCpu The cross context virtual CPU structure.
855 * @param uFlagsAndType Combined flags and type (see EMEXIT_MAKE_FLAGS_AND_TYPE).
856 * @param uFlatPC The flattened program counter (RIP).
857 * @thread EMT(pVCpu)
858 */
859VMM_INT_DECL(PCEMEXITREC) EMHistoryUpdateFlagsAndTypeAndPC(PVMCPUCC pVCpu, uint32_t uFlagsAndType, uint64_t uFlatPC)
860{
861 VMCPU_ASSERT_EMT(pVCpu);
862 Assert(uFlatPC != UINT64_MAX);
863
864 /*
865 * Do the updating.
866 */
867 AssertCompile(RT_ELEMENTS(pVCpu->em.s.aExitHistory) == 256);
868 uint64_t uExitNo = pVCpu->em.s.iNextExit - 1;
869 PEMEXITENTRY pHistEntry = &pVCpu->em.s.aExitHistory[(uintptr_t)uExitNo & 0xff];
870 pHistEntry->uFlagsAndType = uFlagsAndType;
871 pHistEntry->uFlatPC = uFlatPC;
872
873 /*
874 * If common exit type, we will insert/update the exit into the exit record hash table.
875 */
876 if ( (uFlagsAndType & (EMEXIT_F_KIND_MASK | EMEXIT_F_CS_EIP | EMEXIT_F_UNFLATTENED_PC)) == EMEXIT_F_KIND_EM
877#ifdef IN_RING0
878 && pVCpu->em.s.fExitOptimizationEnabledR0
879 && ( !(uFlagsAndType & EMEXIT_F_HM) || pVCpu->em.s.fExitOptimizationEnabledR0PreemptDisabled)
880#else
881 && pVCpu->em.s.fExitOptimizationEnabled
882#endif
883 )
884 return emHistoryAddOrUpdateRecord(pVCpu, uFlagsAndType, uFlatPC, pHistEntry, uExitNo);
885 return NULL;
886}
887
888
889/**
890 * @callback_method_impl{FNDISREADBYTES}
891 */
892static DECLCALLBACK(int) emReadBytes(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
893{
894 PVMCPUCC pVCpu = (PVMCPUCC)pDis->pvUser;
895 RTUINTPTR uSrcAddr = pDis->uInstrAddr + offInstr;
896
897 /*
898 * Figure how much we can or must read.
899 */
900 size_t cbToRead = PAGE_SIZE - (uSrcAddr & PAGE_OFFSET_MASK);
901 if (cbToRead > cbMaxRead)
902 cbToRead = cbMaxRead;
903 else if (cbToRead < cbMinRead)
904 cbToRead = cbMinRead;
905
906 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
907 if (RT_FAILURE(rc))
908 {
909 if (cbToRead > cbMinRead)
910 {
911 cbToRead = cbMinRead;
912 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pDis->abInstr[offInstr], uSrcAddr, cbToRead);
913 }
914 if (RT_FAILURE(rc))
915 {
916 /*
917 * If we fail to find the page via the guest's page tables
918 * we invalidate the page in the host TLB (pertaining to
919 * the guest in the NestedPaging case). See @bugref{6043}.
920 */
921 if (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
922 {
923 HMInvalidatePage(pVCpu, uSrcAddr);
924 if (((uSrcAddr + cbToRead - 1) >> PAGE_SHIFT) != (uSrcAddr >> PAGE_SHIFT))
925 HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
926 }
927 }
928 }
929
930 pDis->cbCachedInstr = offInstr + (uint8_t)cbToRead;
931 return rc;
932}
933
934
935/**
936 * Disassembles the current instruction.
937 *
938 * @returns VBox status code, see SELMToFlatEx and EMInterpretDisasOneEx for
939 * details.
940 *
941 * @param pVM The cross context VM structure.
942 * @param pVCpu The cross context virtual CPU structure.
943 * @param pDis Where to return the parsed instruction info.
944 * @param pcbInstr Where to return the instruction size. (optional)
945 */
946VMM_INT_DECL(int) EMInterpretDisasCurrent(PVMCC pVM, PVMCPUCC pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
947{
948 PCPUMCTXCORE pCtxCore = CPUMCTX2CORE(CPUMQueryGuestCtxPtr(pVCpu));
949 RTGCPTR GCPtrInstr;
950#if 0
951 int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
952#else
953/** @todo Get the CPU mode as well while we're at it! */
954 int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtxCore->eflags, pCtxCore->ss.Sel, pCtxCore->cs.Sel, &pCtxCore->cs,
955 pCtxCore->rip, &GCPtrInstr);
956#endif
957 if (RT_FAILURE(rc))
958 {
959 Log(("EMInterpretDisasOne: Failed to convert %RTsel:%RGv (cpl=%d) - rc=%Rrc !!\n",
960 pCtxCore->cs.Sel, (RTGCPTR)pCtxCore->rip, pCtxCore->ss.Sel & X86_SEL_RPL, rc));
961 return rc;
962 }
963 return EMInterpretDisasOneEx(pVM, pVCpu, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pDis, pcbInstr);
964}
965
966
967/**
968 * Disassembles one instruction.
969 *
970 * This is used by internally by the interpreter and by trap/access handlers.
971 *
972 * @returns VBox status code.
973 *
974 * @param pVM The cross context VM structure.
975 * @param pVCpu The cross context virtual CPU structure.
976 * @param GCPtrInstr The flat address of the instruction.
977 * @param pCtxCore The context core (used to determine the cpu mode).
978 * @param pDis Where to return the parsed instruction info.
979 * @param pcbInstr Where to return the instruction size. (optional)
980 */
981VMM_INT_DECL(int) EMInterpretDisasOneEx(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
982 PDISCPUSTATE pDis, unsigned *pcbInstr)
983{
984 NOREF(pVM);
985 Assert(pCtxCore == CPUMGetGuestCtxCore(pVCpu)); NOREF(pCtxCore);
986 DISCPUMODE enmCpuMode = CPUMGetGuestDisMode(pVCpu);
987 /** @todo Deal with too long instruction (=> \#GP), opcode read errors (=>
988 * \#PF, \#GP, \#??), undefined opcodes (=> \#UD), and such. */
989 int rc = DISInstrWithReader(GCPtrInstr, enmCpuMode, emReadBytes, pVCpu, pDis, pcbInstr);
990 if (RT_SUCCESS(rc))
991 return VINF_SUCCESS;
992 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("DISCoreOne failed to GCPtrInstr=%RGv rc=%Rrc\n", GCPtrInstr, rc));
993 return rc;
994}
995
996
997/**
998 * Interprets the current instruction.
999 *
1000 * @returns VBox status code.
1001 * @retval VINF_* Scheduling instructions.
1002 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1003 * @retval VERR_* Fatal errors.
1004 *
1005 * @param pVCpu The cross context virtual CPU structure.
1006 * @param pRegFrame The register frame.
1007 * Updates the EIP if an instruction was executed successfully.
1008 * @param pvFault The fault address (CR2).
1009 *
1010 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1011 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1012 * to worry about e.g. invalid modrm combinations (!)
1013 */
1014VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
1015{
1016 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1017 LogFlow(("EMInterpretInstruction %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1018 NOREF(pvFault);
1019
1020 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, NULL);
1021 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1022 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1023 rc = VERR_EM_INTERPRETER;
1024 if (rc != VINF_SUCCESS)
1025 Log(("EMInterpretInstruction: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1026
1027 return rc;
1028}
1029
1030
1031/**
1032 * Interprets the current instruction.
1033 *
1034 * @returns VBox status code.
1035 * @retval VINF_* Scheduling instructions.
1036 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1037 * @retval VERR_* Fatal errors.
1038 *
1039 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1040 * @param pRegFrame The register frame.
1041 * Updates the EIP if an instruction was executed successfully.
1042 * @param pvFault The fault address (CR2).
1043 * @param pcbWritten Size of the write (if applicable).
1044 *
1045 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1046 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1047 * to worry about e.g. invalid modrm combinations (!)
1048 */
1049VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten)
1050{
1051 LogFlow(("EMInterpretInstructionEx %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1052 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1053 NOREF(pvFault);
1054
1055 VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, pRegFrame, pcbWritten);
1056 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1057 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1058 rc = VERR_EM_INTERPRETER;
1059 if (rc != VINF_SUCCESS)
1060 Log(("EMInterpretInstructionEx: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1061
1062 return rc;
1063}
1064
1065
1066/**
1067 * Interprets the current instruction using the supplied DISCPUSTATE structure.
1068 *
1069 * IP/EIP/RIP *IS* updated!
1070 *
1071 * @returns VBox strict status code.
1072 * @retval VINF_* Scheduling instructions. When these are returned, it
1073 * starts to get a bit tricky to know whether code was
1074 * executed or not... We'll address this when it becomes a problem.
1075 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1076 * @retval VERR_* Fatal errors.
1077 *
1078 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1079 * @param pDis The disassembler cpu state for the instruction to be
1080 * interpreted.
1081 * @param pRegFrame The register frame. IP/EIP/RIP *IS* changed!
1082 * @param pvFault The fault address (CR2).
1083 * @param enmCodeType Code type (user/supervisor)
1084 *
1085 * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
1086 * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
1087 * to worry about e.g. invalid modrm combinations (!)
1088 *
1089 * @todo At this time we do NOT check if the instruction overwrites vital information.
1090 * Make sure this can't happen!! (will add some assertions/checks later)
1091 */
1092VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPUCC pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pRegFrame,
1093 RTGCPTR pvFault, EMCODETYPE enmCodeType)
1094{
1095 LogFlow(("EMInterpretInstructionDisasState %RGv fault %RGv\n", (RTGCPTR)pRegFrame->rip, pvFault));
1096 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1097 NOREF(pDis); NOREF(pvFault); NOREF(enmCodeType);
1098
1099 VBOXSTRICTRC rc = IEMExecOneBypassWithPrefetchedByPC(pVCpu, pRegFrame, pRegFrame->rip, pDis->abInstr, pDis->cbCachedInstr);
1100 if (RT_UNLIKELY( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
1101 || rc == VERR_IEM_INSTR_NOT_IMPLEMENTED))
1102 rc = VERR_EM_INTERPRETER;
1103
1104 if (rc != VINF_SUCCESS)
1105 Log(("EMInterpretInstructionDisasState: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1106
1107 return rc;
1108}
1109
1110
1111
1112
1113/*
1114 *
1115 * Old interpreter primitives used by HM, move/eliminate later.
1116 * Old interpreter primitives used by HM, move/eliminate later.
1117 * Old interpreter primitives used by HM, move/eliminate later.
1118 * Old interpreter primitives used by HM, move/eliminate later.
1119 * Old interpreter primitives used by HM, move/eliminate later.
1120 *
1121 */
1122
1123
1124/**
1125 * Interpret RDPMC.
1126 *
1127 * @returns VBox status code.
1128 * @param pVM The cross context VM structure.
1129 * @param pVCpu The cross context virtual CPU structure.
1130 * @param pRegFrame The register frame.
1131 *
1132 */
1133VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
1134{
1135 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1136 uint32_t uCR4 = CPUMGetGuestCR4(pVCpu);
1137
1138 /* If X86_CR4_PCE is not set, then CPL must be zero. */
1139 if ( !(uCR4 & X86_CR4_PCE)
1140 && CPUMGetGuestCPL(pVCpu) != 0)
1141 {
1142 Assert(CPUMGetGuestCR0(pVCpu) & X86_CR0_PE);
1143 return VERR_EM_INTERPRETER; /* genuine #GP */
1144 }
1145
1146 /* Just return zero here; rather tricky to properly emulate this, especially as the specs are a mess. */
1147 pRegFrame->rax = 0;
1148 pRegFrame->rdx = 0;
1149 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
1150 * ecx but see @bugref{3472}! */
1151
1152 NOREF(pVM);
1153 return VINF_SUCCESS;
1154}
1155
1156
1157/* VT-x only: */
1158
1159/**
1160 * Interpret DRx write.
1161 *
1162 * @returns VBox status code.
1163 * @param pVM The cross context VM structure.
1164 * @param pVCpu The cross context virtual CPU structure.
1165 * @param pRegFrame The register frame.
1166 * @param DestRegDrx DRx register index (USE_REG_DR*)
1167 * @param SrcRegGen General purpose register index (USE_REG_E**))
1168 *
1169 */
1170VMM_INT_DECL(int) EMInterpretDRxWrite(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
1171{
1172 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1173 uint64_t uNewDrX;
1174 int rc;
1175 NOREF(pVM);
1176
1177 if (CPUMIsGuestIn64BitCode(pVCpu))
1178 rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
1179 else
1180 {
1181 uint32_t val32;
1182 rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
1183 uNewDrX = val32;
1184 }
1185
1186 if (RT_SUCCESS(rc))
1187 {
1188 if (DestRegDrx == 6)
1189 {
1190 uNewDrX |= X86_DR6_RA1_MASK;
1191 uNewDrX &= ~X86_DR6_RAZ_MASK;
1192 }
1193 else if (DestRegDrx == 7)
1194 {
1195 uNewDrX |= X86_DR7_RA1_MASK;
1196 uNewDrX &= ~X86_DR7_RAZ_MASK;
1197 }
1198
1199 /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
1200 rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
1201 if (RT_SUCCESS(rc))
1202 return rc;
1203 AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
1204 }
1205 return VERR_EM_INTERPRETER;
1206}
1207
1208
1209/**
1210 * Interpret DRx read.
1211 *
1212 * @returns VBox status code.
1213 * @param pVM The cross context VM structure.
1214 * @param pVCpu The cross context virtual CPU structure.
1215 * @param pRegFrame The register frame.
1216 * @param DestRegGen General purpose register index (USE_REG_E**))
1217 * @param SrcRegDrx DRx register index (USE_REG_DR*)
1218 */
1219VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
1220{
1221 uint64_t val64;
1222 Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
1223 NOREF(pVM);
1224
1225 int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
1226 AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
1227 if (CPUMIsGuestIn64BitCode(pVCpu))
1228 rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
1229 else
1230 rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
1231
1232 if (RT_SUCCESS(rc))
1233 return VINF_SUCCESS;
1234
1235 return VERR_EM_INTERPRETER;
1236}
1237
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette