GIMAllHv.cpp@ 58591

Last change on this file since 58591 was 58390, checked in by vboxsync, 9 years ago
VMM/GIM: Implement Hyper-V debug receive thread optimization. Added a few statistics to GIM. Fixed a bug in Windows guests' debug DHCP handling.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 38.0 KB

Line
1	/* $Id: GIMAllHv.cpp 58390 2015-10-23 12:35:35Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include "GIMHvInternal.h"
24	#include "GIMInternal.h"
25
26	#include <iprt/asm-amd64-x86.h>
27	#ifdef IN_RING3
28	# include <iprt/mem.h>
29	#endif
30
31	#include <VBox/err.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/hm.h>
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/pdmdev.h>
38	#include <VBox/vmm/pdmapi.h>
39
40
41	#ifdef IN_RING3
42	/**
43	* Read and validate slow hypercall parameters.
44	*
45	* @returns VBox status code.
46	* @param pVM The cross context VM structure.
47	* @param pCtx Pointer to the guest-CPU context.
48	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
49	* @param enmParam The hypercall parameter type.
50	* @param prcHv Where to store the Hyper-V status code. Only valid
51	* to the caller when this function returns
52	* VINF_SUCCESS.
53	*/
54	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
55	{
56	int rc = VINF_SUCCESS;
57	PGIMHV pHv = &pVM->gim.s.u.Hv;
58	RTGCPHYS GCPhysParam;
59	void *pvDst;
60	if (enmParam == GIMHVHYPERCALLPARAM_IN)
61	{
62	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
63	pvDst = pHv->pbHypercallIn;
64	pHv->GCPhysHypercallIn = GCPhysParam;
65	}
66	else
67	{
68	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
69	pvDst = pHv->pbHypercallOut;
70	pHv->GCPhysHypercallOut = GCPhysParam;
71	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
72	}
73
74	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
75	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
76	{
77	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
78	{
79	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
80	if (RT_SUCCESS(rc))
81	{
82	*prcHv = GIM_HV_STATUS_SUCCESS;
83	return VINF_SUCCESS;
84	}
85	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
86	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
87	}
88	else
89	{
90	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
91	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
92	}
93	}
94	else
95	{
96	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
97	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
98	}
99	return rc;
100	}
101
102
103	/**
104	* Helper for reading and validating slow hypercall input and output parameters.
105	*
106	* @returns VBox status code.
107	* @param pVM The cross context VM structure.
108	* @param pCtx Pointer to the guest-CPU context.
109	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
110	* @param prcHv Where to store the Hyper-V status code. Only valid
111	* to the caller when this function returns
112	* VINF_SUCCESS.
113	*/
114	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
115	{
116	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
117	if ( RT_SUCCESS(rc)
118	&& *prcHv == GIM_HV_STATUS_SUCCESS)
119	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
120	return rc;
121	}
122	#endif
123
124
125	/**
126	* Handles all Hyper-V hypercalls.
127	*
128	* @returns VBox status code.
129	* @param pVCpu The cross context virtual CPU structure.
130	* @param pCtx Pointer to the guest-CPU context.
131	*
132	* @thread EMT.
133	*/
134	VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
135	{
136	#ifndef IN_RING3
137	return VINF_GIM_R3_HYPERCALL;
138	#else
139	PVM pVM = pVCpu->CTX_SUFF(pVM);
140
141	/*
142	* Verify that hypercalls are enabled.
143	*/
144	if (!gimHvAreHypercallsEnabled(pVCpu))
145	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
146
147	/*
148	* Verify guest is in ring-0 protected mode.
149	*/
150	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
151	if ( uCpl
152	\|\| CPUMIsGuestInRealModeEx(pCtx))
153	{
154	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
155	}
156
157	/*
158	* Get the hypercall operation code and modes.
159	*/
160	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
161	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
162	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
163	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
164	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
165	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
166	uint64_t cHyperRepsDone = 0;
167
168	int rc = VINF_SUCCESS;
169	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
170	PGIMHV pHv = &pVM->gim.s.u.Hv;
171
172	/*
173	* Validate common hypercall input parameters.
174	*/
175	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
176	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
177	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
178	{
179	/*
180	* Perform the hypercall.
181	*/
182	switch (uHyperOp)
183	{
184	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
185	{
186	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
187	{
188	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
189	if ( RT_SUCCESS(rc)
190	&& rcHv == GIM_HV_STATUS_SUCCESS)
191	{
192	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
193	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
194	if (RT_FAILURE(rc))
195	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
196	}
197	}
198	else
199	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
200	break;
201	}
202
203	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
204	{
205	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
206	{
207	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
208	if ( RT_SUCCESS(rc)
209	&& rcHv == GIM_HV_STATUS_SUCCESS)
210	{
211	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
212	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
213	if (RT_FAILURE(rc))
214	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
215	}
216	}
217	else
218	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
219	break;
220	}
221
222	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
223	{
224	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
225	{
226	uint32_t fFlags = 0;
227	if (!fHyperFast)
228	{
229	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
230	if ( RT_SUCCESS(rc)
231	&& rcHv == GIM_HV_STATUS_SUCCESS)
232	{
233	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
234	fFlags = pIn->fFlags;
235	}
236	}
237	else
238	{
239	rcHv = GIM_HV_STATUS_SUCCESS;
240	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
241	}
242
243	/*
244	* Nothing to flush on the sending side as we don't maintain our own buffers.
245	*/
246	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
247	if (rcHv == GIM_HV_STATUS_SUCCESS)
248	{
249	if (fFlags)
250	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
251	else
252	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
253	}
254	}
255	else
256	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
257	break;
258	}
259
260	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
261	{
262	if (pHv->fIsInterfaceVs)
263	{
264	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
265	if ( RT_SUCCESS(rc)
266	&& rcHv == GIM_HV_STATUS_SUCCESS)
267	{
268	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
269	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
270	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
271	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
272	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->uSint2Msr)
273	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
274	{
275	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
276	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
277	{
278	/*
279	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
280	*/
281	GIMHVMSG HvMsg;
282	RT_ZERO(HvMsg);
283	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
284	HvMsg.MsgHdr.cbPayload = 0xf;
285	HvMsg.aPayload[0] = 0xf;
286	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
287	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
288	if (RT_SUCCESS(rc2))
289	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
290	else
291	{
292	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
293	offMsg, rc));
294	}
295	}
296	}
297
298	/*
299	* Make the call fail after updating the SIMP, so the guest can go back to using
300	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
301	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
302	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
303	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
304	*/
305	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
306	}
307	else
308	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
309	}
310	else
311	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
312	break;
313	}
314
315	default:
316	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
317	break;
318	}
319	}
320	else
321	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
322
323	/*
324	* Update the guest with results of the hypercall.
325	*/
326	if (RT_SUCCESS(rc))
327	{
328	if (fIs64BitMode)
329	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
330	else
331	{
332	pCtx->edx = cHyperRepsDone;
333	pCtx->eax = rcHv;
334	}
335	}
336
337	return rc;
338	#endif
339	}
340
341
342	/**
343	* Returns whether the guest has configured and enabled the use of Hyper-V's
344	* hypercall interface.
345	*
346	* @returns true if hypercalls are enabled, false otherwise.
347	* @param pVCpu The cross context virtual CPU structure.
348	*/
349	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
350	{
351	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
352	}
353
354
355	/**
356	* Returns whether the guest has configured and enabled the use of Hyper-V's
357	* paravirtualized TSC.
358	*
359	* @returns true if paravirt. TSC is enabled, false otherwise.
360	* @param pVM The cross context VM structure.
361	*/
362	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
363	{
364	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
365	}
366
367
368	#ifdef IN_RING3
369	/**
370	* Gets the descriptive OS ID variant as identified via the
371	* MSR_GIM_HV_GUEST_OS_ID MSR.
372	*
373	* @returns The name.
374	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
375	*/
376	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
377	{
378	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
379	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
380	if (uVendor == 1 /* Microsoft */)
381	{
382	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
383	switch (uOsVariant)
384	{
385	case 0: return "Undefined";
386	case 1: return "MS-DOS";
387	case 2: return "Windows 3.x";
388	case 3: return "Windows 9x";
389	case 4: return "Windows NT or derivative";
390	case 5: return "Windows CE";
391	default: return "Unknown";
392	}
393	}
394	return "Unknown";
395	}
396	#endif
397
398
399	/**
400	* MSR read handler for Hyper-V.
401	*
402	* @returns Strict VBox status code like CPUMQueryGuestMsr().
403	* @retval VINF_CPUM_R3_MSR_READ
404	* @retval VERR_CPUM_RAISE_GP_0
405	*
406	* @param pVCpu The cross context virtual CPU structure.
407	* @param idMsr The MSR being read.
408	* @param pRange The range this MSR belongs to.
409	* @param puValue Where to store the MSR value read.
410	*
411	* @thread EMT.
412	*/
413	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
414	{
415	NOREF(pRange);
416	PVM pVM = pVCpu->CTX_SUFF(pVM);
417	PGIMHV pHv = &pVM->gim.s.u.Hv;
418
419	switch (idMsr)
420	{
421	case MSR_GIM_HV_TIME_REF_COUNT:
422	{
423	/* Hyper-V reports the time in 100 ns units (10 MHz). */
424	uint64_t u64Tsc = TMCpuTickGet(pVCpu);
425	uint64_t u64TscHz = pHv->cTscTicksPerSecond;
426	uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
427	*puValue = (u64Tsc / u64Tsc100Ns);
428	return VINF_SUCCESS;
429	}
430
431	case MSR_GIM_HV_VP_INDEX:
432	*puValue = pVCpu->idCpu;
433	return VINF_SUCCESS;
434
435	case MSR_GIM_HV_TPR:
436	PDMApicReadMSR(pVM, pVCpu->idCpu, 0x80, puValue);
437	return VINF_SUCCESS;
438
439	case MSR_GIM_HV_EOI:
440	PDMApicReadMSR(pVM, pVCpu->idCpu, 0x0B, puValue);
441	return VINF_SUCCESS;
442
443	case MSR_GIM_HV_ICR:
444	PDMApicReadMSR(pVM, pVCpu->idCpu, 0x30, puValue);
445	return VINF_SUCCESS;
446
447	case MSR_GIM_HV_GUEST_OS_ID:
448	*puValue = pHv->u64GuestOsIdMsr;
449	return VINF_SUCCESS;
450
451	case MSR_GIM_HV_HYPERCALL:
452	*puValue = pHv->u64HypercallMsr;
453	return VINF_SUCCESS;
454
455	case MSR_GIM_HV_REF_TSC:
456	*puValue = pHv->u64TscPageMsr;
457	return VINF_SUCCESS;
458
459	case MSR_GIM_HV_TSC_FREQ:
460	*puValue = TMCpuTicksPerSecond(pVM);
461	return VINF_SUCCESS;
462
463	case MSR_GIM_HV_APIC_FREQ:
464	{
465	int rc = PDMApicGetTimerFreq(pVM, puValue);
466	if (RT_FAILURE(rc))
467	return VERR_CPUM_RAISE_GP_0;
468	return VINF_SUCCESS;
469	}
470
471	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
472	*puValue = pHv->uDbgStatusMsr;
473	return VINF_SUCCESS;
474
475	case MSR_GIM_HV_SINT2:
476	{
477	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
478	*puValue = pHvCpu->uSint2Msr;
479	return VINF_SUCCESS;
480	}
481
482	case MSR_GIM_HV_SIMP:
483	{
484	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
485	*puValue = pHvCpu->uSimpMsr;
486	return VINF_SUCCESS;
487	}
488
489	case MSR_GIM_HV_RESET:
490	*puValue = 0;
491	return VINF_SUCCESS;
492
493	case MSR_GIM_HV_CRASH_CTL:
494	*puValue = pHv->uCrashCtlMsr;
495	return VINF_SUCCESS;
496
497	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
498	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
499	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
500	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
501	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
502
503	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
504	{
505	if (pHv->fIsVendorMsHv)
506	{
507	#ifndef IN_RING3
508	return VINF_CPUM_R3_MSR_READ;
509	#else
510	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
511	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
512	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
513	return VINF_SUCCESS;
514	#endif
515	}
516	return VERR_CPUM_RAISE_GP_0;
517	}
518
519	default:
520	{
521	#ifdef IN_RING3
522	static uint32_t s_cTimes = 0;
523	if (s_cTimes++ < 20)
524	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
525	#else
526	return VINF_CPUM_R3_MSR_READ;
527	#endif
528	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
529	break;
530	}
531	}
532
533	return VERR_CPUM_RAISE_GP_0;
534	}
535
536
537	/**
538	* MSR write handler for Hyper-V.
539	*
540	* @returns Strict VBox status code like CPUMSetGuestMsr().
541	* @retval VINF_CPUM_R3_MSR_WRITE
542	* @retval VERR_CPUM_RAISE_GP_0
543	*
544	* @param pVCpu The cross context virtual CPU structure.
545	* @param idMsr The MSR being written.
546	* @param pRange The range this MSR belongs to.
547	* @param uRawValue The raw value with the ignored bits not masked.
548	*
549	* @thread EMT.
550	*/
551	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
552	{
553	NOREF(pRange);
554	PVM pVM = pVCpu->CTX_SUFF(pVM);
555	PGIMHV pHv = &pVM->gim.s.u.Hv;
556
557	switch (idMsr)
558	{
559	case MSR_GIM_HV_TPR:
560	PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x80, uRawValue);
561	return VINF_SUCCESS;
562
563	case MSR_GIM_HV_EOI:
564	PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x0B, uRawValue);
565	return VINF_SUCCESS;
566
567	case MSR_GIM_HV_ICR:
568	PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x30, uRawValue);
569	return VINF_SUCCESS;
570
571	case MSR_GIM_HV_GUEST_OS_ID:
572	{
573	#ifndef IN_RING3
574	return VINF_CPUM_R3_MSR_WRITE;
575	#else
576	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
577	if (!uRawValue)
578	{
579	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
580	{
581	gimR3HvDisableHypercallPage(pVM);
582	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT;
583	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
584	}
585	}
586	else
587	{
588	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
589	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
590	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
591	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
592	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
593	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
594
595	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
596	CPUMCPUIDLEAF HyperLeaf;
597	RT_ZERO(HyperLeaf);
598	HyperLeaf.uLeaf = UINT32_C(0x40000002);
599	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
600	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
601	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
602	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
603	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
604	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
605	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
606	AssertRC(rc2);
607	}
608
609	pHv->u64GuestOsIdMsr = uRawValue;
610
611	/*
612	* Notify VMM that hypercalls are now disabled/enabled.
613	*/
614	for (VMCPUID i = 0; i < pVM->cCpus; i++)
615	{
616	if (uRawValue)
617	VMMHypercallsEnable(&pVM->aCpus[i]);
618	else
619	VMMHypercallsDisable(&pVM->aCpus[i]);
620	}
621
622	return VINF_SUCCESS;
623	#endif /* IN_RING3 */
624	}
625
626	case MSR_GIM_HV_HYPERCALL:
627	{
628	#ifndef IN_RING3
629	return VINF_CPUM_R3_MSR_WRITE;
630	#else
631	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
632	* see @bugref{7270#c116}. */
633	/* First, update all but the hypercall page enable bit. */
634	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
635
636	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
637	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
638	if ( fEnable
639	&& !gimHvAreHypercallsEnabled(pVCpu))
640	{
641	return VINF_SUCCESS;
642	}
643
644	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
645	if (!fEnable)
646	{
647	gimR3HvDisableHypercallPage(pVM);
648	pHv->u64HypercallMsr = uRawValue;
649	return VINF_SUCCESS;
650	}
651
652	/* Enable the hypercall-page. */
653	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
654	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
655	if (RT_SUCCESS(rc))
656	{
657	pHv->u64HypercallMsr = uRawValue;
658	return VINF_SUCCESS;
659	}
660
661	return VERR_CPUM_RAISE_GP_0;
662	#endif
663	}
664
665	case MSR_GIM_HV_REF_TSC:
666	{
667	#ifndef IN_RING3
668	return VINF_CPUM_R3_MSR_WRITE;
669	#else /* IN_RING3 */
670	/* First, update all but the TSC-page enable bit. */
671	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
672
673	/* Is the guest disabling the TSC-page? */
674	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
675	if (!fEnable)
676	{
677	gimR3HvDisableTscPage(pVM);
678	pHv->u64TscPageMsr = uRawValue;
679	return VINF_SUCCESS;
680	}
681
682	/* Enable the TSC-page. */
683	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
684	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
685	if (RT_SUCCESS(rc))
686	{
687	pHv->u64TscPageMsr = uRawValue;
688	return VINF_SUCCESS;
689	}
690
691	return VERR_CPUM_RAISE_GP_0;
692	#endif /* IN_RING3 */
693	}
694
695	case MSR_GIM_HV_RESET:
696	{
697	#ifndef IN_RING3
698	return VINF_CPUM_R3_MSR_WRITE;
699	#else
700	if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
701	{
702	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
703	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3);
704	AssertRC(rc);
705	}
706	/* else: Ignore writes to other bits. */
707	return VINF_SUCCESS;
708	#endif /* IN_RING3 */
709	}
710
711	case MSR_GIM_HV_CRASH_CTL:
712	{
713	#ifndef IN_RING3
714	return VINF_CPUM_R3_MSR_WRITE;
715	#else
716	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT)
717	{
718	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
719	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
720	}
721	return VINF_SUCCESS;
722	#endif
723	}
724
725	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
726	{
727	if (!pHv->fDbgEnabled)
728	return VERR_CPUM_RAISE_GP_0;
729	#ifndef IN_RING3
730	return VINF_CPUM_R3_MSR_WRITE;
731	#else
732	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
733	pHv->uDbgSendBufferMsr = GCPhysBuffer;
734	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
735	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
736	else
737	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
738	pHv->uDbgSendBufferMsr = uRawValue;
739	return VINF_SUCCESS;
740	#endif
741	}
742
743	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
744	{
745	if (!pHv->fDbgEnabled)
746	return VERR_CPUM_RAISE_GP_0;
747	#ifndef IN_RING3
748	return VINF_CPUM_R3_MSR_WRITE;
749	#else
750	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
751	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
752	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
753	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
754	else
755	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
756	return VINF_SUCCESS;
757	#endif
758	}
759
760	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
761	{
762	if (!pHv->fDbgEnabled)
763	return VERR_CPUM_RAISE_GP_0;
764	#ifndef IN_RING3
765	return VINF_CPUM_R3_MSR_WRITE;
766	#else
767	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
768	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
769	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
770	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
771	else
772	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
773	return VINF_SUCCESS;
774	#endif
775	}
776
777	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
778	{
779	if (!pHv->fDbgEnabled)
780	return VERR_CPUM_RAISE_GP_0;
781	#ifndef IN_RING3
782	return VINF_CPUM_R3_MSR_WRITE;
783	#else
784	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
785	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
786	{
787	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
788	return VERR_CPUM_RAISE_GP_0;
789	}
790
791	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
792	{
793	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
794	if ( cbWrite > 0
795	&& cbWrite < GIM_HV_PAGE_SIZE)
796	{
797	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
798	{
799	Assert(pHv->pvDbgBuffer);
800	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
801	if (RT_SUCCESS(rc))
802	{
803	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
804	uint32_t cbWritten = 0;
805	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
806	if ( RT_SUCCESS(rc)
807	&& cbWrite == cbWritten)
808	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS_BIT;
809	else
810	pHv->uDbgStatusMsr = 0;
811	}
812	else
813	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
814	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
815	}
816	else
817	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
818	(RTGCPHYS)pHv->uDbgSendBufferMsr));
819	}
820	else
821	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
822	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
823	}
824	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
825	{
826	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
827	{
828	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
829	uint32_t cbReallyRead;
830	Assert(pHv->pvDbgBuffer);
831	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
832	if ( RT_SUCCESS(rc)
833	&& cbReallyRead > 0)
834	{
835	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
836	if (RT_SUCCESS(rc))
837	{
838	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
839	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS_BIT;
840	}
841	else
842	{
843	pHv->uDbgStatusMsr = 0;
844	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
845	}
846	}
847	else
848	pHv->uDbgStatusMsr = 0;
849	}
850	else
851	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n"));
852	}
853	return VINF_SUCCESS;
854	#endif
855	}
856
857	case MSR_GIM_HV_SINT2:
858	{
859	if (!pHv->fDbgEnabled)
860	return VERR_CPUM_RAISE_GP_0;
861	#ifndef IN_RING3
862	return VINF_CPUM_R3_MSR_WRITE;
863	#else
864	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
865	uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
866	if ( !MSR_GIM_HV_SINT_IS_MASKED(uRawValue)
867	&& uVector < 16)
868	{
869	LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2, uVector=%u -> #GP(0)\n", uVector));
870	return VERR_CPUM_RAISE_GP_0;
871	}
872
873	pHvCpu->uSint2Msr = uRawValue;
874	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
875	LogRel(("GIM: HyperV: Masked SINT2\n"));
876	else
877	LogRel(("GIM: HyperV: Unmasked SINT2, uVector=%u\n", uVector));
878	return VINF_SUCCESS;
879	#endif
880	}
881
882	case MSR_GIM_HV_SIMP:
883	{
884	if (!pHv->fDbgEnabled)
885	return VERR_CPUM_RAISE_GP_0;
886	#ifndef IN_RING3
887	return VINF_CPUM_R3_MSR_WRITE;
888	#else
889	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
890	pHvCpu->uSimpMsr = uRawValue;
891	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
892	{
893	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
894	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
895	{
896	uint8_t abSimp[PAGE_SIZE];
897	RT_ZERO(abSimp);
898	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
899	if (RT_SUCCESS(rc2))
900	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at %#RGp\n", GCPhysSimp));
901	else
902	{
903	LogRel(("GIM: HyperV: WrMsr on MSR_GIM_HV_SIMP failed to update SIMP at %#RGp rc=%Rrc -> #GP(0)\n",
904	GCPhysSimp, rc2));
905	return VERR_CPUM_RAISE_GP_0;
906	}
907	}
908	else
909	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n",GCPhysSimp));
910	}
911	else
912	LogRel(("GIM: HyperV: Disabled synthetic interrupt message page\n"));
913	return VINF_SUCCESS;
914	#endif
915	}
916
917	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
918	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
919	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
920	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
921	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
922
923	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
924	case MSR_GIM_HV_VP_INDEX:
925	case MSR_GIM_HV_TSC_FREQ:
926	case MSR_GIM_HV_APIC_FREQ:
927	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
928	return VERR_CPUM_RAISE_GP_0;
929
930	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
931	{
932	if (pHv->fIsVendorMsHv)
933	{
934	#ifndef IN_RING3
935	return VINF_CPUM_R3_MSR_WRITE;
936	#else
937	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
938	return VINF_SUCCESS;
939	#endif
940	}
941	return VERR_CPUM_RAISE_GP_0;
942	}
943
944	default:
945	{
946	#ifdef IN_RING3
947	static uint32_t s_cTimes = 0;
948	if (s_cTimes++ < 20)
949	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
950	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
951	#else
952	return VINF_CPUM_R3_MSR_WRITE;
953	#endif
954	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
955	break;
956	}
957	}
958
959	return VERR_CPUM_RAISE_GP_0;
960	}
961
962
963	/**
964	* Whether we need to trap \#UD exceptions in the guest.
965	*
966	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
967	* enabled. For HM VMs, the hypercall would be handled via the
968	* VMCALL/VMMCALL VM-exit.
969	*
970	* @param pVCpu The cross context virtual CPU structure.
971	*/
972	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
973	{
974	PVM pVM = pVCpu->CTX_SUFF(pVM);
975	if ( !HMIsEnabled(pVM)
976	&& gimHvAreHypercallsEnabled(pVCpu))
977	return true;
978	return false;
979	}
980
981
982	/**
983	* Exception handler for \#UD.
984	*
985	* @param pVCpu The cross context virtual CPU structure.
986	* @param pCtx Pointer to the guest-CPU context.
987	* @param pDis Pointer to the disassembled instruction state at RIP.
988	* Optional, can be NULL.
989	*
990	* @thread EMT.
991	*/
992	VMM_INT_DECL(int) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
993	{
994	/*
995	* If we didn't ask for #UD to be trapped, bail.
996	*/
997	PVM pVM = pVCpu->CTX_SUFF(pVM);
998	if (!gimHvShouldTrapXcptUD(pVCpu))
999	return VERR_GIM_OPERATION_FAILED;
1000
1001	int rc = VINF_SUCCESS;
1002	if (!pDis)
1003	{
1004	/*
1005	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1006	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1007	*/
1008	DISCPUSTATE Dis;
1009	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
1010	pDis = &Dis;
1011	}
1012
1013	if (RT_SUCCESS(rc))
1014	{
1015	CPUMCPUVENDOR enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1016	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1017	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1018	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1019	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1020	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1021	{
1022	/*
1023	* Make sure guest ring-0 is the one making the hypercall.
1024	*/
1025	if (CPUMGetGuestCPL(pVCpu))
1026	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
1027
1028	/*
1029	* Update RIP and perform the hypercall.
1030	*/
1031	pCtx->rip += pDis->cbInstr;
1032	rc = gimHvHypercall(pVCpu, pCtx);
1033	}
1034	else
1035	rc = VERR_GIM_OPERATION_FAILED;
1036	}
1037	return rc;
1038	}
1039

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 58591

Download in other formats: