GIMAllHv.cpp@ 61568

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1	/* $Id: GIMAllHv.cpp 61559 2016-06-08 08:28:30Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include "GIMHvInternal.h"
24	#include "GIMInternal.h"
25
26	#include <iprt/asm-amd64-x86.h>
27	#ifdef IN_RING3
28	# include <iprt/mem.h>
29	#endif
30
31	#include <VBox/err.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/hm.h>
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/pdmdev.h>
38	#include <VBox/vmm/pdmapi.h>
39
40
41	#ifdef IN_RING3
42	/**
43	* Read and validate slow hypercall parameters.
44	*
45	* @returns VBox status code.
46	* @param pVM The cross context VM structure.
47	* @param pCtx Pointer to the guest-CPU context.
48	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
49	* @param enmParam The hypercall parameter type.
50	* @param prcHv Where to store the Hyper-V status code. Only valid
51	* to the caller when this function returns
52	* VINF_SUCCESS.
53	*/
54	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
55	{
56	int rc = VINF_SUCCESS;
57	PGIMHV pHv = &pVM->gim.s.u.Hv;
58	RTGCPHYS GCPhysParam;
59	void *pvDst;
60	if (enmParam == GIMHVHYPERCALLPARAM_IN)
61	{
62	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
63	pvDst = pHv->pbHypercallIn;
64	pHv->GCPhysHypercallIn = GCPhysParam;
65	}
66	else
67	{
68	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
69	pvDst = pHv->pbHypercallOut;
70	pHv->GCPhysHypercallOut = GCPhysParam;
71	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
72	}
73
74	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
75	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
76	{
77	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
78	{
79	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
80	if (RT_SUCCESS(rc))
81	{
82	*prcHv = GIM_HV_STATUS_SUCCESS;
83	return VINF_SUCCESS;
84	}
85	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
86	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
87	}
88	else
89	{
90	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
91	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
92	}
93	}
94	else
95	{
96	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
97	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
98	}
99	return rc;
100	}
101
102
103	/**
104	* Helper for reading and validating slow hypercall input and output parameters.
105	*
106	* @returns VBox status code.
107	* @param pVM The cross context VM structure.
108	* @param pCtx Pointer to the guest-CPU context.
109	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
110	* @param prcHv Where to store the Hyper-V status code. Only valid
111	* to the caller when this function returns
112	* VINF_SUCCESS.
113	*/
114	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
115	{
116	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
117	if ( RT_SUCCESS(rc)
118	&& *prcHv == GIM_HV_STATUS_SUCCESS)
119	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
120	return rc;
121	}
122	#endif
123
124
125	/**
126	* Handles all Hyper-V hypercalls.
127	*
128	* @returns Strict VBox status code.
129	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
130	* failed).
131	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
132	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
133	* guest.
134	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
135	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
136	* memory.
137	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
138	* writing memory.
139	*
140	* @param pVCpu The cross context virtual CPU structure.
141	* @param pCtx Pointer to the guest-CPU context.
142	*
143	* @thread EMT(pVCpu).
144	*/
145	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
146	{
147	VMCPU_ASSERT_EMT(pVCpu);
148
149	#ifndef IN_RING3
150	return VINF_GIM_R3_HYPERCALL;
151	#else
152	PVM pVM = pVCpu->CTX_SUFF(pVM);
153	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
154
155	/*
156	* Verify that hypercalls are enabled by the guest.
157	*/
158	if (!gimHvAreHypercallsEnabled(pVCpu))
159	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
160
161	/*
162	* Verify guest is in ring-0 protected mode.
163	*/
164	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
165	if ( uCpl
166	\|\| CPUMIsGuestInRealModeEx(pCtx))
167	{
168	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
169	}
170
171	/*
172	* Get the hypercall operation code and modes.
173	*/
174	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
175	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
176	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
177	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
178	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
179	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
180	uint64_t cHyperRepsDone = 0;
181
182	int rc = VINF_SUCCESS;
183	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
184	PGIMHV pHv = &pVM->gim.s.u.Hv;
185
186	/*
187	* Validate common hypercall input parameters.
188	*/
189	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
190	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
191	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
192	{
193	/*
194	* Perform the hypercall.
195	*/
196	switch (uHyperOp)
197	{
198	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
199	{
200	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
201	{
202	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
203	if ( RT_SUCCESS(rc)
204	&& rcHv == GIM_HV_STATUS_SUCCESS)
205	{
206	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
207	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
208	if (RT_FAILURE(rc))
209	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
210	}
211	}
212	else
213	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
214	break;
215	}
216
217	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
218	{
219	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
220	{
221	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
222	if ( RT_SUCCESS(rc)
223	&& rcHv == GIM_HV_STATUS_SUCCESS)
224	{
225	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
226	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
227	if (RT_FAILURE(rc))
228	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
229	}
230	}
231	else
232	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
233	break;
234	}
235
236	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
237	{
238	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
239	{
240	uint32_t fFlags = 0;
241	if (!fHyperFast)
242	{
243	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
244	if ( RT_SUCCESS(rc)
245	&& rcHv == GIM_HV_STATUS_SUCCESS)
246	{
247	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
248	fFlags = pIn->fFlags;
249	}
250	}
251	else
252	{
253	rcHv = GIM_HV_STATUS_SUCCESS;
254	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
255	}
256
257	/*
258	* Nothing to flush on the sending side as we don't maintain our own buffers.
259	*/
260	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
261	if (rcHv == GIM_HV_STATUS_SUCCESS)
262	{
263	if (fFlags)
264	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
265	else
266	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
267	}
268	}
269	else
270	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
271	break;
272	}
273
274	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
275	{
276	if (pHv->fIsInterfaceVs)
277	{
278	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
279	if ( RT_SUCCESS(rc)
280	&& rcHv == GIM_HV_STATUS_SUCCESS)
281	{
282	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
283	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
284	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
285	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
286	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->uSint2Msr)
287	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
288	{
289	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
290	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
291	{
292	/*
293	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
294	*/
295	GIMHVMSG HvMsg;
296	RT_ZERO(HvMsg);
297	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
298	HvMsg.MsgHdr.cbPayload = 0xf;
299	HvMsg.aPayload[0] = 0xf;
300	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
301	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
302	if (RT_SUCCESS(rc2))
303	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
304	else
305	{
306	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
307	offMsg, rc));
308	}
309	}
310	}
311
312	/*
313	* Make the call fail after updating the SIMP, so the guest can go back to using
314	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
315	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
316	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
317	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
318	*/
319	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
320	}
321	else
322	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
323	}
324	else
325	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
326	break;
327	}
328
329	default:
330	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
331	break;
332	}
333	}
334	else
335	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
336
337	/*
338	* Update the guest with results of the hypercall.
339	*/
340	if (RT_SUCCESS(rc))
341	{
342	if (fIs64BitMode)
343	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
344	else
345	{
346	pCtx->edx = cHyperRepsDone;
347	pCtx->eax = rcHv;
348	}
349	}
350
351	return rc;
352	#endif
353	}
354
355
356	/**
357	* Returns whether the guest has configured and enabled the use of Hyper-V's
358	* hypercall interface.
359	*
360	* @returns true if hypercalls are enabled, false otherwise.
361	* @param pVCpu The cross context virtual CPU structure.
362	*/
363	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
364	{
365	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
366	}
367
368
369	/**
370	* Returns whether the guest has configured and enabled the use of Hyper-V's
371	* paravirtualized TSC.
372	*
373	* @returns true if paravirt. TSC is enabled, false otherwise.
374	* @param pVM The cross context VM structure.
375	*/
376	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
377	{
378	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
379	}
380
381
382	#ifdef IN_RING3
383	/**
384	* Gets the descriptive OS ID variant as identified via the
385	* MSR_GIM_HV_GUEST_OS_ID MSR.
386	*
387	* @returns The name.
388	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
389	*/
390	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
391	{
392	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
393	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
394	if (uVendor == 1 /* Microsoft */)
395	{
396	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
397	switch (uOsVariant)
398	{
399	case 0: return "Undefined";
400	case 1: return "MS-DOS";
401	case 2: return "Windows 3.x";
402	case 3: return "Windows 9x";
403	case 4: return "Windows NT or derivative";
404	case 5: return "Windows CE";
405	default: return "Unknown";
406	}
407	}
408	return "Unknown";
409	}
410	#endif
411
412
413	/**
414	* MSR read handler for Hyper-V.
415	*
416	* @returns Strict VBox status code like CPUMQueryGuestMsr().
417	* @retval VINF_CPUM_R3_MSR_READ
418	* @retval VERR_CPUM_RAISE_GP_0
419	*
420	* @param pVCpu The cross context virtual CPU structure.
421	* @param idMsr The MSR being read.
422	* @param pRange The range this MSR belongs to.
423	* @param puValue Where to store the MSR value read.
424	*
425	* @thread EMT.
426	*/
427	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
428	{
429	NOREF(pRange);
430	PVM pVM = pVCpu->CTX_SUFF(pVM);
431	PGIMHV pHv = &pVM->gim.s.u.Hv;
432
433	switch (idMsr)
434	{
435	case MSR_GIM_HV_TIME_REF_COUNT:
436	{
437	/* Hyper-V reports the time in 100 ns units (10 MHz). */
438	uint64_t u64Tsc = TMCpuTickGet(pVCpu);
439	uint64_t u64TscHz = pHv->cTscTicksPerSecond;
440	uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
441	*puValue = (u64Tsc / u64Tsc100Ns);
442	return VINF_SUCCESS;
443	}
444
445	case MSR_GIM_HV_VP_INDEX:
446	*puValue = pVCpu->idCpu;
447	return VINF_SUCCESS;
448
449	case MSR_GIM_HV_TPR:
450	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_TPR, puValue);
451
452	case MSR_GIM_HV_ICR:
453	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_ICR, puValue);
454
455	case MSR_GIM_HV_GUEST_OS_ID:
456	*puValue = pHv->u64GuestOsIdMsr;
457	return VINF_SUCCESS;
458
459	case MSR_GIM_HV_HYPERCALL:
460	*puValue = pHv->u64HypercallMsr;
461	return VINF_SUCCESS;
462
463	case MSR_GIM_HV_REF_TSC:
464	*puValue = pHv->u64TscPageMsr;
465	return VINF_SUCCESS;
466
467	case MSR_GIM_HV_TSC_FREQ:
468	*puValue = TMCpuTicksPerSecond(pVM);
469	return VINF_SUCCESS;
470
471	case MSR_GIM_HV_APIC_FREQ:
472	{
473	int rc = PDMApicGetTimerFreq(pVM, puValue);
474	if (RT_FAILURE(rc))
475	return VERR_CPUM_RAISE_GP_0;
476	return VINF_SUCCESS;
477	}
478
479	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
480	*puValue = pHv->uDbgStatusMsr;
481	return VINF_SUCCESS;
482
483	case MSR_GIM_HV_SINT2:
484	{
485	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
486	*puValue = pHvCpu->uSint2Msr;
487	return VINF_SUCCESS;
488	}
489
490	case MSR_GIM_HV_SIMP:
491	{
492	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
493	*puValue = pHvCpu->uSimpMsr;
494	return VINF_SUCCESS;
495	}
496
497	case MSR_GIM_HV_RESET:
498	*puValue = 0;
499	return VINF_SUCCESS;
500
501	case MSR_GIM_HV_CRASH_CTL:
502	*puValue = pHv->uCrashCtlMsr;
503	return VINF_SUCCESS;
504
505	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
506	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
507	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
508	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
509	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
510
511	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
512	{
513	if (pHv->fIsVendorMsHv)
514	{
515	#ifndef IN_RING3
516	return VINF_CPUM_R3_MSR_READ;
517	#else
518	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
519	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
520	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
521	return VINF_SUCCESS;
522	#endif
523	}
524	return VERR_CPUM_RAISE_GP_0;
525	}
526
527	/* Write-only MSRs: */
528	case MSR_GIM_HV_EOI:
529	/* Reserved/unknown MSRs: */
530	default:
531	{
532	#ifdef IN_RING3
533	static uint32_t s_cTimes = 0;
534	if (s_cTimes++ < 20)
535	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
536	#else
537	return VINF_CPUM_R3_MSR_READ;
538	#endif
539	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
540	break;
541	}
542	}
543
544	return VERR_CPUM_RAISE_GP_0;
545	}
546
547
548	/**
549	* MSR write handler for Hyper-V.
550	*
551	* @returns Strict VBox status code like CPUMSetGuestMsr().
552	* @retval VINF_CPUM_R3_MSR_WRITE
553	* @retval VERR_CPUM_RAISE_GP_0
554	*
555	* @param pVCpu The cross context virtual CPU structure.
556	* @param idMsr The MSR being written.
557	* @param pRange The range this MSR belongs to.
558	* @param uRawValue The raw value with the ignored bits not masked.
559	*
560	* @thread EMT.
561	*/
562	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
563	{
564	NOREF(pRange);
565	PVM pVM = pVCpu->CTX_SUFF(pVM);
566	PGIMHV pHv = &pVM->gim.s.u.Hv;
567
568	switch (idMsr)
569	{
570	case MSR_GIM_HV_TPR:
571	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_TPR, uRawValue);
572
573	case MSR_GIM_HV_EOI:
574	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_EOI, uRawValue);
575
576	case MSR_GIM_HV_ICR:
577	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_ICR, uRawValue);
578
579	case MSR_GIM_HV_GUEST_OS_ID:
580	{
581	#ifndef IN_RING3
582	return VINF_CPUM_R3_MSR_WRITE;
583	#else
584	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
585	if (!uRawValue)
586	{
587	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
588	{
589	gimR3HvDisableHypercallPage(pVM);
590	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT;
591	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
592	}
593	}
594	else
595	{
596	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
597	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
598	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
599	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
600	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
601	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
602
603	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
604	CPUMCPUIDLEAF HyperLeaf;
605	RT_ZERO(HyperLeaf);
606	HyperLeaf.uLeaf = UINT32_C(0x40000002);
607	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
608	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
609	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
610	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
611	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
612	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
613	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
614	AssertRC(rc2);
615	}
616
617	pHv->u64GuestOsIdMsr = uRawValue;
618
619	/*
620	* Notify VMM that hypercalls are now disabled/enabled.
621	*/
622	for (VMCPUID i = 0; i < pVM->cCpus; i++)
623	{
624	if (uRawValue)
625	VMMHypercallsEnable(&pVM->aCpus[i]);
626	else
627	VMMHypercallsDisable(&pVM->aCpus[i]);
628	}
629
630	return VINF_SUCCESS;
631	#endif /* IN_RING3 */
632	}
633
634	case MSR_GIM_HV_HYPERCALL:
635	{
636	#ifndef IN_RING3
637	return VINF_CPUM_R3_MSR_WRITE;
638	#else
639	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
640	* see @bugref{7270#c116}. */
641	/* First, update all but the hypercall page enable bit. */
642	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
643
644	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
645	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);
646	if ( fEnable
647	&& !gimHvAreHypercallsEnabled(pVCpu))
648	{
649	return VINF_SUCCESS;
650	}
651
652	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
653	if (!fEnable)
654	{
655	gimR3HvDisableHypercallPage(pVM);
656	pHv->u64HypercallMsr = uRawValue;
657	return VINF_SUCCESS;
658	}
659
660	/* Enable the hypercall-page. */
661	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
662	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
663	if (RT_SUCCESS(rc))
664	{
665	pHv->u64HypercallMsr = uRawValue;
666	return VINF_SUCCESS;
667	}
668
669	return VERR_CPUM_RAISE_GP_0;
670	#endif
671	}
672
673	case MSR_GIM_HV_REF_TSC:
674	{
675	#ifndef IN_RING3
676	return VINF_CPUM_R3_MSR_WRITE;
677	#else /* IN_RING3 */
678	/* First, update all but the TSC-page enable bit. */
679	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
680
681	/* Is the guest disabling the TSC-page? */
682	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
683	if (!fEnable)
684	{
685	gimR3HvDisableTscPage(pVM);
686	pHv->u64TscPageMsr = uRawValue;
687	return VINF_SUCCESS;
688	}
689
690	/* Enable the TSC-page. */
691	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
692	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
693	if (RT_SUCCESS(rc))
694	{
695	pHv->u64TscPageMsr = uRawValue;
696	return VINF_SUCCESS;
697	}
698
699	return VERR_CPUM_RAISE_GP_0;
700	#endif /* IN_RING3 */
701	}
702
703	case MSR_GIM_HV_RESET:
704	{
705	#ifndef IN_RING3
706	return VINF_CPUM_R3_MSR_WRITE;
707	#else
708	if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
709	{
710	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
711	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
712	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
713	}
714	/* else: Ignore writes to other bits. */
715	return VINF_SUCCESS;
716	#endif /* IN_RING3 */
717	}
718
719	case MSR_GIM_HV_CRASH_CTL:
720	{
721	#ifndef IN_RING3
722	return VINF_CPUM_R3_MSR_WRITE;
723	#else
724	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT)
725	{
726	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
727	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
728	}
729	return VINF_SUCCESS;
730	#endif
731	}
732
733	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
734	{
735	if (!pHv->fDbgEnabled)
736	return VERR_CPUM_RAISE_GP_0;
737	#ifndef IN_RING3
738	return VINF_CPUM_R3_MSR_WRITE;
739	#else
740	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
741	pHv->uDbgSendBufferMsr = GCPhysBuffer;
742	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
743	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
744	else
745	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
746	pHv->uDbgSendBufferMsr = uRawValue;
747	return VINF_SUCCESS;
748	#endif
749	}
750
751	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
752	{
753	if (!pHv->fDbgEnabled)
754	return VERR_CPUM_RAISE_GP_0;
755	#ifndef IN_RING3
756	return VINF_CPUM_R3_MSR_WRITE;
757	#else
758	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
759	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
760	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
761	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
762	else
763	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
764	return VINF_SUCCESS;
765	#endif
766	}
767
768	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
769	{
770	if (!pHv->fDbgEnabled)
771	return VERR_CPUM_RAISE_GP_0;
772	#ifndef IN_RING3
773	return VINF_CPUM_R3_MSR_WRITE;
774	#else
775	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
776	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
777	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
778	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
779	else
780	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
781	return VINF_SUCCESS;
782	#endif
783	}
784
785	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
786	{
787	if (!pHv->fDbgEnabled)
788	return VERR_CPUM_RAISE_GP_0;
789	#ifndef IN_RING3
790	return VINF_CPUM_R3_MSR_WRITE;
791	#else
792	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
793	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
794	{
795	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
796	return VERR_CPUM_RAISE_GP_0;
797	}
798
799	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
800	{
801	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
802	if ( cbWrite > 0
803	&& cbWrite < GIM_HV_PAGE_SIZE)
804	{
805	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
806	{
807	Assert(pHv->pvDbgBuffer);
808	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
809	if (RT_SUCCESS(rc))
810	{
811	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
812	uint32_t cbWritten = 0;
813	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
814	if ( RT_SUCCESS(rc)
815	&& cbWrite == cbWritten)
816	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS_BIT;
817	else
818	pHv->uDbgStatusMsr = 0;
819	}
820	else
821	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
822	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
823	}
824	else
825	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
826	(RTGCPHYS)pHv->uDbgSendBufferMsr));
827	}
828	else
829	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
830	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
831	}
832	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
833	{
834	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
835	{
836	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
837	uint32_t cbReallyRead;
838	Assert(pHv->pvDbgBuffer);
839	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
840	if ( RT_SUCCESS(rc)
841	&& cbReallyRead > 0)
842	{
843	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
844	if (RT_SUCCESS(rc))
845	{
846	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
847	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS_BIT;
848	}
849	else
850	{
851	pHv->uDbgStatusMsr = 0;
852	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
853	}
854	}
855	else
856	pHv->uDbgStatusMsr = 0;
857	}
858	else
859	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n", (RTGCPHYS)pHv->uDbgRecvBufferMsr));
860	}
861	return VINF_SUCCESS;
862	#endif
863	}
864
865	case MSR_GIM_HV_SINT2:
866	{
867	if (!pHv->fDbgEnabled)
868	return VERR_CPUM_RAISE_GP_0;
869	#ifndef IN_RING3
870	return VINF_CPUM_R3_MSR_WRITE;
871	#else
872	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
873	uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
874	if ( !MSR_GIM_HV_SINT_IS_MASKED(uRawValue)
875	&& uVector < 16)
876	{
877	LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2, uVector=%u -> #GP(0)\n", uVector));
878	return VERR_CPUM_RAISE_GP_0;
879	}
880
881	pHvCpu->uSint2Msr = uRawValue;
882	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
883	LogRel(("GIM: HyperV: Masked SINT2\n"));
884	else
885	LogRel(("GIM: HyperV: Unmasked SINT2, uVector=%u\n", uVector));
886	return VINF_SUCCESS;
887	#endif
888	}
889
890	case MSR_GIM_HV_SIMP:
891	{
892	if (!pHv->fDbgEnabled)
893	return VERR_CPUM_RAISE_GP_0;
894	#ifndef IN_RING3
895	return VINF_CPUM_R3_MSR_WRITE;
896	#else
897	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
898	pHvCpu->uSimpMsr = uRawValue;
899	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
900	{
901	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
902	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
903	{
904	uint8_t abSimp[PAGE_SIZE];
905	RT_ZERO(abSimp);
906	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
907	if (RT_SUCCESS(rc2))
908	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at %#RGp\n", GCPhysSimp));
909	else
910	{
911	LogRel(("GIM: HyperV: WrMsr on MSR_GIM_HV_SIMP failed to update SIMP at %#RGp rc=%Rrc -> #GP(0)\n",
912	GCPhysSimp, rc2));
913	return VERR_CPUM_RAISE_GP_0;
914	}
915	}
916	else
917	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n",GCPhysSimp));
918	}
919	else
920	LogRel(("GIM: HyperV: Disabled synthetic interrupt message page\n"));
921	return VINF_SUCCESS;
922	#endif
923	}
924
925	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
926	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
927	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
928	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
929	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
930
931	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
932	case MSR_GIM_HV_VP_INDEX:
933	case MSR_GIM_HV_TSC_FREQ:
934	case MSR_GIM_HV_APIC_FREQ:
935	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
936	return VERR_CPUM_RAISE_GP_0;
937
938	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
939	{
940	if (pHv->fIsVendorMsHv)
941	{
942	#ifndef IN_RING3
943	return VINF_CPUM_R3_MSR_WRITE;
944	#else
945	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
946	return VINF_SUCCESS;
947	#endif
948	}
949	return VERR_CPUM_RAISE_GP_0;
950	}
951
952	default:
953	{
954	#ifdef IN_RING3
955	static uint32_t s_cTimes = 0;
956	if (s_cTimes++ < 20)
957	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
958	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
959	#else
960	return VINF_CPUM_R3_MSR_WRITE;
961	#endif
962	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
963	break;
964	}
965	}
966
967	return VERR_CPUM_RAISE_GP_0;
968	}
969
970
971	/**
972	* Whether we need to trap \#UD exceptions in the guest.
973	*
974	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
975	* enabled. For HM VMs, the hypercall would be handled via the
976	* VMCALL/VMMCALL VM-exit.
977	*
978	* @param pVCpu The cross context virtual CPU structure.
979	*/
980	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
981	{
982	PVM pVM = pVCpu->CTX_SUFF(pVM);
983	if ( !HMIsEnabled(pVM)
984	&& gimHvAreHypercallsEnabled(pVCpu))
985	return true;
986	return false;
987	}
988
989
990	/**
991	* Checks the currently disassembled instruction and executes the hypercall if
992	* it's a hypercall instruction.
993	*
994	* @returns Strict VBox status code.
995	* @param pVCpu The cross context virtual CPU structure.
996	* @param pCtx Pointer to the guest-CPU context.
997	* @param pDis Pointer to the disassembled instruction state at RIP.
998	*
999	* @thread EMT(pVCpu).
1000	*
1001	* @todo Make this function static when @bugref{7270#c168} is addressed.
1002	*/
1003	VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
1004	{
1005	Assert(pVCpu);
1006	Assert(pCtx);
1007	Assert(pDis);
1008	VMCPU_ASSERT_EMT(pVCpu);
1009
1010	PVM pVM = pVCpu->CTX_SUFF(pVM);
1011	CPUMCPUVENDOR const enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1012	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1013	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1014	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1015	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1016	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1017	{
1018	return gimHvHypercall(pVCpu, pCtx);
1019	}
1020
1021	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1022	}
1023
1024
1025	/**
1026	* Exception handler for \#UD.
1027	*
1028	* @returns Strict VBox status code.
1029	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1030	* failed).
1031	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1032	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1033	* RIP.
1034	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1035	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1036	* hypercall instruction.
1037	*
1038	* @param pVCpu The cross context virtual CPU structure.
1039	* @param pCtx Pointer to the guest-CPU context.
1040	* @param pDis Pointer to the disassembled instruction state at RIP.
1041	* Optional, can be NULL.
1042	* @param pcbInstr Where to store the instruction length of the hypercall
1043	* instruction. Optional, can be NULL.
1044	*
1045	* @thread EMT(pVCpu).
1046	*/
1047	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1048	{
1049	VMCPU_ASSERT_EMT(pVCpu);
1050
1051	/*
1052	* If we didn't ask for #UD to be trapped, bail.
1053	*/
1054	if (!gimHvShouldTrapXcptUD(pVCpu))
1055	return VERR_GIM_IPE_1;
1056
1057	if (!pDis)
1058	{
1059	/*
1060	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1061	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1062	*/
1063	unsigned cbInstr;
1064	DISCPUSTATE Dis;
1065	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1066	if (RT_SUCCESS(rc))
1067	{
1068	if (pcbInstr)
1069	*pcbInstr = (uint8_t)cbInstr;
1070	return gimHvExecHypercallInstr(pVCpu, pCtx, &Dis);
1071	}
1072
1073	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1074	return rc;
1075	}
1076
1077	return gimHvExecHypercallInstr(pVCpu, pCtx, pDis);
1078	}
1079

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 61568

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