GIMAllHv.cpp@ 78425

Last change on this file since 78425 was 76886, checked in by vboxsync, 6 years ago
VMM (and related changes): Add support for Shanghai/Zhaoxin CPUs. Modified and improved contribution by Journey Ren submitted under MIT license. Thank you!
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1	/* $Id: GIMAllHv.cpp 76886 2019-01-18 10:57:02Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include <VBox/vmm/apic.h>
32	#include <VBox/vmm/em.h>
33	#include "GIMHvInternal.h"
34	#include "GIMInternal.h"
35	#include <VBox/vmm/vm.h>
36
37	#include <VBox/err.h>
38
39	#include <iprt/asm-amd64-x86.h>
40	#ifdef IN_RING3
41	# include <iprt/mem.h>
42	#endif
43
44
45	#ifdef IN_RING3
46	/**
47	* Read and validate slow hypercall parameters.
48	*
49	* @returns VBox status code.
50	* @param pVM The cross context VM structure.
51	* @param pCtx Pointer to the guest-CPU context.
52	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
53	* @param enmParam The hypercall parameter type.
54	* @param prcHv Where to store the Hyper-V status code. Only valid
55	* to the caller when this function returns
56	* VINF_SUCCESS.
57	*/
58	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
59	{
60	int rc = VINF_SUCCESS;
61	PGIMHV pHv = &pVM->gim.s.u.Hv;
62	RTGCPHYS GCPhysParam;
63	void *pvDst;
64	if (enmParam == GIMHVHYPERCALLPARAM_IN)
65	{
66	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
67	pvDst = pHv->pbHypercallIn;
68	pHv->GCPhysHypercallIn = GCPhysParam;
69	}
70	else
71	{
72	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
73	pvDst = pHv->pbHypercallOut;
74	pHv->GCPhysHypercallOut = GCPhysParam;
75	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
76	}
77
78	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
79	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
80	{
81	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
82	{
83	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
84	if (RT_SUCCESS(rc))
85	{
86	*prcHv = GIM_HV_STATUS_SUCCESS;
87	return VINF_SUCCESS;
88	}
89	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
90	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
91	}
92	else
93	{
94	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
95	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
96	}
97	}
98	else
99	{
100	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
101	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
102	}
103	return rc;
104	}
105
106
107	/**
108	* Helper for reading and validating slow hypercall input and output parameters.
109	*
110	* @returns VBox status code.
111	* @param pVM The cross context VM structure.
112	* @param pCtx Pointer to the guest-CPU context.
113	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
114	* @param prcHv Where to store the Hyper-V status code. Only valid
115	* to the caller when this function returns
116	* VINF_SUCCESS.
117	*/
118	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
119	{
120	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
121	if ( RT_SUCCESS(rc)
122	&& *prcHv == GIM_HV_STATUS_SUCCESS)
123	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
124	return rc;
125	}
126	#endif
127
128
129	/**
130	* Handles all Hyper-V hypercalls.
131	*
132	* @returns Strict VBox status code.
133	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
134	* failed).
135	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
136	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
137	* guest.
138	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
139	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
140	* memory.
141	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
142	* writing memory.
143	*
144	* @param pVCpu The cross context virtual CPU structure.
145	* @param pCtx Pointer to the guest-CPU context.
146	*
147	* @thread EMT(pVCpu).
148	*/
149	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
150	{
151	VMCPU_ASSERT_EMT(pVCpu);
152
153	#ifndef IN_RING3
154	RT_NOREF_PV(pVCpu);
155	RT_NOREF_PV(pCtx);
156	return VINF_GIM_R3_HYPERCALL;
157	#else
158	PVM pVM = pVCpu->CTX_SUFF(pVM);
159	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
160
161	/*
162	* Verify that hypercalls are enabled by the guest.
163	*/
164	if (!gimHvAreHypercallsEnabled(pVCpu))
165	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
166
167	/*
168	* Verify guest is in ring-0 protected mode.
169	*/
170	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
171	if ( uCpl
172	\|\| CPUMIsGuestInRealModeEx(pCtx))
173	{
174	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
175	}
176
177	/*
178	* Get the hypercall operation code and modes.
179	* Fast hypercalls have only two or fewer inputs but no output parameters.
180	*/
181	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
182	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
183	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
184	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
185	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
186	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
187	uint64_t cHyperRepsDone = 0;
188
189	/* Currently no repeating hypercalls are supported. */
190	RT_NOREF2(cHyperReps, idxHyperRepStart);
191
192	int rc = VINF_SUCCESS;
193	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
194	PGIMHV pHv = &pVM->gim.s.u.Hv;
195
196	/*
197	* Validate common hypercall input parameters.
198	*/
199	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
200	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
201	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
202	{
203	/*
204	* Perform the hypercall.
205	*/
206	switch (uHyperOp)
207	{
208	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
209	{
210	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
211	{
212	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
213	if ( RT_SUCCESS(rc)
214	&& rcHv == GIM_HV_STATUS_SUCCESS)
215	{
216	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
217	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
218	if (RT_FAILURE(rc))
219	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
220	}
221	}
222	else
223	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
224	break;
225	}
226
227	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
228	{
229	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
230	{
231	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
232	if ( RT_SUCCESS(rc)
233	&& rcHv == GIM_HV_STATUS_SUCCESS)
234	{
235	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
236	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
237	if (RT_FAILURE(rc))
238	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
239	}
240	}
241	else
242	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
243	break;
244	}
245
246	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
247	{
248	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
249	{
250	uint32_t fFlags = 0;
251	if (!fHyperFast)
252	{
253	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
254	if ( RT_SUCCESS(rc)
255	&& rcHv == GIM_HV_STATUS_SUCCESS)
256	{
257	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
258	fFlags = pIn->fFlags;
259	}
260	}
261	else
262	{
263	rcHv = GIM_HV_STATUS_SUCCESS;
264	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
265	}
266
267	/*
268	* Nothing to flush on the sending side as we don't maintain our own buffers.
269	*/
270	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
271	if (rcHv == GIM_HV_STATUS_SUCCESS)
272	{
273	if (fFlags)
274	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
275	else
276	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
277	}
278	}
279	else
280	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
281	break;
282	}
283
284	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
285	{
286	if (pHv->fIsInterfaceVs)
287	{
288	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
289	if ( RT_SUCCESS(rc)
290	&& rcHv == GIM_HV_STATUS_SUCCESS)
291	{
292	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
293	PCGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
294	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
295	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
296	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintMsrs[GIM_HV_VMBUS_MSG_SINT])
297	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
298	{
299	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
300	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
301	{
302	/*
303	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
304	*/
305	GIMHVMSG HvMsg;
306	RT_ZERO(HvMsg);
307	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
308	HvMsg.MsgHdr.cbPayload = 0xf;
309	HvMsg.aPayload[0] = 0xf;
310	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
311	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
312	if (RT_SUCCESS(rc2))
313	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
314	else
315	{
316	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
317	offMsg, rc));
318	}
319	}
320	}
321
322	/*
323	* Make the call fail after updating the SIMP, so the guest can go back to using
324	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
325	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
326	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
327	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
328	*/
329	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
330	}
331	else
332	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
333	}
334	else
335	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
336	break;
337	}
338
339	case GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP: /* Non-rep, extended hypercall. */
340	{
341	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
342	{
343	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
344	if ( RT_SUCCESS(rc)
345	&& rcHv == GIM_HV_STATUS_SUCCESS)
346	{
347	rc = gimR3HvHypercallExtQueryCap(pVM, &rcHv);
348	}
349	}
350	else
351	{
352	LogRel(("GIM: HyperV: Denied HvExtCallQueryCapabilities when the feature is not exposed\n"));
353	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
354	}
355	break;
356	}
357
358	case GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM: /* Non-rep, extended hypercall. */
359	{
360	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
361	{
362	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
363	if ( RT_SUCCESS(rc)
364	&& rcHv == GIM_HV_STATUS_SUCCESS)
365	{
366	rc = gimR3HvHypercallExtGetBootZeroedMem(pVM, &rcHv);
367	}
368	}
369	else
370	{
371	LogRel(("GIM: HyperV: Denied HvExtCallGetBootZeroedMemory when the feature is not exposed\n"));
372	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
373	}
374	break;
375	}
376
377	default:
378	{
379	LogRel(("GIM: HyperV: Unknown/invalid hypercall opcode %#x (%u)\n", uHyperOp, uHyperOp));
380	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
381	break;
382	}
383	}
384	}
385	else
386	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
387
388	/*
389	* Update the guest with results of the hypercall.
390	*/
391	if (RT_SUCCESS(rc))
392	{
393	if (fIs64BitMode)
394	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
395	else
396	{
397	pCtx->edx = cHyperRepsDone;
398	pCtx->eax = rcHv;
399	}
400	}
401
402	return rc;
403	#endif
404	}
405
406
407	/**
408	* Returns whether the guest has configured and enabled the use of Hyper-V's
409	* hypercall interface.
410	*
411	* @returns true if hypercalls are enabled, false otherwise.
412	* @param pVCpu The cross context virtual CPU structure.
413	*/
414	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
415	{
416	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
417	}
418
419
420	/**
421	* Returns whether the guest has configured and enabled the use of Hyper-V's
422	* paravirtualized TSC.
423	*
424	* @returns true if paravirt. TSC is enabled, false otherwise.
425	* @param pVM The cross context VM structure.
426	*/
427	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
428	{
429	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
430	}
431
432
433	#ifdef IN_RING3
434	/**
435	* Gets the descriptive OS ID variant as identified via the
436	* MSR_GIM_HV_GUEST_OS_ID MSR.
437	*
438	* @returns The name.
439	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
440	*/
441	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
442	{
443	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
444	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
445	if (uVendor == 1 /* Microsoft */)
446	{
447	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
448	switch (uOsVariant)
449	{
450	case 0: return "Undefined";
451	case 1: return "MS-DOS";
452	case 2: return "Windows 3.x";
453	case 3: return "Windows 9x";
454	case 4: return "Windows NT or derivative";
455	case 5: return "Windows CE";
456	default: return "Unknown";
457	}
458	}
459	return "Unknown";
460	}
461	#endif
462
463	/**
464	* Gets the time reference count for the current VM.
465	*
466	* @returns The time reference count.
467	* @param pVCpu The cross context virtual CPU structure.
468	*/
469	DECLINLINE(uint64_t) gimHvGetTimeRefCount(PVMCPU pVCpu)
470	{
471	/* Hyper-V reports the time in 100 ns units (10 MHz). */
472	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
473	PCGIMHV pHv = &pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv;
474	uint64_t const u64Tsc = TMCpuTickGet(pVCpu); /** @todo should we be passing VCPU0 always? */
475	uint64_t const u64TscHz = pHv->cTscTicksPerSecond;
476	uint64_t const u64Tsc100NS = u64TscHz / UINT64_C(10000000); /* 100 ns */
477	uint64_t const uTimeRefCount = (u64Tsc / u64Tsc100NS);
478	return uTimeRefCount;
479	}
480
481
482	/**
483	* Starts the synthetic timer.
484	*
485	* @param pVCpu The cross context virtual CPU structure.
486	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
487	*
488	* @remarks Caller needs to hold the timer critical section.
489	* @thread Any.
490	*/
491	VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer)
492	{
493	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
494	Assert(TMTimerIsLockOwner(pTimer));
495
496	uint64_t const uTimerCount = pHvStimer->uStimerCountMsr;
497	if (uTimerCount)
498	{
499	uint64_t const uTimerCountNS = uTimerCount * 100;
500
501	/* For periodic timers, 'uTimerCountNS' represents the relative interval. */
502	if (MSR_GIM_HV_STIMER_IS_PERIODIC(pHvStimer->uStimerConfigMsr))
503	{
504	TMTimerSetNano(pTimer, uTimerCountNS);
505	LogFlow(("GIM%u: HyperV: Started relative periodic STIMER%u with uTimerCountNS=%RU64\n", pVCpu->idCpu,
506	pHvStimer->idxStimer, uTimerCountNS));
507	}
508	else
509	{
510	/* For one-shot timers, 'uTimerCountNS' represents an absolute expiration wrt to Hyper-V reference time,
511	we convert it to a relative time and program the timer. */
512	uint64_t const uCurRefTimeNS = gimHvGetTimeRefCount(pVCpu) * 100;
513	if (uTimerCountNS > uCurRefTimeNS)
514	{
515	uint64_t const uRelativeNS = uTimerCountNS - uCurRefTimeNS;
516	TMTimerSetNano(pTimer, uRelativeNS);
517	LogFlow(("GIM%u: HyperV: Started one-shot relative STIMER%u with uRelativeNS=%RU64\n", pVCpu->idCpu,
518	pHvStimer->idxStimer, uRelativeNS));
519	}
520	}
521	/** @todo frequency hinting? */
522	}
523	}
524
525
526	/**
527	* Stops the synthetic timer for the given VCPU.
528	*
529	* @param pVCpu The cross context virtual CPU structure.
530	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
531	*
532	* @remarks Caller needs to the hold the timer critical section.
533	* @thread EMT(pVCpu).
534	*/
535	static void gimHvStopStimer(PVMCPU pVCpu, PGIMHVSTIMER pHvStimer)
536	{
537	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
538	RT_NOREF(pVCpu);
539
540	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
541	Assert(TMTimerIsLockOwner(pTimer));
542	RT_NOREF(pTimer);
543
544	if (TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
545	TMTimerStop(pHvStimer->CTX_SUFF(pTimer));
546	}
547
548
549	/**
550	* MSR read handler for Hyper-V.
551	*
552	* @returns Strict VBox status code like CPUMQueryGuestMsr().
553	* @retval VINF_CPUM_R3_MSR_READ
554	* @retval VERR_CPUM_RAISE_GP_0
555	*
556	* @param pVCpu The cross context virtual CPU structure.
557	* @param idMsr The MSR being read.
558	* @param pRange The range this MSR belongs to.
559	* @param puValue Where to store the MSR value read.
560	*
561	* @thread EMT.
562	*/
563	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
564	{
565	NOREF(pRange);
566	PVM pVM = pVCpu->CTX_SUFF(pVM);
567	PCGIMHV pHv = &pVM->gim.s.u.Hv;
568
569	switch (idMsr)
570	{
571	case MSR_GIM_HV_TIME_REF_COUNT:
572	*puValue = gimHvGetTimeRefCount(pVCpu);
573	return VINF_SUCCESS;
574
575	case MSR_GIM_HV_VP_INDEX:
576	*puValue = pVCpu->idCpu;
577	return VINF_SUCCESS;
578
579	case MSR_GIM_HV_TPR:
580	*puValue = APICHvGetTpr(pVCpu);
581	return VINF_SUCCESS;
582
583	case MSR_GIM_HV_ICR:
584	*puValue = APICHvGetIcr(pVCpu);
585	return VINF_SUCCESS;
586
587	case MSR_GIM_HV_GUEST_OS_ID:
588	*puValue = pHv->u64GuestOsIdMsr;
589	return VINF_SUCCESS;
590
591	case MSR_GIM_HV_HYPERCALL:
592	*puValue = pHv->u64HypercallMsr;
593	return VINF_SUCCESS;
594
595	case MSR_GIM_HV_REF_TSC:
596	*puValue = pHv->u64TscPageMsr;
597	return VINF_SUCCESS;
598
599	case MSR_GIM_HV_TSC_FREQ:
600	*puValue = TMCpuTicksPerSecond(pVM);
601	return VINF_SUCCESS;
602
603	case MSR_GIM_HV_APIC_FREQ:
604	{
605	int rc = APICGetTimerFreq(pVM, puValue);
606	if (RT_FAILURE(rc))
607	return VERR_CPUM_RAISE_GP_0;
608	return VINF_SUCCESS;
609	}
610
611	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
612	*puValue = pHv->uDbgStatusMsr;
613	return VINF_SUCCESS;
614
615	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
616	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
617	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
618	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
619	{
620	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
621	*puValue = pHvCpu->auSintMsrs[idMsr - MSR_GIM_HV_SINT0];
622	return VINF_SUCCESS;
623	}
624
625	case MSR_GIM_HV_STIMER0_CONFIG:
626	case MSR_GIM_HV_STIMER1_CONFIG:
627	case MSR_GIM_HV_STIMER2_CONFIG:
628	case MSR_GIM_HV_STIMER3_CONFIG:
629	{
630	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
631	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
632	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
633	*puValue = pcHvStimer->uStimerConfigMsr;
634	return VINF_SUCCESS;
635	}
636
637	case MSR_GIM_HV_STIMER0_COUNT:
638	case MSR_GIM_HV_STIMER1_COUNT:
639	case MSR_GIM_HV_STIMER2_COUNT:
640	case MSR_GIM_HV_STIMER3_COUNT:
641	{
642	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
643	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_COUNT) >> 1;
644	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
645	*puValue = pcHvStimer->uStimerCountMsr;
646	return VINF_SUCCESS;
647	}
648
649	case MSR_GIM_HV_EOM:
650	{
651	*puValue = 0;
652	return VINF_SUCCESS;
653	}
654
655	case MSR_GIM_HV_SCONTROL:
656	{
657	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
658	*puValue = pHvCpu->uSControlMsr;
659	return VINF_SUCCESS;
660	}
661
662	case MSR_GIM_HV_SIMP:
663	{
664	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
665	*puValue = pHvCpu->uSimpMsr;
666	return VINF_SUCCESS;
667	}
668
669	case MSR_GIM_HV_SVERSION:
670	*puValue = GIM_HV_SVERSION;
671	return VINF_SUCCESS;
672
673	case MSR_GIM_HV_RESET:
674	*puValue = 0;
675	return VINF_SUCCESS;
676
677	case MSR_GIM_HV_CRASH_CTL:
678	*puValue = pHv->uCrashCtlMsr;
679	return VINF_SUCCESS;
680
681	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
682	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
683	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
684	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
685	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
686
687	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
688	{
689	if (pHv->fIsVendorMsHv)
690	{
691	#ifndef IN_RING3
692	return VINF_CPUM_R3_MSR_READ;
693	#else
694	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
695	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
696	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
697	return VINF_SUCCESS;
698	#endif
699	}
700	break;
701	}
702
703	/* Write-only MSRs: */
704	case MSR_GIM_HV_EOI:
705	/* Reserved/unknown MSRs: */
706	default:
707	{
708	#ifdef IN_RING3
709	static uint32_t s_cTimes = 0;
710	if (s_cTimes++ < 20)
711	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
712	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
713	break;
714	#else
715	return VINF_CPUM_R3_MSR_READ;
716	#endif
717	}
718	}
719
720	return VERR_CPUM_RAISE_GP_0;
721	}
722
723
724	/**
725	* MSR write handler for Hyper-V.
726	*
727	* @returns Strict VBox status code like CPUMSetGuestMsr().
728	* @retval VINF_CPUM_R3_MSR_WRITE
729	* @retval VERR_CPUM_RAISE_GP_0
730	*
731	* @param pVCpu The cross context virtual CPU structure.
732	* @param idMsr The MSR being written.
733	* @param pRange The range this MSR belongs to.
734	* @param uRawValue The raw value with the ignored bits not masked.
735	*
736	* @thread EMT.
737	*/
738	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
739	{
740	NOREF(pRange);
741	PVM pVM = pVCpu->CTX_SUFF(pVM);
742	PGIMHV pHv = &pVM->gim.s.u.Hv;
743
744	switch (idMsr)
745	{
746	case MSR_GIM_HV_TPR:
747	return APICHvSetTpr(pVCpu, uRawValue);
748
749	case MSR_GIM_HV_EOI:
750	return APICHvSetEoi(pVCpu, uRawValue);
751
752	case MSR_GIM_HV_ICR:
753	return APICHvSetIcr(pVCpu, uRawValue);
754
755	case MSR_GIM_HV_GUEST_OS_ID:
756	{
757	#ifndef IN_RING3
758	return VINF_CPUM_R3_MSR_WRITE;
759	#else
760	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
761	if (!uRawValue)
762	{
763	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
764	{
765	gimR3HvDisableHypercallPage(pVM);
766	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
767	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
768	}
769	}
770	else
771	{
772	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
773	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
774	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
775	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
776	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
777	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
778
779	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
780	CPUMCPUIDLEAF HyperLeaf;
781	RT_ZERO(HyperLeaf);
782	HyperLeaf.uLeaf = UINT32_C(0x40000002);
783	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
784	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
785	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
786	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
787	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
788	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
789	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
790	AssertRC(rc2);
791	}
792
793	pHv->u64GuestOsIdMsr = uRawValue;
794
795	/*
796	* Update EM on hypercall instruction enabled state.
797	*/
798	if (uRawValue)
799	for (VMCPUID i = 0; i < pVM->cCpus; i++)
800	EMSetHypercallInstructionsEnabled(&pVM->aCpus[i], true);
801	else
802	for (VMCPUID i = 0; i < pVM->cCpus; i++)
803	EMSetHypercallInstructionsEnabled(&pVM->aCpus[i], false);
804
805	return VINF_SUCCESS;
806	#endif /* IN_RING3 */
807	}
808
809	case MSR_GIM_HV_HYPERCALL:
810	{
811	#ifndef IN_RING3
812	return VINF_CPUM_R3_MSR_WRITE;
813	#else
814	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
815	* see @bugref{7270#c116}. */
816	/* First, update all but the hypercall page enable bit. */
817	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
818
819	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
820	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
821	if ( fEnable
822	&& !gimHvAreHypercallsEnabled(pVCpu))
823	{
824	return VINF_SUCCESS;
825	}
826
827	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
828	if (!fEnable)
829	{
830	gimR3HvDisableHypercallPage(pVM);
831	pHv->u64HypercallMsr = uRawValue;
832	return VINF_SUCCESS;
833	}
834
835	/* Enable the hypercall-page. */
836	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
837	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
838	if (RT_SUCCESS(rc))
839	{
840	pHv->u64HypercallMsr = uRawValue;
841	return VINF_SUCCESS;
842	}
843
844	return VERR_CPUM_RAISE_GP_0;
845	#endif
846	}
847
848	case MSR_GIM_HV_REF_TSC:
849	{
850	#ifndef IN_RING3
851	return VINF_CPUM_R3_MSR_WRITE;
852	#else /* IN_RING3 */
853	/* First, update all but the TSC page enable bit. */
854	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
855
856	/* Is the guest disabling the TSC page? */
857	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
858	if (!fEnable)
859	{
860	gimR3HvDisableTscPage(pVM);
861	pHv->u64TscPageMsr = uRawValue;
862	return VINF_SUCCESS;
863	}
864
865	/* Enable the TSC page. */
866	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
867	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
868	if (RT_SUCCESS(rc))
869	{
870	pHv->u64TscPageMsr = uRawValue;
871	return VINF_SUCCESS;
872	}
873
874	return VERR_CPUM_RAISE_GP_0;
875	#endif /* IN_RING3 */
876	}
877
878	case MSR_GIM_HV_APIC_ASSIST_PAGE:
879	{
880	#ifndef IN_RING3
881	return VINF_CPUM_R3_MSR_WRITE;
882	#else /* IN_RING3 */
883	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
884	pHvCpu->uApicAssistPageMsr = uRawValue;
885
886	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
887	{
888	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
889	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
890	{
891	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
892	if (RT_SUCCESS(rc))
893	{
894	pHvCpu->uApicAssistPageMsr = uRawValue;
895	return VINF_SUCCESS;
896	}
897	}
898	else
899	{
900	LogRelMax(5, ("GIM%u: HyperV: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
901	GCPhysApicAssistPage));
902	}
903	}
904	else
905	gimR3HvDisableApicAssistPage(pVCpu);
906
907	return VERR_CPUM_RAISE_GP_0;
908	#endif /* IN_RING3 */
909	}
910
911	case MSR_GIM_HV_RESET:
912	{
913	#ifndef IN_RING3
914	return VINF_CPUM_R3_MSR_WRITE;
915	#else
916	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
917	{
918	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
919	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
920	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
921	}
922	/* else: Ignore writes to other bits. */
923	return VINF_SUCCESS;
924	#endif /* IN_RING3 */
925	}
926
927	case MSR_GIM_HV_CRASH_CTL:
928	{
929	#ifndef IN_RING3
930	return VINF_CPUM_R3_MSR_WRITE;
931	#else
932	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
933	{
934	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
935	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
936	DBGFR3ReportBugCheck(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, pHv->uCrashP1Msr,
937	pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr);
938	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
939	}
940	return VINF_SUCCESS;
941	#endif
942	}
943
944	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
945	{
946	if (!pHv->fDbgEnabled)
947	return VERR_CPUM_RAISE_GP_0;
948	#ifndef IN_RING3
949	return VINF_CPUM_R3_MSR_WRITE;
950	#else
951	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
952	pHv->uDbgSendBufferMsr = GCPhysBuffer;
953	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
954	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
955	else
956	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
957	pHv->uDbgSendBufferMsr = uRawValue;
958	return VINF_SUCCESS;
959	#endif
960	}
961
962	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
963	{
964	if (!pHv->fDbgEnabled)
965	return VERR_CPUM_RAISE_GP_0;
966	#ifndef IN_RING3
967	return VINF_CPUM_R3_MSR_WRITE;
968	#else
969	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
970	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
971	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
972	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
973	else
974	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
975	return VINF_SUCCESS;
976	#endif
977	}
978
979	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
980	{
981	if (!pHv->fDbgEnabled)
982	return VERR_CPUM_RAISE_GP_0;
983	#ifndef IN_RING3
984	return VINF_CPUM_R3_MSR_WRITE;
985	#else
986	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
987	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
988	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
989	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
990	else
991	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
992	return VINF_SUCCESS;
993	#endif
994	}
995
996	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
997	{
998	if (!pHv->fDbgEnabled)
999	return VERR_CPUM_RAISE_GP_0;
1000	#ifndef IN_RING3
1001	return VINF_CPUM_R3_MSR_WRITE;
1002	#else
1003	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
1004	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1005	{
1006	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
1007	return VERR_CPUM_RAISE_GP_0;
1008	}
1009
1010	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
1011	{
1012	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
1013	if ( cbWrite > 0
1014	&& cbWrite < GIM_HV_PAGE_SIZE)
1015	{
1016	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
1017	{
1018	Assert(pHv->pvDbgBuffer);
1019	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
1020	if (RT_SUCCESS(rc))
1021	{
1022	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
1023	uint32_t cbWritten = 0;
1024	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
1025	if ( RT_SUCCESS(rc)
1026	&& cbWrite == cbWritten)
1027	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
1028	else
1029	pHv->uDbgStatusMsr = 0;
1030	}
1031	else
1032	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
1033	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
1034	}
1035	else
1036	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
1037	(RTGCPHYS)pHv->uDbgSendBufferMsr));
1038	}
1039	else
1040	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
1041	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
1042	}
1043	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1044	{
1045	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
1046	{
1047	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
1048	uint32_t cbReallyRead;
1049	Assert(pHv->pvDbgBuffer);
1050	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
1051	if ( RT_SUCCESS(rc)
1052	&& cbReallyRead > 0)
1053	{
1054	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
1055	if (RT_SUCCESS(rc))
1056	{
1057	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
1058	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
1059	}
1060	else
1061	{
1062	pHv->uDbgStatusMsr = 0;
1063	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
1064	}
1065	}
1066	else
1067	pHv->uDbgStatusMsr = 0;
1068	}
1069	else
1070	{
1071	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n",
1072	(RTGCPHYS)pHv->uDbgRecvBufferMsr));
1073	}
1074	}
1075	return VINF_SUCCESS;
1076	#endif
1077	}
1078
1079	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
1080	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
1081	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
1082	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
1083	{
1084	uint8_t uVector = MSR_GIM_HV_SINT_GET_VECTOR(uRawValue);
1085	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
1086	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
1087	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
1088	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
1089	{
1090	LogRel(("GIM%u: HyperV: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
1091	idxSintMsr, pszDesc, uVector));
1092	return VERR_CPUM_RAISE_GP_0;
1093	}
1094
1095	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1096	pHvCpu->auSintMsrs[idxSintMsr] = uRawValue;
1097	if (fVMBusMsg)
1098	{
1099	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
1100	Log(("GIM%u: HyperV: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
1101	else
1102	Log(("GIM%u: HyperV: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
1103	}
1104	Log(("GIM%u: HyperV: Written SINT%u=%#RX64\n", pVCpu->idCpu, idxSintMsr, uRawValue));
1105	return VINF_SUCCESS;
1106	}
1107
1108	case MSR_GIM_HV_SCONTROL:
1109	{
1110	#ifndef IN_RING3
1111	/** @todo make this RZ later? */
1112	return VINF_CPUM_R3_MSR_WRITE;
1113	#else
1114	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1115	pHvCpu->uSControlMsr = uRawValue;
1116	if (MSR_GIM_HV_SCONTROL_IS_ENABLED(uRawValue))
1117	LogRel(("GIM%u: HyperV: Synthetic interrupt control enabled\n", pVCpu->idCpu));
1118	else
1119	LogRel(("GIM%u: HyperV: Synthetic interrupt control disabled\n", pVCpu->idCpu));
1120	return VINF_SUCCESS;
1121	#endif
1122	}
1123
1124	case MSR_GIM_HV_STIMER0_CONFIG:
1125	case MSR_GIM_HV_STIMER1_CONFIG:
1126	case MSR_GIM_HV_STIMER2_CONFIG:
1127	case MSR_GIM_HV_STIMER3_CONFIG:
1128	{
1129	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1130	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1131
1132	/* Validate the writable bits. */
1133	if (RT_LIKELY(!(uRawValue & ~MSR_GIM_HV_STIMER_RW_VALID)))
1134	{
1135	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1136	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1137	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1138
1139	/* Lock to prevent concurrent access from the timer callback. */
1140	int rc = TMTimerLock(pTimer, VERR_IGNORED);
1141	if (rc == VINF_SUCCESS)
1142	{
1143	/* Update the MSR value. */
1144	pHvStimer->uStimerConfigMsr = uRawValue;
1145	Log(("GIM%u: HyperV: Set STIMER_CONFIG%u=%#RX64\n", pVCpu->idCpu, idxStimer, uRawValue));
1146
1147	/* Process the MSR bits. */
1148	if ( !MSR_GIM_HV_STIMER_GET_SINTX(uRawValue) /* Writing SINTx as 0 causes the timer to be disabled. */
1149	\|\| !MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1150	{
1151	pHvStimer->uStimerConfigMsr &= ~MSR_GIM_HV_STIMER_ENABLE;
1152	gimHvStopStimer(pVCpu, pHvStimer);
1153	Log(("GIM%u: HyperV: Disabled STIMER_CONFIG%u\n", pVCpu->idCpu, idxStimer));
1154	}
1155	else if (MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1156	{
1157	/* Auto-enable implies writing to the STIMERx_COUNT MSR is what starts the timer. */
1158	if (!MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(uRawValue))
1159	{
1160	if (!TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
1161	{
1162	gimHvStartStimer(pVCpu, pHvStimer);
1163	Log(("GIM%u: HyperV: Started STIMER%u\n", pVCpu->idCpu, idxStimer));
1164	}
1165	else
1166	{
1167	/*
1168	* Enabling a timer that's already enabled is undefined behaviour,
1169	* see Hyper-V spec. 15.3.1 "Synthetic Timer Configuration Register".
1170	*
1171	* Our implementation just re-starts the timer. Guests that comform to
1172	* the Hyper-V specs. should not be doing this anyway.
1173	*/
1174	AssertFailed();
1175	gimHvStopStimer(pVCpu, pHvStimer);
1176	gimHvStartStimer(pVCpu, pHvStimer);
1177	}
1178	}
1179	}
1180
1181	TMTimerUnlock(pTimer);
1182	}
1183	return rc;
1184	}
1185	#ifndef IN_RING3
1186	return VINF_CPUM_R3_MSR_WRITE;
1187	#else
1188	LogRel(("GIM%u: HyperV: Setting reserved bits of STIMER%u MSR (uRawValue=%#RX64) -> #GP(0)\n", pVCpu->idCpu,
1189	idxStimer, uRawValue));
1190	return VERR_CPUM_RAISE_GP_0;
1191	#endif
1192	}
1193
1194	case MSR_GIM_HV_STIMER0_COUNT:
1195	case MSR_GIM_HV_STIMER1_COUNT:
1196	case MSR_GIM_HV_STIMER2_COUNT:
1197	case MSR_GIM_HV_STIMER3_COUNT:
1198	{
1199	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1200	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1201	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1202	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1203	int const rcBusy = VINF_CPUM_R3_MSR_WRITE;
1204
1205	/*
1206	* Writing zero to this MSR disables the timer regardless of whether the auto-enable
1207	* flag is set in the config MSR corresponding to the timer.
1208	*/
1209	if (!uRawValue)
1210	{
1211	gimHvStopStimer(pVCpu, pHvStimer);
1212	pHvStimer->uStimerCountMsr = 0;
1213	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64, stopped timer\n", pVCpu->idCpu, idxStimer, uRawValue));
1214	return VINF_SUCCESS;
1215	}
1216
1217	/*
1218	* Concurrent writes to the config. MSR can't happen as it's serialized by way
1219	* of being done on the same EMT as this.
1220	*/
1221	if (MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(pHvStimer->uStimerConfigMsr))
1222	{
1223	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1224	int rc = TMTimerLock(pTimer, rcBusy);
1225	if (rc == VINF_SUCCESS)
1226	{
1227	pHvStimer->uStimerCountMsr = uRawValue;
1228	gimHvStartStimer(pVCpu, pHvStimer);
1229	TMTimerUnlock(pTimer);
1230	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64 %RU64 msec, auto-started timer\n", pVCpu->idCpu, idxStimer,
1231	uRawValue, (uRawValue * 100) / RT_NS_1MS_64));
1232	}
1233	return rc;
1234	}
1235
1236	/* Simple update of the counter without any timer start/stop side-effects. */
1237	pHvStimer->uStimerCountMsr = uRawValue;
1238	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64\n", pVCpu->idCpu, idxStimer, uRawValue));
1239	return VINF_SUCCESS;
1240	}
1241
1242	case MSR_GIM_HV_EOM:
1243	{
1244	/** @todo implement EOM. */
1245	Log(("GIM%u: HyperV: EOM\n", pVCpu->idCpu));
1246	return VINF_SUCCESS;
1247	}
1248
1249	case MSR_GIM_HV_SIEFP:
1250	{
1251	#ifndef IN_RING3
1252	return VINF_CPUM_R3_MSR_WRITE;
1253	#else
1254	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1255	pHvCpu->uSiefpMsr = uRawValue;
1256	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
1257	{
1258	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT;
1259	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
1260	{
1261	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
1262	if (RT_SUCCESS(rc))
1263	{
1264	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt event flags page at %#RGp\n", pVCpu->idCpu,
1265	GCPhysSiefPage));
1266	/** @todo SIEF setup. */
1267	return VINF_SUCCESS;
1268	}
1269	}
1270	else
1271	LogRelMax(5, ("GIM%u: HyperV: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
1272	}
1273	else
1274	gimR3HvDisableSiefPage(pVCpu);
1275
1276	return VERR_CPUM_RAISE_GP_0;
1277	#endif
1278	break;
1279	}
1280
1281	case MSR_GIM_HV_SIMP:
1282	{
1283	#ifndef IN_RING3
1284	return VINF_CPUM_R3_MSR_WRITE;
1285	#else
1286	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1287	pHvCpu->uSimpMsr = uRawValue;
1288	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
1289	{
1290	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
1291	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
1292	{
1293	uint8_t abSimp[PAGE_SIZE];
1294	RT_ZERO(abSimp);
1295	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
1296	if (RT_SUCCESS(rc2))
1297	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at %#RGp\n", pVCpu->idCpu, GCPhysSimp));
1298	else
1299	{
1300	LogRel(("GIM%u: HyperV: Failed to update synthetic interrupt message page at %#RGp. uSimpMsr=%#RX64 rc=%Rrc\n",
1301	pVCpu->idCpu, pHvCpu->uSimpMsr, GCPhysSimp, rc2));
1302	return VERR_CPUM_RAISE_GP_0;
1303	}
1304	}
1305	else
1306	{
1307	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n", pVCpu->idCpu,
1308	GCPhysSimp));
1309	}
1310	}
1311	else
1312	LogRel(("GIM%u: HyperV: Disabled synthetic interrupt message page\n", pVCpu->idCpu));
1313	return VINF_SUCCESS;
1314	#endif
1315	}
1316
1317	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1318	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1319	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1320	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1321	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1322
1323	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1324	case MSR_GIM_HV_VP_INDEX:
1325	case MSR_GIM_HV_TSC_FREQ:
1326	case MSR_GIM_HV_APIC_FREQ:
1327	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1328	break;
1329
1330	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1331	{
1332	if (pHv->fIsVendorMsHv)
1333	{
1334	#ifndef IN_RING3
1335	return VINF_CPUM_R3_MSR_WRITE;
1336	#else
1337	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1338	return VINF_SUCCESS;
1339	#endif
1340	}
1341	return VERR_CPUM_RAISE_GP_0;
1342	}
1343
1344	default:
1345	{
1346	#ifdef IN_RING3
1347	static uint32_t s_cTimes = 0;
1348	if (s_cTimes++ < 20)
1349	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1350	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1351	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1352	break;
1353	#else
1354	return VINF_CPUM_R3_MSR_WRITE;
1355	#endif
1356	}
1357	}
1358
1359	return VERR_CPUM_RAISE_GP_0;
1360	}
1361
1362
1363	/**
1364	* Whether we need to trap \#UD exceptions in the guest.
1365	*
1366	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
1367	* enabled. For HM VMs, the hypercall would be handled via the
1368	* VMCALL/VMMCALL VM-exit.
1369	*
1370	* @param pVCpu The cross context virtual CPU structure.
1371	*/
1372	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1373	{
1374	if ( VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM))
1375	&& gimHvAreHypercallsEnabled(pVCpu))
1376	return true;
1377	return false;
1378	}
1379
1380
1381	/**
1382	* Checks the instruction and executes the hypercall if it's a valid hypercall
1383	* instruction.
1384	*
1385	* This interface is used by \#UD handlers and IEM.
1386	*
1387	* @returns Strict VBox status code.
1388	* @param pVCpu The cross context virtual CPU structure.
1389	* @param pCtx Pointer to the guest-CPU context.
1390	* @param uDisOpcode The disassembler opcode.
1391	* @param cbInstr The instruction length.
1392	*
1393	* @thread EMT(pVCpu).
1394	*/
1395	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercallEx(PVMCPU pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
1396	{
1397	Assert(pVCpu);
1398	Assert(pCtx);
1399	VMCPU_ASSERT_EMT(pVCpu);
1400
1401	PVM pVM = pVCpu->CTX_SUFF(pVM);
1402	CPUMCPUVENDOR const enmGuestCpuVendor = (CPUMCPUVENDOR)pVM->cpum.ro.GuestFeatures.enmCpuVendor;
1403	if ( ( uDisOpcode == OP_VMCALL
1404	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1405	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA
1406	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_SHANGHAI))
1407	\|\| ( uDisOpcode == OP_VMMCALL
1408	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1409	return gimHvHypercall(pVCpu, pCtx);
1410
1411	RT_NOREF_PV(cbInstr);
1412	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1413	}
1414
1415
1416	/**
1417	* Exception handler for \#UD.
1418	*
1419	* @returns Strict VBox status code.
1420	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1421	* failed).
1422	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1423	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1424	* RIP.
1425	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1426	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1427	* hypercall instruction.
1428	*
1429	* @param pVCpu The cross context virtual CPU structure.
1430	* @param pCtx Pointer to the guest-CPU context.
1431	* @param pDis Pointer to the disassembled instruction state at RIP.
1432	* Optional, can be NULL.
1433	* @param pcbInstr Where to store the instruction length of the hypercall
1434	* instruction. Optional, can be NULL.
1435	*
1436	* @thread EMT(pVCpu).
1437	*/
1438	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1439	{
1440	VMCPU_ASSERT_EMT(pVCpu);
1441
1442	/*
1443	* If we didn't ask for #UD to be trapped, bail.
1444	*/
1445	if (!gimHvShouldTrapXcptUD(pVCpu))
1446	return VERR_GIM_IPE_1;
1447
1448	if (!pDis)
1449	{
1450	/*
1451	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1452	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1453	*/
1454	unsigned cbInstr;
1455	DISCPUSTATE Dis;
1456	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1457	if (RT_SUCCESS(rc))
1458	{
1459	if (pcbInstr)
1460	*pcbInstr = (uint8_t)cbInstr;
1461	return gimHvHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
1462	}
1463
1464	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1465	return rc;
1466	}
1467
1468	return gimHvHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
1469	}
1470

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 78425

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