GIMAllHv.cpp@ 62808

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1	/* $Id: GIMAllHv.cpp 62653 2016-07-28 22:11:57Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include "GIMHvInternal.h"
32	#include "GIMInternal.h"
33	#include <VBox/vmm/vm.h>
34
35	#include <VBox/err.h>
36
37	#include <iprt/asm-amd64-x86.h>
38	#ifdef IN_RING3
39	# include <iprt/mem.h>
40	#endif
41
42
43	#ifdef IN_RING3
44	/**
45	* Read and validate slow hypercall parameters.
46	*
47	* @returns VBox status code.
48	* @param pVM The cross context VM structure.
49	* @param pCtx Pointer to the guest-CPU context.
50	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
51	* @param enmParam The hypercall parameter type.
52	* @param prcHv Where to store the Hyper-V status code. Only valid
53	* to the caller when this function returns
54	* VINF_SUCCESS.
55	*/
56	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
57	{
58	int rc = VINF_SUCCESS;
59	PGIMHV pHv = &pVM->gim.s.u.Hv;
60	RTGCPHYS GCPhysParam;
61	void *pvDst;
62	if (enmParam == GIMHVHYPERCALLPARAM_IN)
63	{
64	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
65	pvDst = pHv->pbHypercallIn;
66	pHv->GCPhysHypercallIn = GCPhysParam;
67	}
68	else
69	{
70	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
71	pvDst = pHv->pbHypercallOut;
72	pHv->GCPhysHypercallOut = GCPhysParam;
73	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
74	}
75
76	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
77	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
78	{
79	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
80	{
81	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
82	if (RT_SUCCESS(rc))
83	{
84	*prcHv = GIM_HV_STATUS_SUCCESS;
85	return VINF_SUCCESS;
86	}
87	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
88	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
89	}
90	else
91	{
92	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
93	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
94	}
95	}
96	else
97	{
98	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
99	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
100	}
101	return rc;
102	}
103
104
105	/**
106	* Helper for reading and validating slow hypercall input and output parameters.
107	*
108	* @returns VBox status code.
109	* @param pVM The cross context VM structure.
110	* @param pCtx Pointer to the guest-CPU context.
111	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
112	* @param prcHv Where to store the Hyper-V status code. Only valid
113	* to the caller when this function returns
114	* VINF_SUCCESS.
115	*/
116	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
117	{
118	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
119	if ( RT_SUCCESS(rc)
120	&& *prcHv == GIM_HV_STATUS_SUCCESS)
121	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
122	return rc;
123	}
124	#endif
125
126
127	/**
128	* Handles all Hyper-V hypercalls.
129	*
130	* @returns Strict VBox status code.
131	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
132	* failed).
133	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
134	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
135	* guest.
136	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
137	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
138	* memory.
139	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
140	* writing memory.
141	*
142	* @param pVCpu The cross context virtual CPU structure.
143	* @param pCtx Pointer to the guest-CPU context.
144	*
145	* @thread EMT(pVCpu).
146	*/
147	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
148	{
149	VMCPU_ASSERT_EMT(pVCpu);
150
151	#ifndef IN_RING3
152	RT_NOREF_PV(pVCpu);
153	RT_NOREF_PV(pCtx);
154	return VINF_GIM_R3_HYPERCALL;
155	#else
156	PVM pVM = pVCpu->CTX_SUFF(pVM);
157	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
158
159	/*
160	* Verify that hypercalls are enabled by the guest.
161	*/
162	if (!gimHvAreHypercallsEnabled(pVCpu))
163	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
164
165	/*
166	* Verify guest is in ring-0 protected mode.
167	*/
168	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
169	if ( uCpl
170	\|\| CPUMIsGuestInRealModeEx(pCtx))
171	{
172	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
173	}
174
175	/*
176	* Get the hypercall operation code and modes.
177	*/
178	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
179	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
180	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
181	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
182	/const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn); - unused /
183	/const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn); - unused /
184	uint64_t cHyperRepsDone = 0;
185
186	int rc = VINF_SUCCESS;
187	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
188	PGIMHV pHv = &pVM->gim.s.u.Hv;
189
190	/*
191	* Validate common hypercall input parameters.
192	*/
193	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
194	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
195	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
196	{
197	/*
198	* Perform the hypercall.
199	*/
200	switch (uHyperOp)
201	{
202	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
203	{
204	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
205	{
206	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
207	if ( RT_SUCCESS(rc)
208	&& rcHv == GIM_HV_STATUS_SUCCESS)
209	{
210	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
211	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
212	if (RT_FAILURE(rc))
213	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
214	}
215	}
216	else
217	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
218	break;
219	}
220
221	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
222	{
223	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
224	{
225	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
226	if ( RT_SUCCESS(rc)
227	&& rcHv == GIM_HV_STATUS_SUCCESS)
228	{
229	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
230	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
231	if (RT_FAILURE(rc))
232	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
233	}
234	}
235	else
236	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
237	break;
238	}
239
240	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
241	{
242	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
243	{
244	uint32_t fFlags = 0;
245	if (!fHyperFast)
246	{
247	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
248	if ( RT_SUCCESS(rc)
249	&& rcHv == GIM_HV_STATUS_SUCCESS)
250	{
251	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
252	fFlags = pIn->fFlags;
253	}
254	}
255	else
256	{
257	rcHv = GIM_HV_STATUS_SUCCESS;
258	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
259	}
260
261	/*
262	* Nothing to flush on the sending side as we don't maintain our own buffers.
263	*/
264	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
265	if (rcHv == GIM_HV_STATUS_SUCCESS)
266	{
267	if (fFlags)
268	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
269	else
270	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
271	}
272	}
273	else
274	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
275	break;
276	}
277
278	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
279	{
280	if (pHv->fIsInterfaceVs)
281	{
282	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
283	if ( RT_SUCCESS(rc)
284	&& rcHv == GIM_HV_STATUS_SUCCESS)
285	{
286	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
287	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
288	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
289	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
290	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT])
291	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
292	{
293	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
294	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
295	{
296	/*
297	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
298	*/
299	GIMHVMSG HvMsg;
300	RT_ZERO(HvMsg);
301	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
302	HvMsg.MsgHdr.cbPayload = 0xf;
303	HvMsg.aPayload[0] = 0xf;
304	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
305	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
306	if (RT_SUCCESS(rc2))
307	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
308	else
309	{
310	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
311	offMsg, rc));
312	}
313	}
314	}
315
316	/*
317	* Make the call fail after updating the SIMP, so the guest can go back to using
318	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
319	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
320	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
321	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
322	*/
323	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
324	}
325	else
326	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
327	}
328	else
329	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
330	break;
331	}
332
333	default:
334	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
335	break;
336	}
337	}
338	else
339	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
340
341	/*
342	* Update the guest with results of the hypercall.
343	*/
344	if (RT_SUCCESS(rc))
345	{
346	if (fIs64BitMode)
347	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
348	else
349	{
350	pCtx->edx = cHyperRepsDone;
351	pCtx->eax = rcHv;
352	}
353	}
354
355	return rc;
356	#endif
357	}
358
359
360	/**
361	* Returns whether the guest has configured and enabled the use of Hyper-V's
362	* hypercall interface.
363	*
364	* @returns true if hypercalls are enabled, false otherwise.
365	* @param pVCpu The cross context virtual CPU structure.
366	*/
367	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
368	{
369	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
370	}
371
372
373	/**
374	* Returns whether the guest has configured and enabled the use of Hyper-V's
375	* paravirtualized TSC.
376	*
377	* @returns true if paravirt. TSC is enabled, false otherwise.
378	* @param pVM The cross context VM structure.
379	*/
380	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
381	{
382	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
383	}
384
385
386	#ifdef IN_RING3
387	/**
388	* Gets the descriptive OS ID variant as identified via the
389	* MSR_GIM_HV_GUEST_OS_ID MSR.
390	*
391	* @returns The name.
392	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
393	*/
394	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
395	{
396	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
397	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
398	if (uVendor == 1 /* Microsoft */)
399	{
400	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
401	switch (uOsVariant)
402	{
403	case 0: return "Undefined";
404	case 1: return "MS-DOS";
405	case 2: return "Windows 3.x";
406	case 3: return "Windows 9x";
407	case 4: return "Windows NT or derivative";
408	case 5: return "Windows CE";
409	default: return "Unknown";
410	}
411	}
412	return "Unknown";
413	}
414	#endif
415
416
417	/**
418	* MSR read handler for Hyper-V.
419	*
420	* @returns Strict VBox status code like CPUMQueryGuestMsr().
421	* @retval VINF_CPUM_R3_MSR_READ
422	* @retval VERR_CPUM_RAISE_GP_0
423	*
424	* @param pVCpu The cross context virtual CPU structure.
425	* @param idMsr The MSR being read.
426	* @param pRange The range this MSR belongs to.
427	* @param puValue Where to store the MSR value read.
428	*
429	* @thread EMT.
430	*/
431	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
432	{
433	NOREF(pRange);
434	PVM pVM = pVCpu->CTX_SUFF(pVM);
435	PGIMHV pHv = &pVM->gim.s.u.Hv;
436
437	switch (idMsr)
438	{
439	case MSR_GIM_HV_TIME_REF_COUNT:
440	{
441	/* Hyper-V reports the time in 100 ns units (10 MHz). */
442	uint64_t u64Tsc = TMCpuTickGet(pVCpu);
443	uint64_t u64TscHz = pHv->cTscTicksPerSecond;
444	uint64_t u64Tsc100Ns = u64TscHz / UINT64_C(10000000); /* 100 ns */
445	*puValue = (u64Tsc / u64Tsc100Ns);
446	return VINF_SUCCESS;
447	}
448
449	case MSR_GIM_HV_VP_INDEX:
450	*puValue = pVCpu->idCpu;
451	return VINF_SUCCESS;
452
453	case MSR_GIM_HV_TPR:
454	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_TPR, puValue);
455
456	case MSR_GIM_HV_ICR:
457	return PDMApicReadMsr(pVCpu, MSR_IA32_X2APIC_ICR, puValue);
458
459	case MSR_GIM_HV_GUEST_OS_ID:
460	*puValue = pHv->u64GuestOsIdMsr;
461	return VINF_SUCCESS;
462
463	case MSR_GIM_HV_HYPERCALL:
464	*puValue = pHv->u64HypercallMsr;
465	return VINF_SUCCESS;
466
467	case MSR_GIM_HV_REF_TSC:
468	*puValue = pHv->u64TscPageMsr;
469	return VINF_SUCCESS;
470
471	case MSR_GIM_HV_TSC_FREQ:
472	*puValue = TMCpuTicksPerSecond(pVM);
473	return VINF_SUCCESS;
474
475	case MSR_GIM_HV_APIC_FREQ:
476	{
477	int rc = PDMApicGetTimerFreq(pVM, puValue);
478	if (RT_FAILURE(rc))
479	return VERR_CPUM_RAISE_GP_0;
480	return VINF_SUCCESS;
481	}
482
483	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
484	*puValue = pHv->uDbgStatusMsr;
485	return VINF_SUCCESS;
486
487	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
488	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
489	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
490	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
491	{
492	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
493	*puValue = pHvCpu->auSintXMsr[idMsr - MSR_GIM_HV_SINT0];
494	return VINF_SUCCESS;
495	}
496
497	case MSR_GIM_HV_SIMP:
498	{
499	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
500	*puValue = pHvCpu->uSimpMsr;
501	return VINF_SUCCESS;
502	}
503
504	case MSR_GIM_HV_SVERSION:
505	*puValue = GIM_HV_SVERSION;
506	return VINF_SUCCESS;
507
508	case MSR_GIM_HV_RESET:
509	*puValue = 0;
510	return VINF_SUCCESS;
511
512	case MSR_GIM_HV_CRASH_CTL:
513	*puValue = pHv->uCrashCtlMsr;
514	return VINF_SUCCESS;
515
516	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
517	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
518	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
519	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
520	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
521
522	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
523	{
524	if (pHv->fIsVendorMsHv)
525	{
526	#ifndef IN_RING3
527	return VINF_CPUM_R3_MSR_READ;
528	#else
529	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
530	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
531	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
532	return VINF_SUCCESS;
533	#endif
534	}
535	break;
536	}
537
538	/* Write-only MSRs: */
539	case MSR_GIM_HV_EOI:
540	/* Reserved/unknown MSRs: */
541	default:
542	{
543	#ifdef IN_RING3
544	static uint32_t s_cTimes = 0;
545	if (s_cTimes++ < 20)
546	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
547	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
548	break;
549	#else
550	return VINF_CPUM_R3_MSR_READ;
551	#endif
552	}
553	}
554
555	return VERR_CPUM_RAISE_GP_0;
556	}
557
558
559	/**
560	* MSR write handler for Hyper-V.
561	*
562	* @returns Strict VBox status code like CPUMSetGuestMsr().
563	* @retval VINF_CPUM_R3_MSR_WRITE
564	* @retval VERR_CPUM_RAISE_GP_0
565	*
566	* @param pVCpu The cross context virtual CPU structure.
567	* @param idMsr The MSR being written.
568	* @param pRange The range this MSR belongs to.
569	* @param uRawValue The raw value with the ignored bits not masked.
570	*
571	* @thread EMT.
572	*/
573	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
574	{
575	NOREF(pRange);
576	PVM pVM = pVCpu->CTX_SUFF(pVM);
577	PGIMHV pHv = &pVM->gim.s.u.Hv;
578
579	switch (idMsr)
580	{
581	case MSR_GIM_HV_TPR:
582	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_TPR, uRawValue);
583
584	case MSR_GIM_HV_EOI:
585	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_EOI, uRawValue);
586
587	case MSR_GIM_HV_ICR:
588	return PDMApicWriteMsr(pVCpu, MSR_IA32_X2APIC_ICR, uRawValue);
589
590	case MSR_GIM_HV_GUEST_OS_ID:
591	{
592	#ifndef IN_RING3
593	return VINF_CPUM_R3_MSR_WRITE;
594	#else
595	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
596	if (!uRawValue)
597	{
598	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
599	{
600	gimR3HvDisableHypercallPage(pVM);
601	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
602	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
603	}
604	}
605	else
606	{
607	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
608	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
609	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
610	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
611	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
612	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
613
614	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
615	CPUMCPUIDLEAF HyperLeaf;
616	RT_ZERO(HyperLeaf);
617	HyperLeaf.uLeaf = UINT32_C(0x40000002);
618	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
619	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
620	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
621	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
622	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
623	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
624	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
625	AssertRC(rc2);
626	}
627
628	pHv->u64GuestOsIdMsr = uRawValue;
629
630	/*
631	* Notify VMM that hypercalls are now disabled/enabled.
632	*/
633	for (VMCPUID i = 0; i < pVM->cCpus; i++)
634	{
635	if (uRawValue)
636	VMMHypercallsEnable(&pVM->aCpus[i]);
637	else
638	VMMHypercallsDisable(&pVM->aCpus[i]);
639	}
640
641	return VINF_SUCCESS;
642	#endif /* IN_RING3 */
643	}
644
645	case MSR_GIM_HV_HYPERCALL:
646	{
647	#ifndef IN_RING3
648	return VINF_CPUM_R3_MSR_WRITE;
649	#else
650	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
651	* see @bugref{7270#c116}. */
652	/* First, update all but the hypercall page enable bit. */
653	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
654
655	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
656	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
657	if ( fEnable
658	&& !gimHvAreHypercallsEnabled(pVCpu))
659	{
660	return VINF_SUCCESS;
661	}
662
663	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
664	if (!fEnable)
665	{
666	gimR3HvDisableHypercallPage(pVM);
667	pHv->u64HypercallMsr = uRawValue;
668	return VINF_SUCCESS;
669	}
670
671	/* Enable the hypercall-page. */
672	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
673	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
674	if (RT_SUCCESS(rc))
675	{
676	pHv->u64HypercallMsr = uRawValue;
677	return VINF_SUCCESS;
678	}
679
680	return VERR_CPUM_RAISE_GP_0;
681	#endif
682	}
683
684	case MSR_GIM_HV_REF_TSC:
685	{
686	#ifndef IN_RING3
687	return VINF_CPUM_R3_MSR_WRITE;
688	#else /* IN_RING3 */
689	/* First, update all but the TSC page enable bit. */
690	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
691
692	/* Is the guest disabling the TSC page? */
693	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
694	if (!fEnable)
695	{
696	gimR3HvDisableTscPage(pVM);
697	pHv->u64TscPageMsr = uRawValue;
698	return VINF_SUCCESS;
699	}
700
701	/* Enable the TSC page. */
702	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
703	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
704	if (RT_SUCCESS(rc))
705	{
706	pHv->u64TscPageMsr = uRawValue;
707	return VINF_SUCCESS;
708	}
709
710	return VERR_CPUM_RAISE_GP_0;
711	#endif /* IN_RING3 */
712	}
713
714	case MSR_GIM_HV_APIC_ASSIST_PAGE:
715	{
716	#ifndef IN_RING3
717	return VINF_CPUM_R3_MSR_WRITE;
718	#else /* IN_RING3 */
719	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
720	pHvCpu->uApicAssistPageMsr = uRawValue;
721
722	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
723	{
724	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
725	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
726	{
727	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
728	if (RT_SUCCESS(rc))
729	{
730	pHvCpu->uApicAssistPageMsr = uRawValue;
731	return VINF_SUCCESS;
732	}
733	}
734	else
735	{
736	LogRelMax(5, ("GIM: HyperV%u: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
737	GCPhysApicAssistPage));
738	}
739	}
740	else
741	gimR3HvDisableApicAssistPage(pVCpu);
742
743	return VERR_CPUM_RAISE_GP_0;
744	#endif /* IN_RING3 */
745	}
746
747	case MSR_GIM_HV_RESET:
748	{
749	#ifndef IN_RING3
750	return VINF_CPUM_R3_MSR_WRITE;
751	#else
752	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
753	{
754	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
755	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
756	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
757	}
758	/* else: Ignore writes to other bits. */
759	return VINF_SUCCESS;
760	#endif /* IN_RING3 */
761	}
762
763	case MSR_GIM_HV_CRASH_CTL:
764	{
765	#ifndef IN_RING3
766	return VINF_CPUM_R3_MSR_WRITE;
767	#else
768	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
769	{
770	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
771	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
772
773	if (DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_BSOD_MSR))
774	DBGFEventGenericWithArg(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, DBGFEVENTCTX_OTHER);
775	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
776	}
777	return VINF_SUCCESS;
778	#endif
779	}
780
781	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
782	{
783	if (!pHv->fDbgEnabled)
784	return VERR_CPUM_RAISE_GP_0;
785	#ifndef IN_RING3
786	return VINF_CPUM_R3_MSR_WRITE;
787	#else
788	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
789	pHv->uDbgSendBufferMsr = GCPhysBuffer;
790	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
791	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
792	else
793	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
794	pHv->uDbgSendBufferMsr = uRawValue;
795	return VINF_SUCCESS;
796	#endif
797	}
798
799	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
800	{
801	if (!pHv->fDbgEnabled)
802	return VERR_CPUM_RAISE_GP_0;
803	#ifndef IN_RING3
804	return VINF_CPUM_R3_MSR_WRITE;
805	#else
806	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
807	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
808	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
809	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
810	else
811	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
812	return VINF_SUCCESS;
813	#endif
814	}
815
816	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
817	{
818	if (!pHv->fDbgEnabled)
819	return VERR_CPUM_RAISE_GP_0;
820	#ifndef IN_RING3
821	return VINF_CPUM_R3_MSR_WRITE;
822	#else
823	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
824	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
825	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
826	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
827	else
828	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
829	return VINF_SUCCESS;
830	#endif
831	}
832
833	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
834	{
835	if (!pHv->fDbgEnabled)
836	return VERR_CPUM_RAISE_GP_0;
837	#ifndef IN_RING3
838	return VINF_CPUM_R3_MSR_WRITE;
839	#else
840	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
841	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
842	{
843	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
844	return VERR_CPUM_RAISE_GP_0;
845	}
846
847	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
848	{
849	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
850	if ( cbWrite > 0
851	&& cbWrite < GIM_HV_PAGE_SIZE)
852	{
853	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
854	{
855	Assert(pHv->pvDbgBuffer);
856	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
857	if (RT_SUCCESS(rc))
858	{
859	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
860	uint32_t cbWritten = 0;
861	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
862	if ( RT_SUCCESS(rc)
863	&& cbWrite == cbWritten)
864	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
865	else
866	pHv->uDbgStatusMsr = 0;
867	}
868	else
869	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
870	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
871	}
872	else
873	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
874	(RTGCPHYS)pHv->uDbgSendBufferMsr));
875	}
876	else
877	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
878	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
879	}
880	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
881	{
882	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
883	{
884	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
885	uint32_t cbReallyRead;
886	Assert(pHv->pvDbgBuffer);
887	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
888	if ( RT_SUCCESS(rc)
889	&& cbReallyRead > 0)
890	{
891	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
892	if (RT_SUCCESS(rc))
893	{
894	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
895	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
896	}
897	else
898	{
899	pHv->uDbgStatusMsr = 0;
900	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
901	}
902	}
903	else
904	pHv->uDbgStatusMsr = 0;
905	}
906	else
907	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n", (RTGCPHYS)pHv->uDbgRecvBufferMsr));
908	}
909	return VINF_SUCCESS;
910	#endif
911	}
912
913	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
914	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
915	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
916	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
917	{
918	#ifndef IN_RING3
919	/** @todo make this RZ later? */
920	return VINF_CPUM_R3_MSR_WRITE;
921	#else
922	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
923	uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
924	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
925	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
926	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
927	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
928	{
929	LogRel(("GIM: HyperV%u: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
930	idxSintMsr, pszDesc, uVector));
931	return VERR_CPUM_RAISE_GP_0;
932	}
933
934	pHvCpu->auSintXMsr[idxSintMsr] = uRawValue;
935	if (fVMBusMsg)
936	{
937	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
938	LogRel(("GIM: HyperV%u: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
939	else
940	LogRel(("GIM: HyperV%u: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
941	}
942	return VINF_SUCCESS;
943	#endif
944	}
945
946	case MSR_GIM_HV_SIEFP:
947	{
948	#ifndef IN_RING3
949	return VINF_CPUM_R3_MSR_WRITE;
950	#else
951	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
952	pHvCpu->uSiefpMsr = uRawValue;
953	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
954	{
955	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT;
956	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
957	{
958	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
959	if (RT_SUCCESS(rc))
960	{
961	/** @todo SIEF setup. */
962	return VINF_SUCCESS;
963	}
964	}
965	else
966	LogRelMax(5, ("GIM: HyperV%u: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
967	}
968	else
969	gimR3HvDisableSiefPage(pVCpu);
970
971	return VERR_CPUM_RAISE_GP_0;
972	#endif
973	break;
974	}
975
976	case MSR_GIM_HV_SIMP:
977	{
978	if (!pHv->fDbgEnabled)
979	return VERR_CPUM_RAISE_GP_0;
980	#ifndef IN_RING3
981	return VINF_CPUM_R3_MSR_WRITE;
982	#else
983	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
984	pHvCpu->uSimpMsr = uRawValue;
985	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
986	{
987	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
988	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
989	{
990	uint8_t abSimp[PAGE_SIZE];
991	RT_ZERO(abSimp);
992	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
993	if (RT_SUCCESS(rc2))
994	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at %#RGp\n", GCPhysSimp));
995	else
996	{
997	LogRel(("GIM: HyperV: WrMsr on MSR_GIM_HV_SIMP failed to update SIMP at %#RGp rc=%Rrc -> #GP(0)\n",
998	GCPhysSimp, rc2));
999	return VERR_CPUM_RAISE_GP_0;
1000	}
1001	}
1002	else
1003	LogRel(("GIM: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n",GCPhysSimp));
1004	}
1005	else
1006	LogRel(("GIM: HyperV: Disabled synthetic interrupt message page\n"));
1007	return VINF_SUCCESS;
1008	#endif
1009	}
1010
1011	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1012	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1013	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1014	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1015	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1016
1017	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1018	case MSR_GIM_HV_VP_INDEX:
1019	case MSR_GIM_HV_TSC_FREQ:
1020	case MSR_GIM_HV_APIC_FREQ:
1021	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1022	break;
1023
1024	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1025	{
1026	if (pHv->fIsVendorMsHv)
1027	{
1028	#ifndef IN_RING3
1029	return VINF_CPUM_R3_MSR_WRITE;
1030	#else
1031	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1032	return VINF_SUCCESS;
1033	#endif
1034	}
1035	return VERR_CPUM_RAISE_GP_0;
1036	}
1037
1038	default:
1039	{
1040	#ifdef IN_RING3
1041	static uint32_t s_cTimes = 0;
1042	if (s_cTimes++ < 20)
1043	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1044	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1045	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1046	break;
1047	#else
1048	return VINF_CPUM_R3_MSR_WRITE;
1049	#endif
1050	}
1051	}
1052
1053	return VERR_CPUM_RAISE_GP_0;
1054	}
1055
1056
1057	/**
1058	* Whether we need to trap \#UD exceptions in the guest.
1059	*
1060	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
1061	* enabled. For HM VMs, the hypercall would be handled via the
1062	* VMCALL/VMMCALL VM-exit.
1063	*
1064	* @param pVCpu The cross context virtual CPU structure.
1065	*/
1066	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1067	{
1068	PVM pVM = pVCpu->CTX_SUFF(pVM);
1069	if ( !HMIsEnabled(pVM)
1070	&& gimHvAreHypercallsEnabled(pVCpu))
1071	return true;
1072	return false;
1073	}
1074
1075
1076	/**
1077	* Checks the currently disassembled instruction and executes the hypercall if
1078	* it's a hypercall instruction.
1079	*
1080	* @returns Strict VBox status code.
1081	* @param pVCpu The cross context virtual CPU structure.
1082	* @param pCtx Pointer to the guest-CPU context.
1083	* @param pDis Pointer to the disassembled instruction state at RIP.
1084	*
1085	* @thread EMT(pVCpu).
1086	*
1087	* @todo Make this function static when @bugref{7270#c168} is addressed.
1088	*/
1089	VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
1090	{
1091	Assert(pVCpu);
1092	Assert(pCtx);
1093	Assert(pDis);
1094	VMCPU_ASSERT_EMT(pVCpu);
1095
1096	PVM pVM = pVCpu->CTX_SUFF(pVM);
1097	CPUMCPUVENDOR const enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1098	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1099	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1100	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1101	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1102	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1103	{
1104	return gimHvHypercall(pVCpu, pCtx);
1105	}
1106
1107	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1108	}
1109
1110
1111	/**
1112	* Exception handler for \#UD.
1113	*
1114	* @returns Strict VBox status code.
1115	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1116	* failed).
1117	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1118	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1119	* RIP.
1120	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1121	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1122	* hypercall instruction.
1123	*
1124	* @param pVCpu The cross context virtual CPU structure.
1125	* @param pCtx Pointer to the guest-CPU context.
1126	* @param pDis Pointer to the disassembled instruction state at RIP.
1127	* Optional, can be NULL.
1128	* @param pcbInstr Where to store the instruction length of the hypercall
1129	* instruction. Optional, can be NULL.
1130	*
1131	* @thread EMT(pVCpu).
1132	*/
1133	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1134	{
1135	VMCPU_ASSERT_EMT(pVCpu);
1136
1137	/*
1138	* If we didn't ask for #UD to be trapped, bail.
1139	*/
1140	if (!gimHvShouldTrapXcptUD(pVCpu))
1141	return VERR_GIM_IPE_1;
1142
1143	if (!pDis)
1144	{
1145	/*
1146	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1147	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1148	*/
1149	unsigned cbInstr;
1150	DISCPUSTATE Dis;
1151	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1152	if (RT_SUCCESS(rc))
1153	{
1154	if (pcbInstr)
1155	*pcbInstr = (uint8_t)cbInstr;
1156	return gimHvExecHypercallInstr(pVCpu, pCtx, &Dis);
1157	}
1158
1159	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1160	return rc;
1161	}
1162
1163	return gimHvExecHypercallInstr(pVCpu, pCtx, pDis);
1164	}
1165

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 62808

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