GIMAllHv.cpp@ 71417

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1	/* $Id: GIMAllHv.cpp 70952 2018-02-10 15:47:50Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include <VBox/vmm/apic.h>
32	#include "GIMHvInternal.h"
33	#include "GIMInternal.h"
34	#include <VBox/vmm/vm.h>
35
36	#include <VBox/err.h>
37
38	#include <iprt/asm-amd64-x86.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	#endif
42
43
44	#ifdef IN_RING3
45	/**
46	* Read and validate slow hypercall parameters.
47	*
48	* @returns VBox status code.
49	* @param pVM The cross context VM structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
52	* @param enmParam The hypercall parameter type.
53	* @param prcHv Where to store the Hyper-V status code. Only valid
54	* to the caller when this function returns
55	* VINF_SUCCESS.
56	*/
57	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
58	{
59	int rc = VINF_SUCCESS;
60	PGIMHV pHv = &pVM->gim.s.u.Hv;
61	RTGCPHYS GCPhysParam;
62	void *pvDst;
63	if (enmParam == GIMHVHYPERCALLPARAM_IN)
64	{
65	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
66	pvDst = pHv->pbHypercallIn;
67	pHv->GCPhysHypercallIn = GCPhysParam;
68	}
69	else
70	{
71	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
72	pvDst = pHv->pbHypercallOut;
73	pHv->GCPhysHypercallOut = GCPhysParam;
74	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
75	}
76
77	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
78	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
79	{
80	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
81	{
82	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
83	if (RT_SUCCESS(rc))
84	{
85	*prcHv = GIM_HV_STATUS_SUCCESS;
86	return VINF_SUCCESS;
87	}
88	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
89	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
90	}
91	else
92	{
93	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
94	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
95	}
96	}
97	else
98	{
99	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
100	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
101	}
102	return rc;
103	}
104
105
106	/**
107	* Helper for reading and validating slow hypercall input and output parameters.
108	*
109	* @returns VBox status code.
110	* @param pVM The cross context VM structure.
111	* @param pCtx Pointer to the guest-CPU context.
112	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
113	* @param prcHv Where to store the Hyper-V status code. Only valid
114	* to the caller when this function returns
115	* VINF_SUCCESS.
116	*/
117	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
118	{
119	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
120	if ( RT_SUCCESS(rc)
121	&& *prcHv == GIM_HV_STATUS_SUCCESS)
122	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
123	return rc;
124	}
125	#endif
126
127
128	/**
129	* Handles all Hyper-V hypercalls.
130	*
131	* @returns Strict VBox status code.
132	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
133	* failed).
134	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
135	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
136	* guest.
137	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
138	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
139	* memory.
140	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
141	* writing memory.
142	*
143	* @param pVCpu The cross context virtual CPU structure.
144	* @param pCtx Pointer to the guest-CPU context.
145	*
146	* @thread EMT(pVCpu).
147	*/
148	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
149	{
150	VMCPU_ASSERT_EMT(pVCpu);
151
152	#ifndef IN_RING3
153	RT_NOREF_PV(pVCpu);
154	RT_NOREF_PV(pCtx);
155	return VINF_GIM_R3_HYPERCALL;
156	#else
157	PVM pVM = pVCpu->CTX_SUFF(pVM);
158	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
159
160	/*
161	* Verify that hypercalls are enabled by the guest.
162	*/
163	if (!gimHvAreHypercallsEnabled(pVCpu))
164	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
165
166	/*
167	* Verify guest is in ring-0 protected mode.
168	*/
169	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
170	if ( uCpl
171	\|\| CPUMIsGuestInRealModeEx(pCtx))
172	{
173	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
174	}
175
176	/*
177	* Get the hypercall operation code and modes.
178	*/
179	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
180	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
181	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
182	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
183	/const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn); - unused /
184	/const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn); - unused /
185	uint64_t cHyperRepsDone = 0;
186
187	int rc = VINF_SUCCESS;
188	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
189	PGIMHV pHv = &pVM->gim.s.u.Hv;
190
191	/*
192	* Validate common hypercall input parameters.
193	*/
194	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
195	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
196	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
197	{
198	/*
199	* Perform the hypercall.
200	*/
201	switch (uHyperOp)
202	{
203	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
204	{
205	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
206	{
207	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
208	if ( RT_SUCCESS(rc)
209	&& rcHv == GIM_HV_STATUS_SUCCESS)
210	{
211	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
212	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
213	if (RT_FAILURE(rc))
214	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
215	}
216	}
217	else
218	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
219	break;
220	}
221
222	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
223	{
224	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
225	{
226	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
227	if ( RT_SUCCESS(rc)
228	&& rcHv == GIM_HV_STATUS_SUCCESS)
229	{
230	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
231	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
232	if (RT_FAILURE(rc))
233	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
234	}
235	}
236	else
237	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
238	break;
239	}
240
241	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
242	{
243	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
244	{
245	uint32_t fFlags = 0;
246	if (!fHyperFast)
247	{
248	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
249	if ( RT_SUCCESS(rc)
250	&& rcHv == GIM_HV_STATUS_SUCCESS)
251	{
252	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
253	fFlags = pIn->fFlags;
254	}
255	}
256	else
257	{
258	rcHv = GIM_HV_STATUS_SUCCESS;
259	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
260	}
261
262	/*
263	* Nothing to flush on the sending side as we don't maintain our own buffers.
264	*/
265	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
266	if (rcHv == GIM_HV_STATUS_SUCCESS)
267	{
268	if (fFlags)
269	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
270	else
271	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
272	}
273	}
274	else
275	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
276	break;
277	}
278
279	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
280	{
281	if (pHv->fIsInterfaceVs)
282	{
283	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
284	if ( RT_SUCCESS(rc)
285	&& rcHv == GIM_HV_STATUS_SUCCESS)
286	{
287	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
288	PCGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
289	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
290	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
291	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintMsrs[GIM_HV_VMBUS_MSG_SINT])
292	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
293	{
294	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
295	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
296	{
297	/*
298	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
299	*/
300	GIMHVMSG HvMsg;
301	RT_ZERO(HvMsg);
302	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
303	HvMsg.MsgHdr.cbPayload = 0xf;
304	HvMsg.aPayload[0] = 0xf;
305	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
306	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
307	if (RT_SUCCESS(rc2))
308	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
309	else
310	{
311	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
312	offMsg, rc));
313	}
314	}
315	}
316
317	/*
318	* Make the call fail after updating the SIMP, so the guest can go back to using
319	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
320	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
321	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
322	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
323	*/
324	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
325	}
326	else
327	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
328	}
329	else
330	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
331	break;
332	}
333
334	default:
335	{
336	LogRel(("GIM: HyperV: Unknown/invalid hypercall opcode %#x (%u)\n", uHyperOp, uHyperOp));
337	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
338	break;
339	}
340	}
341	}
342	else
343	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
344
345	/*
346	* Update the guest with results of the hypercall.
347	*/
348	if (RT_SUCCESS(rc))
349	{
350	if (fIs64BitMode)
351	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
352	else
353	{
354	pCtx->edx = cHyperRepsDone;
355	pCtx->eax = rcHv;
356	}
357	}
358
359	return rc;
360	#endif
361	}
362
363
364	/**
365	* Returns whether the guest has configured and enabled the use of Hyper-V's
366	* hypercall interface.
367	*
368	* @returns true if hypercalls are enabled, false otherwise.
369	* @param pVCpu The cross context virtual CPU structure.
370	*/
371	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
372	{
373	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
374	}
375
376
377	/**
378	* Returns whether the guest has configured and enabled the use of Hyper-V's
379	* paravirtualized TSC.
380	*
381	* @returns true if paravirt. TSC is enabled, false otherwise.
382	* @param pVM The cross context VM structure.
383	*/
384	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
385	{
386	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
387	}
388
389
390	#ifdef IN_RING3
391	/**
392	* Gets the descriptive OS ID variant as identified via the
393	* MSR_GIM_HV_GUEST_OS_ID MSR.
394	*
395	* @returns The name.
396	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
397	*/
398	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
399	{
400	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
401	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
402	if (uVendor == 1 /* Microsoft */)
403	{
404	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
405	switch (uOsVariant)
406	{
407	case 0: return "Undefined";
408	case 1: return "MS-DOS";
409	case 2: return "Windows 3.x";
410	case 3: return "Windows 9x";
411	case 4: return "Windows NT or derivative";
412	case 5: return "Windows CE";
413	default: return "Unknown";
414	}
415	}
416	return "Unknown";
417	}
418	#endif
419
420	/**
421	* Gets the time reference count for the current VM.
422	*
423	* @returns The time reference count.
424	* @param pVCpu The cross context virtual CPU structure.
425	*/
426	DECLINLINE(uint64_t) gimHvGetTimeRefCount(PVMCPU pVCpu)
427	{
428	/* Hyper-V reports the time in 100 ns units (10 MHz). */
429	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
430	PCGIMHV pHv = &pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv;
431	uint64_t const u64Tsc = TMCpuTickGet(pVCpu); /** @todo should we be passing VCPU0 always? */
432	uint64_t const u64TscHz = pHv->cTscTicksPerSecond;
433	uint64_t const u64Tsc100NS = u64TscHz / UINT64_C(10000000); /* 100 ns */
434	uint64_t const uTimeRefCount = (u64Tsc / u64Tsc100NS);
435	return uTimeRefCount;
436	}
437
438
439	/**
440	* Starts the synthetic timer.
441	*
442	* @param pVCpu The cross context virtual CPU structure.
443	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
444	*
445	* @remarks Caller needs to hold the timer critical section.
446	* @thread Any.
447	*/
448	VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer)
449	{
450	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
451	Assert(TMTimerIsLockOwner(pTimer));
452
453	uint64_t const uTimerCount = pHvStimer->uStimerCountMsr;
454	if (uTimerCount)
455	{
456	uint64_t const uTimerCountNS = uTimerCount * 100;
457
458	/* For periodic timers, 'uTimerCountNS' represents the relative interval. */
459	if (MSR_GIM_HV_STIMER_IS_PERIODIC(pHvStimer->uStimerConfigMsr))
460	{
461	TMTimerSetNano(pTimer, uTimerCountNS);
462	LogFlow(("GIM%u: HyperV: Started relative periodic STIMER%u with uTimerCountNS=%RU64\n", pVCpu->idCpu,
463	pHvStimer->idxStimer, uTimerCountNS));
464	}
465	else
466	{
467	/* For one-shot timers, 'uTimerCountNS' represents an absolute expiration wrt to Hyper-V reference time,
468	we convert it to a relative time and program the timer. */
469	uint64_t const uCurRefTimeNS = gimHvGetTimeRefCount(pVCpu) * 100;
470	if (uTimerCountNS > uCurRefTimeNS)
471	{
472	uint64_t const uRelativeNS = uTimerCountNS - uCurRefTimeNS;
473	TMTimerSetNano(pTimer, uRelativeNS);
474	LogFlow(("GIM%u: HyperV: Started one-shot relative STIMER%u with uRelativeNS=%RU64\n", pVCpu->idCpu,
475	pHvStimer->idxStimer, uRelativeNS));
476	}
477	}
478	/** @todo frequency hinting? */
479	}
480	}
481
482
483	/**
484	* Stops the synthetic timer for the given VCPU.
485	*
486	* @param pVCpu The cross context virtual CPU structure.
487	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
488	*
489	* @remarks Caller needs to the hold the timer critical section.
490	* @thread EMT(pVCpu).
491	*/
492	static void gimHvStopStimer(PVMCPU pVCpu, PGIMHVSTIMER pHvStimer)
493	{
494	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
495	RT_NOREF(pVCpu);
496
497	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
498	Assert(TMTimerIsLockOwner(pTimer));
499	RT_NOREF(pTimer);
500
501	if (TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
502	TMTimerStop(pHvStimer->CTX_SUFF(pTimer));
503	}
504
505
506	/**
507	* MSR read handler for Hyper-V.
508	*
509	* @returns Strict VBox status code like CPUMQueryGuestMsr().
510	* @retval VINF_CPUM_R3_MSR_READ
511	* @retval VERR_CPUM_RAISE_GP_0
512	*
513	* @param pVCpu The cross context virtual CPU structure.
514	* @param idMsr The MSR being read.
515	* @param pRange The range this MSR belongs to.
516	* @param puValue Where to store the MSR value read.
517	*
518	* @thread EMT.
519	*/
520	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
521	{
522	NOREF(pRange);
523	PVM pVM = pVCpu->CTX_SUFF(pVM);
524	PCGIMHV pHv = &pVM->gim.s.u.Hv;
525
526	switch (idMsr)
527	{
528	case MSR_GIM_HV_TIME_REF_COUNT:
529	*puValue = gimHvGetTimeRefCount(pVCpu);
530	return VINF_SUCCESS;
531
532	case MSR_GIM_HV_VP_INDEX:
533	*puValue = pVCpu->idCpu;
534	return VINF_SUCCESS;
535
536	case MSR_GIM_HV_TPR:
537	*puValue = APICHvGetTpr(pVCpu);
538	return VINF_SUCCESS;
539
540	case MSR_GIM_HV_ICR:
541	*puValue = APICHvGetIcr(pVCpu);
542	return VINF_SUCCESS;
543
544	case MSR_GIM_HV_GUEST_OS_ID:
545	*puValue = pHv->u64GuestOsIdMsr;
546	return VINF_SUCCESS;
547
548	case MSR_GIM_HV_HYPERCALL:
549	*puValue = pHv->u64HypercallMsr;
550	return VINF_SUCCESS;
551
552	case MSR_GIM_HV_REF_TSC:
553	*puValue = pHv->u64TscPageMsr;
554	return VINF_SUCCESS;
555
556	case MSR_GIM_HV_TSC_FREQ:
557	*puValue = TMCpuTicksPerSecond(pVM);
558	return VINF_SUCCESS;
559
560	case MSR_GIM_HV_APIC_FREQ:
561	{
562	int rc = APICGetTimerFreq(pVM, puValue);
563	if (RT_FAILURE(rc))
564	return VERR_CPUM_RAISE_GP_0;
565	return VINF_SUCCESS;
566	}
567
568	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
569	*puValue = pHv->uDbgStatusMsr;
570	return VINF_SUCCESS;
571
572	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
573	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
574	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
575	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
576	{
577	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
578	*puValue = pHvCpu->auSintMsrs[idMsr - MSR_GIM_HV_SINT0];
579	return VINF_SUCCESS;
580	}
581
582	case MSR_GIM_HV_STIMER0_CONFIG:
583	case MSR_GIM_HV_STIMER1_CONFIG:
584	case MSR_GIM_HV_STIMER2_CONFIG:
585	case MSR_GIM_HV_STIMER3_CONFIG:
586	{
587	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
588	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
589	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
590	*puValue = pcHvStimer->uStimerConfigMsr;
591	return VINF_SUCCESS;
592	}
593
594	case MSR_GIM_HV_STIMER0_COUNT:
595	case MSR_GIM_HV_STIMER1_COUNT:
596	case MSR_GIM_HV_STIMER2_COUNT:
597	case MSR_GIM_HV_STIMER3_COUNT:
598	{
599	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
600	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_COUNT) >> 1;
601	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
602	*puValue = pcHvStimer->uStimerCountMsr;
603	return VINF_SUCCESS;
604	}
605
606	case MSR_GIM_HV_EOM:
607	{
608	*puValue = 0;
609	return VINF_SUCCESS;
610	}
611
612	case MSR_GIM_HV_SCONTROL:
613	{
614	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
615	*puValue = pHvCpu->uSControlMsr;
616	return VINF_SUCCESS;
617	}
618
619	case MSR_GIM_HV_SIMP:
620	{
621	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
622	*puValue = pHvCpu->uSimpMsr;
623	return VINF_SUCCESS;
624	}
625
626	case MSR_GIM_HV_SVERSION:
627	*puValue = GIM_HV_SVERSION;
628	return VINF_SUCCESS;
629
630	case MSR_GIM_HV_RESET:
631	*puValue = 0;
632	return VINF_SUCCESS;
633
634	case MSR_GIM_HV_CRASH_CTL:
635	*puValue = pHv->uCrashCtlMsr;
636	return VINF_SUCCESS;
637
638	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
639	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
640	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
641	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
642	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
643
644	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
645	{
646	if (pHv->fIsVendorMsHv)
647	{
648	#ifndef IN_RING3
649	return VINF_CPUM_R3_MSR_READ;
650	#else
651	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
652	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
653	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
654	return VINF_SUCCESS;
655	#endif
656	}
657	break;
658	}
659
660	/* Write-only MSRs: */
661	case MSR_GIM_HV_EOI:
662	/* Reserved/unknown MSRs: */
663	default:
664	{
665	#ifdef IN_RING3
666	static uint32_t s_cTimes = 0;
667	if (s_cTimes++ < 20)
668	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
669	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
670	break;
671	#else
672	return VINF_CPUM_R3_MSR_READ;
673	#endif
674	}
675	}
676
677	return VERR_CPUM_RAISE_GP_0;
678	}
679
680
681	/**
682	* MSR write handler for Hyper-V.
683	*
684	* @returns Strict VBox status code like CPUMSetGuestMsr().
685	* @retval VINF_CPUM_R3_MSR_WRITE
686	* @retval VERR_CPUM_RAISE_GP_0
687	*
688	* @param pVCpu The cross context virtual CPU structure.
689	* @param idMsr The MSR being written.
690	* @param pRange The range this MSR belongs to.
691	* @param uRawValue The raw value with the ignored bits not masked.
692	*
693	* @thread EMT.
694	*/
695	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
696	{
697	NOREF(pRange);
698	PVM pVM = pVCpu->CTX_SUFF(pVM);
699	PGIMHV pHv = &pVM->gim.s.u.Hv;
700
701	switch (idMsr)
702	{
703	case MSR_GIM_HV_TPR:
704	return APICHvSetTpr(pVCpu, uRawValue);
705
706	case MSR_GIM_HV_EOI:
707	return APICHvSetEoi(pVCpu, uRawValue);
708
709	case MSR_GIM_HV_ICR:
710	return APICHvSetIcr(pVCpu, uRawValue);
711
712	case MSR_GIM_HV_GUEST_OS_ID:
713	{
714	#ifndef IN_RING3
715	return VINF_CPUM_R3_MSR_WRITE;
716	#else
717	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
718	if (!uRawValue)
719	{
720	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
721	{
722	gimR3HvDisableHypercallPage(pVM);
723	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
724	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
725	}
726	}
727	else
728	{
729	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
730	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
731	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
732	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
733	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
734	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
735
736	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
737	CPUMCPUIDLEAF HyperLeaf;
738	RT_ZERO(HyperLeaf);
739	HyperLeaf.uLeaf = UINT32_C(0x40000002);
740	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
741	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
742	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
743	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
744	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
745	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
746	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
747	AssertRC(rc2);
748	}
749
750	pHv->u64GuestOsIdMsr = uRawValue;
751
752	/*
753	* Notify VMM that hypercalls are now disabled/enabled.
754	*/
755	for (VMCPUID i = 0; i < pVM->cCpus; i++)
756	{
757	if (uRawValue)
758	VMMHypercallsEnable(&pVM->aCpus[i]);
759	else
760	VMMHypercallsDisable(&pVM->aCpus[i]);
761	}
762
763	return VINF_SUCCESS;
764	#endif /* IN_RING3 */
765	}
766
767	case MSR_GIM_HV_HYPERCALL:
768	{
769	#ifndef IN_RING3
770	return VINF_CPUM_R3_MSR_WRITE;
771	#else
772	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
773	* see @bugref{7270#c116}. */
774	/* First, update all but the hypercall page enable bit. */
775	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
776
777	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
778	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
779	if ( fEnable
780	&& !gimHvAreHypercallsEnabled(pVCpu))
781	{
782	return VINF_SUCCESS;
783	}
784
785	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
786	if (!fEnable)
787	{
788	gimR3HvDisableHypercallPage(pVM);
789	pHv->u64HypercallMsr = uRawValue;
790	return VINF_SUCCESS;
791	}
792
793	/* Enable the hypercall-page. */
794	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
795	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
796	if (RT_SUCCESS(rc))
797	{
798	pHv->u64HypercallMsr = uRawValue;
799	return VINF_SUCCESS;
800	}
801
802	return VERR_CPUM_RAISE_GP_0;
803	#endif
804	}
805
806	case MSR_GIM_HV_REF_TSC:
807	{
808	#ifndef IN_RING3
809	return VINF_CPUM_R3_MSR_WRITE;
810	#else /* IN_RING3 */
811	/* First, update all but the TSC page enable bit. */
812	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
813
814	/* Is the guest disabling the TSC page? */
815	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
816	if (!fEnable)
817	{
818	gimR3HvDisableTscPage(pVM);
819	pHv->u64TscPageMsr = uRawValue;
820	return VINF_SUCCESS;
821	}
822
823	/* Enable the TSC page. */
824	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
825	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
826	if (RT_SUCCESS(rc))
827	{
828	pHv->u64TscPageMsr = uRawValue;
829	return VINF_SUCCESS;
830	}
831
832	return VERR_CPUM_RAISE_GP_0;
833	#endif /* IN_RING3 */
834	}
835
836	case MSR_GIM_HV_APIC_ASSIST_PAGE:
837	{
838	#ifndef IN_RING3
839	return VINF_CPUM_R3_MSR_WRITE;
840	#else /* IN_RING3 */
841	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
842	pHvCpu->uApicAssistPageMsr = uRawValue;
843
844	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
845	{
846	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
847	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
848	{
849	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
850	if (RT_SUCCESS(rc))
851	{
852	pHvCpu->uApicAssistPageMsr = uRawValue;
853	return VINF_SUCCESS;
854	}
855	}
856	else
857	{
858	LogRelMax(5, ("GIM%u: HyperV: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
859	GCPhysApicAssistPage));
860	}
861	}
862	else
863	gimR3HvDisableApicAssistPage(pVCpu);
864
865	return VERR_CPUM_RAISE_GP_0;
866	#endif /* IN_RING3 */
867	}
868
869	case MSR_GIM_HV_RESET:
870	{
871	#ifndef IN_RING3
872	return VINF_CPUM_R3_MSR_WRITE;
873	#else
874	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
875	{
876	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
877	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
878	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
879	}
880	/* else: Ignore writes to other bits. */
881	return VINF_SUCCESS;
882	#endif /* IN_RING3 */
883	}
884
885	case MSR_GIM_HV_CRASH_CTL:
886	{
887	#ifndef IN_RING3
888	return VINF_CPUM_R3_MSR_WRITE;
889	#else
890	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
891	{
892	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
893	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
894
895	if (DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_BSOD_MSR))
896	DBGFEventGenericWithArg(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, DBGFEVENTCTX_OTHER);
897	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
898	}
899	return VINF_SUCCESS;
900	#endif
901	}
902
903	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
904	{
905	if (!pHv->fDbgEnabled)
906	return VERR_CPUM_RAISE_GP_0;
907	#ifndef IN_RING3
908	return VINF_CPUM_R3_MSR_WRITE;
909	#else
910	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
911	pHv->uDbgSendBufferMsr = GCPhysBuffer;
912	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
913	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
914	else
915	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
916	pHv->uDbgSendBufferMsr = uRawValue;
917	return VINF_SUCCESS;
918	#endif
919	}
920
921	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
922	{
923	if (!pHv->fDbgEnabled)
924	return VERR_CPUM_RAISE_GP_0;
925	#ifndef IN_RING3
926	return VINF_CPUM_R3_MSR_WRITE;
927	#else
928	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
929	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
930	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
931	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
932	else
933	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
934	return VINF_SUCCESS;
935	#endif
936	}
937
938	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
939	{
940	if (!pHv->fDbgEnabled)
941	return VERR_CPUM_RAISE_GP_0;
942	#ifndef IN_RING3
943	return VINF_CPUM_R3_MSR_WRITE;
944	#else
945	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
946	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
947	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
948	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
949	else
950	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
951	return VINF_SUCCESS;
952	#endif
953	}
954
955	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
956	{
957	if (!pHv->fDbgEnabled)
958	return VERR_CPUM_RAISE_GP_0;
959	#ifndef IN_RING3
960	return VINF_CPUM_R3_MSR_WRITE;
961	#else
962	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
963	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
964	{
965	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
966	return VERR_CPUM_RAISE_GP_0;
967	}
968
969	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
970	{
971	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
972	if ( cbWrite > 0
973	&& cbWrite < GIM_HV_PAGE_SIZE)
974	{
975	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
976	{
977	Assert(pHv->pvDbgBuffer);
978	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
979	if (RT_SUCCESS(rc))
980	{
981	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
982	uint32_t cbWritten = 0;
983	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
984	if ( RT_SUCCESS(rc)
985	&& cbWrite == cbWritten)
986	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
987	else
988	pHv->uDbgStatusMsr = 0;
989	}
990	else
991	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
992	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
993	}
994	else
995	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
996	(RTGCPHYS)pHv->uDbgSendBufferMsr));
997	}
998	else
999	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
1000	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
1001	}
1002	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1003	{
1004	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
1005	{
1006	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
1007	uint32_t cbReallyRead;
1008	Assert(pHv->pvDbgBuffer);
1009	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
1010	if ( RT_SUCCESS(rc)
1011	&& cbReallyRead > 0)
1012	{
1013	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
1014	if (RT_SUCCESS(rc))
1015	{
1016	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
1017	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
1018	}
1019	else
1020	{
1021	pHv->uDbgStatusMsr = 0;
1022	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
1023	}
1024	}
1025	else
1026	pHv->uDbgStatusMsr = 0;
1027	}
1028	else
1029	{
1030	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n",
1031	(RTGCPHYS)pHv->uDbgRecvBufferMsr));
1032	}
1033	}
1034	return VINF_SUCCESS;
1035	#endif
1036	}
1037
1038	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
1039	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
1040	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
1041	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
1042	{
1043	uint8_t uVector = MSR_GIM_HV_SINT_GET_VECTOR(uRawValue);
1044	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
1045	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
1046	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
1047	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
1048	{
1049	LogRel(("GIM%u: HyperV: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
1050	idxSintMsr, pszDesc, uVector));
1051	return VERR_CPUM_RAISE_GP_0;
1052	}
1053
1054	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1055	pHvCpu->auSintMsrs[idxSintMsr] = uRawValue;
1056	if (fVMBusMsg)
1057	{
1058	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
1059	Log(("GIM%u: HyperV: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
1060	else
1061	Log(("GIM%u: HyperV: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
1062	}
1063	Log(("GIM%u: HyperV: Written SINT%u=%#RX64\n", pVCpu->idCpu, idxSintMsr, uRawValue));
1064	return VINF_SUCCESS;
1065	}
1066
1067	case MSR_GIM_HV_SCONTROL:
1068	{
1069	#ifndef IN_RING3
1070	/** @todo make this RZ later? */
1071	return VINF_CPUM_R3_MSR_WRITE;
1072	#else
1073	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1074	pHvCpu->uSControlMsr = uRawValue;
1075	if (MSR_GIM_HV_SCONTROL_IS_ENABLED(uRawValue))
1076	LogRel(("GIM%u: HyperV: Synthetic interrupt control enabled\n", pVCpu->idCpu));
1077	else
1078	LogRel(("GIM%u: HyperV: Synthetic interrupt control disabled\n", pVCpu->idCpu));
1079	return VINF_SUCCESS;
1080	#endif
1081	}
1082
1083	case MSR_GIM_HV_STIMER0_CONFIG:
1084	case MSR_GIM_HV_STIMER1_CONFIG:
1085	case MSR_GIM_HV_STIMER2_CONFIG:
1086	case MSR_GIM_HV_STIMER3_CONFIG:
1087	{
1088	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1089	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1090
1091	/* Validate the writable bits. */
1092	if (RT_LIKELY(!(uRawValue & ~MSR_GIM_HV_STIMER_RW_VALID)))
1093	{
1094	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1095	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1096	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1097
1098	/* Lock to prevent concurrent access from the timer callback. */
1099	int rc = TMTimerLock(pTimer, VERR_IGNORED);
1100	if (rc == VINF_SUCCESS)
1101	{
1102	/* Update the MSR value. */
1103	pHvStimer->uStimerConfigMsr = uRawValue;
1104	Log(("GIM%u: HyperV: Set STIMER_CONFIG%u=%#RX64\n", pVCpu->idCpu, idxStimer, uRawValue));
1105
1106	/* Process the MSR bits. */
1107	if ( !MSR_GIM_HV_STIMER_GET_SINTX(uRawValue) /* Writing SINTx as 0 causes the timer to be disabled. */
1108	\|\| !MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1109	{
1110	pHvStimer->uStimerConfigMsr &= ~MSR_GIM_HV_STIMER_ENABLE;
1111	gimHvStopStimer(pVCpu, pHvStimer);
1112	Log(("GIM%u: HyperV: Disabled STIMER_CONFIG%u\n", pVCpu->idCpu, idxStimer));
1113	}
1114	else if (MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1115	{
1116	/* Auto-enable implies writing to the STIMERx_COUNT MSR is what starts the timer. */
1117	if (!MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(uRawValue))
1118	{
1119	if (!TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
1120	{
1121	gimHvStartStimer(pVCpu, pHvStimer);
1122	Log(("GIM%u: HyperV: Started STIMER%u\n", pVCpu->idCpu, idxStimer));
1123	}
1124	else
1125	{
1126	/*
1127	* Enabling a timer that's already enabled is undefined behaviour,
1128	* see Hyper-V spec. 15.3.1 "Synthetic Timer Configuration Register".
1129	*
1130	* Our implementation just re-starts the timer. Guests that comform to
1131	* the Hyper-V specs. should not be doing this anyway.
1132	*/
1133	AssertFailed();
1134	gimHvStopStimer(pVCpu, pHvStimer);
1135	gimHvStartStimer(pVCpu, pHvStimer);
1136	}
1137	}
1138	}
1139
1140	TMTimerUnlock(pTimer);
1141	}
1142	return rc;
1143	}
1144	#ifndef IN_RING3
1145	return VINF_CPUM_R3_MSR_WRITE;
1146	#else
1147	LogRel(("GIM%u: HyperV: Setting reserved bits of STIMER%u MSR (uRawValue=%#RX64) -> #GP(0)\n", pVCpu->idCpu,
1148	idxStimer, uRawValue));
1149	return VERR_CPUM_RAISE_GP_0;
1150	#endif
1151	}
1152
1153	case MSR_GIM_HV_STIMER0_COUNT:
1154	case MSR_GIM_HV_STIMER1_COUNT:
1155	case MSR_GIM_HV_STIMER2_COUNT:
1156	case MSR_GIM_HV_STIMER3_COUNT:
1157	{
1158	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1159	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1160	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1161	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1162	int const rcBusy = VINF_CPUM_R3_MSR_WRITE;
1163
1164	/*
1165	* Writing zero to this MSR disables the timer regardless of whether the auto-enable
1166	* flag is set in the config MSR corresponding to the timer.
1167	*/
1168	if (!uRawValue)
1169	{
1170	gimHvStopStimer(pVCpu, pHvStimer);
1171	pHvStimer->uStimerCountMsr = 0;
1172	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64, stopped timer\n", pVCpu->idCpu, idxStimer, uRawValue));
1173	return VINF_SUCCESS;
1174	}
1175
1176	/*
1177	* Concurrent writes to the config. MSR can't happen as it's serialized by way
1178	* of being done on the same EMT as this.
1179	*/
1180	if (MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(pHvStimer->uStimerConfigMsr))
1181	{
1182	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1183	int rc = TMTimerLock(pTimer, rcBusy);
1184	if (rc == VINF_SUCCESS)
1185	{
1186	pHvStimer->uStimerCountMsr = uRawValue;
1187	gimHvStartStimer(pVCpu, pHvStimer);
1188	TMTimerUnlock(pTimer);
1189	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64 %RU64 msec, auto-started timer\n", pVCpu->idCpu, idxStimer,
1190	uRawValue, (uRawValue * 100) / RT_NS_1MS_64));
1191	}
1192	return rc;
1193	}
1194
1195	/* Simple update of the counter without any timer start/stop side-effects. */
1196	pHvStimer->uStimerCountMsr = uRawValue;
1197	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64\n", pVCpu->idCpu, idxStimer, uRawValue));
1198	return VINF_SUCCESS;
1199	}
1200
1201	case MSR_GIM_HV_EOM:
1202	{
1203	/** @todo implement EOM. */
1204	Log(("GIM%u: HyperV: EOM\n", pVCpu->idCpu));
1205	return VINF_SUCCESS;
1206	}
1207
1208	case MSR_GIM_HV_SIEFP:
1209	{
1210	#ifndef IN_RING3
1211	return VINF_CPUM_R3_MSR_WRITE;
1212	#else
1213	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1214	pHvCpu->uSiefpMsr = uRawValue;
1215	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
1216	{
1217	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT;
1218	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
1219	{
1220	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
1221	if (RT_SUCCESS(rc))
1222	{
1223	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt event flags page at %#RGp\n", pVCpu->idCpu,
1224	GCPhysSiefPage));
1225	/** @todo SIEF setup. */
1226	return VINF_SUCCESS;
1227	}
1228	}
1229	else
1230	LogRelMax(5, ("GIM%u: HyperV: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
1231	}
1232	else
1233	gimR3HvDisableSiefPage(pVCpu);
1234
1235	return VERR_CPUM_RAISE_GP_0;
1236	#endif
1237	break;
1238	}
1239
1240	case MSR_GIM_HV_SIMP:
1241	{
1242	#ifndef IN_RING3
1243	return VINF_CPUM_R3_MSR_WRITE;
1244	#else
1245	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1246	pHvCpu->uSimpMsr = uRawValue;
1247	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
1248	{
1249	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
1250	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
1251	{
1252	uint8_t abSimp[PAGE_SIZE];
1253	RT_ZERO(abSimp);
1254	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
1255	if (RT_SUCCESS(rc2))
1256	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at %#RGp\n", pVCpu->idCpu, GCPhysSimp));
1257	else
1258	{
1259	LogRel(("GIM%u: HyperV: Failed to update synthetic interrupt message page at %#RGp. uSimpMsr=%#RX64 rc=%Rrc\n",
1260	pVCpu->idCpu, pHvCpu->uSimpMsr, GCPhysSimp, rc2));
1261	return VERR_CPUM_RAISE_GP_0;
1262	}
1263	}
1264	else
1265	{
1266	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n", pVCpu->idCpu,
1267	GCPhysSimp));
1268	}
1269	}
1270	else
1271	LogRel(("GIM%u: HyperV: Disabled synthetic interrupt message page\n", pVCpu->idCpu));
1272	return VINF_SUCCESS;
1273	#endif
1274	}
1275
1276	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1277	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1278	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1279	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1280	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1281
1282	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1283	case MSR_GIM_HV_VP_INDEX:
1284	case MSR_GIM_HV_TSC_FREQ:
1285	case MSR_GIM_HV_APIC_FREQ:
1286	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1287	break;
1288
1289	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1290	{
1291	if (pHv->fIsVendorMsHv)
1292	{
1293	#ifndef IN_RING3
1294	return VINF_CPUM_R3_MSR_WRITE;
1295	#else
1296	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1297	return VINF_SUCCESS;
1298	#endif
1299	}
1300	return VERR_CPUM_RAISE_GP_0;
1301	}
1302
1303	default:
1304	{
1305	#ifdef IN_RING3
1306	static uint32_t s_cTimes = 0;
1307	if (s_cTimes++ < 20)
1308	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1309	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1310	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1311	break;
1312	#else
1313	return VINF_CPUM_R3_MSR_WRITE;
1314	#endif
1315	}
1316	}
1317
1318	return VERR_CPUM_RAISE_GP_0;
1319	}
1320
1321
1322	/**
1323	* Whether we need to trap \#UD exceptions in the guest.
1324	*
1325	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
1326	* enabled. For HM VMs, the hypercall would be handled via the
1327	* VMCALL/VMMCALL VM-exit.
1328	*
1329	* @param pVCpu The cross context virtual CPU structure.
1330	*/
1331	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1332	{
1333	if ( VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM))
1334	&& gimHvAreHypercallsEnabled(pVCpu))
1335	return true;
1336	return false;
1337	}
1338
1339
1340	/**
1341	* Checks the currently disassembled instruction and executes the hypercall if
1342	* it's a hypercall instruction.
1343	*
1344	* @returns Strict VBox status code.
1345	* @param pVCpu The cross context virtual CPU structure.
1346	* @param pCtx Pointer to the guest-CPU context.
1347	* @param pDis Pointer to the disassembled instruction state at RIP.
1348	*
1349	* @thread EMT(pVCpu).
1350	*
1351	* @todo Make this function static when @bugref{7270#c168} is addressed.
1352	*/
1353	VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
1354	{
1355	Assert(pVCpu);
1356	Assert(pCtx);
1357	Assert(pDis);
1358	VMCPU_ASSERT_EMT(pVCpu);
1359
1360	PVM pVM = pVCpu->CTX_SUFF(pVM);
1361	CPUMCPUVENDOR const enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1362	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1363	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1364	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1365	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1366	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1367	{
1368	return gimHvHypercall(pVCpu, pCtx);
1369	}
1370
1371	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1372	}
1373
1374
1375	/**
1376	* Exception handler for \#UD.
1377	*
1378	* @returns Strict VBox status code.
1379	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1380	* failed).
1381	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1382	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1383	* RIP.
1384	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1385	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1386	* hypercall instruction.
1387	*
1388	* @param pVCpu The cross context virtual CPU structure.
1389	* @param pCtx Pointer to the guest-CPU context.
1390	* @param pDis Pointer to the disassembled instruction state at RIP.
1391	* Optional, can be NULL.
1392	* @param pcbInstr Where to store the instruction length of the hypercall
1393	* instruction. Optional, can be NULL.
1394	*
1395	* @thread EMT(pVCpu).
1396	*/
1397	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1398	{
1399	VMCPU_ASSERT_EMT(pVCpu);
1400
1401	/*
1402	* If we didn't ask for #UD to be trapped, bail.
1403	*/
1404	if (!gimHvShouldTrapXcptUD(pVCpu))
1405	return VERR_GIM_IPE_1;
1406
1407	if (!pDis)
1408	{
1409	/*
1410	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1411	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1412	*/
1413	unsigned cbInstr;
1414	DISCPUSTATE Dis;
1415	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1416	if (RT_SUCCESS(rc))
1417	{
1418	if (pcbInstr)
1419	*pcbInstr = (uint8_t)cbInstr;
1420	return gimHvExecHypercallInstr(pVCpu, pCtx, &Dis);
1421	}
1422
1423	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1424	return rc;
1425	}
1426
1427	return gimHvExecHypercallInstr(pVCpu, pCtx, pDis);
1428	}
1429

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 71417

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