GIMAllHv.cpp@ 72255

Last change on this file since 72255 was 72190, checked in by vboxsync, 7 years ago
VMM/GIM/HyperV: Implement extended hypercalls HvExtCallQueryCapabilities and HvExtCallGetBootZeroedMemory.
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1	/* $Id: GIMAllHv.cpp 72190 2018-05-10 15:19:33Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, Microsoft Hyper-V, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2014-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include <VBox/vmm/pgm.h>
31	#include <VBox/vmm/apic.h>
32	#include "GIMHvInternal.h"
33	#include "GIMInternal.h"
34	#include <VBox/vmm/vm.h>
35
36	#include <VBox/err.h>
37
38	#include <iprt/asm-amd64-x86.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	#endif
42
43
44	#ifdef IN_RING3
45	/**
46	* Read and validate slow hypercall parameters.
47	*
48	* @returns VBox status code.
49	* @param pVM The cross context VM structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
52	* @param enmParam The hypercall parameter type.
53	* @param prcHv Where to store the Hyper-V status code. Only valid
54	* to the caller when this function returns
55	* VINF_SUCCESS.
56	*/
57	static int gimHvReadSlowHypercallParam(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, GIMHVHYPERCALLPARAM enmParam, int *prcHv)
58	{
59	int rc = VINF_SUCCESS;
60	PGIMHV pHv = &pVM->gim.s.u.Hv;
61	RTGCPHYS GCPhysParam;
62	void *pvDst;
63	if (enmParam == GIMHVHYPERCALLPARAM_IN)
64	{
65	GCPhysParam = fIs64BitMode ? pCtx->rdx : (pCtx->rbx << 32) \| pCtx->ecx;
66	pvDst = pHv->pbHypercallIn;
67	pHv->GCPhysHypercallIn = GCPhysParam;
68	}
69	else
70	{
71	GCPhysParam = fIs64BitMode ? pCtx->r8 : (pCtx->rdi << 32) \| pCtx->esi;
72	pvDst = pHv->pbHypercallOut;
73	pHv->GCPhysHypercallOut = GCPhysParam;
74	Assert(enmParam == GIMHVHYPERCALLPARAM_OUT);
75	}
76
77	const char *pcszParam = enmParam == GIMHVHYPERCALLPARAM_IN ? "input" : "output"; NOREF(pcszParam);
78	if (RT_ALIGN_64(GCPhysParam, 8) == GCPhysParam)
79	{
80	if (PGMPhysIsGCPhysNormal(pVM, GCPhysParam))
81	{
82	rc = PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysParam, GIM_HV_PAGE_SIZE);
83	if (RT_SUCCESS(rc))
84	{
85	*prcHv = GIM_HV_STATUS_SUCCESS;
86	return VINF_SUCCESS;
87	}
88	LogRel(("GIM: HyperV: Failed reading %s param at %#RGp. rc=%Rrc\n", pcszParam, GCPhysParam, rc));
89	rc = VERR_GIM_HYPERCALL_MEMORY_READ_FAILED;
90	}
91	else
92	{
93	Log(("GIM: HyperV: Invalid %s param address %#RGp\n", pcszParam, GCPhysParam));
94	*prcHv = GIM_HV_STATUS_INVALID_PARAMETER;
95	}
96	}
97	else
98	{
99	Log(("GIM: HyperV: Misaligned %s param address %#RGp\n", pcszParam, GCPhysParam));
100	*prcHv = GIM_HV_STATUS_INVALID_ALIGNMENT;
101	}
102	return rc;
103	}
104
105
106	/**
107	* Helper for reading and validating slow hypercall input and output parameters.
108	*
109	* @returns VBox status code.
110	* @param pVM The cross context VM structure.
111	* @param pCtx Pointer to the guest-CPU context.
112	* @param fIs64BitMode Whether the guest is currently in 64-bit mode or not.
113	* @param prcHv Where to store the Hyper-V status code. Only valid
114	* to the caller when this function returns
115	* VINF_SUCCESS.
116	*/
117	static int gimHvReadSlowHypercallParamsInOut(PVM pVM, PCPUMCTX pCtx, bool fIs64BitMode, int *prcHv)
118	{
119	int rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, prcHv);
120	if ( RT_SUCCESS(rc)
121	&& *prcHv == GIM_HV_STATUS_SUCCESS)
122	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, prcHv);
123	return rc;
124	}
125	#endif
126
127
128	/**
129	* Handles all Hyper-V hypercalls.
130	*
131	* @returns Strict VBox status code.
132	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
133	* failed).
134	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
135	* @retval VERR_GIM_HYPERCALLS_NOT_ENABLED hypercalls are disabled by the
136	* guest.
137	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
138	* @retval VERR_GIM_HYPERCALL_MEMORY_READ_FAILED hypercall failed while reading
139	* memory.
140	* @retval VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED hypercall failed while
141	* writing memory.
142	*
143	* @param pVCpu The cross context virtual CPU structure.
144	* @param pCtx Pointer to the guest-CPU context.
145	*
146	* @thread EMT(pVCpu).
147	*/
148	VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
149	{
150	VMCPU_ASSERT_EMT(pVCpu);
151
152	#ifndef IN_RING3
153	RT_NOREF_PV(pVCpu);
154	RT_NOREF_PV(pCtx);
155	return VINF_GIM_R3_HYPERCALL;
156	#else
157	PVM pVM = pVCpu->CTX_SUFF(pVM);
158	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
159
160	/*
161	* Verify that hypercalls are enabled by the guest.
162	*/
163	if (!gimHvAreHypercallsEnabled(pVCpu))
164	return VERR_GIM_HYPERCALLS_NOT_ENABLED;
165
166	/*
167	* Verify guest is in ring-0 protected mode.
168	*/
169	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
170	if ( uCpl
171	\|\| CPUMIsGuestInRealModeEx(pCtx))
172	{
173	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
174	}
175
176	/*
177	* Get the hypercall operation code and modes.
178	* Fast hypercalls have only two or fewer inputs but no output parameters.
179	*/
180	const bool fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
181	const uint64_t uHyperIn = fIs64BitMode ? pCtx->rcx : (pCtx->rdx << 32) \| pCtx->eax;
182	const uint16_t uHyperOp = GIM_HV_HYPERCALL_IN_CALL_CODE(uHyperIn);
183	const bool fHyperFast = GIM_HV_HYPERCALL_IN_IS_FAST(uHyperIn);
184	const uint16_t cHyperReps = GIM_HV_HYPERCALL_IN_REP_COUNT(uHyperIn);
185	const uint16_t idxHyperRepStart = GIM_HV_HYPERCALL_IN_REP_START_IDX(uHyperIn);
186	uint64_t cHyperRepsDone = 0;
187
188	/* Currently no repeating hypercalls are supported. */
189	RT_NOREF2(cHyperReps, idxHyperRepStart);
190
191	int rc = VINF_SUCCESS;
192	int rcHv = GIM_HV_STATUS_OPERATION_DENIED;
193	PGIMHV pHv = &pVM->gim.s.u.Hv;
194
195	/*
196	* Validate common hypercall input parameters.
197	*/
198	if ( !GIM_HV_HYPERCALL_IN_RSVD_1(uHyperIn)
199	&& !GIM_HV_HYPERCALL_IN_RSVD_2(uHyperIn)
200	&& !GIM_HV_HYPERCALL_IN_RSVD_3(uHyperIn))
201	{
202	/*
203	* Perform the hypercall.
204	*/
205	switch (uHyperOp)
206	{
207	case GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA: /* Non-rep, memory IO. */
208	{
209	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
210	{
211	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
212	if ( RT_SUCCESS(rc)
213	&& rcHv == GIM_HV_STATUS_SUCCESS)
214	{
215	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via hypercall\n"));
216	rc = gimR3HvHypercallRetrieveDebugData(pVM, &rcHv);
217	if (RT_FAILURE(rc))
218	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallRetrieveDebugData failed. rc=%Rrc\n", rc));
219	}
220	}
221	else
222	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
223	break;
224	}
225
226	case GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA: /* Non-rep, memory IO. */
227	{
228	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
229	{
230	rc = gimHvReadSlowHypercallParamsInOut(pVM, pCtx, fIs64BitMode, &rcHv);
231	if ( RT_SUCCESS(rc)
232	&& rcHv == GIM_HV_STATUS_SUCCESS)
233	{
234	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via hypercall\n"));
235	rc = gimR3HvHypercallPostDebugData(pVM, &rcHv);
236	if (RT_FAILURE(rc))
237	LogRelMax(10, ("GIM: HyperV: gimR3HvHypercallPostDebugData failed. rc=%Rrc\n", rc));
238	}
239	}
240	else
241	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
242	break;
243	}
244
245	case GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION: /* Non-rep, fast (register IO). */
246	{
247	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_DEBUGGING)
248	{
249	uint32_t fFlags = 0;
250	if (!fHyperFast)
251	{
252	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
253	if ( RT_SUCCESS(rc)
254	&& rcHv == GIM_HV_STATUS_SUCCESS)
255	{
256	PGIMHVDEBUGRESETIN pIn = (PGIMHVDEBUGRESETIN)pHv->pbHypercallIn;
257	fFlags = pIn->fFlags;
258	}
259	}
260	else
261	{
262	rcHv = GIM_HV_STATUS_SUCCESS;
263	fFlags = fIs64BitMode ? pCtx->rdx : pCtx->ebx;
264	}
265
266	/*
267	* Nothing to flush on the sending side as we don't maintain our own buffers.
268	*/
269	/** @todo We should probably ask the debug receive thread to flush it's buffer. */
270	if (rcHv == GIM_HV_STATUS_SUCCESS)
271	{
272	if (fFlags)
273	LogRel(("GIM: HyperV: Resetting debug session via hypercall\n"));
274	else
275	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
276	}
277	}
278	else
279	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
280	break;
281	}
282
283	case GIM_HV_HYPERCALL_OP_POST_MESSAGE: /* Non-rep, memory IO. */
284	{
285	if (pHv->fIsInterfaceVs)
286	{
287	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_IN, &rcHv);
288	if ( RT_SUCCESS(rc)
289	&& rcHv == GIM_HV_STATUS_SUCCESS)
290	{
291	PGIMHVPOSTMESSAGEIN pMsgIn = (PGIMHVPOSTMESSAGEIN)pHv->pbHypercallIn;
292	PCGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
293	if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID
294	&& pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS
295	&& !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintMsrs[GIM_HV_VMBUS_MSG_SINT])
296	&& MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr))
297	{
298	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(pHvCpu->uSimpMsr);
299	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
300	{
301	/*
302	* The VMBus client (guest) expects to see 0xf at offsets 4 and 16 and 1 at offset 0.
303	*/
304	GIMHVMSG HvMsg;
305	RT_ZERO(HvMsg);
306	HvMsg.MsgHdr.enmMessageType = GIMHVMSGTYPE_VMBUS;
307	HvMsg.MsgHdr.cbPayload = 0xf;
308	HvMsg.aPayload[0] = 0xf;
309	uint16_t const offMsg = GIM_HV_VMBUS_MSG_SINT * sizeof(GIMHVMSG);
310	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp + offMsg, &HvMsg, sizeof(HvMsg));
311	if (RT_SUCCESS(rc2))
312	LogRel(("GIM: HyperV: SIMP hypercall faking message at %#RGp:%u\n", GCPhysSimp, offMsg));
313	else
314	{
315	LogRel(("GIM: HyperV: Failed to write SIMP message at %#RGp:%u, rc=%Rrc\n", GCPhysSimp,
316	offMsg, rc));
317	}
318	}
319	}
320
321	/*
322	* Make the call fail after updating the SIMP, so the guest can go back to using
323	* the Hyper-V debug MSR interface. Any error code below GIM_HV_STATUS_NOT_ACKNOWLEDGED
324	* and the guest tries to proceed with initializing VMBus which is totally unnecessary
325	* for what we're trying to accomplish, i.e. convince guest to use Hyper-V debugging. Also,
326	* we don't implement other VMBus/SynIC functionality so the guest would #GP and die.
327	*/
328	rcHv = GIM_HV_STATUS_NOT_ACKNOWLEDGED;
329	}
330	else
331	rcHv = GIM_HV_STATUS_INVALID_PARAMETER;
332	}
333	else
334	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
335	break;
336	}
337
338	case GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP: /* Non-rep, extended hypercall. */
339	{
340	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
341	{
342	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
343	if ( RT_SUCCESS(rc)
344	&& rcHv == GIM_HV_STATUS_SUCCESS)
345	{
346	rc = gimR3HvHypercallExtQueryCap(pVM, &rcHv);
347	}
348	}
349	else
350	{
351	LogRel(("GIM: HyperV: Denied HvExtCallQueryCapabilities when the feature is not exposed\n"));
352	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
353	}
354	break;
355	}
356
357	case GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM: /* Non-rep, extended hypercall. */
358	{
359	if (pHv->uPartFlags & GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS)
360	{
361	rc = gimHvReadSlowHypercallParam(pVM, pCtx, fIs64BitMode, GIMHVHYPERCALLPARAM_OUT, &rcHv);
362	if ( RT_SUCCESS(rc)
363	&& rcHv == GIM_HV_STATUS_SUCCESS)
364	{
365	rc = gimR3HvHypercallExtGetBootZeroedMem(pVM, &rcHv);
366	}
367	}
368	else
369	{
370	LogRel(("GIM: HyperV: Denied HvExtCallGetBootZeroedMemory when the feature is not exposed\n"));
371	rcHv = GIM_HV_STATUS_ACCESS_DENIED;
372	}
373	break;
374	}
375
376	default:
377	{
378	LogRel(("GIM: HyperV: Unknown/invalid hypercall opcode %#x (%u)\n", uHyperOp, uHyperOp));
379	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_CODE;
380	break;
381	}
382	}
383	}
384	else
385	rcHv = GIM_HV_STATUS_INVALID_HYPERCALL_INPUT;
386
387	/*
388	* Update the guest with results of the hypercall.
389	*/
390	if (RT_SUCCESS(rc))
391	{
392	if (fIs64BitMode)
393	pCtx->rax = (cHyperRepsDone << 32) \| rcHv;
394	else
395	{
396	pCtx->edx = cHyperRepsDone;
397	pCtx->eax = rcHv;
398	}
399	}
400
401	return rc;
402	#endif
403	}
404
405
406	/**
407	* Returns whether the guest has configured and enabled the use of Hyper-V's
408	* hypercall interface.
409	*
410	* @returns true if hypercalls are enabled, false otherwise.
411	* @param pVCpu The cross context virtual CPU structure.
412	*/
413	VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu)
414	{
415	return RT_BOOL(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64GuestOsIdMsr != 0);
416	}
417
418
419	/**
420	* Returns whether the guest has configured and enabled the use of Hyper-V's
421	* paravirtualized TSC.
422	*
423	* @returns true if paravirt. TSC is enabled, false otherwise.
424	* @param pVM The cross context VM structure.
425	*/
426	VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM)
427	{
428	return MSR_GIM_HV_REF_TSC_IS_ENABLED(pVM->gim.s.u.Hv.u64TscPageMsr);
429	}
430
431
432	#ifdef IN_RING3
433	/**
434	* Gets the descriptive OS ID variant as identified via the
435	* MSR_GIM_HV_GUEST_OS_ID MSR.
436	*
437	* @returns The name.
438	* @param uGuestOsIdMsr The MSR_GIM_HV_GUEST_OS_ID MSR.
439	*/
440	static const char *gimHvGetGuestOsIdVariantName(uint64_t uGuestOsIdMsr)
441	{
442	/* Refer the Hyper-V spec, section 3.6 "Reporting the Guest OS Identity". */
443	uint32_t uVendor = MSR_GIM_HV_GUEST_OS_ID_VENDOR(uGuestOsIdMsr);
444	if (uVendor == 1 /* Microsoft */)
445	{
446	uint32_t uOsVariant = MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uGuestOsIdMsr);
447	switch (uOsVariant)
448	{
449	case 0: return "Undefined";
450	case 1: return "MS-DOS";
451	case 2: return "Windows 3.x";
452	case 3: return "Windows 9x";
453	case 4: return "Windows NT or derivative";
454	case 5: return "Windows CE";
455	default: return "Unknown";
456	}
457	}
458	return "Unknown";
459	}
460	#endif
461
462	/**
463	* Gets the time reference count for the current VM.
464	*
465	* @returns The time reference count.
466	* @param pVCpu The cross context virtual CPU structure.
467	*/
468	DECLINLINE(uint64_t) gimHvGetTimeRefCount(PVMCPU pVCpu)
469	{
470	/* Hyper-V reports the time in 100 ns units (10 MHz). */
471	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
472	PCGIMHV pHv = &pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv;
473	uint64_t const u64Tsc = TMCpuTickGet(pVCpu); /** @todo should we be passing VCPU0 always? */
474	uint64_t const u64TscHz = pHv->cTscTicksPerSecond;
475	uint64_t const u64Tsc100NS = u64TscHz / UINT64_C(10000000); /* 100 ns */
476	uint64_t const uTimeRefCount = (u64Tsc / u64Tsc100NS);
477	return uTimeRefCount;
478	}
479
480
481	/**
482	* Starts the synthetic timer.
483	*
484	* @param pVCpu The cross context virtual CPU structure.
485	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
486	*
487	* @remarks Caller needs to hold the timer critical section.
488	* @thread Any.
489	*/
490	VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer)
491	{
492	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
493	Assert(TMTimerIsLockOwner(pTimer));
494
495	uint64_t const uTimerCount = pHvStimer->uStimerCountMsr;
496	if (uTimerCount)
497	{
498	uint64_t const uTimerCountNS = uTimerCount * 100;
499
500	/* For periodic timers, 'uTimerCountNS' represents the relative interval. */
501	if (MSR_GIM_HV_STIMER_IS_PERIODIC(pHvStimer->uStimerConfigMsr))
502	{
503	TMTimerSetNano(pTimer, uTimerCountNS);
504	LogFlow(("GIM%u: HyperV: Started relative periodic STIMER%u with uTimerCountNS=%RU64\n", pVCpu->idCpu,
505	pHvStimer->idxStimer, uTimerCountNS));
506	}
507	else
508	{
509	/* For one-shot timers, 'uTimerCountNS' represents an absolute expiration wrt to Hyper-V reference time,
510	we convert it to a relative time and program the timer. */
511	uint64_t const uCurRefTimeNS = gimHvGetTimeRefCount(pVCpu) * 100;
512	if (uTimerCountNS > uCurRefTimeNS)
513	{
514	uint64_t const uRelativeNS = uTimerCountNS - uCurRefTimeNS;
515	TMTimerSetNano(pTimer, uRelativeNS);
516	LogFlow(("GIM%u: HyperV: Started one-shot relative STIMER%u with uRelativeNS=%RU64\n", pVCpu->idCpu,
517	pHvStimer->idxStimer, uRelativeNS));
518	}
519	}
520	/** @todo frequency hinting? */
521	}
522	}
523
524
525	/**
526	* Stops the synthetic timer for the given VCPU.
527	*
528	* @param pVCpu The cross context virtual CPU structure.
529	* @param pHvStimer Pointer to the Hyper-V synthetic timer.
530	*
531	* @remarks Caller needs to the hold the timer critical section.
532	* @thread EMT(pVCpu).
533	*/
534	static void gimHvStopStimer(PVMCPU pVCpu, PGIMHVSTIMER pHvStimer)
535	{
536	VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
537	RT_NOREF(pVCpu);
538
539	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
540	Assert(TMTimerIsLockOwner(pTimer));
541	RT_NOREF(pTimer);
542
543	if (TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
544	TMTimerStop(pHvStimer->CTX_SUFF(pTimer));
545	}
546
547
548	/**
549	* MSR read handler for Hyper-V.
550	*
551	* @returns Strict VBox status code like CPUMQueryGuestMsr().
552	* @retval VINF_CPUM_R3_MSR_READ
553	* @retval VERR_CPUM_RAISE_GP_0
554	*
555	* @param pVCpu The cross context virtual CPU structure.
556	* @param idMsr The MSR being read.
557	* @param pRange The range this MSR belongs to.
558	* @param puValue Where to store the MSR value read.
559	*
560	* @thread EMT.
561	*/
562	VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
563	{
564	NOREF(pRange);
565	PVM pVM = pVCpu->CTX_SUFF(pVM);
566	PCGIMHV pHv = &pVM->gim.s.u.Hv;
567
568	switch (idMsr)
569	{
570	case MSR_GIM_HV_TIME_REF_COUNT:
571	*puValue = gimHvGetTimeRefCount(pVCpu);
572	return VINF_SUCCESS;
573
574	case MSR_GIM_HV_VP_INDEX:
575	*puValue = pVCpu->idCpu;
576	return VINF_SUCCESS;
577
578	case MSR_GIM_HV_TPR:
579	*puValue = APICHvGetTpr(pVCpu);
580	return VINF_SUCCESS;
581
582	case MSR_GIM_HV_ICR:
583	*puValue = APICHvGetIcr(pVCpu);
584	return VINF_SUCCESS;
585
586	case MSR_GIM_HV_GUEST_OS_ID:
587	*puValue = pHv->u64GuestOsIdMsr;
588	return VINF_SUCCESS;
589
590	case MSR_GIM_HV_HYPERCALL:
591	*puValue = pHv->u64HypercallMsr;
592	return VINF_SUCCESS;
593
594	case MSR_GIM_HV_REF_TSC:
595	*puValue = pHv->u64TscPageMsr;
596	return VINF_SUCCESS;
597
598	case MSR_GIM_HV_TSC_FREQ:
599	*puValue = TMCpuTicksPerSecond(pVM);
600	return VINF_SUCCESS;
601
602	case MSR_GIM_HV_APIC_FREQ:
603	{
604	int rc = APICGetTimerFreq(pVM, puValue);
605	if (RT_FAILURE(rc))
606	return VERR_CPUM_RAISE_GP_0;
607	return VINF_SUCCESS;
608	}
609
610	case MSR_GIM_HV_SYNTH_DEBUG_STATUS:
611	*puValue = pHv->uDbgStatusMsr;
612	return VINF_SUCCESS;
613
614	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
615	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
616	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
617	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
618	{
619	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
620	*puValue = pHvCpu->auSintMsrs[idMsr - MSR_GIM_HV_SINT0];
621	return VINF_SUCCESS;
622	}
623
624	case MSR_GIM_HV_STIMER0_CONFIG:
625	case MSR_GIM_HV_STIMER1_CONFIG:
626	case MSR_GIM_HV_STIMER2_CONFIG:
627	case MSR_GIM_HV_STIMER3_CONFIG:
628	{
629	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
630	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
631	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
632	*puValue = pcHvStimer->uStimerConfigMsr;
633	return VINF_SUCCESS;
634	}
635
636	case MSR_GIM_HV_STIMER0_COUNT:
637	case MSR_GIM_HV_STIMER1_COUNT:
638	case MSR_GIM_HV_STIMER2_COUNT:
639	case MSR_GIM_HV_STIMER3_COUNT:
640	{
641	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
642	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_COUNT) >> 1;
643	PCGIMHVSTIMER pcHvStimer = &pHvCpu->aStimers[idxStimer];
644	*puValue = pcHvStimer->uStimerCountMsr;
645	return VINF_SUCCESS;
646	}
647
648	case MSR_GIM_HV_EOM:
649	{
650	*puValue = 0;
651	return VINF_SUCCESS;
652	}
653
654	case MSR_GIM_HV_SCONTROL:
655	{
656	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
657	*puValue = pHvCpu->uSControlMsr;
658	return VINF_SUCCESS;
659	}
660
661	case MSR_GIM_HV_SIMP:
662	{
663	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
664	*puValue = pHvCpu->uSimpMsr;
665	return VINF_SUCCESS;
666	}
667
668	case MSR_GIM_HV_SVERSION:
669	*puValue = GIM_HV_SVERSION;
670	return VINF_SUCCESS;
671
672	case MSR_GIM_HV_RESET:
673	*puValue = 0;
674	return VINF_SUCCESS;
675
676	case MSR_GIM_HV_CRASH_CTL:
677	*puValue = pHv->uCrashCtlMsr;
678	return VINF_SUCCESS;
679
680	case MSR_GIM_HV_CRASH_P0: *puValue = pHv->uCrashP0Msr; return VINF_SUCCESS;
681	case MSR_GIM_HV_CRASH_P1: *puValue = pHv->uCrashP1Msr; return VINF_SUCCESS;
682	case MSR_GIM_HV_CRASH_P2: *puValue = pHv->uCrashP2Msr; return VINF_SUCCESS;
683	case MSR_GIM_HV_CRASH_P3: *puValue = pHv->uCrashP3Msr; return VINF_SUCCESS;
684	case MSR_GIM_HV_CRASH_P4: *puValue = pHv->uCrashP4Msr; return VINF_SUCCESS;
685
686	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
687	{
688	if (pHv->fIsVendorMsHv)
689	{
690	#ifndef IN_RING3
691	return VINF_CPUM_R3_MSR_READ;
692	#else
693	LogRelMax(1, ("GIM: HyperV: Guest querying debug options, suggesting %s interface\n",
694	pHv->fDbgHypercallInterface ? "hypercall" : "MSR"));
695	*puValue = pHv->fDbgHypercallInterface ? GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS : 0;
696	return VINF_SUCCESS;
697	#endif
698	}
699	break;
700	}
701
702	/* Write-only MSRs: */
703	case MSR_GIM_HV_EOI:
704	/* Reserved/unknown MSRs: */
705	default:
706	{
707	#ifdef IN_RING3
708	static uint32_t s_cTimes = 0;
709	if (s_cTimes++ < 20)
710	LogRel(("GIM: HyperV: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
711	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
712	break;
713	#else
714	return VINF_CPUM_R3_MSR_READ;
715	#endif
716	}
717	}
718
719	return VERR_CPUM_RAISE_GP_0;
720	}
721
722
723	/**
724	* MSR write handler for Hyper-V.
725	*
726	* @returns Strict VBox status code like CPUMSetGuestMsr().
727	* @retval VINF_CPUM_R3_MSR_WRITE
728	* @retval VERR_CPUM_RAISE_GP_0
729	*
730	* @param pVCpu The cross context virtual CPU structure.
731	* @param idMsr The MSR being written.
732	* @param pRange The range this MSR belongs to.
733	* @param uRawValue The raw value with the ignored bits not masked.
734	*
735	* @thread EMT.
736	*/
737	VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
738	{
739	NOREF(pRange);
740	PVM pVM = pVCpu->CTX_SUFF(pVM);
741	PGIMHV pHv = &pVM->gim.s.u.Hv;
742
743	switch (idMsr)
744	{
745	case MSR_GIM_HV_TPR:
746	return APICHvSetTpr(pVCpu, uRawValue);
747
748	case MSR_GIM_HV_EOI:
749	return APICHvSetEoi(pVCpu, uRawValue);
750
751	case MSR_GIM_HV_ICR:
752	return APICHvSetIcr(pVCpu, uRawValue);
753
754	case MSR_GIM_HV_GUEST_OS_ID:
755	{
756	#ifndef IN_RING3
757	return VINF_CPUM_R3_MSR_WRITE;
758	#else
759	/* Disable the hypercall-page and hypercalls if 0 is written to this MSR. */
760	if (!uRawValue)
761	{
762	if (MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(pHv->u64HypercallMsr))
763	{
764	gimR3HvDisableHypercallPage(pVM);
765	pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE;
766	LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n"));
767	}
768	}
769	else
770	{
771	LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
772	LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
773	MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
774	MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
775	MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
776	MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
777
778	/* Update the CPUID leaf, see Hyper-V spec. "Microsoft Hypervisor CPUID Leaves". */
779	CPUMCPUIDLEAF HyperLeaf;
780	RT_ZERO(HyperLeaf);
781	HyperLeaf.uLeaf = UINT32_C(0x40000002);
782	HyperLeaf.uEax = MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue);
783	HyperLeaf.uEbx = MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue)
784	\| (MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue) << 16);
785	HyperLeaf.uEcx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue);
786	HyperLeaf.uEdx = MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue)
787	\| (MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue) << 24);
788	int rc2 = CPUMR3CpuIdInsert(pVM, &HyperLeaf);
789	AssertRC(rc2);
790	}
791
792	pHv->u64GuestOsIdMsr = uRawValue;
793
794	/*
795	* Notify VMM that hypercalls are now disabled/enabled.
796	*/
797	for (VMCPUID i = 0; i < pVM->cCpus; i++)
798	{
799	if (uRawValue)
800	VMMHypercallsEnable(&pVM->aCpus[i]);
801	else
802	VMMHypercallsDisable(&pVM->aCpus[i]);
803	}
804
805	return VINF_SUCCESS;
806	#endif /* IN_RING3 */
807	}
808
809	case MSR_GIM_HV_HYPERCALL:
810	{
811	#ifndef IN_RING3
812	return VINF_CPUM_R3_MSR_WRITE;
813	#else
814	/** @todo There is/was a problem with hypercalls for FreeBSD 10.1 guests,
815	* see @bugref{7270#c116}. */
816	/* First, update all but the hypercall page enable bit. */
817	pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE);
818
819	/* Hypercall page can only be enabled when the guest has enabled hypercalls. */
820	bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue);
821	if ( fEnable
822	&& !gimHvAreHypercallsEnabled(pVCpu))
823	{
824	return VINF_SUCCESS;
825	}
826
827	/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
828	if (!fEnable)
829	{
830	gimR3HvDisableHypercallPage(pVM);
831	pHv->u64HypercallMsr = uRawValue;
832	return VINF_SUCCESS;
833	}
834
835	/* Enable the hypercall-page. */
836	RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
837	int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
838	if (RT_SUCCESS(rc))
839	{
840	pHv->u64HypercallMsr = uRawValue;
841	return VINF_SUCCESS;
842	}
843
844	return VERR_CPUM_RAISE_GP_0;
845	#endif
846	}
847
848	case MSR_GIM_HV_REF_TSC:
849	{
850	#ifndef IN_RING3
851	return VINF_CPUM_R3_MSR_WRITE;
852	#else /* IN_RING3 */
853	/* First, update all but the TSC page enable bit. */
854	pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE);
855
856	/* Is the guest disabling the TSC page? */
857	bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue);
858	if (!fEnable)
859	{
860	gimR3HvDisableTscPage(pVM);
861	pHv->u64TscPageMsr = uRawValue;
862	return VINF_SUCCESS;
863	}
864
865	/* Enable the TSC page. */
866	RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
867	int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence /, 0 / uTscSequence */);
868	if (RT_SUCCESS(rc))
869	{
870	pHv->u64TscPageMsr = uRawValue;
871	return VINF_SUCCESS;
872	}
873
874	return VERR_CPUM_RAISE_GP_0;
875	#endif /* IN_RING3 */
876	}
877
878	case MSR_GIM_HV_APIC_ASSIST_PAGE:
879	{
880	#ifndef IN_RING3
881	return VINF_CPUM_R3_MSR_WRITE;
882	#else /* IN_RING3 */
883	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
884	pHvCpu->uApicAssistPageMsr = uRawValue;
885
886	if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue))
887	{
888	RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
889	if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage))
890	{
891	int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage);
892	if (RT_SUCCESS(rc))
893	{
894	pHvCpu->uApicAssistPageMsr = uRawValue;
895	return VINF_SUCCESS;
896	}
897	}
898	else
899	{
900	LogRelMax(5, ("GIM%u: HyperV: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu,
901	GCPhysApicAssistPage));
902	}
903	}
904	else
905	gimR3HvDisableApicAssistPage(pVCpu);
906
907	return VERR_CPUM_RAISE_GP_0;
908	#endif /* IN_RING3 */
909	}
910
911	case MSR_GIM_HV_RESET:
912	{
913	#ifndef IN_RING3
914	return VINF_CPUM_R3_MSR_WRITE;
915	#else
916	if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue))
917	{
918	LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
919	int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3, PDMVMRESET_F_GIM);
920	AssertRC(rc); /* Note! Not allowed to return VINF_EM_RESET / VINF_EM_HALT here, so ignore them. */
921	}
922	/* else: Ignore writes to other bits. */
923	return VINF_SUCCESS;
924	#endif /* IN_RING3 */
925	}
926
927	case MSR_GIM_HV_CRASH_CTL:
928	{
929	#ifndef IN_RING3
930	return VINF_CPUM_R3_MSR_WRITE;
931	#else
932	if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY)
933	{
934	LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
935	pHv->uCrashP0Msr, pHv->uCrashP1Msr, pHv->uCrashP2Msr, pHv->uCrashP3Msr, pHv->uCrashP4Msr));
936
937	if (DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_BSOD_MSR))
938	DBGFEventGenericWithArg(pVM, pVCpu, DBGFEVENT_BSOD_MSR, pHv->uCrashP0Msr, DBGFEVENTCTX_OTHER);
939	/* (Do not try pass VINF_EM_DBG_EVENT, doesn't work from here!) */
940	}
941	return VINF_SUCCESS;
942	#endif
943	}
944
945	case MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER:
946	{
947	if (!pHv->fDbgEnabled)
948	return VERR_CPUM_RAISE_GP_0;
949	#ifndef IN_RING3
950	return VINF_CPUM_R3_MSR_WRITE;
951	#else
952	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
953	pHv->uDbgSendBufferMsr = GCPhysBuffer;
954	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
955	LogRel(("GIM: HyperV: Set up debug send buffer at %#RGp\n", GCPhysBuffer));
956	else
957	LogRel(("GIM: HyperV: Destroyed debug send buffer\n"));
958	pHv->uDbgSendBufferMsr = uRawValue;
959	return VINF_SUCCESS;
960	#endif
961	}
962
963	case MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER:
964	{
965	if (!pHv->fDbgEnabled)
966	return VERR_CPUM_RAISE_GP_0;
967	#ifndef IN_RING3
968	return VINF_CPUM_R3_MSR_WRITE;
969	#else
970	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
971	pHv->uDbgRecvBufferMsr = GCPhysBuffer;
972	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
973	LogRel(("GIM: HyperV: Set up debug receive buffer at %#RGp\n", GCPhysBuffer));
974	else
975	LogRel(("GIM: HyperV: Destroyed debug receive buffer\n"));
976	return VINF_SUCCESS;
977	#endif
978	}
979
980	case MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER:
981	{
982	if (!pHv->fDbgEnabled)
983	return VERR_CPUM_RAISE_GP_0;
984	#ifndef IN_RING3
985	return VINF_CPUM_R3_MSR_WRITE;
986	#else
987	RTGCPHYS GCPhysBuffer = (RTGCPHYS)uRawValue;
988	pHv->uDbgPendingBufferMsr = GCPhysBuffer;
989	if (PGMPhysIsGCPhysNormal(pVM, GCPhysBuffer))
990	LogRel(("GIM: HyperV: Set up debug pending buffer at %#RGp\n", uRawValue));
991	else
992	LogRel(("GIM: HyperV: Destroyed debug pending buffer\n"));
993	return VINF_SUCCESS;
994	#endif
995	}
996
997	case MSR_GIM_HV_SYNTH_DEBUG_CONTROL:
998	{
999	if (!pHv->fDbgEnabled)
1000	return VERR_CPUM_RAISE_GP_0;
1001	#ifndef IN_RING3
1002	return VINF_CPUM_R3_MSR_WRITE;
1003	#else
1004	if ( MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue)
1005	&& MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1006	{
1007	LogRel(("GIM: HyperV: Requesting both read and write through debug control MSR -> #GP(0)\n"));
1008	return VERR_CPUM_RAISE_GP_0;
1009	}
1010
1011	if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(uRawValue))
1012	{
1013	uint32_t cbWrite = MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue);
1014	if ( cbWrite > 0
1015	&& cbWrite < GIM_HV_PAGE_SIZE)
1016	{
1017	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgSendBufferMsr))
1018	{
1019	Assert(pHv->pvDbgBuffer);
1020	int rc = PGMPhysSimpleReadGCPhys(pVM, pHv->pvDbgBuffer, (RTGCPHYS)pHv->uDbgSendBufferMsr, cbWrite);
1021	if (RT_SUCCESS(rc))
1022	{
1023	LogRelMax(1, ("GIM: HyperV: Initiated debug data transmission via MSR\n"));
1024	uint32_t cbWritten = 0;
1025	rc = gimR3HvDebugWrite(pVM, pHv->pvDbgBuffer, cbWrite, &cbWritten, false /fUdpPkt/);
1026	if ( RT_SUCCESS(rc)
1027	&& cbWrite == cbWritten)
1028	pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS;
1029	else
1030	pHv->uDbgStatusMsr = 0;
1031	}
1032	else
1033	LogRelMax(5, ("GIM: HyperV: Failed to read debug send buffer at %#RGp, rc=%Rrc\n",
1034	(RTGCPHYS)pHv->uDbgSendBufferMsr, rc));
1035	}
1036	else
1037	LogRelMax(5, ("GIM: HyperV: Debug send buffer address %#RGp invalid! Ignoring debug write!\n",
1038	(RTGCPHYS)pHv->uDbgSendBufferMsr));
1039	}
1040	else
1041	LogRelMax(5, ("GIM: HyperV: Invalid write size %u specified in MSR, ignoring debug write!\n",
1042	MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(uRawValue)));
1043	}
1044	else if (MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(uRawValue))
1045	{
1046	if (PGMPhysIsGCPhysNormal(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr))
1047	{
1048	LogRelMax(1, ("GIM: HyperV: Initiated debug data reception via MSR\n"));
1049	uint32_t cbReallyRead;
1050	Assert(pHv->pvDbgBuffer);
1051	int rc = gimR3HvDebugRead(pVM, pHv->pvDbgBuffer, PAGE_SIZE, PAGE_SIZE, &cbReallyRead, 0, false /fUdpPkt/);
1052	if ( RT_SUCCESS(rc)
1053	&& cbReallyRead > 0)
1054	{
1055	rc = PGMPhysSimpleWriteGCPhys(pVM, (RTGCPHYS)pHv->uDbgRecvBufferMsr, pHv->pvDbgBuffer, cbReallyRead);
1056	if (RT_SUCCESS(rc))
1057	{
1058	pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16;
1059	pHv->uDbgStatusMsr \|= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS;
1060	}
1061	else
1062	{
1063	pHv->uDbgStatusMsr = 0;
1064	LogRelMax(5, ("GIM: HyperV: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));
1065	}
1066	}
1067	else
1068	pHv->uDbgStatusMsr = 0;
1069	}
1070	else
1071	{
1072	LogRelMax(5, ("GIM: HyperV: Debug receive buffer address %#RGp invalid! Ignoring debug read!\n",
1073	(RTGCPHYS)pHv->uDbgRecvBufferMsr));
1074	}
1075	}
1076	return VINF_SUCCESS;
1077	#endif
1078	}
1079
1080	case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3:
1081	case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7:
1082	case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11:
1083	case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15:
1084	{
1085	uint8_t uVector = MSR_GIM_HV_SINT_GET_VECTOR(uRawValue);
1086	bool const fVMBusMsg = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
1087	size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
1088	const char *pszDesc = fVMBusMsg ? "VMBus Message" : "Generic";
1089	if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
1090	{
1091	LogRel(("GIM%u: HyperV: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
1092	idxSintMsr, pszDesc, uVector));
1093	return VERR_CPUM_RAISE_GP_0;
1094	}
1095
1096	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1097	pHvCpu->auSintMsrs[idxSintMsr] = uRawValue;
1098	if (fVMBusMsg)
1099	{
1100	if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
1101	Log(("GIM%u: HyperV: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
1102	else
1103	Log(("GIM%u: HyperV: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
1104	}
1105	Log(("GIM%u: HyperV: Written SINT%u=%#RX64\n", pVCpu->idCpu, idxSintMsr, uRawValue));
1106	return VINF_SUCCESS;
1107	}
1108
1109	case MSR_GIM_HV_SCONTROL:
1110	{
1111	#ifndef IN_RING3
1112	/** @todo make this RZ later? */
1113	return VINF_CPUM_R3_MSR_WRITE;
1114	#else
1115	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1116	pHvCpu->uSControlMsr = uRawValue;
1117	if (MSR_GIM_HV_SCONTROL_IS_ENABLED(uRawValue))
1118	LogRel(("GIM%u: HyperV: Synthetic interrupt control enabled\n", pVCpu->idCpu));
1119	else
1120	LogRel(("GIM%u: HyperV: Synthetic interrupt control disabled\n", pVCpu->idCpu));
1121	return VINF_SUCCESS;
1122	#endif
1123	}
1124
1125	case MSR_GIM_HV_STIMER0_CONFIG:
1126	case MSR_GIM_HV_STIMER1_CONFIG:
1127	case MSR_GIM_HV_STIMER2_CONFIG:
1128	case MSR_GIM_HV_STIMER3_CONFIG:
1129	{
1130	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1131	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1132
1133	/* Validate the writable bits. */
1134	if (RT_LIKELY(!(uRawValue & ~MSR_GIM_HV_STIMER_RW_VALID)))
1135	{
1136	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1137	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1138	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1139
1140	/* Lock to prevent concurrent access from the timer callback. */
1141	int rc = TMTimerLock(pTimer, VERR_IGNORED);
1142	if (rc == VINF_SUCCESS)
1143	{
1144	/* Update the MSR value. */
1145	pHvStimer->uStimerConfigMsr = uRawValue;
1146	Log(("GIM%u: HyperV: Set STIMER_CONFIG%u=%#RX64\n", pVCpu->idCpu, idxStimer, uRawValue));
1147
1148	/* Process the MSR bits. */
1149	if ( !MSR_GIM_HV_STIMER_GET_SINTX(uRawValue) /* Writing SINTx as 0 causes the timer to be disabled. */
1150	\|\| !MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1151	{
1152	pHvStimer->uStimerConfigMsr &= ~MSR_GIM_HV_STIMER_ENABLE;
1153	gimHvStopStimer(pVCpu, pHvStimer);
1154	Log(("GIM%u: HyperV: Disabled STIMER_CONFIG%u\n", pVCpu->idCpu, idxStimer));
1155	}
1156	else if (MSR_GIM_HV_STIMER_IS_ENABLED(uRawValue))
1157	{
1158	/* Auto-enable implies writing to the STIMERx_COUNT MSR is what starts the timer. */
1159	if (!MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(uRawValue))
1160	{
1161	if (!TMTimerIsActive(pHvStimer->CTX_SUFF(pTimer)))
1162	{
1163	gimHvStartStimer(pVCpu, pHvStimer);
1164	Log(("GIM%u: HyperV: Started STIMER%u\n", pVCpu->idCpu, idxStimer));
1165	}
1166	else
1167	{
1168	/*
1169	* Enabling a timer that's already enabled is undefined behaviour,
1170	* see Hyper-V spec. 15.3.1 "Synthetic Timer Configuration Register".
1171	*
1172	* Our implementation just re-starts the timer. Guests that comform to
1173	* the Hyper-V specs. should not be doing this anyway.
1174	*/
1175	AssertFailed();
1176	gimHvStopStimer(pVCpu, pHvStimer);
1177	gimHvStartStimer(pVCpu, pHvStimer);
1178	}
1179	}
1180	}
1181
1182	TMTimerUnlock(pTimer);
1183	}
1184	return rc;
1185	}
1186	#ifndef IN_RING3
1187	return VINF_CPUM_R3_MSR_WRITE;
1188	#else
1189	LogRel(("GIM%u: HyperV: Setting reserved bits of STIMER%u MSR (uRawValue=%#RX64) -> #GP(0)\n", pVCpu->idCpu,
1190	idxStimer, uRawValue));
1191	return VERR_CPUM_RAISE_GP_0;
1192	#endif
1193	}
1194
1195	case MSR_GIM_HV_STIMER0_COUNT:
1196	case MSR_GIM_HV_STIMER1_COUNT:
1197	case MSR_GIM_HV_STIMER2_COUNT:
1198	case MSR_GIM_HV_STIMER3_COUNT:
1199	{
1200	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1201	uint8_t const idxStimer = (idMsr - MSR_GIM_HV_STIMER0_CONFIG) >> 1;
1202	Assert(idxStimer < RT_ELEMENTS(pHvCpu->aStimers));
1203	PGIMHVSTIMER pHvStimer = &pHvCpu->aStimers[idxStimer];
1204	int const rcBusy = VINF_CPUM_R3_MSR_WRITE;
1205
1206	/*
1207	* Writing zero to this MSR disables the timer regardless of whether the auto-enable
1208	* flag is set in the config MSR corresponding to the timer.
1209	*/
1210	if (!uRawValue)
1211	{
1212	gimHvStopStimer(pVCpu, pHvStimer);
1213	pHvStimer->uStimerCountMsr = 0;
1214	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64, stopped timer\n", pVCpu->idCpu, idxStimer, uRawValue));
1215	return VINF_SUCCESS;
1216	}
1217
1218	/*
1219	* Concurrent writes to the config. MSR can't happen as it's serialized by way
1220	* of being done on the same EMT as this.
1221	*/
1222	if (MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(pHvStimer->uStimerConfigMsr))
1223	{
1224	PTMTIMER pTimer = pHvStimer->CTX_SUFF(pTimer);
1225	int rc = TMTimerLock(pTimer, rcBusy);
1226	if (rc == VINF_SUCCESS)
1227	{
1228	pHvStimer->uStimerCountMsr = uRawValue;
1229	gimHvStartStimer(pVCpu, pHvStimer);
1230	TMTimerUnlock(pTimer);
1231	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64 %RU64 msec, auto-started timer\n", pVCpu->idCpu, idxStimer,
1232	uRawValue, (uRawValue * 100) / RT_NS_1MS_64));
1233	}
1234	return rc;
1235	}
1236
1237	/* Simple update of the counter without any timer start/stop side-effects. */
1238	pHvStimer->uStimerCountMsr = uRawValue;
1239	Log(("GIM%u: HyperV: Set STIMER_COUNT%u=%RU64\n", pVCpu->idCpu, idxStimer, uRawValue));
1240	return VINF_SUCCESS;
1241	}
1242
1243	case MSR_GIM_HV_EOM:
1244	{
1245	/** @todo implement EOM. */
1246	Log(("GIM%u: HyperV: EOM\n", pVCpu->idCpu));
1247	return VINF_SUCCESS;
1248	}
1249
1250	case MSR_GIM_HV_SIEFP:
1251	{
1252	#ifndef IN_RING3
1253	return VINF_CPUM_R3_MSR_WRITE;
1254	#else
1255	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1256	pHvCpu->uSiefpMsr = uRawValue;
1257	if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue))
1258	{
1259	RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT;
1260	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage))
1261	{
1262	int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage);
1263	if (RT_SUCCESS(rc))
1264	{
1265	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt event flags page at %#RGp\n", pVCpu->idCpu,
1266	GCPhysSiefPage));
1267	/** @todo SIEF setup. */
1268	return VINF_SUCCESS;
1269	}
1270	}
1271	else
1272	LogRelMax(5, ("GIM%u: HyperV: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage));
1273	}
1274	else
1275	gimR3HvDisableSiefPage(pVCpu);
1276
1277	return VERR_CPUM_RAISE_GP_0;
1278	#endif
1279	break;
1280	}
1281
1282	case MSR_GIM_HV_SIMP:
1283	{
1284	#ifndef IN_RING3
1285	return VINF_CPUM_R3_MSR_WRITE;
1286	#else
1287	PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
1288	pHvCpu->uSimpMsr = uRawValue;
1289	if (MSR_GIM_HV_SIMP_IS_ENABLED(uRawValue))
1290	{
1291	RTGCPHYS GCPhysSimp = MSR_GIM_HV_SIMP_GPA(uRawValue);
1292	if (PGMPhysIsGCPhysNormal(pVM, GCPhysSimp))
1293	{
1294	uint8_t abSimp[PAGE_SIZE];
1295	RT_ZERO(abSimp);
1296	int rc2 = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimp, &abSimp[0], sizeof(abSimp));
1297	if (RT_SUCCESS(rc2))
1298	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at %#RGp\n", pVCpu->idCpu, GCPhysSimp));
1299	else
1300	{
1301	LogRel(("GIM%u: HyperV: Failed to update synthetic interrupt message page at %#RGp. uSimpMsr=%#RX64 rc=%Rrc\n",
1302	pVCpu->idCpu, pHvCpu->uSimpMsr, GCPhysSimp, rc2));
1303	return VERR_CPUM_RAISE_GP_0;
1304	}
1305	}
1306	else
1307	{
1308	LogRel(("GIM%u: HyperV: Enabled synthetic interrupt message page at invalid address %#RGp\n", pVCpu->idCpu,
1309	GCPhysSimp));
1310	}
1311	}
1312	else
1313	LogRel(("GIM%u: HyperV: Disabled synthetic interrupt message page\n", pVCpu->idCpu));
1314	return VINF_SUCCESS;
1315	#endif
1316	}
1317
1318	case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0Msr = uRawValue; return VINF_SUCCESS;
1319	case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1Msr = uRawValue; return VINF_SUCCESS;
1320	case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2Msr = uRawValue; return VINF_SUCCESS;
1321	case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3Msr = uRawValue; return VINF_SUCCESS;
1322	case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4Msr = uRawValue; return VINF_SUCCESS;
1323
1324	case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
1325	case MSR_GIM_HV_VP_INDEX:
1326	case MSR_GIM_HV_TSC_FREQ:
1327	case MSR_GIM_HV_APIC_FREQ:
1328	LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
1329	break;
1330
1331	case MSR_GIM_HV_DEBUG_OPTIONS_MSR:
1332	{
1333	if (pHv->fIsVendorMsHv)
1334	{
1335	#ifndef IN_RING3
1336	return VINF_CPUM_R3_MSR_WRITE;
1337	#else
1338	LogRelMax(5, ("GIM: HyperV: Write debug options MSR with %#RX64 ignored\n", uRawValue));
1339	return VINF_SUCCESS;
1340	#endif
1341	}
1342	return VERR_CPUM_RAISE_GP_0;
1343	}
1344
1345	default:
1346	{
1347	#ifdef IN_RING3
1348	static uint32_t s_cTimes = 0;
1349	if (s_cTimes++ < 20)
1350	LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
1351	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
1352	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
1353	break;
1354	#else
1355	return VINF_CPUM_R3_MSR_WRITE;
1356	#endif
1357	}
1358	}
1359
1360	return VERR_CPUM_RAISE_GP_0;
1361	}
1362
1363
1364	/**
1365	* Whether we need to trap \#UD exceptions in the guest.
1366	*
1367	* We only need to trap \#UD exceptions for raw-mode guests when hypercalls are
1368	* enabled. For HM VMs, the hypercall would be handled via the
1369	* VMCALL/VMMCALL VM-exit.
1370	*
1371	* @param pVCpu The cross context virtual CPU structure.
1372	*/
1373	VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu)
1374	{
1375	if ( VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM))
1376	&& gimHvAreHypercallsEnabled(pVCpu))
1377	return true;
1378	return false;
1379	}
1380
1381
1382	/**
1383	* Checks the currently disassembled instruction and executes the hypercall if
1384	* it's a hypercall instruction.
1385	*
1386	* @returns Strict VBox status code.
1387	* @param pVCpu The cross context virtual CPU structure.
1388	* @param pCtx Pointer to the guest-CPU context.
1389	* @param pDis Pointer to the disassembled instruction state at RIP.
1390	*
1391	* @thread EMT(pVCpu).
1392	*
1393	* @todo Make this function static when @bugref{7270#c168} is addressed.
1394	*/
1395	VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
1396	{
1397	Assert(pVCpu);
1398	Assert(pCtx);
1399	Assert(pDis);
1400	VMCPU_ASSERT_EMT(pVCpu);
1401
1402	PVM pVM = pVCpu->CTX_SUFF(pVM);
1403	CPUMCPUVENDOR const enmGuestCpuVendor = CPUMGetGuestCpuVendor(pVM);
1404	if ( ( pDis->pCurInstr->uOpcode == OP_VMCALL
1405	&& ( enmGuestCpuVendor == CPUMCPUVENDOR_INTEL
1406	\|\| enmGuestCpuVendor == CPUMCPUVENDOR_VIA))
1407	\|\| ( pDis->pCurInstr->uOpcode == OP_VMMCALL
1408	&& enmGuestCpuVendor == CPUMCPUVENDOR_AMD))
1409	{
1410	return gimHvHypercall(pVCpu, pCtx);
1411	}
1412
1413	return VERR_GIM_INVALID_HYPERCALL_INSTR;
1414	}
1415
1416
1417	/**
1418	* Exception handler for \#UD.
1419	*
1420	* @returns Strict VBox status code.
1421	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
1422	* failed).
1423	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
1424	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
1425	* RIP.
1426	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
1427	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
1428	* hypercall instruction.
1429	*
1430	* @param pVCpu The cross context virtual CPU structure.
1431	* @param pCtx Pointer to the guest-CPU context.
1432	* @param pDis Pointer to the disassembled instruction state at RIP.
1433	* Optional, can be NULL.
1434	* @param pcbInstr Where to store the instruction length of the hypercall
1435	* instruction. Optional, can be NULL.
1436	*
1437	* @thread EMT(pVCpu).
1438	*/
1439	VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
1440	{
1441	VMCPU_ASSERT_EMT(pVCpu);
1442
1443	/*
1444	* If we didn't ask for #UD to be trapped, bail.
1445	*/
1446	if (!gimHvShouldTrapXcptUD(pVCpu))
1447	return VERR_GIM_IPE_1;
1448
1449	if (!pDis)
1450	{
1451	/*
1452	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
1453	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
1454	*/
1455	unsigned cbInstr;
1456	DISCPUSTATE Dis;
1457	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, &Dis, &cbInstr);
1458	if (RT_SUCCESS(rc))
1459	{
1460	if (pcbInstr)
1461	*pcbInstr = (uint8_t)cbInstr;
1462	return gimHvExecHypercallInstr(pVCpu, pCtx, &Dis);
1463	}
1464
1465	Log(("GIM: HyperV: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
1466	return rc;
1467	}
1468
1469	return gimHvExecHypercallInstr(pVCpu, pCtx, pDis);
1470	}
1471

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp@ 72255

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