VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 93582

Last change on this file since 93582 was 93115, checked in by vboxsync, 3 years ago

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1/* $Id: GIMAllKvm.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * GIM - Guest Interface Manager, KVM, All Contexts.
4 */
5
6/*
7 * Copyright (C) 2015-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_GIM
23#include <VBox/vmm/gim.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/em.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmapi.h>
30#include "GIMKvmInternal.h"
31#include "GIMInternal.h"
32#include <VBox/vmm/vmcc.h>
33
34#include <VBox/dis.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37
38#include <iprt/asm-amd64-x86.h>
39#include <iprt/time.h>
40
41
42/**
43 * Handles the KVM hypercall.
44 *
45 * @returns Strict VBox status code.
46 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
47 * failed).
48 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
49 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
50 *
51 * @param pVCpu The cross context virtual CPU structure.
52 * @param pCtx Pointer to the guest-CPU context.
53 *
54 * @thread EMT(pVCpu).
55 */
56VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx)
57{
58 VMCPU_ASSERT_EMT(pVCpu);
59
60 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
61 STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
62
63 /*
64 * Get the hypercall operation and arguments.
65 */
66 bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
67 uint64_t uHyperOp = pCtx->rax;
68 uint64_t uHyperArg0 = pCtx->rbx;
69 uint64_t uHyperArg1 = pCtx->rcx;
70 uint64_t uHyperArg2 = pCtx->rdi;
71 uint64_t uHyperArg3 = pCtx->rsi;
72 uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
73 uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
74 if (!fIs64BitMode)
75 {
76 uAndMask = UINT64_C(0xffffffff);
77 uHyperOp &= UINT64_C(0xffffffff);
78 uHyperArg0 &= UINT64_C(0xffffffff);
79 uHyperArg1 &= UINT64_C(0xffffffff);
80 uHyperArg2 &= UINT64_C(0xffffffff);
81 uHyperArg3 &= UINT64_C(0xffffffff);
82 uHyperRet &= UINT64_C(0xffffffff);
83 }
84
85 /*
86 * Verify that guest ring-0 is the one making the hypercall.
87 */
88 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
89 if (RT_UNLIKELY(uCpl))
90 {
91 pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
92 return VERR_GIM_HYPERCALL_ACCESS_DENIED;
93 }
94
95 /*
96 * Do the work.
97 */
98 int rc = VINF_SUCCESS;
99 switch (uHyperOp)
100 {
101 case KVM_HYPERCALL_OP_KICK_CPU:
102 {
103 if (uHyperArg1 < pVM->cCpus)
104 {
105 PVMCPUCC pVCpuDst = VMCC_GET_CPU(pVM, uHyperArg1); /* ASSUMES pVCpu index == ApicId of the VCPU. */
106 EMUnhaltAndWakeUp(pVM, pVCpuDst);
107 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
108 }
109 else
110 {
111 /* Shouldn't ever happen! If it does, throw a guru, as otherwise it'll lead to deadlocks in the guest anyway! */
112 rc = VERR_GIM_HYPERCALL_FAILED;
113 }
114 break;
115 }
116
117 case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
118 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
119 break;
120
121 default:
122 break;
123 }
124
125 /*
126 * Place the result in rax/eax.
127 */
128 pCtx->rax = uHyperRet & uAndMask;
129 return rc;
130}
131
132
133/**
134 * Returns whether the guest has configured and enabled the use of KVM's
135 * hypercall interface.
136 *
137 * @returns true if hypercalls are enabled, false otherwise.
138 * @param pVCpu The cross context virtual CPU structure.
139 */
140VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
141{
142 NOREF(pVCpu);
143 /* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
144 that guests can control, i.e. hypercalls are always enabled. */
145 return true;
146}
147
148
149/**
150 * Returns whether the guest has configured and enabled the use of KVM's
151 * paravirtualized TSC.
152 *
153 * @returns true if paravirt. TSC is enabled, false otherwise.
154 * @param pVM The cross context VM structure.
155 */
156VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVMCC pVM)
157{
158 uint32_t const cCpus = pVM->cCpus;
159 for (uint32_t idCpu = 0; idCpu < cCpus; idCpu++)
160 {
161 PVMCPUCC pVCpu = pVM->CTX_SUFF(apCpus)[idCpu];
162 PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
163 if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
164 return true;
165 }
166 return false;
167}
168
169
170/**
171 * MSR read handler for KVM.
172 *
173 * @returns Strict VBox status code like CPUMQueryGuestMsr().
174 * @retval VINF_CPUM_R3_MSR_READ
175 * @retval VERR_CPUM_RAISE_GP_0
176 *
177 * @param pVCpu The cross context virtual CPU structure.
178 * @param idMsr The MSR being read.
179 * @param pRange The range this MSR belongs to.
180 * @param puValue Where to store the MSR value read.
181 */
182VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183{
184 NOREF(pRange);
185 PVM pVM = pVCpu->CTX_SUFF(pVM);
186 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
187 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
188
189 switch (idMsr)
190 {
191 case MSR_GIM_KVM_SYSTEM_TIME:
192 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
193 *puValue = pKvmCpu->u64SystemTimeMsr;
194 return VINF_SUCCESS;
195
196 case MSR_GIM_KVM_WALL_CLOCK:
197 case MSR_GIM_KVM_WALL_CLOCK_OLD:
198 *puValue = pKvm->u64WallClockMsr;
199 return VINF_SUCCESS;
200
201 default:
202 {
203#ifdef IN_RING3
204 static uint32_t s_cTimes = 0;
205 if (s_cTimes++ < 20)
206 LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
207#endif
208 LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
209 break;
210 }
211 }
212
213 return VERR_CPUM_RAISE_GP_0;
214}
215
216
217/**
218 * MSR write handler for KVM.
219 *
220 * @returns Strict VBox status code like CPUMSetGuestMsr().
221 * @retval VINF_CPUM_R3_MSR_WRITE
222 * @retval VERR_CPUM_RAISE_GP_0
223 *
224 * @param pVCpu The cross context virtual CPU structure.
225 * @param idMsr The MSR being written.
226 * @param pRange The range this MSR belongs to.
227 * @param uRawValue The raw value with the ignored bits not masked.
228 */
229VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
230{
231 NOREF(pRange);
232 switch (idMsr)
233 {
234 case MSR_GIM_KVM_SYSTEM_TIME:
235 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
236 {
237#ifndef IN_RING3
238 RT_NOREF2(pVCpu, uRawValue);
239 return VINF_CPUM_R3_MSR_WRITE;
240#else
241 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
242 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
243 if (uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT)
244 gimR3KvmEnableSystemTime(pVM, pVCpu, uRawValue);
245 else
246 gimR3KvmDisableSystemTime(pVM);
247
248 pKvmCpu->u64SystemTimeMsr = uRawValue;
249 return VINF_SUCCESS;
250#endif /* IN_RING3 */
251 }
252
253 case MSR_GIM_KVM_WALL_CLOCK:
254 case MSR_GIM_KVM_WALL_CLOCK_OLD:
255 {
256#ifndef IN_RING3
257 RT_NOREF2(pVCpu, uRawValue);
258 return VINF_CPUM_R3_MSR_WRITE;
259#else
260 /* Enable the wall-clock struct. */
261 RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
262 if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
263 {
264 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
265 int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
266 if (RT_SUCCESS(rc))
267 {
268 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
269 pKvm->u64WallClockMsr = uRawValue;
270 return VINF_SUCCESS;
271 }
272 }
273 return VERR_CPUM_RAISE_GP_0;
274#endif /* IN_RING3 */
275 }
276
277 default:
278 {
279#ifdef IN_RING3
280 static uint32_t s_cTimes = 0;
281 if (s_cTimes++ < 20)
282 LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
283 uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
284#endif
285 LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
286 break;
287 }
288 }
289
290 return VERR_CPUM_RAISE_GP_0;
291}
292
293
294/**
295 * Whether we need to trap \#UD exceptions in the guest.
296 *
297 * On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
298 * the Intel VMCALL instruction to make hypercalls and we need to trap and
299 * optionally patch them to the AMD-V VMMCALL instruction and handle the
300 * hypercall.
301 *
302 * I guess this was done so that guest teleporation between an AMD and an Intel
303 * machine would working without any changes at the time of teleporation.
304 * However, this also means we -always- need to intercept \#UD exceptions on one
305 * of the two CPU models (Intel or AMD). Hyper-V solves this problem more
306 * elegantly by letting the hypervisor supply an opaque hypercall page.
307 *
308 * For raw-mode VMs, this function will always return true. See gimR3KvmInit().
309 *
310 * @param pVM The cross context VM structure.
311 */
312VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVM pVM)
313{
314 return pVM->gim.s.u.Kvm.fTrapXcptUD;
315}
316
317
318/**
319 * Checks the instruction and executes the hypercall if it's a valid hypercall
320 * instruction.
321 *
322 * This interface is used by \#UD handlers and IEM.
323 *
324 * @returns Strict VBox status code.
325 * @param pVCpu The cross context virtual CPU structure.
326 * @param pCtx Pointer to the guest-CPU context.
327 * @param uDisOpcode The disassembler opcode.
328 * @param cbInstr The instruction length.
329 *
330 * @thread EMT(pVCpu).
331 */
332VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
333{
334 Assert(pVCpu);
335 Assert(pCtx);
336 VMCPU_ASSERT_EMT(pVCpu);
337
338 /*
339 * If the instruction at RIP is the Intel VMCALL instruction or
340 * the AMD VMMCALL instruction handle it as a hypercall.
341 *
342 * Linux/KVM guests always uses the Intel VMCALL instruction but we patch
343 * it to the host-native one whenever we encounter it so subsequent calls
344 * will not require disassembly (when coming from HM).
345 */
346 if ( uDisOpcode == OP_VMCALL
347 || uDisOpcode == OP_VMMCALL)
348 {
349 /*
350 * Perform the hypercall.
351 *
352 * For HM, we can simply resume guest execution without performing the hypercall now and
353 * do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
354 *
355 * For raw-mode we need to do this now anyway. So we do it here regardless with an added
356 * advantage is that it saves one world-switch for the HM case.
357 */
358 VBOXSTRICTRC rcStrict = gimKvmHypercall(pVCpu, pCtx);
359 if (rcStrict == VINF_SUCCESS)
360 {
361 /*
362 * Patch the instruction to so we don't have to spend time disassembling it each time.
363 * Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
364 */
365 PVM pVM = pVCpu->CTX_SUFF(pVM);
366 PCGIMKVM pKvm = &pVM->gim.s.u.Kvm;
367 if ( uDisOpcode != pKvm->uOpcodeNative
368 && cbInstr == sizeof(pKvm->abOpcodeNative) )
369 {
370 /** @todo r=ramshankar: we probably should be doing this in an
371 * EMT rendezvous. */
372 /** @todo Add stats for patching. */
373 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, pKvm->abOpcodeNative, sizeof(pKvm->abOpcodeNative));
374 AssertRC(rc);
375 }
376 }
377 else
378 {
379 /* The KVM provider doesn't have any concept of continuing hypercalls. */
380 Assert(rcStrict != VINF_GIM_HYPERCALL_CONTINUING);
381#ifdef IN_RING3
382 Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
383#endif
384 }
385 return rcStrict;
386 }
387
388 return VERR_GIM_INVALID_HYPERCALL_INSTR;
389}
390
391
392/**
393 * Exception handler for \#UD.
394 *
395 * @returns Strict VBox status code.
396 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
397 * failed).
398 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
399 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
400 * @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
401 * hypercall instruction.
402 *
403 * @param pVM The cross context VM structure.
404 * @param pVCpu The cross context virtual CPU structure.
405 * @param pCtx Pointer to the guest-CPU context.
406 * @param pDis Pointer to the disassembled instruction state at RIP.
407 * Optional, can be NULL.
408 * @param pcbInstr Where to store the instruction length of the hypercall
409 * instruction. Optional, can be NULL.
410 *
411 * @thread EMT(pVCpu).
412 */
413VMM_INT_DECL(VBOXSTRICTRC) gimKvmXcptUD(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
414{
415 VMCPU_ASSERT_EMT(pVCpu);
416
417 /*
418 * If we didn't ask for #UD to be trapped, bail.
419 */
420 if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
421 return VERR_GIM_IPE_3;
422
423 if (!pDis)
424 {
425 unsigned cbInstr;
426 DISCPUSTATE Dis;
427 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbInstr);
428 if (RT_SUCCESS(rc))
429 {
430 if (pcbInstr)
431 *pcbInstr = (uint8_t)cbInstr;
432 return gimKvmHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
433 }
434
435 Log(("GIM: KVM: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
436 return rc;
437 }
438
439 return gimKvmHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
440}
441
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