GIMAllKvm.cpp@ 57350

Last change on this file since 57350 was 57350, checked in by vboxsync, 9 years ago
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1	/* $Id: GIMAllKvm.cpp 57350 2015-08-14 14:06:15Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, KVM, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_GIM
22	#include "GIMKvmInternal.h"
23	#include "GIMInternal.h"
24
25	#include <VBox/err.h>
26	#include <VBox/dis.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/em.h>
29	#include <VBox/vmm/tm.h>
30	#include <VBox/vmm/vm.h>
31	#include <VBox/vmm/pgm.h>
32	#include <VBox/vmm/pdmdev.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/sup.h>
35
36	#include <iprt/asm-amd64-x86.h>
37	#include <iprt/time.h>
38
39
40	/**
41	* Handles the KVM hypercall.
42	*
43	* @returns VBox status code.
44	* @param pVCpu Pointer to the VMCPU.
45	* @param pCtx Pointer to the guest-CPU context.
46	*/
47	VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
48	{
49	/*
50	* Get the hypercall operation and arguments.
51	*/
52	bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
53	uint64_t uHyperOp = pCtx->rax;
54	uint64_t uHyperArg0 = pCtx->rbx;
55	uint64_t uHyperArg1 = pCtx->rcx;
56	uint64_t uHyperArg2 = pCtx->rdi;
57	uint64_t uHyperArg3 = pCtx->rsi;
58	uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
59	uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
60	if (!fIs64BitMode)
61	{
62	uAndMask = UINT64_C(0xffffffff);
63	uHyperOp &= UINT64_C(0xffffffff);
64	uHyperArg0 &= UINT64_C(0xffffffff);
65	uHyperArg1 &= UINT64_C(0xffffffff);
66	uHyperArg2 &= UINT64_C(0xffffffff);
67	uHyperArg3 &= UINT64_C(0xffffffff);
68	uHyperRet &= UINT64_C(0xffffffff);
69	}
70
71	/*
72	* Verify that guest ring-0 is the one making the hypercall.
73	*/
74	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
75	if (uCpl)
76	{
77	pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
78	return VINF_SUCCESS;
79	}
80
81	/*
82	* Do the work.
83	*/
84	switch (uHyperOp)
85	{
86	case KVM_HYPERCALL_OP_KICK_CPU:
87	{
88	PVM pVM = pVCpu->CTX_SUFF(pVM);
89	if (uHyperArg1 < pVM->cCpus)
90	{
91	PVMCPU pVCpuTarget = &pVM->aCpus[uHyperArg1]; /** ASSUMES pVCpu index == ApicId of the VCPU. */
92	VMCPU_FF_SET(pVCpuTarget, VMCPU_FF_UNHALT);
93	#ifdef IN_RING0
94	/*
95	* We might be here with preemption disabled or enabled (i.e. depending on thread-context hooks
96	* being used), so don't try obtaining the GVMMR0 used lock here. See @bugref{7270#c148}.
97	*/
98	GVMMR0SchedWakeUpEx(pVM, pVCpuTarget->idCpu, false /* fTakeUsedLock */);
99	#elif defined(IN_RING3)
100	int rc2 = SUPR3CallVMMR0(pVM->pVMR0, pVCpuTarget->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL);
101	AssertRC(rc2);
102	#elif defined(IN_RC)
103	/* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
104	Assert(pVM->cCpus == 1);
105	#endif
106	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
107	}
108	break;
109	}
110
111	case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
112	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
113	break;
114
115	default:
116	break;
117	}
118
119	/*
120	* Place the result in rax/eax.
121	*/
122	pCtx->rax = uHyperRet & uAndMask;
123	return VINF_SUCCESS;
124	}
125
126
127	/**
128	* Returns whether the guest has configured and enabled the use of KVM's
129	* hypercall interface.
130	*
131	* @returns true if hypercalls are enabled, false otherwise.
132	* @param pVCpu Pointer to the VMCPU.
133	*/
134	VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
135	{
136	/* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
137	that guests can control, i.e. hypercalls are always enabled. */
138	return true;
139	}
140
141
142	/**
143	* Returns whether the guest has configured and enabled the use of KVM's
144	* paravirtualized TSC.
145	*
146	* @returns true if paravirt. TSC is enabled, false otherwise.
147	* @param pVM Pointer to the VM.
148	*/
149	VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM)
150	{
151	uint32_t cCpus = pVM->cCpus;
152	for (uint32_t i = 0; i < cCpus; i++)
153	{
154	PVMCPU pVCpu = &pVM->aCpus[i];
155	PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
156	if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
157	return true;
158	}
159	return false;
160	}
161
162
163	/**
164	* MSR read handler for KVM.
165	*
166	* @returns Strict VBox status code like CPUMQueryGuestMsr().
167	* @retval VINF_CPUM_R3_MSR_READ
168	* @retval VERR_CPUM_RAISE_GP_0
169	*
170	* @param pVCpu Pointer to the VMCPU.
171	* @param idMsr The MSR being read.
172	* @param pRange The range this MSR belongs to.
173	* @param puValue Where to store the MSR value read.
174	*/
175	VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
176	{
177	NOREF(pRange);
178	PVM pVM = pVCpu->CTX_SUFF(pVM);
179	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
180	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
181
182	switch (idMsr)
183	{
184	case MSR_GIM_KVM_SYSTEM_TIME:
185	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
186	*puValue = pKvmCpu->u64SystemTimeMsr;
187	return VINF_SUCCESS;
188
189	case MSR_GIM_KVM_WALL_CLOCK:
190	case MSR_GIM_KVM_WALL_CLOCK_OLD:
191	*puValue = pKvm->u64WallClockMsr;
192	return VINF_SUCCESS;
193
194	default:
195	{
196	#ifdef IN_RING3
197	static uint32_t s_cTimes = 0;
198	if (s_cTimes++ < 20)
199	LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
200	#endif
201	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
202	break;
203	}
204	}
205
206	return VERR_CPUM_RAISE_GP_0;
207	}
208
209
210	/**
211	* MSR write handler for KVM.
212	*
213	* @returns Strict VBox status code like CPUMSetGuestMsr().
214	* @retval VINF_CPUM_R3_MSR_WRITE
215	* @retval VERR_CPUM_RAISE_GP_0
216	*
217	* @param pVCpu Pointer to the VMCPU.
218	* @param idMsr The MSR being written.
219	* @param pRange The range this MSR belongs to.
220	* @param uRawValue The raw value with the ignored bits not masked.
221	*/
222	VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
223	{
224	NOREF(pRange);
225	PVM pVM = pVCpu->CTX_SUFF(pVM);
226	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
227	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
228
229	switch (idMsr)
230	{
231	case MSR_GIM_KVM_SYSTEM_TIME:
232	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
233	{
234	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
235	#ifdef IN_RING0
236	gimR0KvmUpdateSystemTime(pVM, pVCpu);
237	return VINF_CPUM_R3_MSR_WRITE;
238	#elif defined(IN_RC)
239	Assert(pVM->cCpus == 1);
240	if (fEnable)
241	{
242	RTCCUINTREG fEFlags = ASMIntDisableFlags();
243	pKvmCpu->uTsc = TMCpuTickGetNoCheck(pVCpu) \| UINT64_C(1);
244	pKvmCpu->uVirtNanoTS = TMVirtualGetNoCheck(pVM) \| UINT64_C(1);
245	ASMSetFlags(fEFlags);
246	}
247	return VINF_CPUM_R3_MSR_WRITE;
248	#else /* IN_RING3 */
249	if (!fEnable)
250	{
251	gimR3KvmDisableSystemTime(pVM);
252	pKvmCpu->u64SystemTimeMsr = uRawValue;
253	return VINF_SUCCESS;
254	}
255
256	/* Is the system-time struct. already enabled? If so, get flags that need preserving. */
257	uint8_t fFlags = 0;
258	GIMKVMSYSTEMTIME SystemTime;
259	RT_ZERO(SystemTime);
260	if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
261	&& MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
262	{
263	int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
264	if (RT_SUCCESS(rc2))
265	pKvmCpu->fSystemTimeFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
266	}
267
268	/* Enable and populate the system-time struct. */
269	pKvmCpu->u64SystemTimeMsr = uRawValue;
270	pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
271	pKvmCpu->u32SystemTimeVersion += 2;
272	int rc = gimR3KvmEnableSystemTime(pVM, pVCpu);
273	if (RT_FAILURE(rc))
274	{
275	pKvmCpu->u64SystemTimeMsr = 0;
276	return VERR_CPUM_RAISE_GP_0;
277	}
278	return VINF_SUCCESS;
279	#endif
280	}
281
282	case MSR_GIM_KVM_WALL_CLOCK:
283	case MSR_GIM_KVM_WALL_CLOCK_OLD:
284	{
285	#ifndef IN_RING3
286	return VINF_CPUM_R3_MSR_WRITE;
287	#else
288	/* Enable the wall-clock struct. */
289	RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
290	if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
291	{
292	int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
293	if (RT_SUCCESS(rc))
294	{
295	pKvm->u64WallClockMsr = uRawValue;
296	return VINF_SUCCESS;
297	}
298	}
299	return VERR_CPUM_RAISE_GP_0;
300	#endif /* IN_RING3 */
301	}
302
303	default:
304	{
305	#ifdef IN_RING3
306	static uint32_t s_cTimes = 0;
307	if (s_cTimes++ < 20)
308	LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
309	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
310	#endif
311	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
312	break;
313	}
314	}
315
316	return VERR_CPUM_RAISE_GP_0;
317	}
318
319
320	/**
321	* Whether we need to trap #UD exceptions in the guest.
322	*
323	* On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
324	* the Intel VMCALL instruction to make hypercalls and we need to trap and
325	* optionally patch them to the AMD-V VMMCALL instruction and handle the
326	* hypercall.
327	*
328	* I guess this was done so that guest teleporation between an AMD and an Intel
329	* machine would working without any changes at the time of teleporation.
330	* However, this also means we -always- need to intercept #UD exceptions on one
331	* of the two CPU models (Intel or AMD). Hyper-V solves this problem more
332	* elegantly by letting the hypervisor supply an opaque hypercall page.
333	*
334	* For raw-mode VMs, this function will always return true. See gimR3KvmInit().
335	*
336	* @param pVCpu Pointer to the VMCPU.
337	*/
338	VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu)
339	{
340	PVM pVM = pVCpu->CTX_SUFF(pVM);
341	return pVM->gim.s.u.Kvm.fTrapXcptUD;
342	}
343
344
345	/**
346	* Exception handler for #UD.
347	*
348	* @param pVCpu Pointer to the VMCPU.
349	* @param pCtx Pointer to the guest-CPU context.
350	* @param pDis Pointer to the disassembled instruction state at RIP.
351	* Optional, can be NULL.
352	*/
353	VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
354	{
355	/*
356	* If we didn't ask for #UD to be trapped, bail.
357	*/
358	PVM pVM = pVCpu->CTX_SUFF(pVM);
359	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
360	if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
361	return VERR_GIM_OPERATION_FAILED;
362
363	/*
364	* Make sure guest ring-0 is the one making the hypercall.
365	*/
366	if (CPUMGetGuestCPL(pVCpu))
367	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
368
369	int rc = VINF_SUCCESS;
370	if (!pDis)
371	{
372	/*
373	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
374	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
375	*/
376	DISCPUSTATE Dis;
377	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
378	pDis = &Dis;
379	}
380
381	if (RT_SUCCESS(rc))
382	{
383	/*
384	* Patch the instruction to so we don't have to spend time disassembling it each time.
385	* Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
386	*/
387	if ( pDis->pCurInstr->uOpcode == OP_VMCALL
388	\|\| pDis->pCurInstr->uOpcode == OP_VMMCALL)
389	{
390	if ( pDis->pCurInstr->uOpcode != pKvm->uOpCodeNative
391	&& HMIsEnabled(pVM))
392	{
393	uint8_t abHypercall[3];
394	size_t cbWritten = 0;
395	rc = VMMPatchHypercall(pVM, &abHypercall, sizeof(abHypercall), &cbWritten);
396	AssertRC(rc);
397	Assert(sizeof(abHypercall) == pDis->cbInstr);
398	Assert(sizeof(abHypercall) == cbWritten);
399
400	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, &abHypercall, sizeof(abHypercall));
401	}
402
403	/*
404	* Perform the hypercall and update RIP.
405	*
406	* For HM, we can simply resume guest execution without performing the hypercall now and
407	* do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
408	*
409	* For raw-mode we need to do this now anyway. So we do it here regardless with an added
410	* advantage is that it saves one world-switch for the HM case.
411	*/
412	if (RT_SUCCESS(rc))
413	{
414	int rc2 = gimKvmHypercall(pVCpu, pCtx);
415	AssertRC(rc2);
416	pCtx->rip += pDis->cbInstr;
417	}
418	return rc;
419	}
420	}
421
422	return VERR_GIM_OPERATION_FAILED;
423	}
424

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 57350

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