GIMAllKvm.cpp@ 57560

Last change on this file since 57560 was 57560, checked in by vboxsync, 9 years ago
VMM/GIM: unused vars.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 14.0 KB

Line
1	/* $Id: GIMAllKvm.cpp 57560 2015-08-27 12:52:36Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, KVM, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include "GIMKvmInternal.h"
24	#include "GIMInternal.h"
25
26	#include <VBox/err.h>
27	#include <VBox/dis.h>
28	#include <VBox/vmm/hm.h>
29	#include <VBox/vmm/em.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/pgm.h>
33	#include <VBox/vmm/pdmdev.h>
34	#include <VBox/vmm/pdmapi.h>
35	#include <VBox/sup.h>
36
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/time.h>
39
40
41	/**
42	* Handles the KVM hypercall.
43	*
44	* @returns VBox status code.
45	* @param pVCpu Pointer to the VMCPU.
46	* @param pCtx Pointer to the guest-CPU context.
47	*/
48	VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
49	{
50	/*
51	* Get the hypercall operation and arguments.
52	*/
53	bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
54	uint64_t uHyperOp = pCtx->rax;
55	uint64_t uHyperArg0 = pCtx->rbx;
56	uint64_t uHyperArg1 = pCtx->rcx;
57	uint64_t uHyperArg2 = pCtx->rdi;
58	uint64_t uHyperArg3 = pCtx->rsi;
59	uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
60	uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
61	if (!fIs64BitMode)
62	{
63	uAndMask = UINT64_C(0xffffffff);
64	uHyperOp &= UINT64_C(0xffffffff);
65	uHyperArg0 &= UINT64_C(0xffffffff);
66	uHyperArg1 &= UINT64_C(0xffffffff);
67	uHyperArg2 &= UINT64_C(0xffffffff);
68	uHyperArg3 &= UINT64_C(0xffffffff);
69	uHyperRet &= UINT64_C(0xffffffff);
70	}
71
72	/*
73	* Verify that guest ring-0 is the one making the hypercall.
74	*/
75	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
76	if (uCpl)
77	{
78	pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
79	return VINF_SUCCESS;
80	}
81
82	/*
83	* Do the work.
84	*/
85	switch (uHyperOp)
86	{
87	case KVM_HYPERCALL_OP_KICK_CPU:
88	{
89	PVM pVM = pVCpu->CTX_SUFF(pVM);
90	if (uHyperArg1 < pVM->cCpus)
91	{
92	PVMCPU pVCpuTarget = &pVM->aCpus[uHyperArg1]; /** ASSUMES pVCpu index == ApicId of the VCPU. */
93	VMCPU_FF_SET(pVCpuTarget, VMCPU_FF_UNHALT);
94	#ifdef IN_RING0
95	/*
96	* We might be here with preemption disabled or enabled (i.e. depending on thread-context hooks
97	* being used), so don't try obtaining the GVMMR0 used lock here. See @bugref{7270#c148}.
98	*/
99	GVMMR0SchedWakeUpEx(pVM, pVCpuTarget->idCpu, false /* fTakeUsedLock */);
100	#elif defined(IN_RING3)
101	int rc2 = SUPR3CallVMMR0(pVM->pVMR0, pVCpuTarget->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL);
102	AssertRC(rc2);
103	#elif defined(IN_RC)
104	/* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
105	Assert(pVM->cCpus == 1);
106	#endif
107	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
108	}
109	break;
110	}
111
112	case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
113	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
114	break;
115
116	default:
117	break;
118	}
119
120	/*
121	* Place the result in rax/eax.
122	*/
123	pCtx->rax = uHyperRet & uAndMask;
124	return VINF_SUCCESS;
125	}
126
127
128	/**
129	* Returns whether the guest has configured and enabled the use of KVM's
130	* hypercall interface.
131	*
132	* @returns true if hypercalls are enabled, false otherwise.
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
136	{
137	/* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
138	that guests can control, i.e. hypercalls are always enabled. */
139	return true;
140	}
141
142
143	/**
144	* Returns whether the guest has configured and enabled the use of KVM's
145	* paravirtualized TSC.
146	*
147	* @returns true if paravirt. TSC is enabled, false otherwise.
148	* @param pVM Pointer to the VM.
149	*/
150	VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM)
151	{
152	uint32_t cCpus = pVM->cCpus;
153	for (uint32_t i = 0; i < cCpus; i++)
154	{
155	PVMCPU pVCpu = &pVM->aCpus[i];
156	PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
157	if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
158	return true;
159	}
160	return false;
161	}
162
163
164	/**
165	* MSR read handler for KVM.
166	*
167	* @returns Strict VBox status code like CPUMQueryGuestMsr().
168	* @retval VINF_CPUM_R3_MSR_READ
169	* @retval VERR_CPUM_RAISE_GP_0
170	*
171	* @param pVCpu Pointer to the VMCPU.
172	* @param idMsr The MSR being read.
173	* @param pRange The range this MSR belongs to.
174	* @param puValue Where to store the MSR value read.
175	*/
176	VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
177	{
178	NOREF(pRange);
179	PVM pVM = pVCpu->CTX_SUFF(pVM);
180	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
181	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
182
183	switch (idMsr)
184	{
185	case MSR_GIM_KVM_SYSTEM_TIME:
186	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
187	*puValue = pKvmCpu->u64SystemTimeMsr;
188	return VINF_SUCCESS;
189
190	case MSR_GIM_KVM_WALL_CLOCK:
191	case MSR_GIM_KVM_WALL_CLOCK_OLD:
192	*puValue = pKvm->u64WallClockMsr;
193	return VINF_SUCCESS;
194
195	default:
196	{
197	#ifdef IN_RING3
198	static uint32_t s_cTimes = 0;
199	if (s_cTimes++ < 20)
200	LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
201	#endif
202	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
203	break;
204	}
205	}
206
207	return VERR_CPUM_RAISE_GP_0;
208	}
209
210
211	/**
212	* MSR write handler for KVM.
213	*
214	* @returns Strict VBox status code like CPUMSetGuestMsr().
215	* @retval VINF_CPUM_R3_MSR_WRITE
216	* @retval VERR_CPUM_RAISE_GP_0
217	*
218	* @param pVCpu Pointer to the VMCPU.
219	* @param idMsr The MSR being written.
220	* @param pRange The range this MSR belongs to.
221	* @param uRawValue The raw value with the ignored bits not masked.
222	*/
223	VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
224	{
225	NOREF(pRange);
226	PVM pVM = pVCpu->CTX_SUFF(pVM);
227	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
228
229	switch (idMsr)
230	{
231	case MSR_GIM_KVM_SYSTEM_TIME:
232	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
233	{
234	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
235	#ifdef IN_RING0
236	NOREF(fEnable); NOREF(pKvmCpu);
237	gimR0KvmUpdateSystemTime(pVM, pVCpu);
238	return VINF_CPUM_R3_MSR_WRITE;
239	#elif defined(IN_RC)
240	Assert(pVM->cCpus == 1);
241	if (fEnable)
242	{
243	RTCCUINTREG fEFlags = ASMIntDisableFlags();
244	pKvmCpu->uTsc = TMCpuTickGetNoCheck(pVCpu) \| UINT64_C(1);
245	pKvmCpu->uVirtNanoTS = TMVirtualGetNoCheck(pVM) \| UINT64_C(1);
246	ASMSetFlags(fEFlags);
247	}
248	return VINF_CPUM_R3_MSR_WRITE;
249	#else /* IN_RING3 */
250	if (!fEnable)
251	{
252	gimR3KvmDisableSystemTime(pVM);
253	pKvmCpu->u64SystemTimeMsr = uRawValue;
254	return VINF_SUCCESS;
255	}
256
257	/* Is the system-time struct. already enabled? If so, get flags that need preserving. */
258	uint8_t fFlags = 0;
259	GIMKVMSYSTEMTIME SystemTime;
260	RT_ZERO(SystemTime);
261	if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
262	&& MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
263	{
264	int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
265	if (RT_SUCCESS(rc2))
266	pKvmCpu->fSystemTimeFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
267	}
268
269	/* Enable and populate the system-time struct. */
270	pKvmCpu->u64SystemTimeMsr = uRawValue;
271	pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
272	pKvmCpu->u32SystemTimeVersion += 2;
273	int rc = gimR3KvmEnableSystemTime(pVM, pVCpu);
274	if (RT_FAILURE(rc))
275	{
276	pKvmCpu->u64SystemTimeMsr = 0;
277	return VERR_CPUM_RAISE_GP_0;
278	}
279	return VINF_SUCCESS;
280	#endif
281	}
282
283	case MSR_GIM_KVM_WALL_CLOCK:
284	case MSR_GIM_KVM_WALL_CLOCK_OLD:
285	{
286	#ifndef IN_RING3
287	return VINF_CPUM_R3_MSR_WRITE;
288	#else
289	/* Enable the wall-clock struct. */
290	RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
291	if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
292	{
293	int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
294	if (RT_SUCCESS(rc))
295	{
296	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
297	pKvm->u64WallClockMsr = uRawValue;
298	return VINF_SUCCESS;
299	}
300	}
301	return VERR_CPUM_RAISE_GP_0;
302	#endif /* IN_RING3 */
303	}
304
305	default:
306	{
307	#ifdef IN_RING3
308	static uint32_t s_cTimes = 0;
309	if (s_cTimes++ < 20)
310	LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
311	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
312	#endif
313	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
314	break;
315	}
316	}
317
318	return VERR_CPUM_RAISE_GP_0;
319	}
320
321
322	/**
323	* Whether we need to trap #UD exceptions in the guest.
324	*
325	* On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
326	* the Intel VMCALL instruction to make hypercalls and we need to trap and
327	* optionally patch them to the AMD-V VMMCALL instruction and handle the
328	* hypercall.
329	*
330	* I guess this was done so that guest teleporation between an AMD and an Intel
331	* machine would working without any changes at the time of teleporation.
332	* However, this also means we -always- need to intercept #UD exceptions on one
333	* of the two CPU models (Intel or AMD). Hyper-V solves this problem more
334	* elegantly by letting the hypervisor supply an opaque hypercall page.
335	*
336	* For raw-mode VMs, this function will always return true. See gimR3KvmInit().
337	*
338	* @param pVCpu Pointer to the VMCPU.
339	*/
340	VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu)
341	{
342	PVM pVM = pVCpu->CTX_SUFF(pVM);
343	return pVM->gim.s.u.Kvm.fTrapXcptUD;
344	}
345
346
347	/**
348	* Exception handler for #UD.
349	*
350	* @param pVCpu Pointer to the VMCPU.
351	* @param pCtx Pointer to the guest-CPU context.
352	* @param pDis Pointer to the disassembled instruction state at RIP.
353	* Optional, can be NULL.
354	*/
355	VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
356	{
357	/*
358	* If we didn't ask for #UD to be trapped, bail.
359	*/
360	PVM pVM = pVCpu->CTX_SUFF(pVM);
361	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
362	if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
363	return VERR_GIM_OPERATION_FAILED;
364
365	/*
366	* Make sure guest ring-0 is the one making the hypercall.
367	*/
368	if (CPUMGetGuestCPL(pVCpu))
369	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
370
371	int rc = VINF_SUCCESS;
372	if (!pDis)
373	{
374	/*
375	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
376	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
377	*/
378	DISCPUSTATE Dis;
379	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
380	pDis = &Dis;
381	}
382
383	if (RT_SUCCESS(rc))
384	{
385	/*
386	* Patch the instruction to so we don't have to spend time disassembling it each time.
387	* Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
388	*/
389	if ( pDis->pCurInstr->uOpcode == OP_VMCALL
390	\|\| pDis->pCurInstr->uOpcode == OP_VMMCALL)
391	{
392	if ( pDis->pCurInstr->uOpcode != pKvm->uOpCodeNative
393	&& HMIsEnabled(pVM))
394	{
395	uint8_t abHypercall[3];
396	size_t cbWritten = 0;
397	rc = VMMPatchHypercall(pVM, &abHypercall, sizeof(abHypercall), &cbWritten);
398	AssertRC(rc);
399	Assert(sizeof(abHypercall) == pDis->cbInstr);
400	Assert(sizeof(abHypercall) == cbWritten);
401
402	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, &abHypercall, sizeof(abHypercall));
403	}
404
405	/*
406	* Perform the hypercall and update RIP.
407	*
408	* For HM, we can simply resume guest execution without performing the hypercall now and
409	* do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
410	*
411	* For raw-mode we need to do this now anyway. So we do it here regardless with an added
412	* advantage is that it saves one world-switch for the HM case.
413	*/
414	if (RT_SUCCESS(rc))
415	{
416	int rc2 = gimKvmHypercall(pVCpu, pCtx);
417	AssertRC(rc2);
418	pCtx->rip += pDis->cbInstr;
419	}
420	return rc;
421	}
422	}
423
424	return VERR_GIM_OPERATION_FAILED;
425	}
426

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 57560

Download in other formats: