GIMAllKvm.cpp@ 57952

Last change on this file since 57952 was 57851, checked in by vboxsync, 9 years ago
VMM: unused parameter warning fixes.
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1	/* $Id: GIMAllKvm.cpp 57851 2015-09-22 13:10:34Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, KVM, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include "GIMKvmInternal.h"
24	#include "GIMInternal.h"
25
26	#include <VBox/err.h>
27	#include <VBox/dis.h>
28	#include <VBox/vmm/hm.h>
29	#include <VBox/vmm/em.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/pgm.h>
33	#include <VBox/vmm/pdmdev.h>
34	#include <VBox/vmm/pdmapi.h>
35	#include <VBox/sup.h>
36
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/time.h>
39
40
41	/**
42	* Handles the KVM hypercall.
43	*
44	* @returns VBox status code.
45	* @param pVCpu Pointer to the VMCPU.
46	* @param pCtx Pointer to the guest-CPU context.
47	*/
48	VMM_INT_DECL(int) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
49	{
50	/*
51	* Get the hypercall operation and arguments.
52	*/
53	bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
54	uint64_t uHyperOp = pCtx->rax;
55	uint64_t uHyperArg0 = pCtx->rbx;
56	uint64_t uHyperArg1 = pCtx->rcx;
57	uint64_t uHyperArg2 = pCtx->rdi;
58	uint64_t uHyperArg3 = pCtx->rsi;
59	uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
60	uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
61	if (!fIs64BitMode)
62	{
63	uAndMask = UINT64_C(0xffffffff);
64	uHyperOp &= UINT64_C(0xffffffff);
65	uHyperArg0 &= UINT64_C(0xffffffff);
66	uHyperArg1 &= UINT64_C(0xffffffff);
67	uHyperArg2 &= UINT64_C(0xffffffff);
68	uHyperArg3 &= UINT64_C(0xffffffff);
69	uHyperRet &= UINT64_C(0xffffffff);
70	}
71
72	/*
73	* Verify that guest ring-0 is the one making the hypercall.
74	*/
75	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
76	if (uCpl)
77	{
78	pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
79	return VINF_SUCCESS;
80	}
81
82	/*
83	* Do the work.
84	*/
85	switch (uHyperOp)
86	{
87	case KVM_HYPERCALL_OP_KICK_CPU:
88	{
89	PVM pVM = pVCpu->CTX_SUFF(pVM);
90	if (uHyperArg1 < pVM->cCpus)
91	{
92	PVMCPU pVCpuTarget = &pVM->aCpus[uHyperArg1]; /** ASSUMES pVCpu index == ApicId of the VCPU. */
93	VMCPU_FF_SET(pVCpuTarget, VMCPU_FF_UNHALT);
94	#ifdef IN_RING0
95	/*
96	* We might be here with preemption disabled or enabled (i.e. depending on thread-context hooks
97	* being used), so don't try obtaining the GVMMR0 used lock here. See @bugref{7270#c148}.
98	*/
99	GVMMR0SchedWakeUpEx(pVM, pVCpuTarget->idCpu, false /* fTakeUsedLock */);
100	#elif defined(IN_RING3)
101	int rc2 = SUPR3CallVMMR0(pVM->pVMR0, pVCpuTarget->idCpu, VMMR0_DO_GVMM_SCHED_WAKE_UP, NULL);
102	AssertRC(rc2);
103	#elif defined(IN_RC)
104	/* Nothing to do for raw-mode, shouldn't really be used by raw-mode guests anyway. */
105	Assert(pVM->cCpus == 1);
106	#endif
107	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
108	}
109	break;
110	}
111
112	case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
113	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
114	break;
115
116	default:
117	break;
118	}
119
120	/*
121	* Place the result in rax/eax.
122	*/
123	pCtx->rax = uHyperRet & uAndMask;
124	return VINF_SUCCESS;
125	}
126
127
128	/**
129	* Returns whether the guest has configured and enabled the use of KVM's
130	* hypercall interface.
131	*
132	* @returns true if hypercalls are enabled, false otherwise.
133	* @param pVCpu Pointer to the VMCPU.
134	*/
135	VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
136	{
137	NOREF(pVCpu);
138	/* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
139	that guests can control, i.e. hypercalls are always enabled. */
140	return true;
141	}
142
143
144	/**
145	* Returns whether the guest has configured and enabled the use of KVM's
146	* paravirtualized TSC.
147	*
148	* @returns true if paravirt. TSC is enabled, false otherwise.
149	* @param pVM Pointer to the VM.
150	*/
151	VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM)
152	{
153	uint32_t cCpus = pVM->cCpus;
154	for (uint32_t i = 0; i < cCpus; i++)
155	{
156	PVMCPU pVCpu = &pVM->aCpus[i];
157	PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
158	if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
159	return true;
160	}
161	return false;
162	}
163
164
165	/**
166	* MSR read handler for KVM.
167	*
168	* @returns Strict VBox status code like CPUMQueryGuestMsr().
169	* @retval VINF_CPUM_R3_MSR_READ
170	* @retval VERR_CPUM_RAISE_GP_0
171	*
172	* @param pVCpu Pointer to the VMCPU.
173	* @param idMsr The MSR being read.
174	* @param pRange The range this MSR belongs to.
175	* @param puValue Where to store the MSR value read.
176	*/
177	VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
178	{
179	NOREF(pRange);
180	PVM pVM = pVCpu->CTX_SUFF(pVM);
181	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
182	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
183
184	switch (idMsr)
185	{
186	case MSR_GIM_KVM_SYSTEM_TIME:
187	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
188	*puValue = pKvmCpu->u64SystemTimeMsr;
189	return VINF_SUCCESS;
190
191	case MSR_GIM_KVM_WALL_CLOCK:
192	case MSR_GIM_KVM_WALL_CLOCK_OLD:
193	*puValue = pKvm->u64WallClockMsr;
194	return VINF_SUCCESS;
195
196	default:
197	{
198	#ifdef IN_RING3
199	static uint32_t s_cTimes = 0;
200	if (s_cTimes++ < 20)
201	LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
202	#endif
203	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
204	break;
205	}
206	}
207
208	return VERR_CPUM_RAISE_GP_0;
209	}
210
211
212	/**
213	* MSR write handler for KVM.
214	*
215	* @returns Strict VBox status code like CPUMSetGuestMsr().
216	* @retval VINF_CPUM_R3_MSR_WRITE
217	* @retval VERR_CPUM_RAISE_GP_0
218	*
219	* @param pVCpu Pointer to the VMCPU.
220	* @param idMsr The MSR being written.
221	* @param pRange The range this MSR belongs to.
222	* @param uRawValue The raw value with the ignored bits not masked.
223	*/
224	VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
225	{
226	NOREF(pRange);
227	PVM pVM = pVCpu->CTX_SUFF(pVM);
228	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
229
230	switch (idMsr)
231	{
232	case MSR_GIM_KVM_SYSTEM_TIME:
233	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
234	{
235	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
236	#ifdef IN_RING0
237	NOREF(fEnable); NOREF(pKvmCpu);
238	gimR0KvmUpdateSystemTime(pVM, pVCpu);
239	return VINF_CPUM_R3_MSR_WRITE;
240	#elif defined(IN_RC)
241	Assert(pVM->cCpus == 1);
242	if (fEnable)
243	{
244	RTCCUINTREG fEFlags = ASMIntDisableFlags();
245	pKvmCpu->uTsc = TMCpuTickGetNoCheck(pVCpu) \| UINT64_C(1);
246	pKvmCpu->uVirtNanoTS = TMVirtualGetNoCheck(pVM) \| UINT64_C(1);
247	ASMSetFlags(fEFlags);
248	}
249	return VINF_CPUM_R3_MSR_WRITE;
250	#else /* IN_RING3 */
251	if (!fEnable)
252	{
253	gimR3KvmDisableSystemTime(pVM);
254	pKvmCpu->u64SystemTimeMsr = uRawValue;
255	return VINF_SUCCESS;
256	}
257
258	/* Is the system-time struct. already enabled? If so, get flags that need preserving. */
259	uint8_t fFlags = 0;
260	GIMKVMSYSTEMTIME SystemTime;
261	RT_ZERO(SystemTime);
262	if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
263	&& MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
264	{
265	int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
266	if (RT_SUCCESS(rc2))
267	pKvmCpu->fSystemTimeFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
268	}
269
270	/* Enable and populate the system-time struct. */
271	pKvmCpu->u64SystemTimeMsr = uRawValue;
272	pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
273	pKvmCpu->u32SystemTimeVersion += 2;
274	int rc = gimR3KvmEnableSystemTime(pVM, pVCpu);
275	if (RT_FAILURE(rc))
276	{
277	pKvmCpu->u64SystemTimeMsr = 0;
278	return VERR_CPUM_RAISE_GP_0;
279	}
280	return VINF_SUCCESS;
281	#endif
282	}
283
284	case MSR_GIM_KVM_WALL_CLOCK:
285	case MSR_GIM_KVM_WALL_CLOCK_OLD:
286	{
287	#ifndef IN_RING3
288	return VINF_CPUM_R3_MSR_WRITE;
289	#else
290	/* Enable the wall-clock struct. */
291	RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
292	if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
293	{
294	int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
295	if (RT_SUCCESS(rc))
296	{
297	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
298	pKvm->u64WallClockMsr = uRawValue;
299	return VINF_SUCCESS;
300	}
301	}
302	return VERR_CPUM_RAISE_GP_0;
303	#endif /* IN_RING3 */
304	}
305
306	default:
307	{
308	#ifdef IN_RING3
309	static uint32_t s_cTimes = 0;
310	if (s_cTimes++ < 20)
311	LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
312	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
313	#endif
314	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
315	break;
316	}
317	}
318
319	return VERR_CPUM_RAISE_GP_0;
320	}
321
322
323	/**
324	* Whether we need to trap #UD exceptions in the guest.
325	*
326	* On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
327	* the Intel VMCALL instruction to make hypercalls and we need to trap and
328	* optionally patch them to the AMD-V VMMCALL instruction and handle the
329	* hypercall.
330	*
331	* I guess this was done so that guest teleporation between an AMD and an Intel
332	* machine would working without any changes at the time of teleporation.
333	* However, this also means we -always- need to intercept #UD exceptions on one
334	* of the two CPU models (Intel or AMD). Hyper-V solves this problem more
335	* elegantly by letting the hypervisor supply an opaque hypercall page.
336	*
337	* For raw-mode VMs, this function will always return true. See gimR3KvmInit().
338	*
339	* @param pVCpu Pointer to the VMCPU.
340	*/
341	VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu)
342	{
343	PVM pVM = pVCpu->CTX_SUFF(pVM);
344	return pVM->gim.s.u.Kvm.fTrapXcptUD;
345	}
346
347
348	/**
349	* Exception handler for #UD.
350	*
351	* @param pVCpu Pointer to the VMCPU.
352	* @param pCtx Pointer to the guest-CPU context.
353	* @param pDis Pointer to the disassembled instruction state at RIP.
354	* Optional, can be NULL.
355	*/
356	VMM_INT_DECL(int) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis)
357	{
358	/*
359	* If we didn't ask for #UD to be trapped, bail.
360	*/
361	PVM pVM = pVCpu->CTX_SUFF(pVM);
362	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
363	if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
364	return VERR_GIM_OPERATION_FAILED;
365
366	/*
367	* Make sure guest ring-0 is the one making the hypercall.
368	*/
369	if (CPUMGetGuestCPL(pVCpu))
370	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
371
372	int rc = VINF_SUCCESS;
373	if (!pDis)
374	{
375	/*
376	* Disassemble the instruction at RIP to figure out if it's the Intel VMCALL instruction
377	* or the AMD VMMCALL instruction and if so, handle it as a hypercall.
378	*/
379	DISCPUSTATE Dis;
380	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL /* pcbInstr */);
381	pDis = &Dis;
382	}
383
384	if (RT_SUCCESS(rc))
385	{
386	/*
387	* Patch the instruction to so we don't have to spend time disassembling it each time.
388	* Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
389	*/
390	if ( pDis->pCurInstr->uOpcode == OP_VMCALL
391	\|\| pDis->pCurInstr->uOpcode == OP_VMMCALL)
392	{
393	if ( pDis->pCurInstr->uOpcode != pKvm->uOpCodeNative
394	&& HMIsEnabled(pVM))
395	{
396	uint8_t abHypercall[3];
397	size_t cbWritten = 0;
398	rc = VMMPatchHypercall(pVM, &abHypercall, sizeof(abHypercall), &cbWritten);
399	AssertRC(rc);
400	Assert(sizeof(abHypercall) == pDis->cbInstr);
401	Assert(sizeof(abHypercall) == cbWritten);
402
403	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, &abHypercall, sizeof(abHypercall));
404	}
405
406	/*
407	* Perform the hypercall and update RIP.
408	*
409	* For HM, we can simply resume guest execution without performing the hypercall now and
410	* do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
411	*
412	* For raw-mode we need to do this now anyway. So we do it here regardless with an added
413	* advantage is that it saves one world-switch for the HM case.
414	*/
415	if (RT_SUCCESS(rc))
416	{
417	int rc2 = gimKvmHypercall(pVCpu, pCtx);
418	AssertRC(rc2);
419	pCtx->rip += pDis->cbInstr;
420	}
421	return rc;
422	}
423	}
424
425	return VERR_GIM_OPERATION_FAILED;
426	}
427

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 57952

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