VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 79059

Last change on this file since 79059 was 76553, checked in by vboxsync, 6 years ago

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1/* $Id: GIMAllKvm.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * GIM - Guest Interface Manager, KVM, All Contexts.
4 */
5
6/*
7 * Copyright (C) 2015-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_GIM
23#include <VBox/vmm/gim.h>
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/em.h>
26#include <VBox/vmm/tm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmapi.h>
30#include "GIMKvmInternal.h"
31#include "GIMInternal.h"
32#include <VBox/vmm/vm.h>
33
34#include <VBox/dis.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37
38#include <iprt/asm-amd64-x86.h>
39#include <iprt/time.h>
40
41
42/**
43 * Handles the KVM hypercall.
44 *
45 * @returns Strict VBox status code.
46 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
47 * failed).
48 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
49 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
50 *
51 * @param pVCpu The cross context virtual CPU structure.
52 * @param pCtx Pointer to the guest-CPU context.
53 *
54 * @thread EMT(pVCpu).
55 */
56VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
57{
58 VMCPU_ASSERT_EMT(pVCpu);
59
60 PVM pVM = pVCpu->CTX_SUFF(pVM);
61 STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
62
63 /*
64 * Get the hypercall operation and arguments.
65 */
66 bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
67 uint64_t uHyperOp = pCtx->rax;
68 uint64_t uHyperArg0 = pCtx->rbx;
69 uint64_t uHyperArg1 = pCtx->rcx;
70 uint64_t uHyperArg2 = pCtx->rdi;
71 uint64_t uHyperArg3 = pCtx->rsi;
72 uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
73 uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
74 if (!fIs64BitMode)
75 {
76 uAndMask = UINT64_C(0xffffffff);
77 uHyperOp &= UINT64_C(0xffffffff);
78 uHyperArg0 &= UINT64_C(0xffffffff);
79 uHyperArg1 &= UINT64_C(0xffffffff);
80 uHyperArg2 &= UINT64_C(0xffffffff);
81 uHyperArg3 &= UINT64_C(0xffffffff);
82 uHyperRet &= UINT64_C(0xffffffff);
83 }
84
85 /*
86 * Verify that guest ring-0 is the one making the hypercall.
87 */
88 uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
89 if (RT_UNLIKELY(uCpl))
90 {
91 pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
92 return VERR_GIM_HYPERCALL_ACCESS_DENIED;
93 }
94
95 /*
96 * Do the work.
97 */
98 int rc = VINF_SUCCESS;
99 switch (uHyperOp)
100 {
101 case KVM_HYPERCALL_OP_KICK_CPU:
102 {
103 if (uHyperArg1 < pVM->cCpus)
104 {
105 PVMCPU pVCpuDst = &pVM->aCpus[uHyperArg1]; /* ASSUMES pVCpu index == ApicId of the VCPU. */
106 EMUnhaltAndWakeUp(pVM, pVCpuDst);
107 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
108 }
109 else
110 {
111 /* Shouldn't ever happen! If it does, throw a guru, as otherwise it'll lead to deadlocks in the guest anyway! */
112 rc = VERR_GIM_HYPERCALL_FAILED;
113 }
114 break;
115 }
116
117 case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
118 uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
119 break;
120
121 default:
122 break;
123 }
124
125 /*
126 * Place the result in rax/eax.
127 */
128 pCtx->rax = uHyperRet & uAndMask;
129 return rc;
130}
131
132
133/**
134 * Returns whether the guest has configured and enabled the use of KVM's
135 * hypercall interface.
136 *
137 * @returns true if hypercalls are enabled, false otherwise.
138 * @param pVCpu The cross context virtual CPU structure.
139 */
140VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
141{
142 NOREF(pVCpu);
143 /* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
144 that guests can control, i.e. hypercalls are always enabled. */
145 return true;
146}
147
148
149/**
150 * Returns whether the guest has configured and enabled the use of KVM's
151 * paravirtualized TSC.
152 *
153 * @returns true if paravirt. TSC is enabled, false otherwise.
154 * @param pVM The cross context VM structure.
155 */
156VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVM pVM)
157{
158 uint32_t cCpus = pVM->cCpus;
159 for (uint32_t i = 0; i < cCpus; i++)
160 {
161 PVMCPU pVCpu = &pVM->aCpus[i];
162 PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
163 if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
164 return true;
165 }
166 return false;
167}
168
169
170/**
171 * MSR read handler for KVM.
172 *
173 * @returns Strict VBox status code like CPUMQueryGuestMsr().
174 * @retval VINF_CPUM_R3_MSR_READ
175 * @retval VERR_CPUM_RAISE_GP_0
176 *
177 * @param pVCpu The cross context virtual CPU structure.
178 * @param idMsr The MSR being read.
179 * @param pRange The range this MSR belongs to.
180 * @param puValue Where to store the MSR value read.
181 */
182VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183{
184 NOREF(pRange);
185 PVM pVM = pVCpu->CTX_SUFF(pVM);
186 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
187 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
188
189 switch (idMsr)
190 {
191 case MSR_GIM_KVM_SYSTEM_TIME:
192 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
193 *puValue = pKvmCpu->u64SystemTimeMsr;
194 return VINF_SUCCESS;
195
196 case MSR_GIM_KVM_WALL_CLOCK:
197 case MSR_GIM_KVM_WALL_CLOCK_OLD:
198 *puValue = pKvm->u64WallClockMsr;
199 return VINF_SUCCESS;
200
201 default:
202 {
203#ifdef IN_RING3
204 static uint32_t s_cTimes = 0;
205 if (s_cTimes++ < 20)
206 LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
207#endif
208 LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
209 break;
210 }
211 }
212
213 return VERR_CPUM_RAISE_GP_0;
214}
215
216
217/**
218 * MSR write handler for KVM.
219 *
220 * @returns Strict VBox status code like CPUMSetGuestMsr().
221 * @retval VINF_CPUM_R3_MSR_WRITE
222 * @retval VERR_CPUM_RAISE_GP_0
223 *
224 * @param pVCpu The cross context virtual CPU structure.
225 * @param idMsr The MSR being written.
226 * @param pRange The range this MSR belongs to.
227 * @param uRawValue The raw value with the ignored bits not masked.
228 */
229VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
230{
231 NOREF(pRange);
232 PVM pVM = pVCpu->CTX_SUFF(pVM);
233 PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
234
235 switch (idMsr)
236 {
237 case MSR_GIM_KVM_SYSTEM_TIME:
238 case MSR_GIM_KVM_SYSTEM_TIME_OLD:
239 {
240 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
241#ifdef IN_RING0
242 NOREF(fEnable); NOREF(pKvmCpu);
243 gimR0KvmUpdateSystemTime(pVM, pVCpu);
244 return VINF_CPUM_R3_MSR_WRITE;
245#elif defined(IN_RC)
246 Assert(pVM->cCpus == 1);
247 if (fEnable)
248 {
249 RTCCUINTREG fEFlags = ASMIntDisableFlags();
250 pKvmCpu->uTsc = TMCpuTickGetNoCheck(pVCpu) | UINT64_C(1);
251 pKvmCpu->uVirtNanoTS = TMVirtualGetNoCheck(pVM) | UINT64_C(1);
252 ASMSetFlags(fEFlags);
253 }
254 return VINF_CPUM_R3_MSR_WRITE;
255#else /* IN_RING3 */
256 if (!fEnable)
257 {
258 gimR3KvmDisableSystemTime(pVM);
259 pKvmCpu->u64SystemTimeMsr = uRawValue;
260 return VINF_SUCCESS;
261 }
262
263 /* Is the system-time struct. already enabled? If so, get flags that need preserving. */
264 GIMKVMSYSTEMTIME SystemTime;
265 RT_ZERO(SystemTime);
266 if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
267 && MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
268 {
269 int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
270 if (RT_SUCCESS(rc2))
271 pKvmCpu->fSystemTimeFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
272 }
273
274 /* We ASSUME that ring-0/raw-mode have updated these. */
275 /** @todo Get logically atomic NanoTS/TSC pairs in ring-3. */
276 Assert(pKvmCpu->uTsc);
277 Assert(pKvmCpu->uVirtNanoTS);
278
279 /* Enable and populate the system-time struct. */
280 pKvmCpu->u64SystemTimeMsr = uRawValue;
281 pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
282 pKvmCpu->u32SystemTimeVersion += 2;
283 int rc = gimR3KvmEnableSystemTime(pVM, pVCpu);
284 if (RT_FAILURE(rc))
285 {
286 pKvmCpu->u64SystemTimeMsr = 0;
287 /* We shouldn't throw a #GP(0) here for buggy guests (neither does KVM apparently), see @bugref{8627}. */
288 }
289 return VINF_SUCCESS;
290#endif
291 }
292
293 case MSR_GIM_KVM_WALL_CLOCK:
294 case MSR_GIM_KVM_WALL_CLOCK_OLD:
295 {
296#ifndef IN_RING3
297 return VINF_CPUM_R3_MSR_WRITE;
298#else
299 /* Enable the wall-clock struct. */
300 RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
301 if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
302 {
303 int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
304 if (RT_SUCCESS(rc))
305 {
306 PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
307 pKvm->u64WallClockMsr = uRawValue;
308 return VINF_SUCCESS;
309 }
310 }
311 return VERR_CPUM_RAISE_GP_0;
312#endif /* IN_RING3 */
313 }
314
315 default:
316 {
317#ifdef IN_RING3
318 static uint32_t s_cTimes = 0;
319 if (s_cTimes++ < 20)
320 LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
321 uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
322#endif
323 LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
324 break;
325 }
326 }
327
328 return VERR_CPUM_RAISE_GP_0;
329}
330
331
332/**
333 * Whether we need to trap \#UD exceptions in the guest.
334 *
335 * On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
336 * the Intel VMCALL instruction to make hypercalls and we need to trap and
337 * optionally patch them to the AMD-V VMMCALL instruction and handle the
338 * hypercall.
339 *
340 * I guess this was done so that guest teleporation between an AMD and an Intel
341 * machine would working without any changes at the time of teleporation.
342 * However, this also means we -always- need to intercept \#UD exceptions on one
343 * of the two CPU models (Intel or AMD). Hyper-V solves this problem more
344 * elegantly by letting the hypervisor supply an opaque hypercall page.
345 *
346 * For raw-mode VMs, this function will always return true. See gimR3KvmInit().
347 *
348 * @param pVCpu The cross context virtual CPU structure.
349 */
350VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVMCPU pVCpu)
351{
352 PVM pVM = pVCpu->CTX_SUFF(pVM);
353 return pVM->gim.s.u.Kvm.fTrapXcptUD;
354}
355
356
357/**
358 * Checks the instruction and executes the hypercall if it's a valid hypercall
359 * instruction.
360 *
361 * This interface is used by \#UD handlers and IEM.
362 *
363 * @returns Strict VBox status code.
364 * @param pVCpu The cross context virtual CPU structure.
365 * @param pCtx Pointer to the guest-CPU context.
366 * @param uDisOpcode The disassembler opcode.
367 * @param cbInstr The instruction length.
368 *
369 * @thread EMT(pVCpu).
370 */
371VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercallEx(PVMCPU pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
372{
373 Assert(pVCpu);
374 Assert(pCtx);
375 VMCPU_ASSERT_EMT(pVCpu);
376
377 /*
378 * If the instruction at RIP is the Intel VMCALL instruction or
379 * the AMD VMMCALL instruction handle it as a hypercall.
380 *
381 * Linux/KVM guests always uses the Intel VMCALL instruction but we patch
382 * it to the host-native one whenever we encounter it so subsequent calls
383 * will not require disassembly (when coming from HM).
384 */
385 if ( uDisOpcode == OP_VMCALL
386 || uDisOpcode == OP_VMMCALL)
387 {
388 /*
389 * Perform the hypercall.
390 *
391 * For HM, we can simply resume guest execution without performing the hypercall now and
392 * do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
393 *
394 * For raw-mode we need to do this now anyway. So we do it here regardless with an added
395 * advantage is that it saves one world-switch for the HM case.
396 */
397 VBOXSTRICTRC rcStrict = gimKvmHypercall(pVCpu, pCtx);
398 if (rcStrict == VINF_SUCCESS)
399 {
400 /*
401 * Patch the instruction to so we don't have to spend time disassembling it each time.
402 * Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
403 */
404 PVM pVM = pVCpu->CTX_SUFF(pVM);
405 PCGIMKVM pKvm = &pVM->gim.s.u.Kvm;
406 if ( uDisOpcode != pKvm->uOpcodeNative
407 && !VM_IS_RAW_MODE_ENABLED(pVM)
408 && cbInstr == sizeof(pKvm->abOpcodeNative) )
409 {
410 /** @todo r=ramshankar: we probably should be doing this in an
411 * EMT rendezvous. */
412 /** @todo Add stats for patching. */
413 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, pKvm->abOpcodeNative, sizeof(pKvm->abOpcodeNative));
414 AssertRC(rc);
415 }
416 }
417 else
418 {
419 /* The KVM provider doesn't have any concept of continuing hypercalls. */
420 Assert(rcStrict != VINF_GIM_HYPERCALL_CONTINUING);
421#ifdef IN_RING3
422 Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
423#endif
424 }
425 return rcStrict;
426 }
427
428 return VERR_GIM_INVALID_HYPERCALL_INSTR;
429}
430
431
432/**
433 * Exception handler for \#UD.
434 *
435 * @returns Strict VBox status code.
436 * @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
437 * failed).
438 * @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
439 * @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
440 * @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
441 * hypercall instruction.
442 *
443 * @param pVCpu The cross context virtual CPU structure.
444 * @param pCtx Pointer to the guest-CPU context.
445 * @param pDis Pointer to the disassembled instruction state at RIP.
446 * Optional, can be NULL.
447 * @param pcbInstr Where to store the instruction length of the hypercall
448 * instruction. Optional, can be NULL.
449 *
450 * @thread EMT(pVCpu).
451 */
452VMM_INT_DECL(VBOXSTRICTRC) gimKvmXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
453{
454 VMCPU_ASSERT_EMT(pVCpu);
455
456 /*
457 * If we didn't ask for #UD to be trapped, bail.
458 */
459 PVM pVM = pVCpu->CTX_SUFF(pVM);
460 PCGIMKVM pKvm = &pVM->gim.s.u.Kvm;
461 if (RT_UNLIKELY(!pKvm->fTrapXcptUD))
462 return VERR_GIM_IPE_3;
463
464 if (!pDis)
465 {
466 unsigned cbInstr;
467 DISCPUSTATE Dis;
468 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbInstr);
469 if (RT_SUCCESS(rc))
470 {
471 if (pcbInstr)
472 *pcbInstr = (uint8_t)cbInstr;
473 return gimKvmHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
474 }
475
476 Log(("GIM: KVM: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
477 return rc;
478 }
479
480 return gimKvmHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
481}
482
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