GIMAllKvm.cpp@ 83349

Last change on this file since 83349 was 82968, checked in by vboxsync, 5 years ago
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1	/* $Id: GIMAllKvm.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* GIM - Guest Interface Manager, KVM, All Contexts.
4	*/
5
6	/*
7	* Copyright (C) 2015-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_GIM
23	#include <VBox/vmm/gim.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/tm.h>
27	#include <VBox/vmm/pgm.h>
28	#include <VBox/vmm/pdmdev.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include "GIMKvmInternal.h"
31	#include "GIMInternal.h"
32	#include <VBox/vmm/vmcc.h>
33
34	#include <VBox/dis.h>
35	#include <VBox/err.h>
36	#include <VBox/sup.h>
37
38	#include <iprt/asm-amd64-x86.h>
39	#include <iprt/time.h>
40
41
42	/**
43	* Handles the KVM hypercall.
44	*
45	* @returns Strict VBox status code.
46	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
47	* failed).
48	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
49	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
50	*
51	* @param pVCpu The cross context virtual CPU structure.
52	* @param pCtx Pointer to the guest-CPU context.
53	*
54	* @thread EMT(pVCpu).
55	*/
56	VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx)
57	{
58	VMCPU_ASSERT_EMT(pVCpu);
59
60	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
61	STAM_REL_COUNTER_INC(&pVM->gim.s.StatHypercalls);
62
63	/*
64	* Get the hypercall operation and arguments.
65	*/
66	bool const fIs64BitMode = CPUMIsGuestIn64BitCodeEx(pCtx);
67	uint64_t uHyperOp = pCtx->rax;
68	uint64_t uHyperArg0 = pCtx->rbx;
69	uint64_t uHyperArg1 = pCtx->rcx;
70	uint64_t uHyperArg2 = pCtx->rdi;
71	uint64_t uHyperArg3 = pCtx->rsi;
72	uint64_t uHyperRet = KVM_HYPERCALL_RET_ENOSYS;
73	uint64_t uAndMask = UINT64_C(0xffffffffffffffff);
74	if (!fIs64BitMode)
75	{
76	uAndMask = UINT64_C(0xffffffff);
77	uHyperOp &= UINT64_C(0xffffffff);
78	uHyperArg0 &= UINT64_C(0xffffffff);
79	uHyperArg1 &= UINT64_C(0xffffffff);
80	uHyperArg2 &= UINT64_C(0xffffffff);
81	uHyperArg3 &= UINT64_C(0xffffffff);
82	uHyperRet &= UINT64_C(0xffffffff);
83	}
84
85	/*
86	* Verify that guest ring-0 is the one making the hypercall.
87	*/
88	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
89	if (RT_UNLIKELY(uCpl))
90	{
91	pCtx->rax = KVM_HYPERCALL_RET_EPERM & uAndMask;
92	return VERR_GIM_HYPERCALL_ACCESS_DENIED;
93	}
94
95	/*
96	* Do the work.
97	*/
98	int rc = VINF_SUCCESS;
99	switch (uHyperOp)
100	{
101	case KVM_HYPERCALL_OP_KICK_CPU:
102	{
103	if (uHyperArg1 < pVM->cCpus)
104	{
105	PVMCPUCC pVCpuDst = VMCC_GET_CPU(pVM, uHyperArg1); /* ASSUMES pVCpu index == ApicId of the VCPU. */
106	EMUnhaltAndWakeUp(pVM, pVCpuDst);
107	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
108	}
109	else
110	{
111	/* Shouldn't ever happen! If it does, throw a guru, as otherwise it'll lead to deadlocks in the guest anyway! */
112	rc = VERR_GIM_HYPERCALL_FAILED;
113	}
114	break;
115	}
116
117	case KVM_HYPERCALL_OP_VAPIC_POLL_IRQ:
118	uHyperRet = KVM_HYPERCALL_RET_SUCCESS;
119	break;
120
121	default:
122	break;
123	}
124
125	/*
126	* Place the result in rax/eax.
127	*/
128	pCtx->rax = uHyperRet & uAndMask;
129	return rc;
130	}
131
132
133	/**
134	* Returns whether the guest has configured and enabled the use of KVM's
135	* hypercall interface.
136	*
137	* @returns true if hypercalls are enabled, false otherwise.
138	* @param pVCpu The cross context virtual CPU structure.
139	*/
140	VMM_INT_DECL(bool) gimKvmAreHypercallsEnabled(PVMCPU pVCpu)
141	{
142	NOREF(pVCpu);
143	/* KVM paravirt interface doesn't have hypercall control bits (like Hyper-V does)
144	that guests can control, i.e. hypercalls are always enabled. */
145	return true;
146	}
147
148
149	/**
150	* Returns whether the guest has configured and enabled the use of KVM's
151	* paravirtualized TSC.
152	*
153	* @returns true if paravirt. TSC is enabled, false otherwise.
154	* @param pVM The cross context VM structure.
155	*/
156	VMM_INT_DECL(bool) gimKvmIsParavirtTscEnabled(PVMCC pVM)
157	{
158	uint32_t const cCpus = pVM->cCpus;
159	for (uint32_t idCpu = 0; idCpu < cCpus; idCpu++)
160	{
161	PVMCPUCC pVCpu = pVM->CTX_SUFF(apCpus)[idCpu];
162	PGIMKVMCPU pGimKvmCpu = &pVCpu->gim.s.u.KvmCpu;
163	if (MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pGimKvmCpu->u64SystemTimeMsr))
164	return true;
165	}
166	return false;
167	}
168
169
170	/**
171	* MSR read handler for KVM.
172	*
173	* @returns Strict VBox status code like CPUMQueryGuestMsr().
174	* @retval VINF_CPUM_R3_MSR_READ
175	* @retval VERR_CPUM_RAISE_GP_0
176	*
177	* @param pVCpu The cross context virtual CPU structure.
178	* @param idMsr The MSR being read.
179	* @param pRange The range this MSR belongs to.
180	* @param puValue Where to store the MSR value read.
181	*/
182	VMM_INT_DECL(VBOXSTRICTRC) gimKvmReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
183	{
184	NOREF(pRange);
185	PVM pVM = pVCpu->CTX_SUFF(pVM);
186	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
187	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
188
189	switch (idMsr)
190	{
191	case MSR_GIM_KVM_SYSTEM_TIME:
192	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
193	*puValue = pKvmCpu->u64SystemTimeMsr;
194	return VINF_SUCCESS;
195
196	case MSR_GIM_KVM_WALL_CLOCK:
197	case MSR_GIM_KVM_WALL_CLOCK_OLD:
198	*puValue = pKvm->u64WallClockMsr;
199	return VINF_SUCCESS;
200
201	default:
202	{
203	#ifdef IN_RING3
204	static uint32_t s_cTimes = 0;
205	if (s_cTimes++ < 20)
206	LogRel(("GIM: KVM: Unknown/invalid RdMsr (%#x) -> #GP(0)\n", idMsr));
207	#endif
208	LogFunc(("Unknown/invalid RdMsr (%#RX32) -> #GP(0)\n", idMsr));
209	break;
210	}
211	}
212
213	return VERR_CPUM_RAISE_GP_0;
214	}
215
216
217	/**
218	* MSR write handler for KVM.
219	*
220	* @returns Strict VBox status code like CPUMSetGuestMsr().
221	* @retval VINF_CPUM_R3_MSR_WRITE
222	* @retval VERR_CPUM_RAISE_GP_0
223	*
224	* @param pVCpu The cross context virtual CPU structure.
225	* @param idMsr The MSR being written.
226	* @param pRange The range this MSR belongs to.
227	* @param uRawValue The raw value with the ignored bits not masked.
228	*/
229	VMM_INT_DECL(VBOXSTRICTRC) gimKvmWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
230	{
231	NOREF(pRange);
232	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
233	PGIMKVMCPU pKvmCpu = &pVCpu->gim.s.u.KvmCpu;
234
235	switch (idMsr)
236	{
237	case MSR_GIM_KVM_SYSTEM_TIME:
238	case MSR_GIM_KVM_SYSTEM_TIME_OLD:
239	{
240	bool fEnable = RT_BOOL(uRawValue & MSR_GIM_KVM_SYSTEM_TIME_ENABLE_BIT);
241	#ifndef IN_RING3
242	NOREF(fEnable); NOREF(pKvmCpu);
243	gimR0KvmUpdateSystemTime(pVM, pVCpu);
244	return VINF_CPUM_R3_MSR_WRITE;
245	#else /* IN_RING3 */
246	if (!fEnable)
247	{
248	gimR3KvmDisableSystemTime(pVM);
249	pKvmCpu->u64SystemTimeMsr = uRawValue;
250	return VINF_SUCCESS;
251	}
252
253	/* Is the system-time struct. already enabled? If so, get flags that need preserving. */
254	GIMKVMSYSTEMTIME SystemTime;
255	RT_ZERO(SystemTime);
256	if ( MSR_GIM_KVM_SYSTEM_TIME_IS_ENABLED(pKvmCpu->u64SystemTimeMsr)
257	&& MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue) == pKvmCpu->GCPhysSystemTime)
258	{
259	int rc2 = PGMPhysSimpleReadGCPhys(pVM, &SystemTime, pKvmCpu->GCPhysSystemTime, sizeof(GIMKVMSYSTEMTIME));
260	if (RT_SUCCESS(rc2))
261	pKvmCpu->fSystemTimeFlags = (SystemTime.fFlags & GIM_KVM_SYSTEM_TIME_FLAGS_GUEST_PAUSED);
262	}
263
264	/* We ASSUME that ring-0/raw-mode have updated these. */
265	/** @todo Get logically atomic NanoTS/TSC pairs in ring-3. */
266	Assert(pKvmCpu->uTsc);
267	Assert(pKvmCpu->uVirtNanoTS);
268
269	/* Enable and populate the system-time struct. */
270	pKvmCpu->u64SystemTimeMsr = uRawValue;
271	pKvmCpu->GCPhysSystemTime = MSR_GIM_KVM_SYSTEM_TIME_GUEST_GPA(uRawValue);
272	pKvmCpu->u32SystemTimeVersion += 2;
273	int rc = gimR3KvmEnableSystemTime(pVM, pVCpu);
274	if (RT_FAILURE(rc))
275	{
276	pKvmCpu->u64SystemTimeMsr = 0;
277	/* We shouldn't throw a #GP(0) here for buggy guests (neither does KVM apparently), see @bugref{8627}. */
278	}
279	return VINF_SUCCESS;
280	#endif /* IN_RING3 */
281	}
282
283	case MSR_GIM_KVM_WALL_CLOCK:
284	case MSR_GIM_KVM_WALL_CLOCK_OLD:
285	{
286	#ifndef IN_RING3
287	return VINF_CPUM_R3_MSR_WRITE;
288	#else
289	/* Enable the wall-clock struct. */
290	RTGCPHYS GCPhysWallClock = MSR_GIM_KVM_WALL_CLOCK_GUEST_GPA(uRawValue);
291	if (RT_LIKELY(RT_ALIGN_64(GCPhysWallClock, 4) == GCPhysWallClock))
292	{
293	int rc = gimR3KvmEnableWallClock(pVM, GCPhysWallClock);
294	if (RT_SUCCESS(rc))
295	{
296	PGIMKVM pKvm = &pVM->gim.s.u.Kvm;
297	pKvm->u64WallClockMsr = uRawValue;
298	return VINF_SUCCESS;
299	}
300	}
301	return VERR_CPUM_RAISE_GP_0;
302	#endif /* IN_RING3 */
303	}
304
305	default:
306	{
307	#ifdef IN_RING3
308	static uint32_t s_cTimes = 0;
309	if (s_cTimes++ < 20)
310	LogRel(("GIM: KVM: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
311	uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
312	#endif
313	LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
314	break;
315	}
316	}
317
318	return VERR_CPUM_RAISE_GP_0;
319	}
320
321
322	/**
323	* Whether we need to trap \#UD exceptions in the guest.
324	*
325	* On AMD-V we need to trap them because paravirtualized Linux/KVM guests use
326	* the Intel VMCALL instruction to make hypercalls and we need to trap and
327	* optionally patch them to the AMD-V VMMCALL instruction and handle the
328	* hypercall.
329	*
330	* I guess this was done so that guest teleporation between an AMD and an Intel
331	* machine would working without any changes at the time of teleporation.
332	* However, this also means we -always- need to intercept \#UD exceptions on one
333	* of the two CPU models (Intel or AMD). Hyper-V solves this problem more
334	* elegantly by letting the hypervisor supply an opaque hypercall page.
335	*
336	* For raw-mode VMs, this function will always return true. See gimR3KvmInit().
337	*
338	* @param pVM The cross context VM structure.
339	*/
340	VMM_INT_DECL(bool) gimKvmShouldTrapXcptUD(PVM pVM)
341	{
342	return pVM->gim.s.u.Kvm.fTrapXcptUD;
343	}
344
345
346	/**
347	* Checks the instruction and executes the hypercall if it's a valid hypercall
348	* instruction.
349	*
350	* This interface is used by \#UD handlers and IEM.
351	*
352	* @returns Strict VBox status code.
353	* @param pVCpu The cross context virtual CPU structure.
354	* @param pCtx Pointer to the guest-CPU context.
355	* @param uDisOpcode The disassembler opcode.
356	* @param cbInstr The instruction length.
357	*
358	* @thread EMT(pVCpu).
359	*/
360	VMM_INT_DECL(VBOXSTRICTRC) gimKvmHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr)
361	{
362	Assert(pVCpu);
363	Assert(pCtx);
364	VMCPU_ASSERT_EMT(pVCpu);
365
366	/*
367	* If the instruction at RIP is the Intel VMCALL instruction or
368	* the AMD VMMCALL instruction handle it as a hypercall.
369	*
370	* Linux/KVM guests always uses the Intel VMCALL instruction but we patch
371	* it to the host-native one whenever we encounter it so subsequent calls
372	* will not require disassembly (when coming from HM).
373	*/
374	if ( uDisOpcode == OP_VMCALL
375	\|\| uDisOpcode == OP_VMMCALL)
376	{
377	/*
378	* Perform the hypercall.
379	*
380	* For HM, we can simply resume guest execution without performing the hypercall now and
381	* do it on the next VMCALL/VMMCALL exit handler on the patched instruction.
382	*
383	* For raw-mode we need to do this now anyway. So we do it here regardless with an added
384	* advantage is that it saves one world-switch for the HM case.
385	*/
386	VBOXSTRICTRC rcStrict = gimKvmHypercall(pVCpu, pCtx);
387	if (rcStrict == VINF_SUCCESS)
388	{
389	/*
390	* Patch the instruction to so we don't have to spend time disassembling it each time.
391	* Makes sense only for HM as with raw-mode we will be getting a #UD regardless.
392	*/
393	PVM pVM = pVCpu->CTX_SUFF(pVM);
394	PCGIMKVM pKvm = &pVM->gim.s.u.Kvm;
395	if ( uDisOpcode != pKvm->uOpcodeNative
396	&& cbInstr == sizeof(pKvm->abOpcodeNative) )
397	{
398	/** @todo r=ramshankar: we probably should be doing this in an
399	* EMT rendezvous. */
400	/** @todo Add stats for patching. */
401	int rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, pKvm->abOpcodeNative, sizeof(pKvm->abOpcodeNative));
402	AssertRC(rc);
403	}
404	}
405	else
406	{
407	/* The KVM provider doesn't have any concept of continuing hypercalls. */
408	Assert(rcStrict != VINF_GIM_HYPERCALL_CONTINUING);
409	#ifdef IN_RING3
410	Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
411	#endif
412	}
413	return rcStrict;
414	}
415
416	return VERR_GIM_INVALID_HYPERCALL_INSTR;
417	}
418
419
420	/**
421	* Exception handler for \#UD.
422	*
423	* @returns Strict VBox status code.
424	* @retval VINF_SUCCESS if the hypercall succeeded (even if its operation
425	* failed).
426	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
427	* @retval VERR_GIM_HYPERCALL_ACCESS_DENIED CPL is insufficient.
428	* @retval VERR_GIM_INVALID_HYPERCALL_INSTR instruction at RIP is not a valid
429	* hypercall instruction.
430	*
431	* @param pVM The cross context VM structure.
432	* @param pVCpu The cross context virtual CPU structure.
433	* @param pCtx Pointer to the guest-CPU context.
434	* @param pDis Pointer to the disassembled instruction state at RIP.
435	* Optional, can be NULL.
436	* @param pcbInstr Where to store the instruction length of the hypercall
437	* instruction. Optional, can be NULL.
438	*
439	* @thread EMT(pVCpu).
440	*/
441	VMM_INT_DECL(VBOXSTRICTRC) gimKvmXcptUD(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr)
442	{
443	VMCPU_ASSERT_EMT(pVCpu);
444
445	/*
446	* If we didn't ask for #UD to be trapped, bail.
447	*/
448	if (RT_UNLIKELY(!pVM->gim.s.u.Kvm.fTrapXcptUD))
449	return VERR_GIM_IPE_3;
450
451	if (!pDis)
452	{
453	unsigned cbInstr;
454	DISCPUSTATE Dis;
455	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbInstr);
456	if (RT_SUCCESS(rc))
457	{
458	if (pcbInstr)
459	*pcbInstr = (uint8_t)cbInstr;
460	return gimKvmHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
461	}
462
463	Log(("GIM: KVM: Failed to disassemble instruction at CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
464	return rc;
465	}
466
467	return gimKvmHypercallEx(pVCpu, pCtx, pDis->pCurInstr->uOpcode, pDis->cbInstr);
468	}
469

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source: vbox/trunk/src/VBox/VMM/VMMAll/GIMAllKvm.cpp@ 83349

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