HMAll.cpp

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1	/* $Id: HMAll.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2	/** @file
3	* HM - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_HM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/hm.h>
35	#include <VBox/vmm/pgm.h>
36	#include "HMInternal.h"
37	#include <VBox/vmm/vmcc.h>
38	#include <VBox/vmm/hm_vmx.h>
39	#include <VBox/vmm/hm_svm.h>
40	#include <iprt/errcore.h>
41	#include <VBox/log.h>
42	#include <iprt/param.h>
43	#include <iprt/assert.h>
44	#include <iprt/asm.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include <iprt/x86.h>
48
49
50	/*********************************************************************************************************************************
51	* Global Variables *
52	*********************************************************************************************************************************/
53	#define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
54	#define EXIT_REASON_NIL() NULL
55
56	/** Exit reason descriptions for VT-x, used to describe statistics and exit
57	* history. */
58	static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
59	{
60	EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
61	EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
62	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
63	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
64	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
65	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
66	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
67	EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
68	EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
69	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
70	EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
71	EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instruction."),
72	EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
73	EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
74	EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
75	EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMC instruction."),
76	EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
77	EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
78	EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
79	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
80	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
81	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
82	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
83	EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
84	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
85	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
86	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
87	EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
88	EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
89	EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
90	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
91	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
92	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
93	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
94	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
95	EXIT_REASON_NIL(),
96	EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
97	EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
98	EXIT_REASON_NIL(),
99	EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
100	EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
101	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
102	EXIT_REASON_NIL(),
103	EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
104	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
105	EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
106	EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
107	EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
108	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
109	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
110	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
111	EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
112	EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
113	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
114	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
115	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
116	EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
117	EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
118	EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
119	EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
120	EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
121	EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
122	EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
123	EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
124	EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction."),
125	EXIT_REASON_NIL(),
126	EXIT_REASON(VMX_EXIT_SPP_EVENT , 66, "SPP-related event."),
127	EXIT_REASON(VMX_EXIT_UMWAIT , 67, "UMWAIT instruction."),
128	EXIT_REASON(VMX_EXIT_TPAUSE , 68, "TPAUSE instruction.")
129	};
130	/** Array index of the last valid VT-x exit reason. */
131	#define MAX_EXITREASON_VTX 68
132
133	/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
134	* statistics and exit history.
135	*
136	* @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
137	* this array doesn't contain the entire set of exit reasons, we
138	* handle them via hmSvmGetSpecialExitReasonDesc(). */
139	static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
140	{
141	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
142	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
143	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
144	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
145	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
146	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
147	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
148	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
149	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
150	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
151	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
152	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
153	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
154	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
155	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
156	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
157	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
158	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
159	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
160	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
161	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
162	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
163	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
164	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
165	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
166	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
167	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
168	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
169	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
170	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
171	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
172	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
173	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
174	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
175	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
176	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
177	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
178	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
179	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
180	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
181	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
182	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
183	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
184	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
185	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
186	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
187	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
188	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
189	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
190	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
191	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
192	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
193	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
194	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
195	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
196	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
197	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
198	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
199	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
200	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
201	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
202	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
203	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
204	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
205	EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
206	EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
207	EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
208	EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
209	EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
210	EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
211	EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
212	EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
213	EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
214	EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
215	EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
216	EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
217	EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
218	EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
219	EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
220	EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
221	EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
222	EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
223	EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
224	EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
225	EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
226	EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
227	EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
228	EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
229	EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
230	EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
231	EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
232	EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
233	EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
234	EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
235	EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
236	EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
237	EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
238	EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
239	EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
240	EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
241	EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
242	EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE , 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
243	EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
244	EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
245	EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
246	EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
247	EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
248	EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
249	EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
250	EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
251	EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
252	EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
253	EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
254	EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
255	EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
256	EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
257	EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
258	EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
259	EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
260	EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
261	EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
262	EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
263	EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
264	EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
265	EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
266	EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
267	EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
268	EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
269	EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
270	EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
271	EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
272	EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
273	EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
274	EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
275	EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
276	EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
277	EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
278	EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
279	EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
280	EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
281	EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
282	EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
283	EXIT_REASON(SVM_EXIT_RDPRU , 142, "RDPRU instruction."),
284	EXIT_REASON(SVM_EXIT_WRITE_EFER_TRAP, 143, "Write EFER (trap-like)."),
285	EXIT_REASON(SVM_EXIT_WRITE_CR0_TRAP , 144, "Write CR0 (trap-like)."),
286	EXIT_REASON(SVM_EXIT_WRITE_CR1_TRAP , 145, "Write CR1 (trap-like)."),
287	EXIT_REASON(SVM_EXIT_WRITE_CR2_TRAP , 146, "Write CR2 (trap-like)."),
288	EXIT_REASON(SVM_EXIT_WRITE_CR3_TRAP , 147, "Write CR3 (trap-like)."),
289	EXIT_REASON(SVM_EXIT_WRITE_CR4_TRAP , 148, "Write CR4 (trap-like)."),
290	EXIT_REASON(SVM_EXIT_WRITE_CR5_TRAP , 149, "Write CR5 (trap-like)."),
291	EXIT_REASON(SVM_EXIT_WRITE_CR6_TRAP , 150, "Write CR6 (trap-like)."),
292	EXIT_REASON(SVM_EXIT_WRITE_CR7_TRAP , 151, "Write CR7 (trap-like)."),
293	EXIT_REASON(SVM_EXIT_WRITE_CR8_TRAP , 152, "Write CR8 (trap-like)."),
294	EXIT_REASON(SVM_EXIT_WRITE_CR9_TRAP , 153, "Write CR9 (trap-like)."),
295	EXIT_REASON(SVM_EXIT_WRITE_CR10_TRAP, 154, "Write CR10 (trap-like)."),
296	EXIT_REASON(SVM_EXIT_WRITE_CR11_TRAP, 155, "Write CR11 (trap-like)."),
297	EXIT_REASON(SVM_EXIT_WRITE_CR12_TRAP, 156, "Write CR12 (trap-like)."),
298	EXIT_REASON(SVM_EXIT_WRITE_CR13_TRAP, 157, "Write CR13 (trap-like)."),
299	EXIT_REASON(SVM_EXIT_WRITE_CR14_TRAP, 158, "Write CR14 (trap-like)."),
300	EXIT_REASON(SVM_EXIT_WRITE_CR15_TRAP, 159, "Write CR15 (trap-like)."),
301	EXIT_REASON_NIL() ,
302	EXIT_REASON_NIL() ,
303	EXIT_REASON_NIL() ,
304	EXIT_REASON(SVM_EXIT_MCOMMIT , 163, "MCOMMIT instruction."),
305	};
306	/** Array index of the last valid AMD-V exit reason. */
307	#define MAX_EXITREASON_AMDV 163
308
309	/** Special exit reasons not covered in the array above. */
310	#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
311	#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
312	#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
313
314	/**
315	* Gets the SVM exit reason if it's one of the reasons not present in the @c
316	* g_apszSvmExitReasons array.
317	*
318	* @returns The exit reason or NULL if unknown.
319	* @param uExit The exit.
320	*/
321	DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
322	{
323	switch (uExit)
324	{
325	case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
326	case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
327	case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
328	}
329	return EXIT_REASON_NIL();
330	}
331	#undef EXIT_REASON_NIL
332	#undef EXIT_REASON
333
334
335	/**
336	* Checks whether HM (VT-x/AMD-V) is being used by this VM.
337	*
338	* @retval true if used.
339	* @retval false if software virtualization (raw-mode) is used.
340	* @param pVM The cross context VM structure.
341	* @sa HMIsEnabled, HMR3IsEnabled
342	* @internal
343	*/
344	VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
345	{
346	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
347	return pVM->fHMEnabled;
348	}
349
350
351	/**
352	* Checks if the guest is in a suitable state for hardware-assisted execution.
353	*
354	* @returns @c true if it is suitable, @c false otherwise.
355	* @param pVM The cross context VM structure.
356	* @param pVCpu The cross context virtual CPU structure.
357	* @param pCtx Pointer to the guest CPU context.
358	*
359	* @remarks @a pCtx can be a partial context created and not necessarily the same as
360	* pVCpu->cpum.GstCtx.
361	*/
362	VMMDECL(bool) HMCanExecuteGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
363	{
364	Assert(HMIsEnabled(pVM));
365
366	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
367	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
368	\|\| CPUMIsGuestInVmxNonRootMode(pCtx))
369	{
370	LogFunc(("In nested-guest mode - returning false"));
371	return false;
372	}
373	#endif
374
375	/* AMD-V supports real & protected mode with or without paging. */
376	if (pVM->hm.s.svm.fEnabled)
377	{
378	pVCpu->hm.s.fActive = true;
379	return true;
380	}
381
382	bool rc = HMCanExecuteVmxGuest(pVM, pVCpu, pCtx);
383	LogFlowFunc(("returning %RTbool\n", rc));
384	return rc;
385	}
386
387
388	/**
389	* Queues a guest page for invalidation.
390	*
391	* @param pVCpu The cross context virtual CPU structure.
392	* @param GCVirt Page to invalidate.
393	*/
394	static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
395	{
396	/* Nothing to do if a TLB flush is already pending */
397	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
398	return;
399	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
400	NOREF(GCVirt);
401	}
402
403
404	/**
405	* Invalidates a guest page.
406	*
407	* @returns VBox status code.
408	* @param pVCpu The cross context virtual CPU structure.
409	* @param GCVirt Page to invalidate.
410	*/
411	VMM_INT_DECL(int) HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
412	{
413	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
414	#ifdef IN_RING0
415	return HMR0InvalidatePage(pVCpu, GCVirt);
416	#else
417	hmQueueInvlPage(pVCpu, GCVirt);
418	return VINF_SUCCESS;
419	#endif
420	}
421
422
423	#ifdef IN_RING0
424
425	/**
426	* Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
427	*
428	*/
429	static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void pvUser1, void pvUser2)
430	{
431	NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
432	return;
433	}
434
435
436	/**
437	* Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
438	*/
439	static void hmR0PokeCpu(PVMCPUCC pVCpu, RTCPUID idHostCpu)
440	{
441	uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits);
442
443	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
444	int rc = RTMpPokeCpu(idHostCpu);
445	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
446
447	/* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
448	back to a less efficient implementation (broadcast). */
449	if (rc == VERR_NOT_SUPPORTED)
450	{
451	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
452	/* synchronous. */
453	RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
454	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
455	}
456	else
457	{
458	if (rc == VINF_SUCCESS)
459	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
460	else
461	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
462
463	/** @todo If more than one CPU is going to be poked, we could optimize this
464	* operation by poking them first and wait afterwards. Would require
465	* recording who to poke and their current cWorldSwitchExits values,
466	* that's something not suitable for stack... So, pVCpu->hm.s.something
467	* then. */
468	/* Spin until the VCPU has switched back (poking is async). */
469	while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
470	&& cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits))
471	ASMNopPause();
472
473	if (rc == VINF_SUCCESS)
474	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
475	else
476	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
477	}
478	}
479
480	#endif /* IN_RING0 */
481
482	/**
483	* Flushes the guest TLB.
484	*
485	* @returns VBox status code.
486	* @param pVCpu The cross context virtual CPU structure.
487	*/
488	VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
489	{
490	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
491	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
492	return VINF_SUCCESS;
493	}
494
495
496	/**
497	* Poke an EMT so it can perform the appropriate TLB shootdowns.
498	*
499	* @param pVCpu The cross context virtual CPU structure of the
500	* EMT poke.
501	* @param fAccountFlushStat Whether to account the call to
502	* StatTlbShootdownFlush or StatTlbShootdown.
503	*/
504	static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
505	{
506	if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
507	{
508	if (fAccountFlushStat)
509	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
510	else
511	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
512	#ifdef IN_RING0
513	RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
514	if (idHostCpu != NIL_RTCPUID)
515	hmR0PokeCpu(pVCpu, idHostCpu);
516	#else
517	VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
518	#endif
519	}
520	else
521	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
522	}
523
524
525	/**
526	* Invalidates a guest page on all VCPUs.
527	*
528	* @returns VBox status code.
529	* @param pVM The cross context VM structure.
530	* @param GCVirt Page to invalidate.
531	*/
532	VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVMCC pVM, RTGCPTR GCVirt)
533	{
534	/*
535	* The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
536	* host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
537	*
538	* This is the reason why we do not care about thread preemption here and just
539	* execute HMInvalidatePage() assuming it might be the 'right' CPU.
540	*/
541	VMCPUID const idCurCpu = VMMGetCpuId(pVM);
542	STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idCurCpu)->hm.s.StatFlushPage);
543
544	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
545	{
546	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
547
548	/* Nothing to do if a TLB flush is already pending; the VCPU should
549	have already been poked if it were active. */
550	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
551	continue;
552
553	if (pVCpu->idCpu == idCurCpu)
554	HMInvalidatePage(pVCpu, GCVirt);
555	else
556	{
557	hmQueueInvlPage(pVCpu, GCVirt);
558	hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
559	}
560	}
561
562	return VINF_SUCCESS;
563	}
564
565
566	/**
567	* Flush the TLBs of all VCPUs.
568	*
569	* @returns VBox status code.
570	* @param pVM The cross context VM structure.
571	*/
572	VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVMCC pVM)
573	{
574	if (pVM->cCpus == 1)
575	return HMFlushTlb(VMCC_GET_CPU_0(pVM));
576
577	VMCPUID const idThisCpu = VMMGetCpuId(pVM);
578
579	STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idThisCpu)->hm.s.StatFlushTlb);
580
581	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
582	{
583	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
584
585	/* Nothing to do if a TLB flush is already pending; the VCPU should
586	have already been poked if it were active. */
587	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
588	{
589	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
590	if (idThisCpu != idCpu)
591	hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
592	}
593	}
594
595	return VINF_SUCCESS;
596	}
597
598
599	/**
600	* Invalidates a guest page by physical address.
601	*
602	* @returns VBox status code.
603	* @param pVM The cross context VM structure.
604	* @param GCPhys Page to invalidate.
605	*
606	* @remarks Assumes the current instruction references this physical page
607	* though a virtual address!
608	*/
609	VMM_INT_DECL(int) HMInvalidatePhysPage(PVMCC pVM, RTGCPHYS GCPhys)
610	{
611	if (!HMIsNestedPagingActive(pVM))
612	return VINF_SUCCESS;
613
614	/*
615	* AMD-V: Doesn't support invalidation with guest physical addresses.
616	*
617	* VT-x: Doesn't support invalidation with guest physical addresses.
618	* INVVPID instruction takes only a linear address while invept only flushes by EPT
619	* not individual addresses.
620	*
621	* We update the force flag and flush before the next VM-entry, see @bugref{6568}.
622	*/
623	RT_NOREF(GCPhys);
624	/** @todo Remove or figure out to way to update the Phys STAT counter. */
625	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
626	return HMFlushTlbOnAllVCpus(pVM);
627	}
628
629
630	/**
631	* Checks if nested paging is enabled.
632	*
633	* @returns true if nested paging is active, false otherwise.
634	* @param pVM The cross context VM structure.
635	*
636	* @remarks Works before hmR3InitFinalizeR0.
637	*/
638	VMM_INT_DECL(bool) HMIsNestedPagingActive(PVMCC pVM)
639	{
640	return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING);
641	}
642
643
644	/**
645	* Checks if both nested paging and unhampered guest execution are enabled.
646	*
647	* The almost complete guest execution in hardware is only applicable to VT-x.
648	*
649	* @returns true if we have both enabled, otherwise false.
650	* @param pVM The cross context VM structure.
651	*
652	* @remarks Works before hmR3InitFinalizeR0.
653	*/
654	VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVMCC pVM)
655	{
656	return HMIsEnabled(pVM)
657	&& CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING)
658	&& ( CTX_EXPR(pVM->hm.s.vmx.fUnrestrictedGuestCfg, pVM->hmr0.s.vmx.fUnrestrictedGuest, RT_NOTHING)
659	\|\| pVM->hm.s.svm.fSupported);
660	}
661
662
663	/**
664	* Checks if this VM is using HM and is long-mode capable.
665	*
666	* Use VMR3IsLongModeAllowed() instead of this, when possible.
667	*
668	* @returns true if long mode is allowed, false otherwise.
669	* @param pVM The cross context VM structure.
670	* @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
671	*/
672	VMM_INT_DECL(bool) HMIsLongModeAllowed(PVMCC pVM)
673	{
674	return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fAllow64BitGuestsCfg, pVM->hmr0.s.fAllow64BitGuests, RT_NOTHING);
675	}
676
677
678	/**
679	* Checks if MSR bitmaps are active. It is assumed that when it's available
680	* it will be used as well.
681	*
682	* @returns true if MSR bitmaps are available, false otherwise.
683	* @param pVM The cross context VM structure.
684	*/
685	VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
686	{
687	if (HMIsEnabled(pVM))
688	{
689	if (pVM->hm.s.svm.fSupported)
690	return true;
691
692	if ( pVM->hm.s.vmx.fSupported
693	&& ( CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1, g_HmMsrs.u.vmx.ProcCtls.n.allowed1, RT_NOTHING)
694	& VMX_PROC_CTLS_USE_MSR_BITMAPS))
695	return true;
696	}
697	return false;
698	}
699
700
701	/**
702	* Checks if AMD-V is active.
703	*
704	* @returns true if AMD-V is active.
705	* @param pVM The cross context VM structure.
706	*
707	* @remarks Works before hmR3InitFinalizeR0.
708	*/
709	VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
710	{
711	return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
712	}
713
714
715	/**
716	* Checks if VT-x is active.
717	*
718	* @returns true if VT-x is active.
719	* @param pVM The cross context VM structure.
720	*
721	* @remarks Works before hmR3InitFinalizeR0.
722	*/
723	VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
724	{
725	return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
726	}
727
728
729	/**
730	* Checks if an interrupt event is currently pending.
731	*
732	* @returns Interrupt event pending state.
733	* @param pVM The cross context VM structure.
734	*/
735	VMM_INT_DECL(bool) HMHasPendingIrq(PVMCC pVM)
736	{
737	PVMCPUCC pVCpu = VMMGetCpu(pVM);
738	return !!pVCpu->hm.s.Event.fPending;
739	}
740
741
742	/**
743	* Sets or clears the single instruction flag.
744	*
745	* When set, HM will try its best to return to ring-3 after executing a single
746	* instruction. This can be used for debugging. See also
747	* EMR3HmSingleInstruction.
748	*
749	* @returns The old flag state.
750	* @param pVM The cross context VM structure.
751	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
752	* @param fEnable The new flag state.
753	*/
754	VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable)
755	{
756	VMCPU_ASSERT_EMT(pVCpu);
757	bool fOld = pVCpu->hm.s.fSingleInstruction;
758	pVCpu->hm.s.fSingleInstruction = fEnable;
759	pVCpu->hm.s.fUseDebugLoop = fEnable \|\| pVM->hm.s.fUseDebugLoop;
760	return fOld;
761	}
762
763
764	/**
765	* Notification callback which is called whenever there is a chance that a CR3
766	* value might have changed.
767	*
768	* This is called by PGM.
769	*
770	* @param pVM The cross context VM structure.
771	* @param pVCpu The cross context virtual CPU structure.
772	* @param enmShadowMode New shadow paging mode.
773	* @param enmGuestMode New guest paging mode.
774	*/
775	VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPUCC pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
776	{
777	#ifdef IN_RING3
778	/* Ignore page mode changes during state loading. */
779	if (VMR3GetState(pVM) == VMSTATE_LOADING)
780	return;
781	#endif
782
783	pVCpu->hm.s.enmShadowMode = enmShadowMode;
784
785	/*
786	* If the guest left protected mode VMX execution, we'll have to be
787	* extra careful if/when the guest switches back to protected mode.
788	*/
789	if (enmGuestMode == PGMMODE_REAL)
790	{
791	PVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
792	pVmcsInfoShared->fWasInRealMode = true;
793	}
794
795	#ifdef IN_RING0
796	/*
797	* We need to tickle SVM and VT-x state updates.
798	*
799	* Note! We could probably reduce this depending on what exactly changed.
800	*/
801	if (VM_IS_HM_ENABLED(pVM))
802	{
803	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER); /* No recursion! */
804	uint64_t fChanged = HM_CHANGED_GUEST_CR0 \| HM_CHANGED_GUEST_CR3 \| HM_CHANGED_GUEST_CR4 \| HM_CHANGED_GUEST_EFER_MSR;
805	if (pVM->hm.s.svm.fSupported)
806	fChanged \|= HM_CHANGED_SVM_XCPT_INTERCEPTS;
807	else
808	fChanged \|= HM_CHANGED_VMX_XCPT_INTERCEPTS \| HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
809	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
810	}
811	#endif
812
813	Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
814	PGMGetModeName(enmShadowMode)));
815	}
816
817
818	/**
819	* Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
820	*
821	* This abstraction exists to insulate the support driver from including VMX
822	* structures from HM headers.
823	*
824	* @param pHwvirtMsrs The hardware-virtualization MSRs.
825	* @param pVmxMsrs Where to store the VMX MSRs.
826	*/
827	VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
828	{
829	AssertReturnVoid(pHwvirtMsrs);
830	AssertReturnVoid(pVmxMsrs);
831	pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
832	pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.PinCtls.u;
833	pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.ProcCtls.u;
834	pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.ProcCtls2.u;
835	pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.ExitCtls.u;
836	pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.EntryCtls.u;
837	pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.TruePinCtls.u;
838	pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.TrueProcCtls.u;
839	pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.TrueEntryCtls.u;
840	pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.TrueExitCtls.u;
841	pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
842	pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
843	pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
844	pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
845	pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
846	pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
847	pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
848	pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
849	pVmxMsrs->u64ProcCtls3 = pHwvirtMsrs->u.vmx.u64ProcCtls3;
850	pVmxMsrs->u64ExitCtls2 = pHwvirtMsrs->u.vmx.u64ExitCtls2;
851	}
852
853
854	/**
855	* Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
856	*
857	* This abstraction exists to insulate the support driver from including SVM
858	* structures from HM headers.
859	*
860	* @param pHwvirtMsrs The hardware-virtualization MSRs.
861	* @param pSvmMsrs Where to store the SVM MSRs.
862	*/
863	VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
864	{
865	AssertReturnVoid(pHwvirtMsrs);
866	AssertReturnVoid(pSvmMsrs);
867	pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
868	}
869
870
871	/**
872	* Gets the name of a VT-x exit code.
873	*
874	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
875	* @param uExit The VT-x exit to name.
876	*/
877	VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
878	{
879	uint16_t const uReason = VMX_EXIT_REASON_BASIC(uExit);
880	if (uReason <= MAX_EXITREASON_VTX)
881	{
882	Assert(uReason < RT_ELEMENTS(g_apszVmxExitReasons));
883	return g_apszVmxExitReasons[uReason];
884	}
885	return NULL;
886	}
887
888
889	/**
890	* Gets the name of an AMD-V exit code.
891	*
892	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
893	* @param uExit The AMD-V exit to name.
894	*/
895	VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
896	{
897	if (uExit <= MAX_EXITREASON_AMDV)
898	{
899	Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
900	return g_apszSvmExitReasons[uExit];
901	}
902	return hmSvmGetSpecialExitReasonDesc(uExit);
903	}
904

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp

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