VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp@ 78402

Last change on this file since 78402 was 78253, checked in by vboxsync, 6 years ago

VMM/HM: Remove couple of unused functions.
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File size: 35.2 KB
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1/* $Id: HMAll.cpp 78253 2019-04-23 04:17:43Z vboxsync $ */
2/** @file
3 * HM - All contexts.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/hm.h>
25#include <VBox/vmm/pgm.h>
26#include "HMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/hm_vmx.h>
29#include <VBox/vmm/hm_svm.h>
30#include <iprt/errcore.h>
31#include <VBox/log.h>
32#include <iprt/param.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35#include <iprt/string.h>
36#include <iprt/thread.h>
37#include <iprt/x86.h>
38#include <iprt/asm-amd64-x86.h>
39
40
41/*********************************************************************************************************************************
42* Global Variables *
43*********************************************************************************************************************************/
44#define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
45#define EXIT_REASON_NIL() NULL
46
47/** Exit reason descriptions for VT-x, used to describe statistics and exit
48 * history. */
49static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
50{
51 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
52 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
53 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
54 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
55 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
56 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
57 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
58 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
59 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
60 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
61 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
62 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
63 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
64 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
65 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
66 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
67 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
68 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
69 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
70 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
71 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
72 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
73 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
74 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
75 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
76 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
77 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
78 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
79 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
80 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
81 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
82 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
83 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
84 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
85 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
86 EXIT_REASON_NIL(),
87 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
88 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
89 EXIT_REASON_NIL(),
90 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
91 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
92 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
93 EXIT_REASON_NIL(),
94 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
95 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
96 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
97 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
98 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
99 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
100 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
101 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
102 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
103 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
104 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
105 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
106 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
107 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
108 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
109 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
110 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
111 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
112 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
113 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
114 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
115 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
116};
117/** Array index of the last valid VT-x exit reason. */
118#define MAX_EXITREASON_VTX 64
119
120/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
121 * statistics and exit history.
122 *
123 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
124 * this array doesn't contain the entire set of exit reasons, we
125 * handle them via hmSvmGetSpecialExitReasonDesc(). */
126static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
213 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
219 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
220 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
221 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
222 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
223 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
231 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
232 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
252 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
270};
271/** Array index of the last valid AMD-V exit reason. */
272#define MAX_EXITREASON_AMDV 141
273
274/** Special exit reasons not covered in the array above. */
275#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
276#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
277#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
278
279/**
280 * Gets the SVM exit reason if it's one of the reasons not present in the @c
281 * g_apszSvmExitReasons array.
282 *
283 * @returns The exit reason or NULL if unknown.
284 * @param uExit The exit.
285 */
286DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
287{
288 switch (uExit)
289 {
290 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
291 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
292 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
293 }
294 return EXIT_REASON_NIL();
295}
296#undef EXIT_REASON_NIL
297#undef EXIT_REASON
298
299
300/**
301 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
302 *
303 * @retval true if used.
304 * @retval false if software virtualization (raw-mode) is used.
305 * @param pVM The cross context VM structure.
306 * @sa HMIsEnabled, HMR3IsEnabled
307 * @internal
308 */
309VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
310{
311 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
312 return pVM->fHMEnabled;
313}
314
315
316/**
317 * Checks if the guest is in a suitable state for hardware-assisted execution.
318 *
319 * @returns @c true if it is suitable, @c false otherwise.
320 * @param pVCpu The cross context virtual CPU structure.
321 * @param pCtx Pointer to the guest CPU context.
322 *
323 * @remarks @a pCtx can be a partial context created and not necessarily the same as
324 * pVCpu->cpum.GstCtx.
325 */
326VMMDECL(bool) HMCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
327{
328 PVM pVM = pVCpu->CTX_SUFF(pVM);
329 Assert(HMIsEnabled(pVM));
330
331#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
332 if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
333 || CPUMIsGuestInVmxNonRootMode(pCtx))
334 {
335 LogFunc(("In nested-guest mode - returning false"));
336 return false;
337 }
338#endif
339
340 /* AMD-V supports real & protected mode with or without paging. */
341 if (pVM->hm.s.svm.fEnabled)
342 {
343 pVCpu->hm.s.fActive = true;
344 return true;
345 }
346
347 bool rc = HMCanExecuteVmxGuest(pVCpu, pCtx);
348 LogFlowFunc(("returning %RTbool\n", rc));
349 return rc;
350}
351
352
353/**
354 * Queues a guest page for invalidation.
355 *
356 * @returns VBox status code.
357 * @param pVCpu The cross context virtual CPU structure.
358 * @param GCVirt Page to invalidate.
359 */
360static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
361{
362 /* Nothing to do if a TLB flush is already pending */
363 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
364 return;
365 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
366 NOREF(GCVirt);
367}
368
369
370/**
371 * Invalidates a guest page.
372 *
373 * @returns VBox status code.
374 * @param pVCpu The cross context virtual CPU structure.
375 * @param GCVirt Page to invalidate.
376 */
377VMM_INT_DECL(int) HMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
378{
379 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
380#ifdef IN_RING0
381 return HMR0InvalidatePage(pVCpu, GCVirt);
382#else
383 hmQueueInvlPage(pVCpu, GCVirt);
384 return VINF_SUCCESS;
385#endif
386}
387
388
389#ifdef IN_RING0
390
391/**
392 * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
393 *
394 */
395static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
396{
397 NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
398 return;
399}
400
401
402/**
403 * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
404 */
405static void hmR0PokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu)
406{
407 uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits);
408
409 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
410 int rc = RTMpPokeCpu(idHostCpu);
411 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
412
413 /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
414 back to a less efficient implementation (broadcast). */
415 if (rc == VERR_NOT_SUPPORTED)
416 {
417 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
418 /* synchronous. */
419 RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
420 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
421 }
422 else
423 {
424 if (rc == VINF_SUCCESS)
425 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
426 else
427 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
428
429/** @todo If more than one CPU is going to be poked, we could optimize this
430 * operation by poking them first and wait afterwards. Would require
431 * recording who to poke and their current cWorldSwitchExits values,
432 * that's something not suitable for stack... So, pVCpu->hm.s.something
433 * then. */
434 /* Spin until the VCPU has switched back (poking is async). */
435 while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
436 && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hm.s.cWorldSwitchExits))
437 ASMNopPause();
438
439 if (rc == VINF_SUCCESS)
440 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
441 else
442 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
443 }
444}
445
446#endif /* IN_RING0 */
447#ifndef IN_RC
448
449/**
450 * Flushes the guest TLB.
451 *
452 * @returns VBox status code.
453 * @param pVCpu The cross context virtual CPU structure.
454 */
455VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
456{
457 LogFlow(("HMFlushTlb\n"));
458
459 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
460 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
461 return VINF_SUCCESS;
462}
463
464/**
465 * Poke an EMT so it can perform the appropriate TLB shootdowns.
466 *
467 * @param pVCpu The cross context virtual CPU structure of the
468 * EMT poke.
469 * @param fAccountFlushStat Whether to account the call to
470 * StatTlbShootdownFlush or StatTlbShootdown.
471 */
472static void hmPokeCpuForTlbFlush(PVMCPU pVCpu, bool fAccountFlushStat)
473{
474 if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
475 {
476 if (fAccountFlushStat)
477 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
478 else
479 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
480#ifdef IN_RING0
481 RTCPUID idHostCpu = pVCpu->hm.s.idEnteredCpu;
482 if (idHostCpu != NIL_RTCPUID)
483 hmR0PokeCpu(pVCpu, idHostCpu);
484#else
485 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
486#endif
487 }
488 else
489 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
490}
491
492
493/**
494 * Invalidates a guest page on all VCPUs.
495 *
496 * @returns VBox status code.
497 * @param pVM The cross context VM structure.
498 * @param GCVirt Page to invalidate.
499 */
500VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt)
501{
502 /*
503 * The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
504 * host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
505 *
506 * This is the reason why we do not care about thread preemption here and just
507 * execute HMInvalidatePage() assuming it might be the 'right' CPU.
508 */
509 VMCPUID idCurCpu = VMMGetCpuId(pVM);
510 STAM_COUNTER_INC(&pVM->aCpus[idCurCpu].hm.s.StatFlushPage);
511
512 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
513 {
514 PVMCPU pVCpu = &pVM->aCpus[idCpu];
515
516 /* Nothing to do if a TLB flush is already pending; the VCPU should
517 have already been poked if it were active. */
518 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
519 continue;
520
521 if (pVCpu->idCpu == idCurCpu)
522 HMInvalidatePage(pVCpu, GCVirt);
523 else
524 {
525 hmQueueInvlPage(pVCpu, GCVirt);
526 hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
527 }
528 }
529
530 return VINF_SUCCESS;
531}
532
533
534/**
535 * Flush the TLBs of all VCPUs.
536 *
537 * @returns VBox status code.
538 * @param pVM The cross context VM structure.
539 */
540VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVM pVM)
541{
542 if (pVM->cCpus == 1)
543 return HMFlushTlb(&pVM->aCpus[0]);
544
545 VMCPUID idThisCpu = VMMGetCpuId(pVM);
546
547 STAM_COUNTER_INC(&pVM->aCpus[idThisCpu].hm.s.StatFlushTlb);
548
549 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
550 {
551 PVMCPU pVCpu = &pVM->aCpus[idCpu];
552
553 /* Nothing to do if a TLB flush is already pending; the VCPU should
554 have already been poked if it were active. */
555 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
556 {
557 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
558 if (idThisCpu != idCpu)
559 hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
560 }
561 }
562
563 return VINF_SUCCESS;
564}
565
566
567/**
568 * Invalidates a guest page by physical address.
569 *
570 * @returns VBox status code.
571 * @param pVM The cross context VM structure.
572 * @param GCPhys Page to invalidate.
573 *
574 * @remarks Assumes the current instruction references this physical page
575 * though a virtual address!
576 */
577VMM_INT_DECL(int) HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
578{
579 if (!HMIsNestedPagingActive(pVM))
580 return VINF_SUCCESS;
581
582 /*
583 * AMD-V: Doesn't support invalidation with guest physical addresses.
584 *
585 * VT-x: Doesn't support invalidation with guest physical addresses.
586 * INVVPID instruction takes only a linear address while invept only flushes by EPT
587 * not individual addresses.
588 *
589 * We update the force flag and flush before the next VM-entry, see @bugref{6568}.
590 */
591 RT_NOREF(GCPhys);
592 /** @todo Remove or figure out to way to update the Phys STAT counter. */
593 /* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
594 return HMFlushTlbOnAllVCpus(pVM);
595}
596
597
598/**
599 * Checks if nested paging is enabled.
600 *
601 * @returns true if nested paging is active, false otherwise.
602 * @param pVM The cross context VM structure.
603 *
604 * @remarks Works before hmR3InitFinalizeR0.
605 */
606VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM)
607{
608 return HMIsEnabled(pVM) && pVM->hm.s.fNestedPaging;
609}
610
611
612/**
613 * Checks if both nested paging and unhampered guest execution are enabled.
614 *
615 * The almost complete guest execution in hardware is only applicable to VT-x.
616 *
617 * @returns true if we have both enabled, otherwise false.
618 * @param pVM The cross context VM structure.
619 *
620 * @remarks Works before hmR3InitFinalizeR0.
621 */
622VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM)
623{
624 return HMIsEnabled(pVM)
625 && pVM->hm.s.fNestedPaging
626 && ( pVM->hm.s.vmx.fUnrestrictedGuest
627 || pVM->hm.s.svm.fSupported);
628}
629
630
631/**
632 * Checks if this VM is using HM and is long-mode capable.
633 *
634 * Use VMR3IsLongModeAllowed() instead of this, when possible.
635 *
636 * @returns true if long mode is allowed, false otherwise.
637 * @param pVM The cross context VM structure.
638 * @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
639 */
640VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM)
641{
642 return HMIsEnabled(pVM) && pVM->hm.s.fAllow64BitGuests;
643}
644
645
646/**
647 * Checks if MSR bitmaps are active. It is assumed that when it's available
648 * it will be used as well.
649 *
650 * @returns true if MSR bitmaps are available, false otherwise.
651 * @param pVM The cross context VM structure.
652 */
653VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
654{
655 if (HMIsEnabled(pVM))
656 {
657 if (pVM->hm.s.svm.fSupported)
658 return true;
659
660 if ( pVM->hm.s.vmx.fSupported
661 && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
662 return true;
663 }
664 return false;
665}
666
667
668/**
669 * Checks if AMD-V is active.
670 *
671 * @returns true if AMD-V is active.
672 * @param pVM The cross context VM structure.
673 *
674 * @remarks Works before hmR3InitFinalizeR0.
675 */
676VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
677{
678 return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
679}
680
681
682/**
683 * Checks if VT-x is active.
684 *
685 * @returns true if VT-x is active.
686 * @param pVM The cross context VM structure.
687 *
688 * @remarks Works before hmR3InitFinalizeR0.
689 */
690VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
691{
692 return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
693}
694
695#endif /* !IN_RC */
696
697/**
698 * Checks if an interrupt event is currently pending.
699 *
700 * @returns Interrupt event pending state.
701 * @param pVM The cross context VM structure.
702 */
703VMM_INT_DECL(bool) HMHasPendingIrq(PVM pVM)
704{
705 PVMCPU pVCpu = VMMGetCpu(pVM);
706 return !!pVCpu->hm.s.Event.fPending;
707}
708
709
710/**
711 * Return the PAE PDPE entries.
712 *
713 * @returns Pointer to the PAE PDPE array.
714 * @param pVCpu The cross context virtual CPU structure.
715 */
716VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)
717{
718 return &pVCpu->hm.s.aPdpes[0];
719}
720
721
722/**
723 * Sets or clears the single instruction flag.
724 *
725 * When set, HM will try its best to return to ring-3 after executing a single
726 * instruction. This can be used for debugging. See also
727 * EMR3HmSingleInstruction.
728 *
729 * @returns The old flag state.
730 * @param pVM The cross context VM structure.
731 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
732 * @param fEnable The new flag state.
733 */
734VMM_INT_DECL(bool) HMSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
735{
736 VMCPU_ASSERT_EMT(pVCpu);
737 bool fOld = pVCpu->hm.s.fSingleInstruction;
738 pVCpu->hm.s.fSingleInstruction = fEnable;
739 pVCpu->hm.s.fUseDebugLoop = fEnable || pVM->hm.s.fUseDebugLoop;
740 return fOld;
741}
742
743
744#ifndef IN_RC
745/**
746 * Notification callback which is called whenever there is a chance that a CR3
747 * value might have changed.
748 *
749 * This is called by PGM.
750 *
751 * @param pVM The cross context VM structure.
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param enmShadowMode New shadow paging mode.
754 * @param enmGuestMode New guest paging mode.
755 */
756VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
757{
758# ifdef IN_RING3
759 /* Ignore page mode changes during state loading. */
760 if (VMR3GetState(pVM) == VMSTATE_LOADING)
761 return;
762# endif
763
764 pVCpu->hm.s.enmShadowMode = enmShadowMode;
765
766 /*
767 * If the guest left protected mode VMX execution, we'll have to be
768 * extra careful if/when the guest switches back to protected mode.
769 */
770 if (enmGuestMode == PGMMODE_REAL)
771 {
772 PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
773 pVmcsInfo->fWasInRealMode = true;
774 }
775
776# ifdef IN_RING0
777 /*
778 * We need to tickle SVM and VT-x state updates.
779 *
780 * Note! We could probably reduce this depending on what exactly changed.
781 */
782 if (VM_IS_HM_ENABLED(pVM))
783 {
784 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER); /* No recursion! */
785 uint64_t fChanged = HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 | HM_CHANGED_GUEST_EFER_MSR;
786 if (pVM->hm.s.svm.fSupported)
787 fChanged |= HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS;
788 else
789 fChanged |= HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS | HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
790 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
791 }
792# endif
793
794 Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
795 PGMGetModeName(enmShadowMode)));
796}
797#endif /* !IN_RC */
798
799
800/**
801 * Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
802 *
803 * This abstraction exists to insulate the support driver from including VMX
804 * structures from HM headers.
805 *
806 * @param pHwvirtMsrs The hardware-virtualization MSRs.
807 * @param pVmxMsrs Where to store the VMX MSRs.
808 */
809VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
810{
811 AssertReturnVoid(pHwvirtMsrs);
812 AssertReturnVoid(pVmxMsrs);
813 pVmxMsrs->u64FeatCtrl = pHwvirtMsrs->u.vmx.u64FeatCtrl;
814 pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
815 pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.u64PinCtls;
816 pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.u64ProcCtls;
817 pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.u64ProcCtls2;
818 pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.u64ExitCtls;
819 pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.u64EntryCtls;
820 pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.u64TruePinCtls;
821 pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.u64TrueProcCtls;
822 pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.u64TrueEntryCtls;
823 pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.u64TrueExitCtls;
824 pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
825 pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
826 pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
827 pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
828 pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
829 pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
830 pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
831 pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
832}
833
834
835/**
836 * Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
837 *
838 * This abstraction exists to insulate the support driver from including SVM
839 * structures from HM headers.
840 *
841 * @param pHwvirtMsrs The hardware-virtualization MSRs.
842 * @param pSvmMsrs Where to store the SVM MSRs.
843 */
844VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
845{
846 AssertReturnVoid(pHwvirtMsrs);
847 AssertReturnVoid(pSvmMsrs);
848 pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
849}
850
851
852/**
853 * Gets the name of a VT-x exit code.
854 *
855 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
856 * @param uExit The VT-x exit to name.
857 */
858VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
859{
860 if (uExit <= MAX_EXITREASON_VTX)
861 {
862 Assert(uExit < RT_ELEMENTS(g_apszVmxExitReasons));
863 return g_apszVmxExitReasons[uExit];
864 }
865 return NULL;
866}
867
868
869/**
870 * Gets the name of an AMD-V exit code.
871 *
872 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
873 * @param uExit The AMD-V exit to name.
874 */
875VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
876{
877 if (uExit <= MAX_EXITREASON_AMDV)
878 {
879 Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
880 return g_apszSvmExitReasons[uExit];
881 }
882 return hmSvmGetSpecialExitReasonDesc(uExit);
883}
884
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