HMAll.cpp@ 87497

Last change on this file since 87497 was 87497, checked in by vboxsync, 4 years ago
VMM/HMR3ResetCpu: Only touch the vmx fields if we're in vmx mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 37.4 KB

Line
1	/* $Id: HMAll.cpp 87497 2021-02-01 11:39:30Z vboxsync $ */
2	/** @file
3	* HM - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/hm_vmx.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <iprt/errcore.h>
31	#include <VBox/log.h>
32	#include <iprt/param.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/string.h>
36	#include <iprt/thread.h>
37	#include <iprt/x86.h>
38	#include <iprt/asm-amd64-x86.h>
39
40
41	/*********************************************************************************************************************************
42	* Global Variables *
43	*********************************************************************************************************************************/
44	#define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
45	#define EXIT_REASON_NIL() NULL
46
47	/** Exit reason descriptions for VT-x, used to describe statistics and exit
48	* history. */
49	static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
50	{
51	EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
52	EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
53	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
54	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
55	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
56	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
57	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
58	EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
59	EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
60	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
61	EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
62	EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instruction."),
63	EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
64	EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
65	EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
66	EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMC instruction."),
67	EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
68	EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
69	EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
70	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
71	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
72	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
73	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
74	EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
75	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
76	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
77	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
78	EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
79	EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
80	EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
81	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
82	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
83	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
84	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
85	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
86	EXIT_REASON_NIL(),
87	EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
88	EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
89	EXIT_REASON_NIL(),
90	EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
91	EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
92	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
93	EXIT_REASON_NIL(),
94	EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
95	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
96	EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
97	EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
98	EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
99	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
100	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
101	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
102	EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
103	EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
104	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
105	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
106	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
107	EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
108	EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
109	EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
110	EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
111	EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
112	EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
113	EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
114	EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
115	EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction."),
116	EXIT_REASON_NIL(),
117	EXIT_REASON(VMX_EXIT_SPP_EVENT , 66, "SPP-related event."),
118	EXIT_REASON(VMX_EXIT_UMWAIT , 67, "UMWAIT instruction."),
119	EXIT_REASON(VMX_EXIT_TPAUSE , 68, "TPAUSE instruction.")
120	};
121	/** Array index of the last valid VT-x exit reason. */
122	#define MAX_EXITREASON_VTX 68
123
124	/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
125	* statistics and exit history.
126	*
127	* @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
128	* this array doesn't contain the entire set of exit reasons, we
129	* handle them via hmSvmGetSpecialExitReasonDesc(). */
130	static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
131	{
132	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
133	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
134	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
135	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
136	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
137	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
138	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
139	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
140	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
141	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
142	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
143	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
144	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
145	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
146	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
147	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
148	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
149	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
150	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
151	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
152	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
153	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
154	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
155	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
156	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
157	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
158	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
159	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
160	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
161	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
162	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
163	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
164	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
165	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
166	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
167	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
168	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
169	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
170	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
171	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
172	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
173	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
174	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
175	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
176	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
177	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
178	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
179	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
180	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
181	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
182	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
183	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
184	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
185	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
186	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
187	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
188	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
189	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
190	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
191	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
192	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
193	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
194	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
195	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
196	EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
197	EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
198	EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
199	EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
200	EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
201	EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
202	EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
203	EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
204	EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
205	EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
206	EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
207	EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
208	EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
209	EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
210	EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
211	EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
212	EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
213	EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
214	EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
215	EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
216	EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
217	EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
218	EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
219	EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
220	EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
221	EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
222	EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
223	EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
224	EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
225	EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
226	EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
227	EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
228	EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
229	EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
230	EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
231	EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
232	EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
233	EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE , 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
234	EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
235	EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
236	EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
237	EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
238	EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
239	EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
240	EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
241	EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
242	EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
243	EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
244	EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
245	EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
246	EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
247	EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
248	EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
249	EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
250	EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
251	EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
252	EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
253	EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
254	EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
255	EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
256	EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
257	EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
258	EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
259	EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
260	EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
261	EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
262	EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
263	EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
264	EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
265	EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
266	EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
267	EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
268	EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
269	EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
270	EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
271	EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
272	EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
273	EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
274	EXIT_REASON(SVM_EXIT_RDPRU , 142, "RDPRU instruction."),
275	EXIT_REASON(SVM_EXIT_WRITE_EFER_TRAP, 143, "Write EFER (trap-like)."),
276	EXIT_REASON(SVM_EXIT_WRITE_CR0_TRAP , 144, "Write CR0 (trap-like)."),
277	EXIT_REASON(SVM_EXIT_WRITE_CR1_TRAP , 145, "Write CR1 (trap-like)."),
278	EXIT_REASON(SVM_EXIT_WRITE_CR2_TRAP , 146, "Write CR2 (trap-like)."),
279	EXIT_REASON(SVM_EXIT_WRITE_CR3_TRAP , 147, "Write CR3 (trap-like)."),
280	EXIT_REASON(SVM_EXIT_WRITE_CR4_TRAP , 148, "Write CR4 (trap-like)."),
281	EXIT_REASON(SVM_EXIT_WRITE_CR5_TRAP , 149, "Write CR5 (trap-like)."),
282	EXIT_REASON(SVM_EXIT_WRITE_CR6_TRAP , 150, "Write CR6 (trap-like)."),
283	EXIT_REASON(SVM_EXIT_WRITE_CR7_TRAP , 151, "Write CR7 (trap-like)."),
284	EXIT_REASON(SVM_EXIT_WRITE_CR8_TRAP , 152, "Write CR8 (trap-like)."),
285	EXIT_REASON(SVM_EXIT_WRITE_CR9_TRAP , 153, "Write CR9 (trap-like)."),
286	EXIT_REASON(SVM_EXIT_WRITE_CR10_TRAP, 154, "Write CR10 (trap-like)."),
287	EXIT_REASON(SVM_EXIT_WRITE_CR11_TRAP, 155, "Write CR11 (trap-like)."),
288	EXIT_REASON(SVM_EXIT_WRITE_CR12_TRAP, 156, "Write CR12 (trap-like)."),
289	EXIT_REASON(SVM_EXIT_WRITE_CR13_TRAP, 157, "Write CR13 (trap-like)."),
290	EXIT_REASON(SVM_EXIT_WRITE_CR14_TRAP, 158, "Write CR14 (trap-like)."),
291	EXIT_REASON(SVM_EXIT_WRITE_CR15_TRAP, 159, "Write CR15 (trap-like)."),
292	EXIT_REASON_NIL() ,
293	EXIT_REASON_NIL() ,
294	EXIT_REASON_NIL() ,
295	EXIT_REASON(SVM_EXIT_MCOMMIT , 163, "MCOMMIT instruction."),
296	};
297	/** Array index of the last valid AMD-V exit reason. */
298	#define MAX_EXITREASON_AMDV 163
299
300	/** Special exit reasons not covered in the array above. */
301	#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
302	#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
303	#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
304
305	/**
306	* Gets the SVM exit reason if it's one of the reasons not present in the @c
307	* g_apszSvmExitReasons array.
308	*
309	* @returns The exit reason or NULL if unknown.
310	* @param uExit The exit.
311	*/
312	DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
313	{
314	switch (uExit)
315	{
316	case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
317	case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
318	case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
319	}
320	return EXIT_REASON_NIL();
321	}
322	#undef EXIT_REASON_NIL
323	#undef EXIT_REASON
324
325
326	/**
327	* Checks whether HM (VT-x/AMD-V) is being used by this VM.
328	*
329	* @retval true if used.
330	* @retval false if software virtualization (raw-mode) is used.
331	* @param pVM The cross context VM structure.
332	* @sa HMIsEnabled, HMR3IsEnabled
333	* @internal
334	*/
335	VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
336	{
337	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
338	return pVM->fHMEnabled;
339	}
340
341
342	/**
343	* Checks if the guest is in a suitable state for hardware-assisted execution.
344	*
345	* @returns @c true if it is suitable, @c false otherwise.
346	* @param pVM The cross context VM structure.
347	* @param pVCpu The cross context virtual CPU structure.
348	* @param pCtx Pointer to the guest CPU context.
349	*
350	* @remarks @a pCtx can be a partial context created and not necessarily the same as
351	* pVCpu->cpum.GstCtx.
352	*/
353	VMMDECL(bool) HMCanExecuteGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
354	{
355	Assert(HMIsEnabled(pVM));
356
357	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
358	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
359	\|\| CPUMIsGuestInVmxNonRootMode(pCtx))
360	{
361	LogFunc(("In nested-guest mode - returning false"));
362	return false;
363	}
364	#endif
365
366	/* AMD-V supports real & protected mode with or without paging. */
367	if (pVM->hm.s.svm.fEnabled)
368	{
369	pVCpu->hm.s.fActive = true;
370	return true;
371	}
372
373	bool rc = HMCanExecuteVmxGuest(pVM, pVCpu, pCtx);
374	LogFlowFunc(("returning %RTbool\n", rc));
375	return rc;
376	}
377
378
379	/**
380	* Queues a guest page for invalidation.
381	*
382	* @returns VBox status code.
383	* @param pVCpu The cross context virtual CPU structure.
384	* @param GCVirt Page to invalidate.
385	*/
386	static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
387	{
388	/* Nothing to do if a TLB flush is already pending */
389	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
390	return;
391	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
392	NOREF(GCVirt);
393	}
394
395
396	/**
397	* Invalidates a guest page.
398	*
399	* @returns VBox status code.
400	* @param pVCpu The cross context virtual CPU structure.
401	* @param GCVirt Page to invalidate.
402	*/
403	VMM_INT_DECL(int) HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
404	{
405	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
406	#ifdef IN_RING0
407	return HMR0InvalidatePage(pVCpu, GCVirt);
408	#else
409	hmQueueInvlPage(pVCpu, GCVirt);
410	return VINF_SUCCESS;
411	#endif
412	}
413
414
415	#ifdef IN_RING0
416
417	/**
418	* Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
419	*
420	*/
421	static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void pvUser1, void pvUser2)
422	{
423	NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
424	return;
425	}
426
427
428	/**
429	* Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
430	*/
431	static void hmR0PokeCpu(PVMCPUCC pVCpu, RTCPUID idHostCpu)
432	{
433	uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits);
434
435	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
436	int rc = RTMpPokeCpu(idHostCpu);
437	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
438
439	/* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
440	back to a less efficient implementation (broadcast). */
441	if (rc == VERR_NOT_SUPPORTED)
442	{
443	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
444	/* synchronous. */
445	RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
446	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
447	}
448	else
449	{
450	if (rc == VINF_SUCCESS)
451	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
452	else
453	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
454
455	/** @todo If more than one CPU is going to be poked, we could optimize this
456	* operation by poking them first and wait afterwards. Would require
457	* recording who to poke and their current cWorldSwitchExits values,
458	* that's something not suitable for stack... So, pVCpu->hm.s.something
459	* then. */
460	/* Spin until the VCPU has switched back (poking is async). */
461	while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
462	&& cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits))
463	ASMNopPause();
464
465	if (rc == VINF_SUCCESS)
466	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
467	else
468	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
469	}
470	}
471
472	#endif /* IN_RING0 */
473
474	/**
475	* Flushes the guest TLB.
476	*
477	* @returns VBox status code.
478	* @param pVCpu The cross context virtual CPU structure.
479	*/
480	VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
481	{
482	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
483	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
484	return VINF_SUCCESS;
485	}
486
487
488	/**
489	* Poke an EMT so it can perform the appropriate TLB shootdowns.
490	*
491	* @param pVCpu The cross context virtual CPU structure of the
492	* EMT poke.
493	* @param fAccountFlushStat Whether to account the call to
494	* StatTlbShootdownFlush or StatTlbShootdown.
495	*/
496	static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
497	{
498	if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
499	{
500	if (fAccountFlushStat)
501	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
502	else
503	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
504	#ifdef IN_RING0
505	RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
506	if (idHostCpu != NIL_RTCPUID)
507	hmR0PokeCpu(pVCpu, idHostCpu);
508	#else
509	VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
510	#endif
511	}
512	else
513	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
514	}
515
516
517	/**
518	* Invalidates a guest page on all VCPUs.
519	*
520	* @returns VBox status code.
521	* @param pVM The cross context VM structure.
522	* @param GCVirt Page to invalidate.
523	*/
524	VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVMCC pVM, RTGCPTR GCVirt)
525	{
526	/*
527	* The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
528	* host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
529	*
530	* This is the reason why we do not care about thread preemption here and just
531	* execute HMInvalidatePage() assuming it might be the 'right' CPU.
532	*/
533	VMCPUID const idCurCpu = VMMGetCpuId(pVM);
534	STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idCurCpu)->hm.s.StatFlushPage);
535
536	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
537	{
538	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
539
540	/* Nothing to do if a TLB flush is already pending; the VCPU should
541	have already been poked if it were active. */
542	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
543	continue;
544
545	if (pVCpu->idCpu == idCurCpu)
546	HMInvalidatePage(pVCpu, GCVirt);
547	else
548	{
549	hmQueueInvlPage(pVCpu, GCVirt);
550	hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
551	}
552	}
553
554	return VINF_SUCCESS;
555	}
556
557
558	/**
559	* Flush the TLBs of all VCPUs.
560	*
561	* @returns VBox status code.
562	* @param pVM The cross context VM structure.
563	*/
564	VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVMCC pVM)
565	{
566	if (pVM->cCpus == 1)
567	return HMFlushTlb(VMCC_GET_CPU_0(pVM));
568
569	VMCPUID const idThisCpu = VMMGetCpuId(pVM);
570
571	STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idThisCpu)->hm.s.StatFlushTlb);
572
573	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
574	{
575	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
576
577	/* Nothing to do if a TLB flush is already pending; the VCPU should
578	have already been poked if it were active. */
579	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
580	{
581	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
582	if (idThisCpu != idCpu)
583	hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
584	}
585	}
586
587	return VINF_SUCCESS;
588	}
589
590
591	/**
592	* Invalidates a guest page by physical address.
593	*
594	* @returns VBox status code.
595	* @param pVM The cross context VM structure.
596	* @param GCPhys Page to invalidate.
597	*
598	* @remarks Assumes the current instruction references this physical page
599	* though a virtual address!
600	*/
601	VMM_INT_DECL(int) HMInvalidatePhysPage(PVMCC pVM, RTGCPHYS GCPhys)
602	{
603	if (!HMIsNestedPagingActive(pVM))
604	return VINF_SUCCESS;
605
606	/*
607	* AMD-V: Doesn't support invalidation with guest physical addresses.
608	*
609	* VT-x: Doesn't support invalidation with guest physical addresses.
610	* INVVPID instruction takes only a linear address while invept only flushes by EPT
611	* not individual addresses.
612	*
613	* We update the force flag and flush before the next VM-entry, see @bugref{6568}.
614	*/
615	RT_NOREF(GCPhys);
616	/** @todo Remove or figure out to way to update the Phys STAT counter. */
617	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
618	return HMFlushTlbOnAllVCpus(pVM);
619	}
620
621
622	/**
623	* Checks if nested paging is enabled.
624	*
625	* @returns true if nested paging is active, false otherwise.
626	* @param pVM The cross context VM structure.
627	*
628	* @remarks Works before hmR3InitFinalizeR0.
629	*/
630	VMM_INT_DECL(bool) HMIsNestedPagingActive(PVM pVM)
631	{
632	return HMIsEnabled(pVM) && pVM->hm.s.fNestedPaging;
633	}
634
635
636	/**
637	* Checks if both nested paging and unhampered guest execution are enabled.
638	*
639	* The almost complete guest execution in hardware is only applicable to VT-x.
640	*
641	* @returns true if we have both enabled, otherwise false.
642	* @param pVM The cross context VM structure.
643	*
644	* @remarks Works before hmR3InitFinalizeR0.
645	*/
646	VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM)
647	{
648	return HMIsEnabled(pVM)
649	&& pVM->hm.s.fNestedPaging
650	&& ( pVM->hm.s.vmx.fUnrestrictedGuest
651	\|\| pVM->hm.s.svm.fSupported);
652	}
653
654
655	/**
656	* Checks if this VM is using HM and is long-mode capable.
657	*
658	* Use VMR3IsLongModeAllowed() instead of this, when possible.
659	*
660	* @returns true if long mode is allowed, false otherwise.
661	* @param pVM The cross context VM structure.
662	* @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
663	*/
664	VMM_INT_DECL(bool) HMIsLongModeAllowed(PVM pVM)
665	{
666	return HMIsEnabled(pVM) && pVM->hm.s.fAllow64BitGuests;
667	}
668
669
670	/**
671	* Checks if MSR bitmaps are active. It is assumed that when it's available
672	* it will be used as well.
673	*
674	* @returns true if MSR bitmaps are available, false otherwise.
675	* @param pVM The cross context VM structure.
676	*/
677	VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
678	{
679	if (HMIsEnabled(pVM))
680	{
681	if (pVM->hm.s.svm.fSupported)
682	return true;
683
684	if ( pVM->hm.s.vmx.fSupported
685	&& (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
686	return true;
687	}
688	return false;
689	}
690
691
692	/**
693	* Checks if AMD-V is active.
694	*
695	* @returns true if AMD-V is active.
696	* @param pVM The cross context VM structure.
697	*
698	* @remarks Works before hmR3InitFinalizeR0.
699	*/
700	VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
701	{
702	return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
703	}
704
705
706	/**
707	* Checks if VT-x is active.
708	*
709	* @returns true if VT-x is active.
710	* @param pVM The cross context VM structure.
711	*
712	* @remarks Works before hmR3InitFinalizeR0.
713	*/
714	VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
715	{
716	return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
717	}
718
719
720	/**
721	* Checks if an interrupt event is currently pending.
722	*
723	* @returns Interrupt event pending state.
724	* @param pVM The cross context VM structure.
725	*/
726	VMM_INT_DECL(bool) HMHasPendingIrq(PVMCC pVM)
727	{
728	PVMCPUCC pVCpu = VMMGetCpu(pVM);
729	return !!pVCpu->hm.s.Event.fPending;
730	}
731
732
733	/**
734	* Return the PAE PDPE entries.
735	*
736	* @returns Pointer to the PAE PDPE array.
737	* @param pVCpu The cross context virtual CPU structure.
738	*/
739	VMM_INT_DECL(PX86PDPE) HMGetPaePdpes(PVMCPU pVCpu)
740	{
741	return &pVCpu->hm.s.aPdpes[0];
742	}
743
744
745	/**
746	* Sets or clears the single instruction flag.
747	*
748	* When set, HM will try its best to return to ring-3 after executing a single
749	* instruction. This can be used for debugging. See also
750	* EMR3HmSingleInstruction.
751	*
752	* @returns The old flag state.
753	* @param pVM The cross context VM structure.
754	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
755	* @param fEnable The new flag state.
756	*/
757	VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable)
758	{
759	VMCPU_ASSERT_EMT(pVCpu);
760	bool fOld = pVCpu->hm.s.fSingleInstruction;
761	pVCpu->hm.s.fSingleInstruction = fEnable;
762	pVCpu->hm.s.fUseDebugLoop = fEnable \|\| pVM->hm.s.fUseDebugLoop;
763	return fOld;
764	}
765
766
767	/**
768	* Notification callback which is called whenever there is a chance that a CR3
769	* value might have changed.
770	*
771	* This is called by PGM.
772	*
773	* @param pVM The cross context VM structure.
774	* @param pVCpu The cross context virtual CPU structure.
775	* @param enmShadowMode New shadow paging mode.
776	* @param enmGuestMode New guest paging mode.
777	*/
778	VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPUCC pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
779	{
780	#ifdef IN_RING3
781	/* Ignore page mode changes during state loading. */
782	if (VMR3GetState(pVM) == VMSTATE_LOADING)
783	return;
784	#endif
785
786	pVCpu->hm.s.enmShadowMode = enmShadowMode;
787
788	/*
789	* If the guest left protected mode VMX execution, we'll have to be
790	* extra careful if/when the guest switches back to protected mode.
791	*/
792	if ( enmGuestMode == PGMMODE_REAL
793	&& pVM->hm.s.vmx.fEnabled)
794	{
795	PVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
796	pVmcsInfoShared->fWasInRealMode = true;
797	}
798
799	#ifdef IN_RING0
800	/*
801	* We need to tickle SVM and VT-x state updates.
802	*
803	* Note! We could probably reduce this depending on what exactly changed.
804	*/
805	if (VM_IS_HM_ENABLED(pVM))
806	{
807	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER); /* No recursion! */
808	uint64_t fChanged = HM_CHANGED_GUEST_CR0 \| HM_CHANGED_GUEST_CR3 \| HM_CHANGED_GUEST_CR4 \| HM_CHANGED_GUEST_EFER_MSR;
809	if (pVM->hm.s.svm.fSupported)
810	fChanged \|= HM_CHANGED_SVM_XCPT_INTERCEPTS;
811	else
812	fChanged \|= HM_CHANGED_VMX_XCPT_INTERCEPTS \| HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
813	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
814	}
815	#endif
816
817	Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
818	PGMGetModeName(enmShadowMode)));
819	}
820
821
822	/**
823	* Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
824	*
825	* This abstraction exists to insulate the support driver from including VMX
826	* structures from HM headers.
827	*
828	* @param pHwvirtMsrs The hardware-virtualization MSRs.
829	* @param pVmxMsrs Where to store the VMX MSRs.
830	*/
831	VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
832	{
833	AssertReturnVoid(pHwvirtMsrs);
834	AssertReturnVoid(pVmxMsrs);
835	pVmxMsrs->u64FeatCtrl = pHwvirtMsrs->u.vmx.u64FeatCtrl;
836	pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
837	pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.u64PinCtls;
838	pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.u64ProcCtls;
839	pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.u64ProcCtls2;
840	pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.u64ExitCtls;
841	pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.u64EntryCtls;
842	pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.u64TruePinCtls;
843	pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.u64TrueProcCtls;
844	pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.u64TrueEntryCtls;
845	pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.u64TrueExitCtls;
846	pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
847	pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
848	pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
849	pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
850	pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
851	pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
852	pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
853	pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
854	}
855
856
857	/**
858	* Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
859	*
860	* This abstraction exists to insulate the support driver from including SVM
861	* structures from HM headers.
862	*
863	* @param pHwvirtMsrs The hardware-virtualization MSRs.
864	* @param pSvmMsrs Where to store the SVM MSRs.
865	*/
866	VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
867	{
868	AssertReturnVoid(pHwvirtMsrs);
869	AssertReturnVoid(pSvmMsrs);
870	pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
871	}
872
873
874	/**
875	* Gets the name of a VT-x exit code.
876	*
877	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
878	* @param uExit The VT-x exit to name.
879	*/
880	VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
881	{
882	uint16_t const uReason = VMX_EXIT_REASON_BASIC(uExit);
883	if (uReason <= MAX_EXITREASON_VTX)
884	{
885	Assert(uReason < RT_ELEMENTS(g_apszVmxExitReasons));
886	return g_apszVmxExitReasons[uReason];
887	}
888	return NULL;
889	}
890
891
892	/**
893	* Gets the name of an AMD-V exit code.
894	*
895	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
896	* @param uExit The AMD-V exit to name.
897	*/
898	VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
899	{
900	if (uExit <= MAX_EXITREASON_AMDV)
901	{
902	Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
903	return g_apszSvmExitReasons[uExit];
904	}
905	return hmSvmGetSpecialExitReasonDesc(uExit);
906	}
907

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp@ 87497

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