HMSVMAll.cpp@ 71529

Last change on this file since 71529 was 71529, checked in by vboxsync, 7 years ago
VMM/HM: Fixes to MSRPM bit accesses. Implemented merging of guest and nested-guest MSRPMs. Other nits and cleanups.
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1	/* $Id: HMSVMAll.cpp 71529 2018-03-28 06:32:43Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/hm_svm.h>
31
32
33	#ifndef IN_RC
34	/**
35	* Emulates a simple MOV TPR (CR8) instruction.
36	*
37	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
38	* at EIP and does the required.
39	*
40	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
41	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
42	* TPR). See hmR3ReplaceTprInstr() for the details.
43	*
44	* @returns VBox status code.
45	* @retval VINF_SUCCESS if the access was handled successfully.
46	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
47	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
48	*
49	* @param pVCpu The cross context virtual CPU structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param pfUpdateRipAndRF Whether the guest RIP/EIP has been updated as
52	* part of the TPR patch operation.
53	*/
54	static int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdateRipAndRF)
55	{
56	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
57
58	/*
59	* We do this in a loop as we increment the RIP after a successful emulation
60	* and the new RIP may be a patched instruction which needs emulation as well.
61	*/
62	bool fUpdateRipAndRF = false;
63	bool fPatchFound = false;
64	PVM pVM = pVCpu->CTX_SUFF(pVM);
65	for (;;)
66	{
67	bool fPending;
68	uint8_t u8Tpr;
69
70	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
71	if (!pPatch)
72	break;
73
74	fPatchFound = true;
75	switch (pPatch->enmType)
76	{
77	case HMTPRINSTR_READ:
78	{
79	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
80	AssertRC(rc);
81
82	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
83	AssertRC(rc);
84	pCtx->rip += pPatch->cbOp;
85	pCtx->eflags.Bits.u1RF = 0;
86	fUpdateRipAndRF = true;
87	break;
88	}
89
90	case HMTPRINSTR_WRITE_REG:
91	case HMTPRINSTR_WRITE_IMM:
92	{
93	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
94	{
95	uint32_t u32Val;
96	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
97	AssertRC(rc);
98	u8Tpr = u32Val;
99	}
100	else
101	u8Tpr = (uint8_t)pPatch->uSrcOperand;
102
103	int rc2 = APICSetTpr(pVCpu, u8Tpr);
104	AssertRC(rc2);
105	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
106
107	pCtx->rip += pPatch->cbOp;
108	pCtx->eflags.Bits.u1RF = 0;
109	fUpdateRipAndRF = true;
110	break;
111	}
112
113	default:
114	{
115	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
116	pVCpu->hm.s.u32HMError = pPatch->enmType;
117	*pfUpdateRipAndRF = fUpdateRipAndRF;
118	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
119	}
120	}
121	}
122
123	*pfUpdateRipAndRF = fUpdateRipAndRF;
124	if (fPatchFound)
125	return VINF_SUCCESS;
126	return VERR_NOT_FOUND;
127	}
128
129
130	/**
131	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
132	* in IEM).
133	*
134	* @param pVCpu The cross context virtual CPU structure.
135	* @param pCtx Pointer to the guest-CPU context.
136	*
137	* @sa hmR0SvmVmRunCacheVmcb.
138	*/
139	VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx)
140	{
141	/*
142	* Restore the nested-guest VMCB fields which have been modified for executing
143	* the nested-guest under SVM R0.
144	*/
145	if (pCtx->hwvirt.svm.fHMCachedVmcb)
146	{
147	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
148	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
149	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
150	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
151
152	/*
153	* The fields that are guaranteed to be read-only during SVM guest execution
154	* can safely be restored from our VMCB cache. Other fields like control registers
155	* are already updated by hardware-assisted SVM or by IEM. We only restore those
156	* fields that are potentially modified by hardware-assisted SVM.
157	*/
158	pVmcbNstGstCtrl->u16InterceptRdCRx = pNstGstVmcbCache->u16InterceptRdCRx;
159	pVmcbNstGstCtrl->u16InterceptWrCRx = pNstGstVmcbCache->u16InterceptWrCRx;
160	pVmcbNstGstCtrl->u16InterceptRdDRx = pNstGstVmcbCache->u16InterceptRdDRx;
161	pVmcbNstGstCtrl->u16InterceptWrDRx = pNstGstVmcbCache->u16InterceptWrDRx;
162	pVmcbNstGstCtrl->u32InterceptXcpt = pNstGstVmcbCache->u32InterceptXcpt;
163	pVmcbNstGstCtrl->u64InterceptCtrl = pNstGstVmcbCache->u64InterceptCtrl;
164	pVmcbNstGstState->u64DBGCTL = pNstGstVmcbCache->u64DBGCTL;
165	pVmcbNstGstCtrl->u32VmcbCleanBits = pNstGstVmcbCache->u32VmcbCleanBits;
166	pVmcbNstGstCtrl->u64IOPMPhysAddr = pNstGstVmcbCache->u64IOPMPhysAddr;
167	pVmcbNstGstCtrl->u64MSRPMPhysAddr = pNstGstVmcbCache->u64MSRPMPhysAddr;
168	pVmcbNstGstCtrl->u64TSCOffset = pNstGstVmcbCache->u64TSCOffset;
169	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pNstGstVmcbCache->fVIntrMasking;
170	pVmcbNstGstCtrl->TLBCtrl = pNstGstVmcbCache->TLBCtrl;
171	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pNstGstVmcbCache->u1NestedPaging;
172	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pNstGstVmcbCache->u1LbrVirt;
173	pCtx->hwvirt.svm.fHMCachedVmcb = false;
174	}
175
176	/*
177	* Currently, VMRUN, #VMEXIT transitions involves trips to ring-3 that would flag a full
178	* CPU state change. However, if we exit to ring-3 in response to receiving a physical
179	* interrupt, we skip signaling any CPU state change as normally no change
180	* is done to the execution state (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
181	* However, with nested-guests, the state can change for e.g., we might perform a
182	* SVM_EXIT_INTR #VMEXIT for the nested-guest in ring-3. Hence we signal a full CPU
183	* state change here.
184	*/
185	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
186	}
187
188
189	/**
190	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
191	* enabled for the VM.
192	*
193	* @returns @c true if VGIF is enabled, @c false otherwise.
194	* @param pVM The cross context VM structure.
195	*
196	* @remarks This value returned by this functions is expected by the callers not
197	* to change throughout the lifetime of the VM.
198	*/
199	VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM)
200	{
201	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
202	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
203
204	return HMIsEnabled(pVM) && fVGif && fUseVGif;
205	}
206
207
208	/**
209	* Applies the TSC offset of an SVM nested-guest if any and returns the new TSC
210	* value for the nested-guest.
211	*
212	* @returns The TSC offset after applying any nested-guest TSC offset.
213	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
214	* @param uTicks The guest TSC.
215	*
216	* @remarks This function looks at the VMCB cache rather than directly at the
217	* nested-guest VMCB. The latter may have been modified for executing
218	* using hardware-assisted SVM.
219	*
220	* @sa CPUMApplyNestedGuestTscOffset.
221	*/
222	VMM_INT_DECL(uint64_t) HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks)
223	{
224	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
225	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
226	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
227	NOREF(pCtx);
228	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
229	return uTicks + pVmcbNstGstCache->u64TSCOffset;
230	}
231	#endif /* !IN_RC */
232
233
234	/**
235	* Performs the operations necessary that are part of the vmmcall instruction
236	* execution in the guest.
237	*
238	* @returns Strict VBox status code (i.e. informational status codes too).
239	* @retval VINF_SUCCESS on successful handling, no \#UD needs to be thrown,
240	* update RIP and eflags.RF depending on @a pfUpdatedRipAndRF and
241	* continue guest execution.
242	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
243	* RIP.
244	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
245	*
246	* @param pVCpu The cross context virtual CPU structure.
247	* @param pCtx Pointer to the guest-CPU context.
248	* @param pfUpdatedRipAndRF Whether the guest RIP/EIP has been updated as
249	* part of handling the VMMCALL operation.
250	*/
251	VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdatedRipAndRF)
252	{
253	#ifndef IN_RC
254	/*
255	* TPR patched instruction emulation for 32-bit guests.
256	*/
257	PVM pVM = pVCpu->CTX_SUFF(pVM);
258	if (pVM->hm.s.fTprPatchingAllowed)
259	{
260	int rc = hmSvmEmulateMovTpr(pVCpu, pCtx, pfUpdatedRipAndRF);
261	if (RT_SUCCESS(rc))
262	return VINF_SUCCESS;
263
264	if (rc != VERR_NOT_FOUND)
265	{
266	Log(("hmSvmExitVmmCall: hmSvmEmulateMovTpr returns %Rrc\n", rc));
267	return rc;
268	}
269	}
270	#endif
271
272	/*
273	* Paravirtualized hypercalls.
274	*/
275	*pfUpdatedRipAndRF = false;
276	if (pVCpu->hm.s.fHypercallsEnabled)
277	return GIMHypercall(pVCpu, pCtx);
278
279	return VERR_NOT_AVAILABLE;
280	}
281
282
283	/**
284	* Converts an SVM event type to a TRPM event type.
285	*
286	* @returns The TRPM event type.
287	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
288	* of recognized trap types.
289	*
290	* @param pEvent Pointer to the SVM event.
291	*/
292	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent)
293	{
294	uint8_t const uType = pEvent->n.u3Type;
295	switch (uType)
296	{
297	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
298	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
299	case SVM_EVENT_EXCEPTION:
300	case SVM_EVENT_NMI: return TRPM_TRAP;
301	default:
302	break;
303	}
304	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
305	return TRPM_32BIT_HACK;
306	}
307
308
309	/**
310	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
311	*
312	* @returns VBox status code.
313	* @param idMsr The MSR being requested.
314	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
315	* bitmap for @a idMsr.
316	* @param puMsrpmBit Where to store the bit offset starting at the byte
317	* returned in @a pbOffMsrpm.
318	*/
319	VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit)
320	{
321	Assert(pbOffMsrpm);
322	Assert(puMsrpmBit);
323
324	/*
325	* MSRPM Layout:
326	* Byte offset MSR range
327	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
328	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
329	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
330	* 0x1800 - 0x1fff Reserved
331	*
332	* Each MSR is represented by 2 permission bits (read and write).
333	*/
334	if (idMsr <= 0x00001fff)
335	{
336	/* Pentium-compatible MSRs. */
337	uint32_t const bitoffMsr = idMsr << 1;
338	*pbOffMsrpm = bitoffMsr >> 3;
339	*puMsrpmBit = bitoffMsr & 7;
340	return VINF_SUCCESS;
341	}
342
343	if ( idMsr >= 0xc0000000
344	&& idMsr <= 0xc0001fff)
345	{
346	/* AMD Sixth Generation x86 Processor MSRs. */
347	uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
348	*pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
349	*puMsrpmBit = bitoffMsr & 7;
350	return VINF_SUCCESS;
351	}
352
353	if ( idMsr >= 0xc0010000
354	&& idMsr <= 0xc0011fff)
355	{
356	/* AMD Seventh and Eighth Generation Processor MSRs. */
357	uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
358	*pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
359	*puMsrpmBit = bitoffMsr & 7;
360	return VINF_SUCCESS;
361	}
362
363	*pbOffMsrpm = 0;
364	*puMsrpmBit = 0;
365	return VERR_OUT_OF_RANGE;
366	}
367
368
369	/**
370	* Determines whether an IOIO intercept is active for the nested-guest or not.
371	*
372	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
373	* @param u16Port The IO port being accessed.
374	* @param enmIoType The type of IO access.
375	* @param cbReg The IO operand size in bytes.
376	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
377	* @param iEffSeg The effective segment number.
378	* @param fRep Whether this is a repeating IO instruction (REP prefix).
379	* @param fStrIo Whether this is a string IO instruction.
380	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
381	* Optional, can be NULL.
382	*/
383	VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
384	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
385	PSVMIOIOEXITINFO pIoExitInfo)
386	{
387	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
388	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
389
390	/*
391	* The IOPM layout:
392	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
393	* two 4K pages.
394	*
395	* For IO instructions that access more than a single byte, the permission bits
396	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
397	*
398	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
399	* we need 3 extra bits beyond the second 4K page.
400	*/
401	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
402
403	uint16_t const offIopm = u16Port >> 3;
404	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
405	uint8_t const cShift = u16Port - (offIopm << 3);
406	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
407
408	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
409	Assert(pbIopm);
410	pbIopm += offIopm;
411	uint16_t const u16Iopm = (uint16_t )pbIopm;
412	if (u16Iopm & fIopmMask)
413	{
414	if (pIoExitInfo)
415	{
416	static const uint32_t s_auIoOpSize[] =
417	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
418
419	static const uint32_t s_auIoAddrSize[] =
420	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
421
422	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
423	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
424	pIoExitInfo->n.u1STR = fStrIo;
425	pIoExitInfo->n.u1REP = fRep;
426	pIoExitInfo->n.u3SEG = iEffSeg & 7;
427	pIoExitInfo->n.u1Type = enmIoType;
428	pIoExitInfo->n.u16Port = u16Port;
429	}
430	return true;
431	}
432
433	/** @todo remove later (for debugging as VirtualBox always traps all IO
434	* intercepts). */
435	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
436	return false;
437	}
438
439
440	/**
441	* Checks if the guest VMCB has the specified ctrl/instruction intercept active.
442	*
443	* @returns @c true if in intercept is set, @c false otherwise.
444	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
445	* @param pCtx Pointer to the context.
446	* @param fIntercept The SVM control/instruction intercept, see
447	* SVM_CTRL_INTERCEPT_*.
448	*/
449	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
450	{
451	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
452	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
453	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
454	}
455
456
457	/**
458	* Checks if the guest VMCB has the specified CR read intercept active.
459	*
460	* @returns @c true if in intercept is set, @c false otherwise.
461	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
462	* @param pCtx Pointer to the context.
463	* @param uCr The CR register number (0 to 15).
464	*/
465	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
466	{
467	Assert(uCr < 16);
468	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
469	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
470	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
471	}
472
473
474	/**
475	* Checks if the guest VMCB has the specified CR write intercept
476	* active.
477	*
478	* @returns @c true if in intercept is set, @c false otherwise.
479	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
480	* @param pCtx Pointer to the context.
481	* @param uCr The CR register number (0 to 15).
482	*/
483	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
484	{
485	Assert(uCr < 16);
486	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
487	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
488	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
489	}
490
491
492	/**
493	* Checks if the guest VMCB has the specified DR read intercept
494	* active.
495	*
496	* @returns @c true if in intercept is set, @c false otherwise.
497	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
498	* @param pCtx Pointer to the context.
499	* @param uDr The DR register number (0 to 15).
500	*/
501	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
502	{
503	Assert(uDr < 16);
504	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
505	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
506	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
507	}
508
509
510	/**
511	* Checks if the guest VMCB has the specified DR write intercept active.
512	*
513	* @returns @c true if in intercept is set, @c false otherwise.
514	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
515	* @param pCtx Pointer to the context.
516	* @param uDr The DR register number (0 to 15).
517	*/
518	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
519	{
520	Assert(uDr < 16);
521	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
522	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
523	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
524	}
525
526
527	/**
528	* Checks if the guest VMCB has the specified exception intercept active.
529	*
530	* @returns true if in intercept is active, false otherwise.
531	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
532	* @param pCtx Pointer to the context.
533	* @param uVector The exception / interrupt vector.
534	*/
535	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
536	{
537	Assert(uVector < 32);
538	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
539	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
540	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
541	}
542
543
544	/**
545	* Checks whether the SVM nested-guest is in a state to receive physical (APIC)
546	* interrupts.
547	*
548	* @returns true if it's ready, false otherwise.
549	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
550	* @param pCtx The guest-CPU context.
551	*
552	* @remarks This function looks at the VMCB cache rather than directly at the
553	* nested-guest VMCB. The latter may have been modified for executing
554	* using hardware-assisted SVM.
555	*
556	* @sa CPUMCanSvmNstGstTakePhysIntr.
557	*/
558	VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
559	{
560	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
561	Assert(pCtx->hwvirt.fGif);
562	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
563	X86EFLAGS fEFlags;
564	if (pVmcbNstGstCache->fVIntrMasking)
565	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
566	else
567	fEFlags.u = pCtx->eflags.u;
568	return fEFlags.Bits.u1IF;
569	}
570
571
572	/**
573	* Checks whether the SVM nested-guest is in a state to receive virtual (setup
574	* for injection by VMRUN instruction) interrupts.
575	*
576	* @returns true if it's ready, false otherwise.
577	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
578	* @param pCtx The guest-CPU context.
579	*
580	* @remarks This function looks at the VMCB cache rather than directly at the
581	* nested-guest VMCB. The latter may have been modified for executing
582	* using hardware-assisted SVM.
583	*
584	* @sa CPUMCanSvmNstGstTakeVirtIntr.
585	*/
586	VMM_INT_DECL(bool) HMCanSvmNstGstTakeVirtIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
587	{
588	#ifdef IN_RC
589	RT_NOREF2(pVCpu, pCtx);
590	AssertReleaseFailedReturn(false);
591	#else
592	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
593	Assert(pCtx->hwvirt.fGif);
594	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
595
596	PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
597	if ( !pVmcbCtrl->IntCtrl.n.u1IgnoreTPR
598	&& pVmcbCtrl->IntCtrl.n.u4VIntrPrio <= pVmcbCtrl->IntCtrl.n.u8VTPR)
599	return false;
600
601	X86EFLAGS fEFlags;
602	if (pVmcbNstGstCache->fVIntrMasking)
603	fEFlags.u = pCtx->eflags.u;
604	else
605	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
606	return fEFlags.Bits.u1IF;
607	#endif
608	}
609

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 71529

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