HMSVMAll.cpp@ 66974

Last change on this file since 66974 was 66751, checked in by vboxsync, 8 years ago
VMM: Nested Hw.virt: Adjusted the helper functions for use with nested-guest interrupt injection.
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File size: 49.2 KB

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1	/* $Id: HMSVMAll.cpp 66751 2017-05-02 17:12:08Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/hm_svm.h>
31
32
33	#ifndef IN_RC
34	/**
35	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
36	* guests. This simply looks up the patch record at EIP and does the required.
37	*
38	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
39	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
40	* TPR). See hmR3ReplaceTprInstr() for the details.
41	*
42	* @returns VBox status code.
43	* @retval VINF_SUCCESS if the access was handled successfully.
44	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
45	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
46	*
47	* @param pVCpu The cross context virtual CPU structure.
48	* @param pCtx Pointer to the guest-CPU context.
49	* @param pfUpdateRipAndRF Whether the guest RIP/EIP has been updated as
50	* part of the TPR patch operation.
51	*/
52	static int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdateRipAndRF)
53	{
54	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
55
56	/*
57	* We do this in a loop as we increment the RIP after a successful emulation
58	* and the new RIP may be a patched instruction which needs emulation as well.
59	*/
60	bool fUpdateRipAndRF = false;
61	bool fPatchFound = false;
62	PVM pVM = pVCpu->CTX_SUFF(pVM);
63	for (;;)
64	{
65	bool fPending;
66	uint8_t u8Tpr;
67
68	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
69	if (!pPatch)
70	break;
71
72	fPatchFound = true;
73	switch (pPatch->enmType)
74	{
75	case HMTPRINSTR_READ:
76	{
77	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
78	AssertRC(rc);
79
80	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
81	AssertRC(rc);
82	pCtx->rip += pPatch->cbOp;
83	pCtx->eflags.Bits.u1RF = 0;
84	fUpdateRipAndRF = true;
85	break;
86	}
87
88	case HMTPRINSTR_WRITE_REG:
89	case HMTPRINSTR_WRITE_IMM:
90	{
91	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
92	{
93	uint32_t u32Val;
94	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
95	AssertRC(rc);
96	u8Tpr = u32Val;
97	}
98	else
99	u8Tpr = (uint8_t)pPatch->uSrcOperand;
100
101	int rc2 = APICSetTpr(pVCpu, u8Tpr);
102	AssertRC(rc2);
103	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
104
105	pCtx->rip += pPatch->cbOp;
106	pCtx->eflags.Bits.u1RF = 0;
107	fUpdateRipAndRF = true;
108	break;
109	}
110
111	default:
112	{
113	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
114	pVCpu->hm.s.u32HMError = pPatch->enmType;
115	*pfUpdateRipAndRF = fUpdateRipAndRF;
116	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
117	}
118	}
119	}
120
121	*pfUpdateRipAndRF = fUpdateRipAndRF;
122	if (fPatchFound)
123	return VINF_SUCCESS;
124	return VERR_NOT_FOUND;
125	}
126	#endif /* !IN_RC */
127
128
129	/**
130	* Performs the operations necessary that are part of the vmmcall instruction
131	* execution in the guest.
132	*
133	* @returns Strict VBox status code (i.e. informational status codes too).
134	* @retval VINF_SUCCESS on successful handling, no \#UD needs to be thrown,
135	* update RIP and eflags.RF depending on @a pfUpdatedRipAndRF and
136	* continue guest execution.
137	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
138	* RIP.
139	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
140	*
141	* @param pVCpu The cross context virtual CPU structure.
142	* @param pCtx Pointer to the guest-CPU context.
143	* @param pfUpdatedRipAndRF Whether the guest RIP/EIP has been updated as
144	* part of handling the VMMCALL operation.
145	*/
146	VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdatedRipAndRF)
147	{
148	#ifndef IN_RC
149	/*
150	* TPR patched instruction emulation for 32-bit guests.
151	*/
152	PVM pVM = pVCpu->CTX_SUFF(pVM);
153	if (pVM->hm.s.fTprPatchingAllowed)
154	{
155	int rc = hmSvmEmulateMovTpr(pVCpu, pCtx, pfUpdatedRipAndRF);
156	if (RT_SUCCESS(rc))
157	return VINF_SUCCESS;
158
159	if (rc != VERR_NOT_FOUND)
160	{
161	Log(("hmSvmExitVmmCall: hmSvmEmulateMovTpr returns %Rrc\n", rc));
162	return rc;
163	}
164	}
165	#endif
166
167	/*
168	* Paravirtualized hypercalls.
169	*/
170	*pfUpdatedRipAndRF = false;
171	if (pVCpu->hm.s.fHypercallsEnabled)
172	return GIMHypercall(pVCpu, pCtx);
173
174	return VERR_NOT_AVAILABLE;
175	}
176
177
178	/**
179	* Converts an SVM event type to a TRPM event type.
180	*
181	* @returns The TRPM event type.
182	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
183	* of recognized trap types.
184	*
185	* @param pEvent Pointer to the SVM event.
186	*/
187	VMM_INT_DECL(TRPMEVENT) hmSvmEventToTrpmEventType(PCSVMEVENT pEvent)
188	{
189	uint8_t const uType = pEvent->n.u3Type;
190	switch (uType)
191	{
192	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
193	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
194	case SVM_EVENT_EXCEPTION:
195	case SVM_EVENT_NMI: return TRPM_TRAP;
196	default:
197	break;
198	}
199	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
200	return TRPM_32BIT_HACK;
201	}
202
203
204	#ifndef IN_RC
205	/**
206	* Converts an IEM exception event type to an SVM event type.
207	*
208	* @returns The SVM event type.
209	* @retval UINT8_MAX if the specified type of event isn't among the set
210	* of recognized IEM event types.
211	*
212	* @param uVector The vector of the event.
213	* @param fIemXcptFlags The IEM exception / interrupt flags.
214	*/
215	static uint8_t hmSvmEventTypeFromIemEvent(uint32_t uVector, uint32_t fIemXcptFlags)
216	{
217	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
218	{
219	if (uVector != X86_XCPT_NMI)
220	return SVM_EVENT_EXCEPTION;
221	return SVM_EVENT_NMI;
222	}
223
224	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
225	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
226	return SVM_EVENT_EXCEPTION;
227
228	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
229	return SVM_EVENT_EXTERNAL_IRQ;
230
231	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
232	return SVM_EVENT_SOFTWARE_INT;
233
234	AssertMsgFailed(("hmSvmEventTypeFromIemEvent: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
235	return UINT8_MAX;
236	}
237
238
239	/**
240	* Performs the operations necessary that are part of the vmrun instruction
241	* execution in the guest.
242	*
243	* @returns Strict VBox status code (i.e. informational status codes too).
244	* @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
245	* code execution.
246	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
247	* (SVM_EXIT_INVALID most likely).
248	*
249	* @param pVCpu The cross context virtual CPU structure.
250	* @param pCtx Pointer to the guest-CPU context.
251	* @param GCPhysVmcb Guest physical address of the VMCB to run.
252	*/
253	/** @todo move this to IEM and make the VMRUN version that can execute under
254	* hardware SVM here instead. */
255	VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPHYS GCPhysVmcb)
256	{
257	Assert(pVCpu);
258	Assert(pCtx);
259	PVM pVM = pVCpu->CTX_SUFF(pVM);
260
261	/*
262	* Cache the physical address of the VMCB for #VMEXIT exceptions.
263	*/
264	pCtx->hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
265
266	/*
267	* Save host state.
268	*/
269	SVMVMCBSTATESAVE VmcbNstGst;
270	int rc = PGMPhysSimpleReadGCPhys(pVM, &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), sizeof(SVMVMCBSTATESAVE));
271	if (RT_SUCCESS(rc))
272	{
273	PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
274	pHostState->es = pCtx->es;
275	pHostState->cs = pCtx->cs;
276	pHostState->ss = pCtx->ss;
277	pHostState->ds = pCtx->ds;
278	pHostState->gdtr = pCtx->gdtr;
279	pHostState->idtr = pCtx->idtr;
280	pHostState->uEferMsr = pCtx->msrEFER;
281	pHostState->uCr0 = pCtx->cr0;
282	pHostState->uCr3 = pCtx->cr3;
283	pHostState->uCr4 = pCtx->cr4;
284	pHostState->rflags = pCtx->rflags;
285	pHostState->uRip = pCtx->rip;
286	pHostState->uRsp = pCtx->rsp;
287	pHostState->uRax = pCtx->rax;
288
289	/*
290	* Load the VMCB controls.
291	*/
292	rc = PGMPhysSimpleReadGCPhys(pVM, &pCtx->hwvirt.svm.VmcbCtrl, GCPhysVmcb, sizeof(pCtx->hwvirt.svm.VmcbCtrl));
293	if (RT_SUCCESS(rc))
294	{
295	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl;
296
297	/*
298	* Validate guest-state and controls.
299	*/
300	/* VMRUN must always be intercepted. */
301	if (!CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VMRUN))
302	{
303	Log(("HMSvmVmRun: VMRUN instruction not intercepted -> #VMEXIT\n"));
304	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
305	}
306
307	/* Nested paging. */
308	if ( pVmcbCtrl->NestedPaging.n.u1NestedPaging
309	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
310	{
311	Log(("HMSvmVmRun: Nested paging not supported -> #VMEXIT\n"));
312	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
313	}
314
315	/* AVIC. */
316	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
317	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
318	{
319	Log(("HMSvmVmRun: AVIC not supported -> #VMEXIT\n"));
320	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
321	}
322
323	/* Last branch record (LBR) virtualization. */
324	if ( (pVmcbCtrl->u64LBRVirt & SVM_LBR_VIRT_ENABLE)
325	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
326	{
327	Log(("HMSvmVmRun: LBR virtualization not supported -> #VMEXIT\n"));
328	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
329	}
330
331	/* Guest ASID. */
332	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
333	{
334	Log(("HMSvmVmRun: Guest ASID is invalid -> #VMEXIT\n"));
335	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
336	}
337
338	/* IO permission bitmap. */
339	RTGCPHYS GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
340	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
341	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap))
342	{
343	Log(("HMSvmVmRun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
344	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
345	}
346
347	/* MSR permission bitmap. */
348	RTGCPHYS GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
349	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
350	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap))
351	{
352	Log(("HMSvmVmRun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
353	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
354	}
355
356	/* CR0. */
357	if ( !(VmcbNstGst.u64CR0 & X86_CR0_CD)
358	&& (VmcbNstGst.u64CR0 & X86_CR0_NW))
359	{
360	Log(("HMSvmVmRun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", VmcbNstGst.u64CR0));
361	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
362	}
363	if (VmcbNstGst.u64CR0 >> 32)
364	{
365	Log(("HMSvmVmRun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", VmcbNstGst.u64CR0));
366	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
367	}
368	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
369
370	/* DR6 and DR7. */
371	if ( VmcbNstGst.u64DR6 >> 32
372	\|\| VmcbNstGst.u64DR7 >> 32)
373	{
374	Log(("HMSvmVmRun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", VmcbNstGst.u64DR6,
375	VmcbNstGst.u64DR6));
376	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
377	}
378
379	/** @todo gPAT MSR validation? */
380
381	/*
382	* Copy segments from nested-guest VMCB state to the guest-CPU state.
383	*
384	* We do this here as we need to use the CS attributes and it's easier this way
385	* then using the VMCB format selectors. It doesn't really matter where we copy
386	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
387	*/
388	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, ES, es);
389	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, CS, cs);
390	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, SS, ss);
391	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, DS, ds);
392
393	/** @todo Segment attribute overrides by VMRUN. */
394
395	/*
396	* CPL adjustments and overrides.
397	*
398	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
399	* We shall thus adjust both CS.DPL and SS.DPL here.
400	*/
401	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = VmcbNstGst.u8CPL;
402	if (CPUMIsGuestInV86ModeEx(pCtx))
403	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 3;
404	if (CPUMIsGuestInRealModeEx(pCtx))
405	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 0;
406
407	/*
408	* Continue validating guest-state and controls.
409	*/
410	/* EFER, CR0 and CR4. */
411	uint64_t uValidEfer;
412	rc = CPUMQueryValidatedGuestEfer(pVM, VmcbNstGst.u64CR0, 0 /* uOldEfer */, VmcbNstGst.u64EFER, &uValidEfer);
413	if (RT_FAILURE(rc))
414	{
415	Log(("HMSvmVmRun: EFER invalid uOldEfer=%#RX64 uValidEfer=%#RX64 -> #VMEXIT\n", VmcbNstGst.u64EFER, uValidEfer));
416	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
417	}
418	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
419	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
420	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
421	bool const fPaging = RT_BOOL(VmcbNstGst.u64CR0 & X86_CR0_PG);
422	bool const fPae = RT_BOOL(VmcbNstGst.u64CR4 & X86_CR4_PAE);
423	bool const fProtMode = RT_BOOL(VmcbNstGst.u64CR0 & X86_CR0_PE);
424	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
425	bool const fLongModeConformCS = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
426	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
427	if (fLongModeWithPaging)
428	uValidEfer \|= MSR_K6_EFER_LMA;
429	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
430	if ( !fSvm
431	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
432	\|\| (fLongModeWithPaging && !fPae)
433	\|\| (fLongModeWithPaging && !fProtMode)
434	\|\| ( fLongModeEnabled
435	&& fPaging
436	&& fPae
437	&& fLongModeConformCS))
438	{
439	Log(("HMSvmVmRun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
440	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
441	}
442
443	/*
444	* Preserve the required force-flags.
445	*
446	* We only preserve the force-flags that would affect the execution of the
447	* nested-guest (or the guest).
448	*
449	* - VMCPU_FF_INHIBIT_INTERRUPTS need not be preserved as it's for a single
450	* instruction which is this VMRUN instruction itself.
451	*
452	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
453	* execution of a subsequent IRET instruction in the guest.
454	*
455	* - The remaining FFs (e.g. timers) can stay in place so that we will be
456	* able to generate interrupts that should cause #VMEXITs for the
457	* nested-guest.
458	*/
459	/** @todo anything missed more here? */
460	pCtx->hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
461
462	/*
463	* Interrupt shadow.
464	*/
465	if (pVmcbCtrl->u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
466	EMSetInhibitInterruptsPC(pVCpu, VmcbNstGst.u64RIP);
467
468	/*
469	* TLB flush control.
470	*/
471	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
472	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
473	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
474	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
475	PGMFlushTLB(pVCpu, VmcbNstGst.u64CR3, true /* fGlobal */);
476
477	/** @todo @bugref{7243}: SVM TSC offset, see tmCpuTickGetInternal. */
478
479	/*
480	* Copy the remaining guest state from the VMCB to the guest-CPU context.
481	*/
482	pCtx->gdtr.cbGdt = VmcbNstGst.GDTR.u32Limit;
483	pCtx->gdtr.pGdt = VmcbNstGst.GDTR.u64Base;
484	pCtx->idtr.cbIdt = VmcbNstGst.IDTR.u32Limit;
485	pCtx->idtr.pIdt = VmcbNstGst.IDTR.u64Base;
486	pCtx->cr0 = VmcbNstGst.u64CR0; /** @todo What about informing PGM about CR0.WP? */
487	pCtx->cr4 = VmcbNstGst.u64CR4;
488	pCtx->cr3 = VmcbNstGst.u64CR3;
489	pCtx->cr2 = VmcbNstGst.u64CR2;
490	pCtx->dr[6] = VmcbNstGst.u64DR6;
491	pCtx->dr[7] = VmcbNstGst.u64DR7;
492	pCtx->rflags.u = VmcbNstGst.u64RFlags;
493	pCtx->rax = VmcbNstGst.u64RAX;
494	pCtx->rsp = VmcbNstGst.u64RSP;
495	pCtx->rip = VmcbNstGst.u64RIP;
496	pCtx->msrEFER = uValidEfer;
497
498	/* Mask DR6, DR7 bits mandatory set/clear bits. */
499	pCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
500	pCtx->dr[6] \|= X86_DR6_RA1_MASK;
501	pCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
502	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
503
504	/*
505	* Check for pending virtual interrupts.
506	*/
507	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
508	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
509
510	/*
511	* Clear global interrupt flags to allow interrupts in the guest.
512	*/
513	pCtx->hwvirt.svm.fGif = 1;
514
515	/*
516	* Event injection.
517	*/
518	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
519	pCtx->hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
520	if (pEventInject->n.u1Valid)
521	{
522	uint8_t const uVector = pEventInject->n.u8Vector;
523	TRPMEVENT const enmType = hmSvmEventToTrpmEventType(pEventInject);
524	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
525
526	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
527	if (enmType == TRPM_32BIT_HACK)
528	{
529	Log(("HMSvmVmRun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
530	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
531	}
532	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
533	{
534	if ( uVector == X86_XCPT_NMI
535	\|\| uVector > X86_XCPT_LAST)
536	{
537	Log(("HMSvmVmRun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
538	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
539	}
540	if ( uVector == X86_XCPT_BR
541	&& CPUMIsGuestInLongModeEx(pCtx))
542	{
543	Log(("HMSvmVmRun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
544	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
545	}
546	/** @todo any others? */
547	}
548
549	/*
550	* Update the exit interruption info field so that if an exception occurs
551	* while delivering the event causing a #VMEXIT, we only need to update
552	* the valid bit while the rest is already in place.
553	*/
554	pVmcbCtrl->ExitIntInfo.u = pVmcbCtrl->EventInject.u;
555	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
556
557	/** @todo NRIP: Software interrupts can only be pushed properly if we support
558	* NRIP for the nested-guest to calculate the instruction length
559	* below. */
560	VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
561	if ( rcStrict == VINF_SVM_VMEXIT
562	\|\| rcStrict == VERR_SVM_VMEXIT_FAILED)
563	return rcStrict;
564	}
565
566	return VINF_SUCCESS;
567	}
568
569	/* Shouldn't really happen as the caller should've validated the physical address already. */
570	Log(("HMSvmVmRun: Failed to read nested-guest VMCB control area at %#RGp -> #VMEXIT\n",
571	GCPhysVmcb));
572	return VERR_SVM_IPE_4;
573	}
574
575	/* Shouldn't really happen as the caller should've validated the physical address already. */
576	Log(("HMSvmVmRun: Failed to read nested-guest VMCB save-state area at %#RGp -> #VMEXIT\n",
577	GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest)));
578	return VERR_SVM_IPE_5;
579	}
580
581
582	/**
583	* SVM nested-guest \#VMEXIT handler.
584	*
585	* @returns Strict VBox status code.
586	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
587	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
588	* "host state" and a shutdown is required.
589	*
590	* @param pVCpu The cross context virtual CPU structure.
591	* @param pCtx The guest-CPU context.
592	* @param uExitCode The exit code.
593	* @param uExitInfo1 The exit info. 1 field.
594	* @param uExitInfo2 The exit info. 2 field.
595	*/
596	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstVmExit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
597	uint64_t uExitInfo2)
598	{
599	if ( CPUMIsGuestInNestedHwVirtMode(pCtx)
600	\|\| uExitCode == SVM_EXIT_INVALID)
601	{
602	/*
603	* Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
604	*/
605	pCtx->hwvirt.svm.fGif = 0;
606
607	/*
608	* Save the nested-guest state into the VMCB state-save area.
609	*/
610	SVMVMCBSTATESAVE VmcbNstGst;
611	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, ES, es);
612	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, CS, cs);
613	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, SS, ss);
614	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, DS, ds);
615	VmcbNstGst.GDTR.u32Limit = pCtx->gdtr.cbGdt;
616	VmcbNstGst.GDTR.u64Base = pCtx->gdtr.pGdt;
617	VmcbNstGst.IDTR.u32Limit = pCtx->idtr.cbIdt;
618	VmcbNstGst.IDTR.u32Limit = pCtx->idtr.pIdt;
619	VmcbNstGst.u64EFER = pCtx->msrEFER;
620	VmcbNstGst.u64CR4 = pCtx->cr4;
621	VmcbNstGst.u64CR3 = pCtx->cr3;
622	VmcbNstGst.u64CR2 = pCtx->cr2;
623	VmcbNstGst.u64CR0 = pCtx->cr0;
624	/** @todo Nested paging. */
625	VmcbNstGst.u64RFlags = pCtx->rflags.u64;
626	VmcbNstGst.u64RIP = pCtx->rip;
627	VmcbNstGst.u64RSP = pCtx->rsp;
628	VmcbNstGst.u64RAX = pCtx->rax;
629	VmcbNstGst.u64DR7 = pCtx->dr[6];
630	VmcbNstGst.u64DR6 = pCtx->dr[7];
631	VmcbNstGst.u8CPL = pCtx->ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
632
633	/* Save interrupt shadow of the nested-guest instruction if any. */
634	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
635	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
636	pCtx->hwvirt.svm.VmcbCtrl.u64IntShadow \|= SVM_INTERRUPT_SHADOW_ACTIVE;
637
638	/*
639	* Save additional state and intercept information.
640	*/
641	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
642	{
643	Assert(pCtx->hwvirt.svm.VmcbCtrl.IntCtrl.n.u1VIrqPending);
644	Assert(pCtx->hwvirt.svm.VmcbCtrl.IntCtrl.n.u8VIntrVector);
645	}
646	/** @todo Save V_TPR, V_IRQ. */
647	/** @todo NRIP. */
648
649	/* Save exit information. */
650	pCtx->hwvirt.svm.VmcbCtrl.u64ExitCode = uExitCode;
651	pCtx->hwvirt.svm.VmcbCtrl.u64ExitInfo1 = uExitInfo1;
652	pCtx->hwvirt.svm.VmcbCtrl.u64ExitInfo2 = uExitInfo2;
653
654	/*
655	* Update the exit interrupt information field if this #VMEXIT happened as a result
656	* of delivering an event.
657	*/
658	{
659	uint8_t uExitIntVector;
660	uint32_t uExitIntErr;
661	uint32_t fExitIntFlags;
662	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
663	NULL /* uExitIntCr2 */);
664	pCtx->hwvirt.svm.VmcbCtrl.ExitIntInfo.n.u1Valid = fRaisingEvent;
665	if (fRaisingEvent)
666	{
667	pCtx->hwvirt.svm.VmcbCtrl.ExitIntInfo.n.u8Vector = uExitIntVector;
668	pCtx->hwvirt.svm.VmcbCtrl.ExitIntInfo.n.u3Type = hmSvmEventTypeFromIemEvent(uExitIntVector, fExitIntFlags);
669	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
670	{
671	pCtx->hwvirt.svm.VmcbCtrl.ExitIntInfo.n.u1ErrorCodeValid = true;
672	pCtx->hwvirt.svm.VmcbCtrl.ExitIntInfo.n.u32ErrorCode = uExitIntErr;
673	}
674	}
675	}
676
677	/*
678	* Clear event injection in the VMCB.
679	*/
680	pCtx->hwvirt.svm.VmcbCtrl.EventInject.n.u1Valid = 0;
681
682	/*
683	* Write back the VMCB controls to the guest VMCB in guest physical memory.
684	*/
685	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, &pCtx->hwvirt.svm.VmcbCtrl,
686	sizeof(pCtx->hwvirt.svm.VmcbCtrl));
687	if (RT_SUCCESS(rc))
688	{
689	/*
690	* Prepare for guest's "host mode" by clearing internal processor state bits.
691	*
692	* Some of these like TSC offset can then be used unconditionally in our TM code
693	* but the offset in the guest's VMCB will remain as it should as we've written
694	* back the VMCB controls above.
695	*/
696	RT_ZERO(pCtx->hwvirt.svm.VmcbCtrl);
697	#if 0
698	/* Clear TSC offset. */
699	pCtx->hwvirt.svm.VmcbCtrl.u64TSCOffset = 0;
700	pCtx->hwvirt.svm.VmcbCtrl.IntCtrl.n.u1VIrqValid = 0;
701	pCtx->hwvirt.svm.VmcbCtrl.IntCtrl.n.u1VIntrMasking = 0;
702	#endif
703	/* Restore guest's force-flags. */
704	if (pCtx->hwvirt.fLocalForcedActions)
705	VMCPU_FF_SET(pVCpu, pCtx->hwvirt.fLocalForcedActions);
706
707	/* Clear nested-guest's interrupt pending. */
708	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
709	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
710
711	/** @todo Nested paging. */
712	/** @todo ASID. */
713
714	/*
715	* Reload the guest's "host state".
716	*/
717	PSVMHOSTSTATE pHostState = &pCtx->hwvirt.svm.HostState;
718	pCtx->es = pHostState->es;
719	pCtx->cs = pHostState->cs;
720	pCtx->ss = pHostState->ss;
721	pCtx->ds = pHostState->ds;
722	pCtx->gdtr = pHostState->gdtr;
723	pCtx->idtr = pHostState->idtr;
724	pCtx->msrEFER = pHostState->uEferMsr;
725	pCtx->cr0 = pHostState->uCr0 \| X86_CR0_PE;
726	pCtx->cr3 = pHostState->uCr3;
727	pCtx->cr4 = pHostState->uCr4;
728	pCtx->rflags = pHostState->rflags;
729	pCtx->rflags.Bits.u1VM = 0;
730	pCtx->rip = pHostState->uRip;
731	pCtx->rsp = pHostState->uRsp;
732	pCtx->rax = pHostState->uRax;
733	pCtx->dr[7] &= ~(X86_DR7_ENABLED_MASK \| X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
734	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
735
736	/** @todo if RIP is not canonical or outside the CS segment limit, we need to
737	* raise \#GP(0) in the guest. */
738
739	/** @todo check the loaded host-state for consistency. Figure out what
740	* exactly this involves? */
741
742	rc = VINF_SVM_VMEXIT;
743	}
744	else
745	{
746	Log(("HMNstGstSvmVmExit: Writing VMCB at %#RGp failed\n", pCtx->hwvirt.svm.GCPhysVmcb));
747	Assert(!CPUMIsGuestInNestedHwVirtMode(pCtx));
748	rc = VERR_SVM_VMEXIT_FAILED;
749	}
750
751	return rc;
752	}
753
754	Log(("HMNstGstSvmVmExit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode,
755	uExitInfo1, uExitInfo2));
756	RT_NOREF2(uExitInfo1, uExitInfo2);
757	return VERR_SVM_IPE_5;
758	}
759
760
761	/**
762	* Checks whether an interrupt is pending for the nested-guest.
763	*
764	* @returns VBox status code.
765	* @retval true if there's a pending interrupt, false otherwise.
766	*
767	* @param pVCpu The cross context virtual CPU structure.
768	* @param pCtx The guest-CPU context.
769	*/
770	VMM_INT_DECL(bool) HMSvmNstGstCanTakeInterrupt(PVMCPU pVCpu, PCCPUMCTX pCtx)
771	{
772	PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl;
773	Assert(CPUMIsGuestInNestedHwVirtMode(pCtx));
774
775	X86RFLAGS RFlags;
776	if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)
777	RFlags.u = pCtx->rflags.u;
778	else
779	RFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
780
781	if (!RFlags.Bits.u1IF)
782	return false;
783
784	if ( !pVmcbCtrl->IntCtrl.n.u1IgnoreTPR
785	&& pVmcbCtrl->IntCtrl.n.u4VIntrPrio <= pVmcbCtrl->IntCtrl.n.u8VTPR)
786	return false;
787
788	/* Paranoia. */
789	Assert(RT_BOOL(pCtx->hwvirt.svm.fGif));
790	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
791	Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
792	RT_NOREF(pVCpu);
793	return true;
794	}
795
796
797	/**
798	* Gets the pending nested-guest interrupt.
799	*
800	* @returns The nested-guest interrupt to inject.
801	* @param pCtx The guest-CPU context.
802	*/
803	VMM_INT_DECL(uint8_t) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx)
804	{
805	PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl;
806	return pVmcbCtrl->IntCtrl.n.u8VIntrVector;
807	}
808
809
810	/**
811	* Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
812	* intercept is active.
813	*
814	* @returns Strict VBox status code.
815	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
816	* we're not executing a nested-guest.
817	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
818	* successfully.
819	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
820	* failed and a shutdown needs to be initiated for the geust.
821	*
822	* @param pVCpu The cross context virtual CPU structure.
823	* @param pCtx The guest-CPU context.
824	* @param uExitCode The SVM exit code (see SVM_EXIT_XXX).
825	* @param uExitInfo1 The exit info. 1 field.
826	* @param uExitInfo2 The exit info. 2 field.
827	*/
828	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
829	uint64_t uExitInfo2)
830	{
831	#define HMSVM_CTRL_INTERCEPT_VMEXIT(a_Intercept) \
832	do { \
833	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \
834	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \
835	break; \
836	} while (0)
837
838	if (!CPUMIsGuestInNestedHwVirtMode(pCtx))
839	return VINF_HM_INTERCEPT_NOT_ACTIVE;
840
841	switch (uExitCode)
842	{
843	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
844	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
845	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
846	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15:
847	case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
848	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
849	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27:
850	case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
851	{
852	if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0)))
853	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
854	break;
855	}
856
857	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
858	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
859	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
860	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
861	{
862	if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0))
863	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
864	break;
865	}
866
867	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
868	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
869	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
870	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
871	{
872	if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0))
873	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
874	break;
875	}
876
877	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
878	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
879	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
880	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
881	{
882	if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0))
883	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
884	break;
885	}
886
887	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
888	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
889	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
890	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
891	{
892	if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0))
893	return HMSvmNstGstVmExit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
894	break;
895	}
896
897	case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTR);
898	case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_NMI);
899	case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SMI);
900	case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INIT);
901	case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VINTR);
902	case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES);
903	case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_READS);
904	case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_READS);
905	case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_READS);
906	case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_READS);
907	case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_WRITES);
908	case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_WRITES);
909	case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_WRITES);
910	case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_WRITES);
911	case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSC);
912	case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDPMC);
913	case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PUSHF);
914	case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_POPF);
915	case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CPUID);
916	case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RSM);
917	case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IRET);
918	case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTN);
919	case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVD);
920	case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PAUSE);
921	case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_HLT);
922	case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPG);
923	case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPGA);
924	case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TASK_SWITCH);
925	case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_FERR_FREEZE);
926	case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SHUTDOWN);
927	case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMRUN);
928	case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMMCALL);
929	case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMLOAD);
930	case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMSAVE);
931	case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_STGI);
932	case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CLGI);
933	case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SKINIT);
934	case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSCP);
935	case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_ICEBP);
936	case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_WBINVD);
937	case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MONITOR);
938	case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT);
939	case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT_ARMED);
940	case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_XSETBV);
941
942	case SVM_EXIT_IOIO:
943	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
944	return VERR_SVM_IPE_1;
945
946	case SVM_EXIT_MSR:
947	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
948	return VERR_SVM_IPE_1;
949
950	case SVM_EXIT_NPF:
951	case SVM_EXIT_AVIC_INCOMPLETE_IPI:
952	case SVM_EXIT_AVIC_NOACCEL:
953	AssertMsgFailed(("Todo Implement.\n"));
954	return VERR_SVM_IPE_1;
955
956	default:
957	AssertMsgFailed(("Unsupported SVM exit code %#RX64\n", uExitCode));
958	return VERR_SVM_IPE_1;
959	}
960
961	return VINF_HM_INTERCEPT_NOT_ACTIVE;
962
963	#undef HMSVM_CTRL_INTERCEPT_VMEXIT
964	}
965
966
967	/**
968	* Handles nested-guest SVM IO intercepts and performs the \#VMEXIT
969	* if the intercept is active.
970	*
971	* @returns Strict VBox status code.
972	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
973	* we're not executing a nested-guest.
974	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
975	* successfully.
976	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
977	* failed and a shutdown needs to be initiated for the geust.
978	*
979	* @param pVCpu The cross context virtual CPU structure.
980	* @param pCtx The guest-CPU context.
981	* @param pIoExitInfo The SVM IOIO exit info. structure.
982	* @param uNextRip The RIP of the instruction following the IO
983	* instruction.
984	*/
985	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleIOIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMIOIOEXITINFO pIoExitInfo,
986	uint64_t uNextRip)
987	{
988	/*
989	* Check if any IO accesses are being intercepted.
990	*/
991	Assert(CPUMIsGuestInNestedHwVirtMode(pCtx));
992	Assert(CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT));
993
994	/*
995	* The IOPM layout:
996	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
997	* two 4K pages.
998	*
999	* For IO instructions that access more than a single byte, the permission bits
1000	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
1001	*
1002	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
1003	* we need 3 extra bits beyond the second 4K page.
1004	*/
1005	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
1006	uint8_t const pbIopm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
1007
1008	uint16_t const u16Port = pIoExitInfo->n.u16Port;
1009	uint16_t const offIopm = u16Port >> 3;
1010	uint16_t const fSizeMask = s_auSizeMasks[(pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
1011	uint8_t const cShift = u16Port - (offIopm << 3);
1012	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
1013
1014	pbIopm += offIopm;
1015	uint16_t const u16Iopm = (uint16_t )pbIopm;
1016	if (u16Iopm & fIopmMask)
1017	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_IOIO, pIoExitInfo->u, uNextRip);
1018
1019	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1020	}
1021
1022
1023	/**
1024	* Handles nested-guest SVM MSR read/write intercepts and performs the \#VMEXIT
1025	* if the intercept is active.
1026	*
1027	* @returns Strict VBox status code.
1028	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1029	* specify interception of the accessed MSR @a idMsr.
1030	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1031	* successfully.
1032	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1033	* failed and a shutdown needs to be initiated for the geust.
1034	*
1035	* @param pVCpu The cross context virtual CPU structure.
1036	* @param pCtx The guest-CPU context.
1037	* @param idMsr The MSR being accessed in the nested-guest.
1038	* @param fWrite Whether this is an MSR write access, @c false implies an
1039	* MSR read.
1040	*/
1041	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
1042	{
1043	/*
1044	* Check if any MSRs are being intercepted.
1045	*/
1046	Assert(CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_MSR_PROT));
1047	Assert(CPUMIsGuestInNestedHwVirtMode(pCtx));
1048
1049	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1050
1051	/*
1052	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1053	*/
1054	uint16_t offMsrpm;
1055	uint32_t uMsrpmBit;
1056	int rc = hmSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1057	if (RT_SUCCESS(rc))
1058	{
1059	Assert(uMsrpmBit < 0x3fff);
1060	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1061	if (fWrite)
1062	++uMsrpmBit;
1063
1064	/*
1065	* Check if the bit is set, if so, trigger a #VMEXIT.
1066	*/
1067	uint8_t pbMsrpm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1068	pbMsrpm += offMsrpm;
1069	if (ASMBitTest(pbMsrpm, uMsrpmBit))
1070	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1071	}
1072	else
1073	{
1074	/*
1075	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1076	*/
1077	Log(("HMSvmNstGstHandleIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool\n", idMsr, fWrite));
1078	return HMSvmNstGstVmExit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1079	}
1080	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1081	}
1082
1083
1084	/**
1085	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
1086	*
1087	* @returns VBox status code.
1088	* @param idMsr The MSR being requested.
1089	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
1090	* bitmap for @a idMsr.
1091	* @param puMsrpmBit Where to store the bit offset starting at the byte
1092	* returned in @a pbOffMsrpm.
1093	*/
1094	VMM_INT_DECL(int) hmSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint32_t puMsrpmBit)
1095	{
1096	Assert(pbOffMsrpm);
1097	Assert(puMsrpmBit);
1098
1099	/*
1100	* MSRPM Layout:
1101	* Byte offset MSR range
1102	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
1103	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
1104	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
1105	* 0x1800 - 0x1fff Reserved
1106	*
1107	* Each MSR is represented by 2 permission bits (read and write).
1108	*/
1109	if (idMsr <= 0x00001fff)
1110	{
1111	/* Pentium-compatible MSRs. */
1112	*pbOffMsrpm = 0;
1113	*puMsrpmBit = idMsr << 1;
1114	return VINF_SUCCESS;
1115	}
1116
1117	if ( idMsr >= 0xc0000000
1118	&& idMsr <= 0xc0001fff)
1119	{
1120	/* AMD Sixth Generation x86 Processor MSRs. */
1121	*pbOffMsrpm = 0x800;
1122	*puMsrpmBit = (idMsr - 0xc0000000) << 1;
1123	return VINF_SUCCESS;
1124	}
1125
1126	if ( idMsr >= 0xc0010000
1127	&& idMsr <= 0xc0011fff)
1128	{
1129	/* AMD Seventh and Eighth Generation Processor MSRs. */
1130	*pbOffMsrpm += 0x1000;
1131	*puMsrpmBit = (idMsr - 0xc0001000) << 1;
1132	return VINF_SUCCESS;
1133	}
1134
1135	*pbOffMsrpm = 0;
1136	*puMsrpmBit = 0;
1137	return VERR_OUT_OF_RANGE;
1138	}
1139	#endif /* !IN_RC */
1140

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 66974

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