HMSVMAll.cpp@ 71417

Last change on this file since 71417 was 71417, checked in by vboxsync, 7 years ago
VMM/HM: Comment.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 22.6 KB

Line
1	/* $Id: HMSVMAll.cpp 71417 2018-03-21 09:39:31Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/hm_svm.h>
31
32
33	#ifndef IN_RC
34	/**
35	* Emulates a simple MOV TPR (CR8) instruction.
36	*
37	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
38	* at EIP and does the required.
39	*
40	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
41	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
42	* TPR). See hmR3ReplaceTprInstr() for the details.
43	*
44	* @returns VBox status code.
45	* @retval VINF_SUCCESS if the access was handled successfully.
46	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
47	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
48	*
49	* @param pVCpu The cross context virtual CPU structure.
50	* @param pCtx Pointer to the guest-CPU context.
51	* @param pfUpdateRipAndRF Whether the guest RIP/EIP has been updated as
52	* part of the TPR patch operation.
53	*/
54	static int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdateRipAndRF)
55	{
56	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
57
58	/*
59	* We do this in a loop as we increment the RIP after a successful emulation
60	* and the new RIP may be a patched instruction which needs emulation as well.
61	*/
62	bool fUpdateRipAndRF = false;
63	bool fPatchFound = false;
64	PVM pVM = pVCpu->CTX_SUFF(pVM);
65	for (;;)
66	{
67	bool fPending;
68	uint8_t u8Tpr;
69
70	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
71	if (!pPatch)
72	break;
73
74	fPatchFound = true;
75	switch (pPatch->enmType)
76	{
77	case HMTPRINSTR_READ:
78	{
79	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
80	AssertRC(rc);
81
82	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
83	AssertRC(rc);
84	pCtx->rip += pPatch->cbOp;
85	pCtx->eflags.Bits.u1RF = 0;
86	fUpdateRipAndRF = true;
87	break;
88	}
89
90	case HMTPRINSTR_WRITE_REG:
91	case HMTPRINSTR_WRITE_IMM:
92	{
93	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
94	{
95	uint32_t u32Val;
96	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
97	AssertRC(rc);
98	u8Tpr = u32Val;
99	}
100	else
101	u8Tpr = (uint8_t)pPatch->uSrcOperand;
102
103	int rc2 = APICSetTpr(pVCpu, u8Tpr);
104	AssertRC(rc2);
105	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
106
107	pCtx->rip += pPatch->cbOp;
108	pCtx->eflags.Bits.u1RF = 0;
109	fUpdateRipAndRF = true;
110	break;
111	}
112
113	default:
114	{
115	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
116	pVCpu->hm.s.u32HMError = pPatch->enmType;
117	*pfUpdateRipAndRF = fUpdateRipAndRF;
118	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
119	}
120	}
121	}
122
123	*pfUpdateRipAndRF = fUpdateRipAndRF;
124	if (fPatchFound)
125	return VINF_SUCCESS;
126	return VERR_NOT_FOUND;
127	}
128
129
130	/**
131	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
132	* in IEM).
133	*
134	* @param pVCpu The cross context virtual CPU structure.
135	* @param pCtx Pointer to the guest-CPU context.
136	*
137	* @sa hmR0SvmVmRunCacheVmcb.
138	*/
139	VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx)
140	{
141	/*
142	* Restore the nested-guest VMCB fields which have been modified for executing
143	* the nested-guest under SVM R0.
144	*/
145	if (pCtx->hwvirt.svm.fHMCachedVmcb)
146	{
147	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
148	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
149	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
150	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
151
152	/*
153	* The fields that are guaranteed to be read-only during SVM guest execution
154	* can safely be restored from our VMCB cache. Other fields like control registers
155	* can potentially be modified (if the nested-hypervisor is not intercepting writes)
156	* and thus we restore the actual virtual CPU values of these registers.
157	*/
158	pVmcbNstGstCtrl->u16InterceptRdCRx = pNstGstVmcbCache->u16InterceptRdCRx;
159	pVmcbNstGstCtrl->u16InterceptWrCRx = pNstGstVmcbCache->u16InterceptWrCRx;
160	pVmcbNstGstCtrl->u16InterceptRdDRx = pNstGstVmcbCache->u16InterceptRdDRx;
161	pVmcbNstGstCtrl->u16InterceptWrDRx = pNstGstVmcbCache->u16InterceptWrDRx;
162	pVmcbNstGstCtrl->u32InterceptXcpt = pNstGstVmcbCache->u32InterceptXcpt;
163	pVmcbNstGstCtrl->u64InterceptCtrl = pNstGstVmcbCache->u64InterceptCtrl;
164	pVmcbNstGstState->u64CR0 = pCtx->cr0;
165	pVmcbNstGstState->u64CR3 = pCtx->cr3;
166	pVmcbNstGstState->u64CR4 = pCtx->cr4;
167	pVmcbNstGstState->u64EFER = pCtx->msrEFER;
168	pVmcbNstGstState->u64DBGCTL = pNstGstVmcbCache->u64DBGCTL;
169	pVmcbNstGstCtrl->u32VmcbCleanBits = pNstGstVmcbCache->u32VmcbCleanBits;
170	pVmcbNstGstCtrl->u64IOPMPhysAddr = pNstGstVmcbCache->u64IOPMPhysAddr;
171	pVmcbNstGstCtrl->u64MSRPMPhysAddr = pNstGstVmcbCache->u64MSRPMPhysAddr;
172	pVmcbNstGstCtrl->u64TSCOffset = pNstGstVmcbCache->u64TSCOffset;
173	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pNstGstVmcbCache->fVIntrMasking;
174	pVmcbNstGstCtrl->TLBCtrl = pNstGstVmcbCache->TLBCtrl;
175	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pNstGstVmcbCache->u1NestedPaging;
176	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pNstGstVmcbCache->u1LbrVirt;
177	pCtx->hwvirt.svm.fHMCachedVmcb = false;
178	}
179
180	/*
181	* Currently, VMRUN, #VMEXIT transitions involves trips to ring-3 that would flag a full
182	* CPU state change. However, if we exit to ring-3 in response to receiving a physical
183	* interrupt, we skip signaling any CPU state change as normally no change
184	* is done to the execution state (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
185	* However, with nested-guests, the state can change for e.g., we might perform a
186	* SVM_EXIT_INTR #VMEXIT for the nested-guest in ring-3. Hence we signal a full CPU
187	* state change here.
188	*/
189	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
190	}
191
192
193	/**
194	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
195	* enabled for the VM.
196	*
197	* @returns @c true if VGIF is enabled, @c false otherwise.
198	* @param pVM The cross context VM structure.
199	*
200	* @remarks This value returned by this functions is expected by the callers not
201	* to change throughout the lifetime of the VM.
202	*/
203	VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM)
204	{
205	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
206	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
207
208	return HMIsEnabled(pVM) && fVGif && fUseVGif;
209	}
210
211
212	/**
213	* Applies the TSC offset of an SVM nested-guest if any and returns the new TSC
214	* value for the nested-guest.
215	*
216	* @returns The TSC offset after applying any nested-guest TSC offset.
217	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
218	* @param uTicks The guest TSC.
219	*
220	* @remarks This function looks at the VMCB cache rather than directly at the
221	* nested-guest VMCB. The latter may have been modified for executing
222	* using hardware-assisted SVM.
223	*
224	* @sa CPUMApplyNestedGuestTscOffset.
225	*/
226	VMM_INT_DECL(uint64_t) HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks)
227	{
228	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
229	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
230	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
231	NOREF(pCtx);
232	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
233	return uTicks + pVmcbNstGstCache->u64TSCOffset;
234	}
235	#endif /* !IN_RC */
236
237
238	/**
239	* Performs the operations necessary that are part of the vmmcall instruction
240	* execution in the guest.
241	*
242	* @returns Strict VBox status code (i.e. informational status codes too).
243	* @retval VINF_SUCCESS on successful handling, no \#UD needs to be thrown,
244	* update RIP and eflags.RF depending on @a pfUpdatedRipAndRF and
245	* continue guest execution.
246	* @retval VINF_GIM_HYPERCALL_CONTINUING continue hypercall without updating
247	* RIP.
248	* @retval VINF_GIM_R3_HYPERCALL re-start the hypercall from ring-3.
249	*
250	* @param pVCpu The cross context virtual CPU structure.
251	* @param pCtx Pointer to the guest-CPU context.
252	* @param pfUpdatedRipAndRF Whether the guest RIP/EIP has been updated as
253	* part of handling the VMMCALL operation.
254	*/
255	VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfUpdatedRipAndRF)
256	{
257	#ifndef IN_RC
258	/*
259	* TPR patched instruction emulation for 32-bit guests.
260	*/
261	PVM pVM = pVCpu->CTX_SUFF(pVM);
262	if (pVM->hm.s.fTprPatchingAllowed)
263	{
264	int rc = hmSvmEmulateMovTpr(pVCpu, pCtx, pfUpdatedRipAndRF);
265	if (RT_SUCCESS(rc))
266	return VINF_SUCCESS;
267
268	if (rc != VERR_NOT_FOUND)
269	{
270	Log(("hmSvmExitVmmCall: hmSvmEmulateMovTpr returns %Rrc\n", rc));
271	return rc;
272	}
273	}
274	#endif
275
276	/*
277	* Paravirtualized hypercalls.
278	*/
279	*pfUpdatedRipAndRF = false;
280	if (pVCpu->hm.s.fHypercallsEnabled)
281	return GIMHypercall(pVCpu, pCtx);
282
283	return VERR_NOT_AVAILABLE;
284	}
285
286
287	/**
288	* Converts an SVM event type to a TRPM event type.
289	*
290	* @returns The TRPM event type.
291	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
292	* of recognized trap types.
293	*
294	* @param pEvent Pointer to the SVM event.
295	*/
296	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent)
297	{
298	uint8_t const uType = pEvent->n.u3Type;
299	switch (uType)
300	{
301	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
302	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
303	case SVM_EVENT_EXCEPTION:
304	case SVM_EVENT_NMI: return TRPM_TRAP;
305	default:
306	break;
307	}
308	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
309	return TRPM_32BIT_HACK;
310	}
311
312
313	/**
314	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
315	*
316	* @returns VBox status code.
317	* @param idMsr The MSR being requested.
318	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
319	* bitmap for @a idMsr.
320	* @param puMsrpmBit Where to store the bit offset starting at the byte
321	* returned in @a pbOffMsrpm.
322	*/
323	VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint32_t puMsrpmBit)
324	{
325	Assert(pbOffMsrpm);
326	Assert(puMsrpmBit);
327
328	/*
329	* MSRPM Layout:
330	* Byte offset MSR range
331	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
332	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
333	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
334	* 0x1800 - 0x1fff Reserved
335	*
336	* Each MSR is represented by 2 permission bits (read and write).
337	*/
338	if (idMsr <= 0x00001fff)
339	{
340	/* Pentium-compatible MSRs. */
341	*pbOffMsrpm = 0;
342	*puMsrpmBit = idMsr << 1;
343	return VINF_SUCCESS;
344	}
345
346	if ( idMsr >= 0xc0000000
347	&& idMsr <= 0xc0001fff)
348	{
349	/* AMD Sixth Generation x86 Processor MSRs. */
350	*pbOffMsrpm = 0x800;
351	*puMsrpmBit = (idMsr - 0xc0000000) << 1;
352	return VINF_SUCCESS;
353	}
354
355	if ( idMsr >= 0xc0010000
356	&& idMsr <= 0xc0011fff)
357	{
358	/* AMD Seventh and Eighth Generation Processor MSRs. */
359	*pbOffMsrpm = 0x1000;
360	*puMsrpmBit = (idMsr - 0xc0010000) << 1;
361	return VINF_SUCCESS;
362	}
363
364	*pbOffMsrpm = 0;
365	*puMsrpmBit = 0;
366	return VERR_OUT_OF_RANGE;
367	}
368
369
370	/**
371	* Determines whether an IOIO intercept is active for the nested-guest or not.
372	*
373	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
374	* @param u16Port The IO port being accessed.
375	* @param enmIoType The type of IO access.
376	* @param cbReg The IO operand size in bytes.
377	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
378	* @param iEffSeg The effective segment number.
379	* @param fRep Whether this is a repeating IO instruction (REP prefix).
380	* @param fStrIo Whether this is a string IO instruction.
381	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
382	* Optional, can be NULL.
383	*/
384	VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
385	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
386	PSVMIOIOEXITINFO pIoExitInfo)
387	{
388	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
389	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
390
391	/*
392	* The IOPM layout:
393	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
394	* two 4K pages.
395	*
396	* For IO instructions that access more than a single byte, the permission bits
397	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
398	*
399	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
400	* we need 3 extra bits beyond the second 4K page.
401	*/
402	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
403
404	uint16_t const offIopm = u16Port >> 3;
405	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
406	uint8_t const cShift = u16Port - (offIopm << 3);
407	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
408
409	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
410	Assert(pbIopm);
411	pbIopm += offIopm;
412	uint16_t const u16Iopm = (uint16_t )pbIopm;
413	if (u16Iopm & fIopmMask)
414	{
415	if (pIoExitInfo)
416	{
417	static const uint32_t s_auIoOpSize[] =
418	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
419
420	static const uint32_t s_auIoAddrSize[] =
421	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
422
423	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
424	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
425	pIoExitInfo->n.u1STR = fStrIo;
426	pIoExitInfo->n.u1REP = fRep;
427	pIoExitInfo->n.u3SEG = iEffSeg & 7;
428	pIoExitInfo->n.u1Type = enmIoType;
429	pIoExitInfo->n.u16Port = u16Port;
430	}
431	return true;
432	}
433
434	/** @todo remove later (for debugging as VirtualBox always traps all IO
435	* intercepts). */
436	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
437	return false;
438	}
439
440
441	/**
442	* Checks if the guest VMCB has the specified ctrl/instruction intercept active.
443	*
444	* @returns @c true if in intercept is set, @c false otherwise.
445	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
446	* @param pCtx Pointer to the context.
447	* @param fIntercept The SVM control/instruction intercept, see
448	* SVM_CTRL_INTERCEPT_*.
449	*/
450	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fIntercept)
451	{
452	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
453	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
454	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
455	}
456
457
458	/**
459	* Checks if the guest VMCB has the specified CR read intercept active.
460	*
461	* @returns @c true if in intercept is set, @c false otherwise.
462	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
463	* @param pCtx Pointer to the context.
464	* @param uCr The CR register number (0 to 15).
465	*/
466	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
467	{
468	Assert(uCr < 16);
469	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
470	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
471	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
472	}
473
474
475	/**
476	* Checks if the guest VMCB has the specified CR write intercept
477	* active.
478	*
479	* @returns @c true if in intercept is set, @c false otherwise.
480	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
481	* @param pCtx Pointer to the context.
482	* @param uCr The CR register number (0 to 15).
483	*/
484	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uCr)
485	{
486	Assert(uCr < 16);
487	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
488	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
489	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
490	}
491
492
493	/**
494	* Checks if the guest VMCB has the specified DR read intercept
495	* active.
496	*
497	* @returns @c true if in intercept is set, @c false otherwise.
498	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
499	* @param pCtx Pointer to the context.
500	* @param uDr The DR register number (0 to 15).
501	*/
502	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
503	{
504	Assert(uDr < 16);
505	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
506	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
507	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
508	}
509
510
511	/**
512	* Checks if the guest VMCB has the specified DR write intercept active.
513	*
514	* @returns @c true if in intercept is set, @c false otherwise.
515	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
516	* @param pCtx Pointer to the context.
517	* @param uDr The DR register number (0 to 15).
518	*/
519	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uDr)
520	{
521	Assert(uDr < 16);
522	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
523	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
524	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
525	}
526
527
528	/**
529	* Checks if the guest VMCB has the specified exception intercept active.
530	*
531	* @returns true if in intercept is active, false otherwise.
532	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
533	* @param pCtx Pointer to the context.
534	* @param uVector The exception / interrupt vector.
535	*/
536	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, PCCPUMCTX pCtx, uint8_t uVector)
537	{
538	Assert(uVector < 32);
539	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
540	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
541	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
542	}
543
544
545	/**
546	* Checks whether the SVM nested-guest is in a state to receive physical (APIC)
547	* interrupts.
548	*
549	* @returns true if it's ready, false otherwise.
550	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
551	* @param pCtx The guest-CPU context.
552	*
553	* @remarks This function looks at the VMCB cache rather than directly at the
554	* nested-guest VMCB. The latter may have been modified for executing
555	* using hardware-assisted SVM.
556	*
557	* @sa CPUMCanSvmNstGstTakePhysIntr.
558	*/
559	VMM_INT_DECL(bool) HMCanSvmNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
560	{
561	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
562	Assert(pCtx->hwvirt.fGif);
563	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
564	X86EFLAGS fEFlags;
565	if (pVmcbNstGstCache->fVIntrMasking)
566	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
567	else
568	fEFlags.u = pCtx->eflags.u;
569	return fEFlags.Bits.u1IF;
570	}
571
572
573	/**
574	* Checks whether the SVM nested-guest is in a state to receive virtual (setup
575	* for injection by VMRUN instruction) interrupts.
576	*
577	* @returns true if it's ready, false otherwise.
578	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
579	* @param pCtx The guest-CPU context.
580	*
581	* @remarks This function looks at the VMCB cache rather than directly at the
582	* nested-guest VMCB. The latter may have been modified for executing
583	* using hardware-assisted SVM.
584	*
585	* @sa CPUMCanSvmNstGstTakeVirtIntr.
586	*/
587	VMM_INT_DECL(bool) HMCanSvmNstGstTakeVirtIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
588	{
589	#ifdef IN_RC
590	RT_NOREF2(pVCpu, pCtx);
591	AssertReleaseFailedReturn(false);
592	#else
593	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
594	Assert(pCtx->hwvirt.fGif);
595	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
596
597	PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
598	if ( !pVmcbCtrl->IntCtrl.n.u1IgnoreTPR
599	&& pVmcbCtrl->IntCtrl.n.u4VIntrPrio <= pVmcbCtrl->IntCtrl.n.u8VTPR)
600	return false;
601
602	X86EFLAGS fEFlags;
603	if (pVmcbNstGstCache->fVIntrMasking)
604	fEFlags.u = pCtx->eflags.u;
605	else
606	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
607	return fEFlags.Bits.u1IF;
608	#endif
609	}
610

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 71417

Download in other formats: