HMSVMAll.cpp@ 72727

Last change on this file since 72727 was 72643, checked in by vboxsync, 7 years ago
VMM: Make SVM R0 code use CPUMCTX_EXTRN_xxx flags and cleanups. bugref:9193
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1	/* $Id: HMSVMAll.cpp 72643 2018-06-21 16:02:03Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/vm.h>
30	#include <VBox/vmm/hm_svm.h>
31
32
33	#ifndef IN_RC
34
35	/**
36	* Emulates a simple MOV TPR (CR8) instruction.
37	*
38	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
39	* at EIP and does the required.
40	*
41	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
42	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
43	* TPR). See hmR3ReplaceTprInstr() for the details.
44	*
45	* @returns VBox status code.
46	* @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
47	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
48	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
49	*
50	* @param pVCpu The cross context virtual CPU structure.
51	* @param pCtx Pointer to the guest-CPU context.
52	*/
53	int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx)
54	{
55	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
56
57	/*
58	* We do this in a loop as we increment the RIP after a successful emulation
59	* and the new RIP may be a patched instruction which needs emulation as well.
60	*/
61	bool fPatchFound = false;
62	PVM pVM = pVCpu->CTX_SUFF(pVM);
63	for (;;)
64	{
65	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
66	if (!pPatch)
67	break;
68	fPatchFound = true;
69
70	uint8_t u8Tpr;
71	switch (pPatch->enmType)
72	{
73	case HMTPRINSTR_READ:
74	{
75	bool fPending;
76	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
77	AssertRC(rc);
78
79	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
80	AssertRC(rc);
81	pCtx->rip += pPatch->cbOp;
82	pCtx->eflags.Bits.u1RF = 0;
83	break;
84	}
85
86	case HMTPRINSTR_WRITE_REG:
87	case HMTPRINSTR_WRITE_IMM:
88	{
89	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
90	{
91	uint32_t u32Val;
92	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
93	AssertRC(rc);
94	u8Tpr = u32Val;
95	}
96	else
97	u8Tpr = (uint8_t)pPatch->uSrcOperand;
98
99	int rc2 = APICSetTpr(pVCpu, u8Tpr);
100	AssertRC(rc2);
101	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
102
103	pCtx->rip += pPatch->cbOp;
104	pCtx->eflags.Bits.u1RF = 0;
105	break;
106	}
107
108	default:
109	{
110	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
111	pVCpu->hm.s.u32HMError = pPatch->enmType;
112	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
113	}
114	}
115	}
116
117	return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
118	}
119
120
121	/**
122	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
123	* in IEM).
124	*
125	* @param pVCpu The cross context virtual CPU structure.
126	* @param pCtx Pointer to the guest-CPU context.
127	*
128	* @sa hmR0SvmVmRunCacheVmcb.
129	*/
130	VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx)
131	{
132	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
133	if (pVmcbNstGstCache->fCacheValid)
134	{
135	/*
136	* Restore fields as our own code might look at the VMCB controls as part
137	* of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
138	* restore these fields because currently none of them are written back to memory
139	* by a physical CPU on #VMEXIT.
140	*/
141	PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
142	pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
143	pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
144	pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
145	pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
146	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
147	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
148	pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
149	pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
150	pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
151	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
152	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
153	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
154	pVmcbNstGstCache->fCacheValid = false;
155	}
156
157	/*
158	* Currently, VMRUN, #VMEXIT transitions involves trips to ring-3 that would flag a full
159	* CPU state change. However, if we exit to ring-3 in response to receiving a physical
160	* interrupt, we skip signaling any CPU state change as normally no change is done to the
161	* execution state (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
162	*
163	* With nested-guests, the state can change on trip to ring-3 for e.g., we might perform a
164	* SVM_EXIT_INTR #VMEXIT for the nested-guest in ring-3. Hence we signal a full CPU state
165	* change here.
166	*/
167	/** @todo Only signal state needed for VM-exit (e.g. skip
168	* LDTR, TR etc., see IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK.
169	* Do this while extending HM_CHANGED_xxx flags. See
170	* todo in hmR0SvmHandleExitNested(). */
171	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
172	}
173
174
175	/**
176	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
177	* enabled for the VM.
178	*
179	* @returns @c true if VGIF is enabled, @c false otherwise.
180	* @param pVM The cross context VM structure.
181	*
182	* @remarks This value returned by this functions is expected by the callers not
183	* to change throughout the lifetime of the VM.
184	*/
185	VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM)
186	{
187	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
188	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
189
190	return HMIsEnabled(pVM) && fVGif && fUseVGif;
191	}
192
193
194	/**
195	* Applies the TSC offset of an SVM nested-guest if any and returns the new TSC
196	* value for the nested-guest.
197	*
198	* @returns The TSC offset after applying any nested-guest TSC offset.
199	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
200	* @param uTicks The guest TSC.
201	*
202	* @remarks This function looks at the VMCB cache rather than directly at the
203	* nested-guest VMCB. The latter may have been modified for executing
204	* using hardware-assisted SVM.
205	*
206	* @note If you make any changes to this function, please check if
207	* hmR0SvmNstGstUndoTscOffset() needs adjusting.
208	*
209	* @sa CPUMApplyNestedGuestTscOffset(), hmR0SvmNstGstUndoTscOffset().
210	*/
211	VMM_INT_DECL(uint64_t) HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks)
212	{
213	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
214	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); RT_NOREF(pCtx);
215	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
216	Assert(pVmcbNstGstCache->fCacheValid);
217	return uTicks + pVmcbNstGstCache->u64TSCOffset;
218	}
219
220
221	/**
222	* Interface used by IEM to handle patched TPR accesses.
223	*
224	* @returns VBox status code
225	* @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
226	* @retval VERR_NOT_FOUND if hypercall was _not_ handled.
227	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
228	*
229	* @param pVCpu The cross context virtual CPU structure.
230	* @param pCtx Pointer to the guest-CPU context.
231	*/
232	VMM_INT_DECL(int) HMHCSvmMaybeMovTprHypercall(PVMCPU pVCpu, PCPUMCTX pCtx)
233	{
234	PVM pVM = pVCpu->CTX_SUFF(pVM);
235	if (pVM->hm.s.fTprPatchingAllowed)
236	{
237	int rc = hmSvmEmulateMovTpr(pVCpu, pCtx);
238	if (RT_SUCCESS(rc))
239	return VINF_SUCCESS;
240	return rc;
241	}
242	return VERR_NOT_FOUND;
243	}
244
245	#endif /* !IN_RC */
246
247	/**
248	* Converts an SVM event type to a TRPM event type.
249	*
250	* @returns The TRPM event type.
251	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
252	* of recognized trap types.
253	*
254	* @param pEvent Pointer to the SVM event.
255	*/
256	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent)
257	{
258	uint8_t const uType = pEvent->n.u3Type;
259	switch (uType)
260	{
261	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
262	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
263	case SVM_EVENT_EXCEPTION:
264	case SVM_EVENT_NMI: return TRPM_TRAP;
265	default:
266	break;
267	}
268	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
269	return TRPM_32BIT_HACK;
270	}
271
272
273	/**
274	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
275	*
276	* @returns VBox status code.
277	* @param idMsr The MSR being requested.
278	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
279	* bitmap for @a idMsr.
280	* @param puMsrpmBit Where to store the bit offset starting at the byte
281	* returned in @a pbOffMsrpm.
282	*/
283	VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit)
284	{
285	Assert(pbOffMsrpm);
286	Assert(puMsrpmBit);
287
288	/*
289	* MSRPM Layout:
290	* Byte offset MSR range
291	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
292	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
293	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
294	* 0x1800 - 0x1fff Reserved
295	*
296	* Each MSR is represented by 2 permission bits (read and write).
297	*/
298	if (idMsr <= 0x00001fff)
299	{
300	/* Pentium-compatible MSRs. */
301	uint32_t const bitoffMsr = idMsr << 1;
302	*pbOffMsrpm = bitoffMsr >> 3;
303	*puMsrpmBit = bitoffMsr & 7;
304	return VINF_SUCCESS;
305	}
306
307	if ( idMsr >= 0xc0000000
308	&& idMsr <= 0xc0001fff)
309	{
310	/* AMD Sixth Generation x86 Processor MSRs. */
311	uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
312	*pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
313	*puMsrpmBit = bitoffMsr & 7;
314	return VINF_SUCCESS;
315	}
316
317	if ( idMsr >= 0xc0010000
318	&& idMsr <= 0xc0011fff)
319	{
320	/* AMD Seventh and Eighth Generation Processor MSRs. */
321	uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
322	*pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
323	*puMsrpmBit = bitoffMsr & 7;
324	return VINF_SUCCESS;
325	}
326
327	*pbOffMsrpm = 0;
328	*puMsrpmBit = 0;
329	return VERR_OUT_OF_RANGE;
330	}
331
332
333	/**
334	* Determines whether an IOIO intercept is active for the nested-guest or not.
335	*
336	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
337	* @param u16Port The IO port being accessed.
338	* @param enmIoType The type of IO access.
339	* @param cbReg The IO operand size in bytes.
340	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
341	* @param iEffSeg The effective segment number.
342	* @param fRep Whether this is a repeating IO instruction (REP prefix).
343	* @param fStrIo Whether this is a string IO instruction.
344	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
345	* Optional, can be NULL.
346	*/
347	VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
348	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
349	PSVMIOIOEXITINFO pIoExitInfo)
350	{
351	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
352	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
353
354	/*
355	* The IOPM layout:
356	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
357	* two 4K pages.
358	*
359	* For IO instructions that access more than a single byte, the permission bits
360	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
361	*
362	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
363	* we need 3 extra bits beyond the second 4K page.
364	*/
365	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
366
367	uint16_t const offIopm = u16Port >> 3;
368	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
369	uint8_t const cShift = u16Port - (offIopm << 3);
370	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
371
372	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
373	Assert(pbIopm);
374	pbIopm += offIopm;
375	uint16_t const u16Iopm = (uint16_t )pbIopm;
376	if (u16Iopm & fIopmMask)
377	{
378	if (pIoExitInfo)
379	{
380	static const uint32_t s_auIoOpSize[] =
381	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
382
383	static const uint32_t s_auIoAddrSize[] =
384	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
385
386	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
387	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
388	pIoExitInfo->n.u1Str = fStrIo;
389	pIoExitInfo->n.u1Rep = fRep;
390	pIoExitInfo->n.u3Seg = iEffSeg & 7;
391	pIoExitInfo->n.u1Type = enmIoType;
392	pIoExitInfo->n.u16Port = u16Port;
393	}
394	return true;
395	}
396
397	/** @todo remove later (for debugging as VirtualBox always traps all IO
398	* intercepts). */
399	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
400	return false;
401	}
402
403
404	/**
405	* Returns whether HM has cached the nested-guest VMCB.
406	*
407	* If the VMCB is cached by HM, it means HM may have potentially modified the
408	* VMCB for execution using hardware-assisted SVM.
409	*
410	* @returns true if HM has cached the nested-guest VMCB, false otherwise.
411	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
412	*/
413	VMM_INT_DECL(bool) HMHasGuestSvmVmcbCached(PVMCPU pVCpu)
414	{
415	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
416	return pVmcbNstGstCache->fCacheValid;
417	}
418
419
420	/**
421	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
422	* active.
423	*
424	* @returns @c true if in intercept is set, @c false otherwise.
425	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
426	* @param fIntercept The SVM control/instruction intercept, see
427	* SVM_CTRL_INTERCEPT_*.
428	*/
429	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, uint64_t fIntercept)
430	{
431	Assert(HMHasGuestSvmVmcbCached(pVCpu));
432	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
433	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
434	}
435
436
437	/**
438	* Checks if the nested-guest VMCB has the specified CR read intercept active.
439	*
440	* @returns @c true if in intercept is set, @c false otherwise.
441	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
442	* @param uCr The CR register number (0 to 15).
443	*/
444	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
445	{
446	Assert(uCr < 16);
447	Assert(HMHasGuestSvmVmcbCached(pVCpu));
448	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
449	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
450	}
451
452
453	/**
454	* Checks if the nested-guest VMCB has the specified CR write intercept active.
455	*
456	* @returns @c true if in intercept is set, @c false otherwise.
457	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
458	* @param uCr The CR register number (0 to 15).
459	*/
460	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
461	{
462	Assert(uCr < 16);
463	Assert(HMHasGuestSvmVmcbCached(pVCpu));
464	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
465	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
466	}
467
468
469	/**
470	* Checks if the nested-guest VMCB has the specified DR read intercept active.
471	*
472	* @returns @c true if in intercept is set, @c false otherwise.
473	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
474	* @param uDr The DR register number (0 to 15).
475	*/
476	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
477	{
478	Assert(uDr < 16);
479	Assert(HMHasGuestSvmVmcbCached(pVCpu));
480	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
481	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
482	}
483
484
485	/**
486	* Checks if the nested-guest VMCB has the specified DR write intercept active.
487	*
488	* @returns @c true if in intercept is set, @c false otherwise.
489	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
490	* @param uDr The DR register number (0 to 15).
491	*/
492	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
493	{
494	Assert(uDr < 16);
495	Assert(HMHasGuestSvmVmcbCached(pVCpu));
496	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
497	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
498	}
499
500
501	/**
502	* Checks if the nested-guest VMCB has the specified exception intercept active.
503	*
504	* @returns true if in intercept is active, false otherwise.
505	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
506	* @param uVector The exception / interrupt vector.
507	*/
508	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, uint8_t uVector)
509	{
510	Assert(uVector < 32);
511	Assert(HMHasGuestSvmVmcbCached(pVCpu));
512	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
513	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
514	}
515
516
517	/**
518	* Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
519	*
520	* @returns true if virtual-interrupts are masked, @c false otherwise.
521	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
522	*/
523	VMM_INT_DECL(bool) HMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu)
524	{
525	Assert(HMHasGuestSvmVmcbCached(pVCpu));
526	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
527	return pVmcbNstGstCache->fVIntrMasking;
528	}
529
530
531	/**
532	* Checks if the nested-guest VMCB has nested-paging enabled.
533	*
534	* @returns true if nested-paging is enabled, @c false otherwise.
535	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
536	*/
537	VMM_INT_DECL(bool) HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu)
538	{
539	Assert(HMHasGuestSvmVmcbCached(pVCpu));
540	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
541	return pVmcbNstGstCache->fNestedPaging;
542	}
543
544
545	/**
546	* Returns the nested-guest VMCB pause-filter count.
547	*
548	* @returns The pause-filter count.
549	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
550	*/
551	VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu)
552	{
553	Assert(HMHasGuestSvmVmcbCached(pVCpu));
554	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
555	return pVmcbNstGstCache->u16PauseFilterCount;
556	}
557

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 72727

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