HMSVMAll.cpp@ 75884

Last change on this file since 75884 was 75759, checked in by vboxsync, 6 years ago
VMM: Nested SVM: bugref:7243 Remove super confusing virtual-GIF vs GIF handling.
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1	/* $Id: HMSVMAll.cpp 75759 2018-11-27 07:10:10Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/vm.h>
29
30
31	#ifndef IN_RC
32
33	/**
34	* Emulates a simple MOV TPR (CR8) instruction.
35	*
36	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
37	* at EIP and does the required.
38	*
39	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
40	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
41	* TPR). See hmR3ReplaceTprInstr() for the details.
42	*
43	* @returns VBox status code.
44	* @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
45	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
46	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
47	*
48	* @param pVCpu The cross context virtual CPU structure.
49	* @param pCtx Pointer to the guest-CPU context.
50	*/
51	int hmSvmEmulateMovTpr(PVMCPU pVCpu)
52	{
53	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
54	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
55
56	/*
57	* We do this in a loop as we increment the RIP after a successful emulation
58	* and the new RIP may be a patched instruction which needs emulation as well.
59	*/
60	bool fPatchFound = false;
61	PVM pVM = pVCpu->CTX_SUFF(pVM);
62	for (;;)
63	{
64	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
65	if (!pPatch)
66	break;
67	fPatchFound = true;
68
69	uint8_t u8Tpr;
70	switch (pPatch->enmType)
71	{
72	case HMTPRINSTR_READ:
73	{
74	bool fPending;
75	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
76	AssertRC(rc);
77
78	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
79	AssertRC(rc);
80	pCtx->rip += pPatch->cbOp;
81	pCtx->eflags.Bits.u1RF = 0;
82	break;
83	}
84
85	case HMTPRINSTR_WRITE_REG:
86	case HMTPRINSTR_WRITE_IMM:
87	{
88	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
89	{
90	uint32_t u32Val;
91	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
92	AssertRC(rc);
93	u8Tpr = u32Val;
94	}
95	else
96	u8Tpr = (uint8_t)pPatch->uSrcOperand;
97
98	int rc2 = APICSetTpr(pVCpu, u8Tpr);
99	AssertRC(rc2);
100	pCtx->rip += pPatch->cbOp;
101	pCtx->eflags.Bits.u1RF = 0;
102	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR
103	\| HM_CHANGED_GUEST_RIP
104	\| HM_CHANGED_GUEST_RFLAGS);
105	break;
106	}
107
108	default:
109	{
110	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
111	pVCpu->hm.s.u32HMError = pPatch->enmType;
112	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
113	}
114	}
115	}
116
117	return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
118	}
119
120	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
121	/**
122	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
123	* in IEM).
124	*
125	* @param pVCpu The cross context virtual CPU structure.
126	* @param pCtx Pointer to the guest-CPU context.
127	*
128	* @sa hmR0SvmVmRunCacheVmcb.
129	*/
130	VMM_INT_DECL(void) HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx)
131	{
132	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
133	if (pVmcbNstGstCache->fCacheValid)
134	{
135	/*
136	* Restore fields as our own code might look at the VMCB controls as part
137	* of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
138	* restore these fields because currently none of them are written back to memory
139	* by a physical CPU on #VMEXIT.
140	*/
141	PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
142	pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
143	pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
144	pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
145	pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
146	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
147	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
148	pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
149	pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
150	pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
151	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
152	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
153	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
154	pVmcbNstGstCache->fCacheValid = false;
155	}
156
157	/*
158	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
159	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
160	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
161	*
162	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
163	* try to inject a nested-guest physical interrupt and cause a SVM_EXIT_INTR #VMEXIT for
164	* the nested-guest from ring-3. Import the complete state here as we will be swapping
165	* to the guest VMCB after the #VMEXIT.
166	*/
167	CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
168	AssertMsg(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL),
169	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", pVCpu->cpum.GstCtx.fExtrn, CPUMCTX_EXTRN_ALL));
170	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
171	}
172	# endif
173
174	/**
175	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
176	* enabled for the VM.
177	*
178	* @returns @c true if VGIF is enabled, @c false otherwise.
179	* @param pVM The cross context VM structure.
180	*
181	* @remarks This value returned by this functions is expected by the callers not
182	* to change throughout the lifetime of the VM.
183	*/
184	VMM_INT_DECL(bool) HMSvmIsVGifActive(PVM pVM)
185	{
186	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
187	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
188	return fVGif && fUseVGif;
189	}
190
191
192	/**
193	* Applies the TSC offset of an SVM nested-guest if any and returns the new TSC
194	* value for the nested-guest.
195	*
196	* @returns The TSC offset after applying any nested-guest TSC offset.
197	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
198	* @param uTicks The guest TSC.
199	*
200	* @remarks This function looks at the VMCB cache rather than directly at the
201	* nested-guest VMCB. The latter may have been modified for executing
202	* using hardware-assisted SVM.
203	*
204	* @note If you make any changes to this function, please check if
205	* hmR0SvmNstGstUndoTscOffset() needs adjusting.
206	*
207	* @sa CPUMApplyNestedGuestTscOffset(), hmR0SvmNstGstUndoTscOffset().
208	*/
209	VMM_INT_DECL(uint64_t) HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks)
210	{
211	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
212	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); RT_NOREF(pCtx);
213	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
214	Assert(pVmcbNstGstCache->fCacheValid);
215	return uTicks + pVmcbNstGstCache->u64TSCOffset;
216	}
217
218
219	/**
220	* Interface used by IEM to handle patched TPR accesses.
221	*
222	* @returns VBox status code
223	* @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
224	* @retval VERR_NOT_FOUND if hypercall was _not_ handled.
225	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
226	*
227	* @param pVCpu The cross context virtual CPU structure.
228	*/
229	VMM_INT_DECL(int) HMHCSvmMaybeMovTprHypercall(PVMCPU pVCpu)
230	{
231	PVM pVM = pVCpu->CTX_SUFF(pVM);
232	if (pVM->hm.s.fTprPatchingAllowed)
233	{
234	int rc = hmSvmEmulateMovTpr(pVCpu);
235	if (RT_SUCCESS(rc))
236	return VINF_SUCCESS;
237	return rc;
238	}
239	return VERR_NOT_FOUND;
240	}
241
242
243	/**
244	* Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
245	* incorrect code bytes may be fetched after a world-switch".
246	*
247	* @param pu32Family Where to store the CPU family (can be NULL).
248	* @param pu32Model Where to store the CPU model (can be NULL).
249	* @param pu32Stepping Where to store the CPU stepping (can be NULL).
250	* @returns true if the erratum applies, false otherwise.
251	*/
252	VMM_INT_DECL(int) HMSvmIsSubjectToErratum170(uint32_t pu32Family, uint32_t pu32Model, uint32_t *pu32Stepping)
253	{
254	/*
255	* Erratum 170 which requires a forced TLB flush for each world switch:
256	* See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
257	*
258	* All BH-G1/2 and DH-G1/2 models include a fix:
259	* Athlon X2: 0x6b 1/2
260	* 0x68 1/2
261	* Athlon 64: 0x7f 1
262	* 0x6f 2
263	* Sempron: 0x7f 1/2
264	* 0x6f 2
265	* 0x6c 2
266	* 0x7c 2
267	* Turion 64: 0x68 2
268	*/
269	uint32_t u32Dummy;
270	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
271	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
272	u32BaseFamily = (u32Version >> 8) & 0xf;
273	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
274	u32Model = ((u32Version >> 4) & 0xf);
275	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
276	u32Stepping = u32Version & 0xf;
277
278	bool fErratumApplies = false;
279	if ( u32Family == 0xf
280	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
281	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
282	{
283	fErratumApplies = true;
284	}
285
286	if (pu32Family)
287	*pu32Family = u32Family;
288	if (pu32Model)
289	*pu32Model = u32Model;
290	if (pu32Stepping)
291	*pu32Stepping = u32Stepping;
292
293	return fErratumApplies;
294	}
295
296	#endif /* !IN_RC */
297
298	/**
299	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
300	*
301	* @returns VBox status code.
302	* @param idMsr The MSR being requested.
303	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
304	* bitmap for @a idMsr.
305	* @param puMsrpmBit Where to store the bit offset starting at the byte
306	* returned in @a pbOffMsrpm.
307	*/
308	VMM_INT_DECL(int) HMSvmGetMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit)
309	{
310	Assert(pbOffMsrpm);
311	Assert(puMsrpmBit);
312
313	/*
314	* MSRPM Layout:
315	* Byte offset MSR range
316	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
317	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
318	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
319	* 0x1800 - 0x1fff Reserved
320	*
321	* Each MSR is represented by 2 permission bits (read and write).
322	*/
323	if (idMsr <= 0x00001fff)
324	{
325	/* Pentium-compatible MSRs. */
326	uint32_t const bitoffMsr = idMsr << 1;
327	*pbOffMsrpm = bitoffMsr >> 3;
328	*puMsrpmBit = bitoffMsr & 7;
329	return VINF_SUCCESS;
330	}
331
332	if ( idMsr >= 0xc0000000
333	&& idMsr <= 0xc0001fff)
334	{
335	/* AMD Sixth Generation x86 Processor MSRs. */
336	uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
337	*pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
338	*puMsrpmBit = bitoffMsr & 7;
339	return VINF_SUCCESS;
340	}
341
342	if ( idMsr >= 0xc0010000
343	&& idMsr <= 0xc0011fff)
344	{
345	/* AMD Seventh and Eighth Generation Processor MSRs. */
346	uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
347	*pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
348	*puMsrpmBit = bitoffMsr & 7;
349	return VINF_SUCCESS;
350	}
351
352	*pbOffMsrpm = 0;
353	*puMsrpmBit = 0;
354	return VERR_OUT_OF_RANGE;
355	}
356
357
358	/**
359	* Determines whether an IOIO intercept is active for the nested-guest or not.
360	*
361	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
362	* @param u16Port The IO port being accessed.
363	* @param enmIoType The type of IO access.
364	* @param cbReg The IO operand size in bytes.
365	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
366	* @param iEffSeg The effective segment number.
367	* @param fRep Whether this is a repeating IO instruction (REP prefix).
368	* @param fStrIo Whether this is a string IO instruction.
369	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
370	* Optional, can be NULL.
371	*/
372	VMM_INT_DECL(bool) HMSvmIsIOInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
373	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
374	PSVMIOIOEXITINFO pIoExitInfo)
375	{
376	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
377	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
378
379	/*
380	* The IOPM layout:
381	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
382	* two 4K pages.
383	*
384	* For IO instructions that access more than a single byte, the permission bits
385	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
386	*
387	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
388	* we need 3 extra bits beyond the second 4K page.
389	*/
390	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
391
392	uint16_t const offIopm = u16Port >> 3;
393	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
394	uint8_t const cShift = u16Port - (offIopm << 3);
395	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
396
397	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
398	Assert(pbIopm);
399	pbIopm += offIopm;
400	uint16_t const u16Iopm = (uint16_t )pbIopm;
401	if (u16Iopm & fIopmMask)
402	{
403	if (pIoExitInfo)
404	{
405	static const uint32_t s_auIoOpSize[] =
406	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
407
408	static const uint32_t s_auIoAddrSize[] =
409	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
410
411	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
412	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
413	pIoExitInfo->n.u1Str = fStrIo;
414	pIoExitInfo->n.u1Rep = fRep;
415	pIoExitInfo->n.u3Seg = iEffSeg & 7;
416	pIoExitInfo->n.u1Type = enmIoType;
417	pIoExitInfo->n.u16Port = u16Port;
418	}
419	return true;
420	}
421
422	/** @todo remove later (for debugging as VirtualBox always traps all IO
423	* intercepts). */
424	AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
425	return false;
426	}
427
428
429	/**
430	* Converts an SVM event type to a TRPM event type.
431	*
432	* @returns The TRPM event type.
433	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
434	* of recognized trap types.
435	*
436	* @param pEvent Pointer to the SVM event.
437	*/
438	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent)
439	{
440	uint8_t const uType = pEvent->n.u3Type;
441	switch (uType)
442	{
443	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
444	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
445	case SVM_EVENT_EXCEPTION:
446	case SVM_EVENT_NMI: return TRPM_TRAP;
447	default:
448	break;
449	}
450	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
451	return TRPM_32BIT_HACK;
452	}
453
454
455	/**
456	* Returns whether HM has cached the nested-guest VMCB.
457	*
458	* If the VMCB is cached by HM, it means HM may have potentially modified the
459	* VMCB for execution using hardware-assisted SVM.
460	*
461	* @returns true if HM has cached the nested-guest VMCB, false otherwise.
462	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
463	*/
464	VMM_INT_DECL(bool) HMHasGuestSvmVmcbCached(PVMCPU pVCpu)
465	{
466	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
467	return pVmcbNstGstCache->fCacheValid;
468	}
469
470
471	/**
472	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
473	* active.
474	*
475	* @returns @c true if in intercept is set, @c false otherwise.
476	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
477	* @param fIntercept The SVM control/instruction intercept, see
478	* SVM_CTRL_INTERCEPT_*.
479	*/
480	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, uint64_t fIntercept)
481	{
482	Assert(HMHasGuestSvmVmcbCached(pVCpu));
483	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
484	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
485	}
486
487
488	/**
489	* Checks if the nested-guest VMCB has the specified CR read intercept active.
490	*
491	* @returns @c true if in intercept is set, @c false otherwise.
492	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
493	* @param uCr The CR register number (0 to 15).
494	*/
495	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
496	{
497	Assert(uCr < 16);
498	Assert(HMHasGuestSvmVmcbCached(pVCpu));
499	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
500	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
501	}
502
503
504	/**
505	* Checks if the nested-guest VMCB has the specified CR write intercept active.
506	*
507	* @returns @c true if in intercept is set, @c false otherwise.
508	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
509	* @param uCr The CR register number (0 to 15).
510	*/
511	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
512	{
513	Assert(uCr < 16);
514	Assert(HMHasGuestSvmVmcbCached(pVCpu));
515	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
516	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
517	}
518
519
520	/**
521	* Checks if the nested-guest VMCB has the specified DR read intercept active.
522	*
523	* @returns @c true if in intercept is set, @c false otherwise.
524	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
525	* @param uDr The DR register number (0 to 15).
526	*/
527	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
528	{
529	Assert(uDr < 16);
530	Assert(HMHasGuestSvmVmcbCached(pVCpu));
531	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
532	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
533	}
534
535
536	/**
537	* Checks if the nested-guest VMCB has the specified DR write intercept active.
538	*
539	* @returns @c true if in intercept is set, @c false otherwise.
540	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
541	* @param uDr The DR register number (0 to 15).
542	*/
543	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
544	{
545	Assert(uDr < 16);
546	Assert(HMHasGuestSvmVmcbCached(pVCpu));
547	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
548	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
549	}
550
551
552	/**
553	* Checks if the nested-guest VMCB has the specified exception intercept active.
554	*
555	* @returns true if in intercept is active, false otherwise.
556	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
557	* @param uVector The exception / interrupt vector.
558	*/
559	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, uint8_t uVector)
560	{
561	Assert(uVector < 32);
562	Assert(HMHasGuestSvmVmcbCached(pVCpu));
563	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
564	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
565	}
566
567
568	/**
569	* Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
570	*
571	* @returns true if virtual-interrupts are masked, @c false otherwise.
572	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
573	*/
574	VMM_INT_DECL(bool) HMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu)
575	{
576	Assert(HMHasGuestSvmVmcbCached(pVCpu));
577	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
578	return pVmcbNstGstCache->fVIntrMasking;
579	}
580
581
582	/**
583	* Checks if the nested-guest VMCB has nested-paging enabled.
584	*
585	* @returns true if nested-paging is enabled, @c false otherwise.
586	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
587	*/
588	VMM_INT_DECL(bool) HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu)
589	{
590	Assert(HMHasGuestSvmVmcbCached(pVCpu));
591	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
592	return pVmcbNstGstCache->fNestedPaging;
593	}
594
595
596	/**
597	* Returns the nested-guest VMCB pause-filter count.
598	*
599	* @returns The pause-filter count.
600	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
601	*/
602	VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu)
603	{
604	Assert(HMHasGuestSvmVmcbCached(pVCpu));
605	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
606	return pVmcbNstGstCache->u16PauseFilterCount;
607	}
608

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 75884

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