HMSVMAll.cpp@ 78352

Last change on this file since 78352 was 78220, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
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1	/* $Id: HMSVMAll.cpp 78220 2019-04-20 04:08:44Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/vm.h>
29
30	#include <VBox/err.h>
31
32
33	#ifndef IN_RC
34
35	/**
36	* Emulates a simple MOV TPR (CR8) instruction.
37	*
38	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
39	* at EIP and does the required.
40	*
41	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
42	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
43	* TPR). See hmR3ReplaceTprInstr() for the details.
44	*
45	* @returns VBox status code.
46	* @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
47	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
48	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
49	*
50	* @param pVCpu The cross context virtual CPU structure.
51	* @param pCtx Pointer to the guest-CPU context.
52	*/
53	VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu)
54	{
55	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
56	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
57
58	/*
59	* We do this in a loop as we increment the RIP after a successful emulation
60	* and the new RIP may be a patched instruction which needs emulation as well.
61	*/
62	bool fPatchFound = false;
63	PVM pVM = pVCpu->CTX_SUFF(pVM);
64	for (;;)
65	{
66	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
67	if (!pPatch)
68	break;
69	fPatchFound = true;
70
71	uint8_t u8Tpr;
72	switch (pPatch->enmType)
73	{
74	case HMTPRINSTR_READ:
75	{
76	bool fPending;
77	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
78	AssertRC(rc);
79
80	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
81	AssertRC(rc);
82	pCtx->rip += pPatch->cbOp;
83	pCtx->eflags.Bits.u1RF = 0;
84	break;
85	}
86
87	case HMTPRINSTR_WRITE_REG:
88	case HMTPRINSTR_WRITE_IMM:
89	{
90	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
91	{
92	uint32_t u32Val;
93	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
94	AssertRC(rc);
95	u8Tpr = u32Val;
96	}
97	else
98	u8Tpr = (uint8_t)pPatch->uSrcOperand;
99
100	int rc2 = APICSetTpr(pVCpu, u8Tpr);
101	AssertRC(rc2);
102	pCtx->rip += pPatch->cbOp;
103	pCtx->eflags.Bits.u1RF = 0;
104	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR
105	\| HM_CHANGED_GUEST_RIP
106	\| HM_CHANGED_GUEST_RFLAGS);
107	break;
108	}
109
110	default:
111	{
112	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
113	pVCpu->hm.s.u32HMError = pPatch->enmType;
114	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
115	}
116	}
117	}
118
119	return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
120	}
121
122	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
123	/**
124	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
125	* in IEM).
126	*
127	* @param pVCpu The cross context virtual CPU structure.
128	* @param pCtx Pointer to the guest-CPU context.
129	*
130	* @sa hmR0SvmVmRunCacheVmcb.
131	*/
132	VMM_INT_DECL(void) HMNotifySvmNstGstVmexit(PVMCPU pVCpu, PCPUMCTX pCtx)
133	{
134	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
135	if (pVmcbNstGstCache->fCacheValid)
136	{
137	/*
138	* Restore fields as our own code might look at the VMCB controls as part
139	* of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
140	* restore these fields because currently none of them are written back to memory
141	* by a physical CPU on #VMEXIT.
142	*/
143	PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
144	pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
145	pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
146	pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
147	pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
148	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
149	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
150	pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
151	pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
152	pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
153	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
154	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
155	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
156	pVmcbNstGstCache->fCacheValid = false;
157	}
158
159	/*
160	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
161	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
162	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
163	*
164	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
165	* try to inject a nested-guest physical interrupt and cause a SVM_EXIT_INTR #VMEXIT for
166	* the nested-guest from ring-3. Import the complete state here as we will be swapping
167	* to the guest VMCB after the #VMEXIT.
168	*/
169	CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
170	AssertMsg(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL),
171	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", pVCpu->cpum.GstCtx.fExtrn, CPUMCTX_EXTRN_ALL));
172	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
173	}
174	# endif
175
176	/**
177	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
178	* enabled for the VM.
179	*
180	* @returns @c true if VGIF is enabled, @c false otherwise.
181	* @param pVM The cross context VM structure.
182	*
183	* @remarks This value returned by this functions is expected by the callers not
184	* to change throughout the lifetime of the VM.
185	*/
186	VMM_INT_DECL(bool) HMIsSvmVGifActive(PVM pVM)
187	{
188	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
189	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
190	return fVGif && fUseVGif;
191	}
192
193
194	/**
195	* Applies the TSC offset of an SVM nested-guest if any and returns the new TSC
196	* value for the nested-guest.
197	*
198	* @returns The TSC offset after applying any nested-guest TSC offset.
199	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
200	* @param uTicks The guest TSC.
201	*
202	* @remarks This function looks at the VMCB cache rather than directly at the
203	* nested-guest VMCB. The latter may have been modified for executing
204	* using hardware-assisted SVM.
205	*
206	* @sa CPUMRemoveNestedGuestTscOffset, HMRemoveSvmNstGstTscOffset.
207	*/
208	VMM_INT_DECL(uint64_t) HMApplySvmNstGstTscOffset(PVMCPU pVCpu, uint64_t uTicks)
209	{
210	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
211	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); RT_NOREF(pCtx);
212	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
213	Assert(pVmcbNstGstCache->fCacheValid);
214	return uTicks + pVmcbNstGstCache->u64TSCOffset;
215	}
216
217
218	/**
219	* Removes the TSC offset of an SVM nested-guest if any and returns the new TSC
220	* value for the guest.
221	*
222	* @returns The TSC offset after removing any nested-guest TSC offset.
223	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
224	* @param uTicks The nested-guest TSC.
225	*
226	* @remarks This function looks at the VMCB cache rather than directly at the
227	* nested-guest VMCB. The latter may have been modified for executing
228	* using hardware-assisted SVM.
229	*
230	* @sa CPUMApplyNestedGuestTscOffset, HMApplySvmNstGstTscOffset.
231	*/
232	VMM_INT_DECL(uint64_t) HMRemoveSvmNstGstTscOffset(PVMCPU pVCpu, uint64_t uTicks)
233	{
234	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
235	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); RT_NOREF(pCtx);
236	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
237	Assert(pVmcbNstGstCache->fCacheValid);
238	return uTicks - pVmcbNstGstCache->u64TSCOffset;
239	}
240
241
242	/**
243	* Interface used by IEM to handle patched TPR accesses.
244	*
245	* @returns VBox status code
246	* @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
247	* @retval VERR_NOT_FOUND if hypercall was _not_ handled.
248	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
249	*
250	* @param pVCpu The cross context virtual CPU structure.
251	*/
252	VMM_INT_DECL(int) HMHCMaybeMovTprSvmHypercall(PVMCPU pVCpu)
253	{
254	PVM pVM = pVCpu->CTX_SUFF(pVM);
255	if (pVM->hm.s.fTprPatchingAllowed)
256	{
257	int rc = hmEmulateSvmMovTpr(pVCpu);
258	if (RT_SUCCESS(rc))
259	return VINF_SUCCESS;
260	return rc;
261	}
262	return VERR_NOT_FOUND;
263	}
264
265
266	/**
267	* Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
268	* incorrect code bytes may be fetched after a world-switch".
269	*
270	* @param pu32Family Where to store the CPU family (can be NULL).
271	* @param pu32Model Where to store the CPU model (can be NULL).
272	* @param pu32Stepping Where to store the CPU stepping (can be NULL).
273	* @returns true if the erratum applies, false otherwise.
274	*/
275	VMM_INT_DECL(int) HMIsSubjectToSvmErratum170(uint32_t pu32Family, uint32_t pu32Model, uint32_t *pu32Stepping)
276	{
277	/*
278	* Erratum 170 which requires a forced TLB flush for each world switch:
279	* See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
280	*
281	* All BH-G1/2 and DH-G1/2 models include a fix:
282	* Athlon X2: 0x6b 1/2
283	* 0x68 1/2
284	* Athlon 64: 0x7f 1
285	* 0x6f 2
286	* Sempron: 0x7f 1/2
287	* 0x6f 2
288	* 0x6c 2
289	* 0x7c 2
290	* Turion 64: 0x68 2
291	*/
292	uint32_t u32Dummy;
293	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
294	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
295	u32BaseFamily = (u32Version >> 8) & 0xf;
296	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
297	u32Model = ((u32Version >> 4) & 0xf);
298	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
299	u32Stepping = u32Version & 0xf;
300
301	bool fErratumApplies = false;
302	if ( u32Family == 0xf
303	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
304	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
305	{
306	fErratumApplies = true;
307	}
308
309	if (pu32Family)
310	*pu32Family = u32Family;
311	if (pu32Model)
312	*pu32Model = u32Model;
313	if (pu32Stepping)
314	*pu32Stepping = u32Stepping;
315
316	return fErratumApplies;
317	}
318
319	#endif /* !IN_RC */
320
321	/**
322	* Gets the MSR permission bitmap byte and bit offset for the specified MSR.
323	*
324	* @returns VBox status code.
325	* @param idMsr The MSR being requested.
326	* @param pbOffMsrpm Where to store the byte offset in the MSR permission
327	* bitmap for @a idMsr.
328	* @param puMsrpmBit Where to store the bit offset starting at the byte
329	* returned in @a pbOffMsrpm.
330	*/
331	VMM_INT_DECL(int) HMGetSvmMsrpmOffsetAndBit(uint32_t idMsr, uint16_t pbOffMsrpm, uint8_t puMsrpmBit)
332	{
333	Assert(pbOffMsrpm);
334	Assert(puMsrpmBit);
335
336	/*
337	* MSRPM Layout:
338	* Byte offset MSR range
339	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
340	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
341	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
342	* 0x1800 - 0x1fff Reserved
343	*
344	* Each MSR is represented by 2 permission bits (read and write).
345	*/
346	if (idMsr <= 0x00001fff)
347	{
348	/* Pentium-compatible MSRs. */
349	uint32_t const bitoffMsr = idMsr << 1;
350	*pbOffMsrpm = bitoffMsr >> 3;
351	*puMsrpmBit = bitoffMsr & 7;
352	return VINF_SUCCESS;
353	}
354
355	if ( idMsr >= 0xc0000000
356	&& idMsr <= 0xc0001fff)
357	{
358	/* AMD Sixth Generation x86 Processor MSRs. */
359	uint32_t const bitoffMsr = (idMsr - 0xc0000000) << 1;
360	*pbOffMsrpm = 0x800 + (bitoffMsr >> 3);
361	*puMsrpmBit = bitoffMsr & 7;
362	return VINF_SUCCESS;
363	}
364
365	if ( idMsr >= 0xc0010000
366	&& idMsr <= 0xc0011fff)
367	{
368	/* AMD Seventh and Eighth Generation Processor MSRs. */
369	uint32_t const bitoffMsr = (idMsr - 0xc0010000) << 1;
370	*pbOffMsrpm = 0x1000 + (bitoffMsr >> 3);
371	*puMsrpmBit = bitoffMsr & 7;
372	return VINF_SUCCESS;
373	}
374
375	*pbOffMsrpm = 0;
376	*puMsrpmBit = 0;
377	return VERR_OUT_OF_RANGE;
378	}
379
380
381	/**
382	* Determines whether an IOIO intercept is active for the nested-guest or not.
383	*
384	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
385	* @param u16Port The IO port being accessed.
386	* @param enmIoType The type of IO access.
387	* @param cbReg The IO operand size in bytes.
388	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
389	* @param iEffSeg The effective segment number.
390	* @param fRep Whether this is a repeating IO instruction (REP prefix).
391	* @param fStrIo Whether this is a string IO instruction.
392	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO struct to be filled.
393	* Optional, can be NULL.
394	*/
395	VMM_INT_DECL(bool) HMIsSvmIoInterceptActive(void *pvIoBitmap, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
396	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
397	PSVMIOIOEXITINFO pIoExitInfo)
398	{
399	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
400	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
401
402	/*
403	* The IOPM layout:
404	* Each bit represents one 8-bit port. That makes a total of 0..65535 bits or
405	* two 4K pages.
406	*
407	* For IO instructions that access more than a single byte, the permission bits
408	* for all bytes are checked; if any bit is set to 1, the IO access is intercepted.
409	*
410	* Since it's possible to do a 32-bit IO access at port 65534 (accessing 4 bytes),
411	* we need 3 extra bits beyond the second 4K page.
412	*/
413	static const uint16_t s_auSizeMasks[] = { 0, 1, 3, 0, 0xf, 0, 0, 0 };
414
415	uint16_t const offIopm = u16Port >> 3;
416	uint16_t const fSizeMask = s_auSizeMasks[(cAddrSizeBits >> SVM_IOIO_OP_SIZE_SHIFT) & 7];
417	uint8_t const cShift = u16Port - (offIopm << 3);
418	uint16_t const fIopmMask = (1 << cShift) \| (fSizeMask << cShift);
419
420	uint8_t const pbIopm = (uint8_t )pvIoBitmap;
421	Assert(pbIopm);
422	pbIopm += offIopm;
423	uint16_t const u16Iopm = (uint16_t )pbIopm;
424	if (u16Iopm & fIopmMask)
425	{
426	if (pIoExitInfo)
427	{
428	static const uint32_t s_auIoOpSize[] =
429	{ SVM_IOIO_32_BIT_OP, SVM_IOIO_8_BIT_OP, SVM_IOIO_16_BIT_OP, 0, SVM_IOIO_32_BIT_OP, 0, 0, 0 };
430
431	static const uint32_t s_auIoAddrSize[] =
432	{ 0, SVM_IOIO_16_BIT_ADDR, SVM_IOIO_32_BIT_ADDR, 0, SVM_IOIO_64_BIT_ADDR, 0, 0, 0 };
433
434	pIoExitInfo->u = s_auIoOpSize[cbReg & 7];
435	pIoExitInfo->u \|= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
436	pIoExitInfo->n.u1Str = fStrIo;
437	pIoExitInfo->n.u1Rep = fRep;
438	pIoExitInfo->n.u3Seg = iEffSeg & 7;
439	pIoExitInfo->n.u1Type = enmIoType;
440	pIoExitInfo->n.u16Port = u16Port;
441	}
442	return true;
443	}
444
445	/** @todo remove later (for debugging as VirtualBox always traps all IO
446	* intercepts). */
447	AssertMsgFailed(("CPUMSvmIsIOInterceptActive: We expect an IO intercept here!\n"));
448	return false;
449	}
450
451
452	/**
453	* Converts an SVM event type to a TRPM event type.
454	*
455	* @returns The TRPM event type.
456	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
457	* of recognized trap types.
458	*
459	* @param pEvent Pointer to the SVM event.
460	* @param uVector The vector associated with the event.
461	*/
462	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent, uint8_t uVector)
463	{
464	uint8_t const uType = pEvent->n.u3Type;
465	switch (uType)
466	{
467	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
468	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
469	case SVM_EVENT_NMI: return TRPM_TRAP;
470	case SVM_EVENT_EXCEPTION:
471	{
472	if ( uVector == X86_XCPT_BP
473	\|\| uVector == X86_XCPT_OF)
474	return TRPM_SOFTWARE_INT;
475	return TRPM_TRAP;
476	}
477	default:
478	break;
479	}
480	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
481	return TRPM_32BIT_HACK;
482	}
483
484
485	/**
486	* Returns whether HM has cached the nested-guest VMCB.
487	*
488	* If the VMCB is cached by HM, it means HM may have potentially modified the
489	* VMCB for execution using hardware-assisted SVM.
490	*
491	* @returns true if HM has cached the nested-guest VMCB, false otherwise.
492	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
493	*/
494	VMM_INT_DECL(bool) HMHasGuestSvmVmcbCached(PVMCPU pVCpu)
495	{
496	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
497	return pVmcbNstGstCache->fCacheValid;
498	}
499
500
501	/**
502	* Checks if the nested-guest VMCB has the specified ctrl/instruction intercept
503	* active.
504	*
505	* @returns @c true if in intercept is set, @c false otherwise.
506	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
507	* @param fIntercept The SVM control/instruction intercept, see
508	* SVM_CTRL_INTERCEPT_*.
509	*/
510	VMM_INT_DECL(bool) HMIsGuestSvmCtrlInterceptSet(PVMCPU pVCpu, uint64_t fIntercept)
511	{
512	Assert(HMHasGuestSvmVmcbCached(pVCpu));
513	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
514	return RT_BOOL(pVmcbNstGstCache->u64InterceptCtrl & fIntercept);
515	}
516
517
518	/**
519	* Checks if the nested-guest VMCB has the specified CR read intercept active.
520	*
521	* @returns @c true if in intercept is set, @c false otherwise.
522	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
523	* @param uCr The CR register number (0 to 15).
524	*/
525	VMM_INT_DECL(bool) HMIsGuestSvmReadCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
526	{
527	Assert(uCr < 16);
528	Assert(HMHasGuestSvmVmcbCached(pVCpu));
529	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
530	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdCRx & (1 << uCr));
531	}
532
533
534	/**
535	* Checks if the nested-guest VMCB has the specified CR write intercept active.
536	*
537	* @returns @c true if in intercept is set, @c false otherwise.
538	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
539	* @param uCr The CR register number (0 to 15).
540	*/
541	VMM_INT_DECL(bool) HMIsGuestSvmWriteCRxInterceptSet(PVMCPU pVCpu, uint8_t uCr)
542	{
543	Assert(uCr < 16);
544	Assert(HMHasGuestSvmVmcbCached(pVCpu));
545	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
546	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrCRx & (1 << uCr));
547	}
548
549
550	/**
551	* Checks if the nested-guest VMCB has the specified DR read intercept active.
552	*
553	* @returns @c true if in intercept is set, @c false otherwise.
554	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
555	* @param uDr The DR register number (0 to 15).
556	*/
557	VMM_INT_DECL(bool) HMIsGuestSvmReadDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
558	{
559	Assert(uDr < 16);
560	Assert(HMHasGuestSvmVmcbCached(pVCpu));
561	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
562	return RT_BOOL(pVmcbNstGstCache->u16InterceptRdDRx & (1 << uDr));
563	}
564
565
566	/**
567	* Checks if the nested-guest VMCB has the specified DR write intercept active.
568	*
569	* @returns @c true if in intercept is set, @c false otherwise.
570	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
571	* @param uDr The DR register number (0 to 15).
572	*/
573	VMM_INT_DECL(bool) HMIsGuestSvmWriteDRxInterceptSet(PVMCPU pVCpu, uint8_t uDr)
574	{
575	Assert(uDr < 16);
576	Assert(HMHasGuestSvmVmcbCached(pVCpu));
577	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
578	return RT_BOOL(pVmcbNstGstCache->u16InterceptWrDRx & (1 << uDr));
579	}
580
581
582	/**
583	* Checks if the nested-guest VMCB has the specified exception intercept active.
584	*
585	* @returns true if in intercept is active, false otherwise.
586	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
587	* @param uVector The exception / interrupt vector.
588	*/
589	VMM_INT_DECL(bool) HMIsGuestSvmXcptInterceptSet(PVMCPU pVCpu, uint8_t uVector)
590	{
591	Assert(uVector < 32);
592	Assert(HMHasGuestSvmVmcbCached(pVCpu));
593	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
594	return RT_BOOL(pVmcbNstGstCache->u32InterceptXcpt & (1 << uVector));
595	}
596
597
598	/**
599	* Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
600	*
601	* @returns true if virtual-interrupts are masked, @c false otherwise.
602	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
603	*/
604	VMM_INT_DECL(bool) HMIsGuestSvmVirtIntrMasking(PVMCPU pVCpu)
605	{
606	Assert(HMHasGuestSvmVmcbCached(pVCpu));
607	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
608	return pVmcbNstGstCache->fVIntrMasking;
609	}
610
611
612	/**
613	* Checks if the nested-guest VMCB has nested-paging enabled.
614	*
615	* @returns true if nested-paging is enabled, @c false otherwise.
616	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
617	*/
618	VMM_INT_DECL(bool) HMIsGuestSvmNestedPagingEnabled(PVMCPU pVCpu)
619	{
620	Assert(HMHasGuestSvmVmcbCached(pVCpu));
621	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
622	return pVmcbNstGstCache->fNestedPaging;
623	}
624
625
626	/**
627	* Returns the nested-guest VMCB pause-filter count.
628	*
629	* @returns The pause-filter count.
630	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
631	*/
632	VMM_INT_DECL(uint16_t) HMGetGuestSvmPauseFilterCount(PVMCPU pVCpu)
633	{
634	Assert(HMHasGuestSvmVmcbCached(pVCpu));
635	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
636	return pVmcbNstGstCache->u16PauseFilterCount;
637	}
638

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 78352

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