HMSVMAll.cpp@ 92780

Last change on this file since 92780 was 91287, checked in by vboxsync, 3 years ago
VMM/CPUM,++: Moved the nested SVM VMCB allocation into CPUMCTX. bugref:10093
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1	/* $Id: HMSVMAll.cpp 91287 2021-09-16 21:30:45Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/apic.h>
26	#include <VBox/vmm/gim.h>
27	#include <VBox/vmm/iem.h>
28	#include <VBox/vmm/vmcc.h>
29
30	#include <VBox/err.h>
31
32
33
34	/**
35	* Emulates a simple MOV TPR (CR8) instruction.
36	*
37	* Used for TPR patching on 32-bit guests. This simply looks up the patch record
38	* at EIP and does the required.
39	*
40	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
41	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
42	* TPR). See hmR3ReplaceTprInstr() for the details.
43	*
44	* @returns VBox status code.
45	* @retval VINF_SUCCESS if the access was handled successfully, RIP + RFLAGS updated.
46	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
47	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
48	*
49	* @param pVM The cross context VM structure.
50	* @param pVCpu The cross context virtual CPU structure.
51	*/
52	VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu)
53	{
54	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
55	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
56
57	/*
58	* We do this in a loop as we increment the RIP after a successful emulation
59	* and the new RIP may be a patched instruction which needs emulation as well.
60	*/
61	bool fPatchFound = false;
62	for (;;)
63	{
64	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
65	if (!pPatch)
66	break;
67	fPatchFound = true;
68
69	uint8_t u8Tpr;
70	switch (pPatch->enmType)
71	{
72	case HMTPRINSTR_READ:
73	{
74	bool fPending;
75	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
76	AssertRC(rc);
77
78	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
79	AssertRC(rc);
80	pCtx->rip += pPatch->cbOp;
81	pCtx->eflags.Bits.u1RF = 0;
82	break;
83	}
84
85	case HMTPRINSTR_WRITE_REG:
86	case HMTPRINSTR_WRITE_IMM:
87	{
88	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
89	{
90	uint32_t u32Val;
91	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
92	AssertRC(rc);
93	u8Tpr = u32Val;
94	}
95	else
96	u8Tpr = (uint8_t)pPatch->uSrcOperand;
97
98	int rc2 = APICSetTpr(pVCpu, u8Tpr);
99	AssertRC(rc2);
100	pCtx->rip += pPatch->cbOp;
101	pCtx->eflags.Bits.u1RF = 0;
102	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR
103	\| HM_CHANGED_GUEST_RIP
104	\| HM_CHANGED_GUEST_RFLAGS);
105	break;
106	}
107
108	default:
109	{
110	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
111	pVCpu->hm.s.u32HMError = pPatch->enmType;
112	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
113	}
114	}
115	}
116
117	return fPatchFound ? VINF_SUCCESS : VERR_NOT_FOUND;
118	}
119
120	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
121	/**
122	* Notification callback for when a \#VMEXIT happens outside SVM R0 code (e.g.
123	* in IEM).
124	*
125	* @param pVCpu The cross context virtual CPU structure.
126	* @param pCtx Pointer to the guest-CPU context.
127	*
128	* @sa hmR0SvmVmRunCacheVmcb.
129	*/
130	VMM_INT_DECL(void) HMNotifySvmNstGstVmexit(PVMCPUCC pVCpu, PCPUMCTX pCtx)
131	{
132	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
133	if (pVmcbNstGstCache->fCacheValid)
134	{
135	/*
136	* Restore fields as our own code might look at the VMCB controls as part
137	* of the #VMEXIT handling in IEM. Otherwise, strictly speaking we don't need to
138	* restore these fields because currently none of them are written back to memory
139	* by a physical CPU on #VMEXIT.
140	*/
141	PSVMVMCBCTRL pVmcbNstGstCtrl = &pCtx->hwvirt.svm.Vmcb.ctrl;
142	pVmcbNstGstCtrl->u16InterceptRdCRx = pVmcbNstGstCache->u16InterceptRdCRx;
143	pVmcbNstGstCtrl->u16InterceptWrCRx = pVmcbNstGstCache->u16InterceptWrCRx;
144	pVmcbNstGstCtrl->u16InterceptRdDRx = pVmcbNstGstCache->u16InterceptRdDRx;
145	pVmcbNstGstCtrl->u16InterceptWrDRx = pVmcbNstGstCache->u16InterceptWrDRx;
146	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcbNstGstCache->u16PauseFilterThreshold;
147	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
148	pVmcbNstGstCtrl->u32InterceptXcpt = pVmcbNstGstCache->u32InterceptXcpt;
149	pVmcbNstGstCtrl->u64InterceptCtrl = pVmcbNstGstCache->u64InterceptCtrl;
150	pVmcbNstGstCtrl->u64TSCOffset = pVmcbNstGstCache->u64TSCOffset;
151	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = pVmcbNstGstCache->fVIntrMasking;
152	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVmcbNstGstCache->fNestedPaging;
153	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcbNstGstCache->fLbrVirt;
154	pVmcbNstGstCache->fCacheValid = false;
155	}
156
157	/*
158	* Transitions to ring-3 flag a full CPU-state change except if we transition to ring-3
159	* in response to a physical CPU interrupt as no changes to the guest-CPU state are
160	* expected (see VINF_EM_RAW_INTERRUPT handling in hmR0SvmExitToRing3).
161	*
162	* However, with nested-guests, the state -can- change on trips to ring-3 for we might
163	* try to inject a nested-guest physical interrupt and cause a SVM_EXIT_INTR #VMEXIT for
164	* the nested-guest from ring-3. Import the complete state here as we will be swapping
165	* to the guest VMCB after the #VMEXIT.
166	*/
167	CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
168	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_ALL);
169	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
170	}
171	#endif
172
173	/**
174	* Checks if the Virtual GIF (Global Interrupt Flag) feature is supported and
175	* enabled for the VM.
176	*
177	* @returns @c true if VGIF is enabled, @c false otherwise.
178	* @param pVM The cross context VM structure.
179	*
180	* @remarks This value returned by this functions is expected by the callers not
181	* to change throughout the lifetime of the VM.
182	*/
183	VMM_INT_DECL(bool) HMIsSvmVGifActive(PCVMCC pVM)
184	{
185	#ifdef IN_RING0
186	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
187	#else
188	bool const fVGif = RT_BOOL(pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
189	#endif
190	return fVGif && pVM->hm.s.svm.fVGif;
191	}
192
193
194	/**
195	* Interface used by IEM to handle patched TPR accesses.
196	*
197	* @returns VBox status code
198	* @retval VINF_SUCCESS if hypercall was handled, RIP + RFLAGS all dealt with.
199	* @retval VERR_NOT_FOUND if hypercall was _not_ handled.
200	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE on IPE.
201	*
202	* @param pVM The cross context VM structure.
203	* @param pVCpu The cross context virtual CPU structure.
204	*/
205	VMM_INT_DECL(int) HMHCMaybeMovTprSvmHypercall(PVMCC pVM, PVMCPUCC pVCpu)
206	{
207	if (pVM->hm.s.fTprPatchingAllowed)
208	{
209	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
210	if (RT_SUCCESS(rc))
211	return VINF_SUCCESS;
212	return rc;
213	}
214	return VERR_NOT_FOUND;
215	}
216
217
218	/**
219	* Checks if the current AMD CPU is subject to erratum 170 "In SVM mode,
220	* incorrect code bytes may be fetched after a world-switch".
221	*
222	* @param pu32Family Where to store the CPU family (can be NULL).
223	* @param pu32Model Where to store the CPU model (can be NULL).
224	* @param pu32Stepping Where to store the CPU stepping (can be NULL).
225	* @returns true if the erratum applies, false otherwise.
226	*/
227	VMM_INT_DECL(int) HMIsSubjectToSvmErratum170(uint32_t pu32Family, uint32_t pu32Model, uint32_t *pu32Stepping)
228	{
229	/*
230	* Erratum 170 which requires a forced TLB flush for each world switch:
231	* See AMD spec. "Revision Guide for AMD NPT Family 0Fh Processors".
232	*
233	* All BH-G1/2 and DH-G1/2 models include a fix:
234	* Athlon X2: 0x6b 1/2
235	* 0x68 1/2
236	* Athlon 64: 0x7f 1
237	* 0x6f 2
238	* Sempron: 0x7f 1/2
239	* 0x6f 2
240	* 0x6c 2
241	* 0x7c 2
242	* Turion 64: 0x68 2
243	*/
244	uint32_t u32Dummy;
245	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
246	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
247	u32BaseFamily = (u32Version >> 8) & 0xf;
248	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
249	u32Model = ((u32Version >> 4) & 0xf);
250	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
251	u32Stepping = u32Version & 0xf;
252
253	bool fErratumApplies = false;
254	if ( u32Family == 0xf
255	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
256	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
257	{
258	fErratumApplies = true;
259	}
260
261	if (pu32Family)
262	*pu32Family = u32Family;
263	if (pu32Model)
264	*pu32Model = u32Model;
265	if (pu32Stepping)
266	*pu32Stepping = u32Stepping;
267
268	return fErratumApplies;
269	}
270
271
272
273	/**
274	* Converts an SVM event type to a TRPM event type.
275	*
276	* @returns The TRPM event type.
277	* @retval TRPM_32BIT_HACK if the specified type of event isn't among the set
278	* of recognized trap types.
279	*
280	* @param pEvent Pointer to the SVM event.
281	* @param uVector The vector associated with the event.
282	*/
283	VMM_INT_DECL(TRPMEVENT) HMSvmEventToTrpmEventType(PCSVMEVENT pEvent, uint8_t uVector)
284	{
285	uint8_t const uType = pEvent->n.u3Type;
286	switch (uType)
287	{
288	case SVM_EVENT_EXTERNAL_IRQ: return TRPM_HARDWARE_INT;
289	case SVM_EVENT_SOFTWARE_INT: return TRPM_SOFTWARE_INT;
290	case SVM_EVENT_NMI: return TRPM_TRAP;
291	case SVM_EVENT_EXCEPTION:
292	{
293	if ( uVector == X86_XCPT_BP
294	\|\| uVector == X86_XCPT_OF)
295	return TRPM_SOFTWARE_INT;
296	return TRPM_TRAP;
297	}
298	default:
299	break;
300	}
301	AssertMsgFailed(("HMSvmEventToTrpmEvent: Invalid pending-event type %#x\n", uType));
302	return TRPM_32BIT_HACK;
303	}
304
305
306	/**
307	* Gets the SVM nested-guest control intercepts if cached by HM.
308	*
309	* @returns @c true on success, @c false otherwise.
310	* @param pVCpu The cross context virtual CPU structure of the calling
311	* EMT.
312	* @param pu64Intercepts Where to store the control intercepts. Only updated when
313	* @c true is returned.
314	*/
315	VMM_INT_DECL(bool) HMGetGuestSvmCtrlIntercepts(PCVMCPU pVCpu, uint64_t *pu64Intercepts)
316	{
317	Assert(pu64Intercepts);
318	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
319	if (pVmcbNstGstCache->fCacheValid)
320	{
321	*pu64Intercepts = pVmcbNstGstCache->u64InterceptCtrl;
322	return true;
323	}
324	return false;
325	}
326
327
328	/**
329	* Gets the SVM nested-guest CRx-read intercepts if cached by HM.
330	*
331	* @returns @c true on success, @c false otherwise.
332	* @param pVCpu The cross context virtual CPU structure of the calling
333	* EMT.
334	* @param pu16Intercepts Where to store the CRx-read intercepts. Only updated
335	* when @c true is returned.
336	*/
337	VMM_INT_DECL(bool) HMGetGuestSvmReadCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
338	{
339	Assert(pu16Intercepts);
340	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
341	if (pVmcbNstGstCache->fCacheValid)
342	{
343	*pu16Intercepts = pVmcbNstGstCache->u16InterceptRdCRx;
344	return true;
345	}
346	return false;
347	}
348
349
350	/**
351	* Gets the SVM nested-guest CRx-write intercepts if cached by HM.
352	*
353	* @returns @c true on success, @c false otherwise.
354	* @param pVCpu The cross context virtual CPU structure of the calling
355	* EMT.
356	* @param pu16Intercepts Where to store the CRx-write intercepts. Only updated
357	* when @c true is returned.
358	*/
359	VMM_INT_DECL(bool) HMGetGuestSvmWriteCRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
360	{
361	Assert(pu16Intercepts);
362	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
363	if (pVmcbNstGstCache->fCacheValid)
364	{
365	*pu16Intercepts = pVmcbNstGstCache->u16InterceptWrCRx;
366	return true;
367	}
368	return false;
369	}
370
371
372	/**
373	* Gets the SVM nested-guest DRx-read intercepts if cached by HM.
374	*
375	* @returns @c true on success, @c false otherwise.
376	* @param pVCpu The cross context virtual CPU structure of the calling
377	* EMT.
378	* @param pu16Intercepts Where to store the DRx-read intercepts. Only updated
379	* when @c true is returned.
380	*/
381	VMM_INT_DECL(bool) HMGetGuestSvmReadDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
382	{
383	Assert(pu16Intercepts);
384	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
385	if (pVmcbNstGstCache->fCacheValid)
386	{
387	*pu16Intercepts = pVmcbNstGstCache->u16InterceptRdDRx;
388	return true;
389	}
390	return false;
391	}
392
393
394	/**
395	* Gets the SVM nested-guest DRx-write intercepts if cached by HM.
396	*
397	* @returns @c true on success, @c false otherwise.
398	* @param pVCpu The cross context virtual CPU structure of the calling
399	* EMT.
400	* @param pu16Intercepts Where to store the DRx-write intercepts. Only updated
401	* when @c true is returned.
402	*/
403	VMM_INT_DECL(bool) HMGetGuestSvmWriteDRxIntercepts(PCVMCPU pVCpu, uint16_t *pu16Intercepts)
404	{
405	Assert(pu16Intercepts);
406	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
407	if (pVmcbNstGstCache->fCacheValid)
408	{
409	*pu16Intercepts = pVmcbNstGstCache->u16InterceptWrDRx;
410	return true;
411	}
412	return false;
413	}
414
415
416	/**
417	* Gets the SVM nested-guest exception intercepts if cached by HM.
418	*
419	* @returns @c true on success, @c false otherwise.
420	* @param pVCpu The cross context virtual CPU structure of the calling
421	* EMT.
422	* @param pu32Intercepts Where to store the exception intercepts. Only updated
423	* when @c true is returned.
424	*/
425	VMM_INT_DECL(bool) HMGetGuestSvmXcptIntercepts(PCVMCPU pVCpu, uint32_t *pu32Intercepts)
426	{
427	Assert(pu32Intercepts);
428	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
429	if (pVmcbNstGstCache->fCacheValid)
430	{
431	*pu32Intercepts = pVmcbNstGstCache->u32InterceptXcpt;
432	return true;
433	}
434	return false;
435	}
436
437
438	/**
439	* Checks if the nested-guest VMCB has virtual-interrupts masking enabled.
440	*
441	* @returns @c true on success, @c false otherwise.
442	* @param pVCpu The cross context virtual CPU structure of the calling
443	* EMT.
444	* @param pfVIntrMasking Where to store the virtual-interrupt masking bit.
445	* Updated only when @c true is returned.
446	*/
447	VMM_INT_DECL(bool) HMGetGuestSvmVirtIntrMasking(PCVMCPU pVCpu, bool *pfVIntrMasking)
448	{
449	Assert(pfVIntrMasking);
450	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
451	if (pVmcbNstGstCache->fCacheValid)
452	{
453	*pfVIntrMasking = pVmcbNstGstCache->fVIntrMasking;
454	return true;
455	}
456	return false;
457	}
458
459
460	/**
461	* Gets the SVM nested-guest nested-paging bit if cached by HM.
462	*
463	* @returns @c true on success, @c false otherwise.
464	* @param pVCpu The cross context virtual CPU structure of the
465	* calling EMT.
466	* @param pfNestedPaging Where to store the nested-paging bit. Updated only
467	* when @c true is returned.
468	*/
469	VMM_INT_DECL(bool) HMGetGuestSvmNestedPaging(PCVMCPU pVCpu, bool *pfNestedPaging)
470	{
471	Assert(pfNestedPaging);
472	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
473	if (pVmcbNstGstCache->fCacheValid)
474	{
475	*pfNestedPaging = pVmcbNstGstCache->fNestedPaging;
476	return true;
477	}
478	return false;
479	}
480
481
482	/**
483	* Returns the nested-guest VMCB pause-filter count.
484	*
485	* @returns @c true on success, @c false otherwise.
486	* @param pVCpu The cross context virtual CPU structure of the
487	* calling EMT.
488	* @param pu16PauseFilterCount Where to store the pause-filter count. Only
489	* updated @c true is returned.
490	*/
491	VMM_INT_DECL(bool) HMGetGuestSvmPauseFilterCount(PCVMCPU pVCpu, uint16_t *pu16PauseFilterCount)
492	{
493	Assert(pu16PauseFilterCount);
494	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
495	if (pVmcbNstGstCache->fCacheValid)
496	{
497	*pu16PauseFilterCount = pVmcbNstGstCache->u16PauseFilterCount;
498	return true;
499	}
500	return false;
501	}
502
503
504	/**
505	* Returns the SVM nested-guest TSC offset if cached by HM.
506	*
507	* @returns The TSC offset after applying any nested-guest TSC offset.
508	* @param pVCpu The cross context virtual CPU structure of the calling
509	* EMT.
510	* @param pu64TscOffset Where to store the TSC offset. Only updated when @c
511	* true is returned.
512	*/
513	VMM_INT_DECL(bool) HMGetGuestSvmTscOffset(PCVMCPU pVCpu, uint64_t *pu64TscOffset)
514	{
515	Assert(pu64TscOffset);
516	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
517	if (pVmcbNstGstCache->fCacheValid)
518	{
519	*pu64TscOffset = pVmcbNstGstCache->u64TSCOffset;
520	return true;
521	}
522	return false;
523	}
524

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp@ 92780

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