HMVMXAll.cpp@ 75323

Last change on this file since 75323 was 75301, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 VM-exit bits; APIC-access and APIC-write infrastructure. Handling of instruction/event boundary pending APIC bits todo.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 55.9 KB

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1	/* $Id: HMVMXAll.cpp 75301 2018-11-07 10:28:57Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27
28
29	/*********************************************************************************************************************************
30	* Global Variables *
31	*********************************************************************************************************************************/
32	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
33	/** VMX virtual-instructions and VM-exit diagnostics. */
34	static const char * const g_apszVmxVDiagDesc[] =
35	{
36	/* Internal processing errors. */
37	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
38	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
54	/* VMXON. */
55	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
75	/* VMXOFF. */
76	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
82	/* VMPTRLD. */
83	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
95	/* VMPTRST. */
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
97	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
101	/* VMCLEAR. */
102	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
103	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
112	/* VMWRITE. */
113	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
114	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
122	/* VMREAD. */
123	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
124	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
131	/* VMLAUNCH/VMRESUME. */
132	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
133	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
134	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrReadPhys , "PtrReadPhys" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
358	/* kVmxVDiag_End */
359	};
360	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
361	#undef VMXV_DIAG_DESC
362
363
364	/**
365	* Gets a copy of the VMX host MSRs that were read by HM during ring-0
366	* initialization.
367	*
368	* @return VBox status code.
369	* @param pVM The cross context VM structure.
370	* @param pVmxMsrs Where to store the VMXMSRS struct (only valid when
371	* VINF_SUCCESS is returned).
372	*
373	* @remarks Caller needs to take care not to call this function too early. Call
374	* after HM initialization is fully complete.
375	*/
376	VMM_INT_DECL(int) HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs)
377	{
378	AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
379	AssertPtrReturn(pVmxMsrs, VERR_INVALID_PARAMETER);
380	if (pVM->hm.s.vmx.fSupported)
381	{
382	*pVmxMsrs = pVM->hm.s.vmx.Msrs;
383	return VINF_SUCCESS;
384	}
385	return VERR_VMX_NOT_SUPPORTED;
386	}
387
388
389	/**
390	* Gets the specified VMX host MSR that was read by HM during ring-0
391	* initialization.
392	*
393	* @return VBox status code.
394	* @param pVM The cross context VM structure.
395	* @param idMsr The MSR.
396	* @param puValue Where to store the MSR value (only updated when VINF_SUCCESS
397	* is returned).
398	*
399	* @remarks Caller needs to take care not to call this function too early. Call
400	* after HM initialization is fully complete.
401	*/
402	VMM_INT_DECL(int) HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue)
403	{
404	AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
405	AssertPtrReturn(puValue, VERR_INVALID_PARAMETER);
406
407	if (pVM->hm.s.vmx.fSupported)
408	{
409	PCVMXMSRS pVmxMsrs = &pVM->hm.s.vmx.Msrs;
410	switch (idMsr)
411	{
412	case MSR_IA32_FEATURE_CONTROL: *puValue = pVmxMsrs->u64FeatCtrl; break;
413	case MSR_IA32_VMX_BASIC: *puValue = pVmxMsrs->u64Basic; break;
414	case MSR_IA32_VMX_PINBASED_CTLS: *puValue = pVmxMsrs->PinCtls.u; break;
415	case MSR_IA32_VMX_PROCBASED_CTLS: *puValue = pVmxMsrs->ProcCtls.u; break;
416	case MSR_IA32_VMX_PROCBASED_CTLS2: *puValue = pVmxMsrs->ProcCtls2.u; break;
417	case MSR_IA32_VMX_EXIT_CTLS: *puValue = pVmxMsrs->ExitCtls.u; break;
418	case MSR_IA32_VMX_ENTRY_CTLS: *puValue = pVmxMsrs->EntryCtls.u; break;
419	case MSR_IA32_VMX_TRUE_PINBASED_CTLS: *puValue = pVmxMsrs->TruePinCtls.u; break;
420	case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: *puValue = pVmxMsrs->TrueProcCtls.u; break;
421	case MSR_IA32_VMX_TRUE_ENTRY_CTLS: *puValue = pVmxMsrs->TrueEntryCtls.u; break;
422	case MSR_IA32_VMX_TRUE_EXIT_CTLS: *puValue = pVmxMsrs->TrueExitCtls.u; break;
423	case MSR_IA32_VMX_MISC: *puValue = pVmxMsrs->u64Misc; break;
424	case MSR_IA32_VMX_CR0_FIXED0: *puValue = pVmxMsrs->u64Cr0Fixed0; break;
425	case MSR_IA32_VMX_CR0_FIXED1: *puValue = pVmxMsrs->u64Cr0Fixed1; break;
426	case MSR_IA32_VMX_CR4_FIXED0: *puValue = pVmxMsrs->u64Cr4Fixed0; break;
427	case MSR_IA32_VMX_CR4_FIXED1: *puValue = pVmxMsrs->u64Cr4Fixed1; break;
428	case MSR_IA32_VMX_VMCS_ENUM: *puValue = pVmxMsrs->u64VmcsEnum; break;
429	case MSR_IA32_VMX_VMFUNC: *puValue = pVmxMsrs->u64VmFunc; break;
430	case MSR_IA32_VMX_EPT_VPID_CAP: *puValue = pVmxMsrs->u64EptVpidCaps; break;
431	default:
432	{
433	AssertMsgFailed(("Invalid MSR %#x\n", idMsr));
434	return VERR_NOT_FOUND;
435	}
436	}
437	return VINF_SUCCESS;
438	}
439	return VERR_VMX_NOT_SUPPORTED;
440	}
441
442
443	/**
444	* Gets the description of a VMX instruction/Vm-exit diagnostic.
445	*
446	* @returns The descriptive string.
447	* @param enmDiag The VMX diagnostic.
448	*/
449	VMM_INT_DECL(const char *) HMVmxGetDiagDesc(VMXVDIAG enmDiag)
450	{
451	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
452	return g_apszVmxVDiagDesc[enmDiag];
453	return "Unknown/invalid";
454	}
455
456
457	/**
458	* Gets the description for a VMX abort reason.
459	*
460	* @returns The descriptive string.
461	* @param enmAbort The VMX abort reason.
462	*/
463	VMM_INT_DECL(const char *) HMVmxGetAbortDesc(VMXABORT enmAbort)
464	{
465	switch (enmAbort)
466	{
467	case VMXABORT_NONE: return "VMXABORT_NONE";
468	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
469	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
470	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
471	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
472	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
473	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
474	default:
475	break;
476	}
477	return "Unknown/invalid";
478	}
479
480
481	/**
482	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
483	* VMX when unrestricted execution isn't available.
484	*
485	* @returns true if selector is suitable for VMX, otherwise
486	* false.
487	* @param pSel Pointer to the selector to check (CS).
488	* @param uStackDpl The CPL, aka the DPL of the stack segment.
489	*/
490	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
491	{
492	/*
493	* Segment must be an accessed code segment, it must be present and it must
494	* be usable.
495	* Note! These are all standard requirements and if CS holds anything else
496	* we've got buggy code somewhere!
497	*/
498	AssertCompile(X86DESCATTR_TYPE == 0xf);
499	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
500	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
501	("%#x\n", pSel->Attr.u),
502	false);
503
504	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
505	must equal SS.DPL for non-confroming segments.
506	Note! This is also a hard requirement like above. */
507	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
508	? pSel->Attr.n.u2Dpl <= uStackDpl
509	: pSel->Attr.n.u2Dpl == uStackDpl,
510	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
511	false);
512
513	/*
514	* The following two requirements are VT-x specific:
515	* - G bit must be set if any high limit bits are set.
516	* - G bit must be clear if any low limit bits are clear.
517	*/
518	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
519	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
520	return true;
521	return false;
522	}
523
524
525	/**
526	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
527	* hardware-assisted VMX when unrestricted execution isn't available.
528	*
529	* @returns true if selector is suitable for VMX, otherwise
530	* false.
531	* @param pSel Pointer to the selector to check
532	* (DS/ES/FS/GS).
533	*/
534	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
535	{
536	/*
537	* Unusable segments are OK. These days they should be marked as such, as
538	* but as an alternative we for old saved states and AMD<->VT-x migration
539	* we also treat segments with all the attributes cleared as unusable.
540	*/
541	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
542	return true;
543
544	/** @todo tighten these checks. Will require CPUM load adjusting. */
545
546	/* Segment must be accessed. */
547	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
548	{
549	/* Code segments must also be readable. */
550	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
551	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
552	{
553	/* The S bit must be set. */
554	if (pSel->Attr.n.u1DescType)
555	{
556	/* Except for conforming segments, DPL >= RPL. */
557	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
558	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
559	{
560	/* Segment must be present. */
561	if (pSel->Attr.n.u1Present)
562	{
563	/*
564	* The following two requirements are VT-x specific:
565	* - G bit must be set if any high limit bits are set.
566	* - G bit must be clear if any low limit bits are clear.
567	*/
568	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
569	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
570	return true;
571	}
572	}
573	}
574	}
575	}
576
577	return false;
578	}
579
580
581	/**
582	* Checks if the stack selector (SS) is suitable for execution using
583	* hardware-assisted VMX when unrestricted execution isn't available.
584	*
585	* @returns true if selector is suitable for VMX, otherwise
586	* false.
587	* @param pSel Pointer to the selector to check (SS).
588	*/
589	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
590	{
591	/*
592	* Unusable segments are OK. These days they should be marked as such, as
593	* but as an alternative we for old saved states and AMD<->VT-x migration
594	* we also treat segments with all the attributes cleared as unusable.
595	*/
596	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
597	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
598	return true;
599
600	/*
601	* Segment must be an accessed writable segment, it must be present.
602	* Note! These are all standard requirements and if SS holds anything else
603	* we've got buggy code somewhere!
604	*/
605	AssertCompile(X86DESCATTR_TYPE == 0xf);
606	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
607	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
608	("%#x\n", pSel->Attr.u), false);
609
610	/*
611	* DPL must equal RPL. But in real mode or soon after enabling protected
612	* mode, it might not be.
613	*/
614	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
615	{
616	/*
617	* The following two requirements are VT-x specific:
618	* - G bit must be set if any high limit bits are set.
619	* - G bit must be clear if any low limit bits are clear.
620	*/
621	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
622	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
623	return true;
624	}
625	return false;
626	}
627
628
629	/**
630	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
631	*
632	* @returns @c true if it is suitable, @c false otherwise.
633	* @param pVCpu The cross context virtual CPU structure.
634	* @param pCtx Pointer to the guest CPU context.
635	*
636	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
637	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
638	* Secondly, if additional checks are added that require more of the CPU
639	* state, make sure REM (which supplies a partial state) is updated.
640	*/
641	VMM_INT_DECL(bool) HMVmxCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
642	{
643	PVM pVM = pVCpu->CTX_SUFF(pVM);
644	Assert(HMIsEnabled(pVM));
645	Assert(!CPUMIsGuestVmxEnabled(pCtx));
646	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
647	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
648
649	pVCpu->hm.s.fActive = false;
650
651	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
652	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
653	{
654	/*
655	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
656	* guest execution feature is missing (VT-x only).
657	*/
658	if (fSupportsRealMode)
659	{
660	if (CPUMIsGuestInRealModeEx(pCtx))
661	{
662	/*
663	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
664	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
665	* and attrributes must be 0x9b for code and 0x93 for code segments.
666	* If this is not true, we cannot execute real mode as V86 and have to fall
667	* back to emulation.
668	*/
669	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
670	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
671	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
672	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
673	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
674	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
675	{
676	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
677	return false;
678	}
679	if ( (pCtx->cs.u32Limit != 0xffff)
680	\|\| (pCtx->ds.u32Limit != 0xffff)
681	\|\| (pCtx->es.u32Limit != 0xffff)
682	\|\| (pCtx->ss.u32Limit != 0xffff)
683	\|\| (pCtx->fs.u32Limit != 0xffff)
684	\|\| (pCtx->gs.u32Limit != 0xffff))
685	{
686	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
687	return false;
688	}
689	if ( (pCtx->cs.Attr.u != 0x9b)
690	\|\| (pCtx->ds.Attr.u != 0x93)
691	\|\| (pCtx->es.Attr.u != 0x93)
692	\|\| (pCtx->ss.Attr.u != 0x93)
693	\|\| (pCtx->fs.Attr.u != 0x93)
694	\|\| (pCtx->gs.Attr.u != 0x93))
695	{
696	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
697	return false;
698	}
699	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
700	}
701	else
702	{
703	/*
704	* Verify the requirements for executing code in protected mode. VT-x can't
705	* handle the CPU state right after a switch from real to protected mode
706	* (all sorts of RPL & DPL assumptions).
707	*/
708	if (pVCpu->hm.s.vmx.fWasInRealMode)
709	{
710	/** @todo If guest is in V86 mode, these checks should be different! */
711	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
712	{
713	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
714	return false;
715	}
716	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
717	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
718	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
719	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
720	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
721	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
722	{
723	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
724	return false;
725	}
726	}
727	}
728	}
729	else
730	{
731	if ( !CPUMIsGuestInLongModeEx(pCtx)
732	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
733	{
734	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
735	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
736	return false;
737
738	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
739	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
740	return false;
741
742	/*
743	* The guest is about to complete the switch to protected mode. Wait a bit longer.
744	* Windows XP; switch to protected mode; all selectors are marked not present
745	* in the hidden registers (possible recompiler bug; see load_seg_vm).
746	*/
747	/** @todo Is this supposed recompiler bug still relevant with IEM? */
748	if (pCtx->cs.Attr.n.u1Present == 0)
749	return false;
750	if (pCtx->ss.Attr.n.u1Present == 0)
751	return false;
752
753	/*
754	* Windows XP: possible same as above, but new recompiler requires new
755	* heuristics? VT-x doesn't seem to like something about the guest state and
756	* this stuff avoids it.
757	*/
758	/** @todo This check is actually wrong, it doesn't take the direction of the
759	* stack segment into account. But, it does the job for now. */
760	if (pCtx->rsp >= pCtx->ss.u32Limit)
761	return false;
762	}
763	}
764	}
765
766	if (pVM->hm.s.vmx.fEnabled)
767	{
768	uint32_t uCr0Mask;
769
770	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
771	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
772
773	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
774	uCr0Mask &= ~X86_CR0_NE;
775
776	if (fSupportsRealMode)
777	{
778	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
779	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
780	}
781	else
782	{
783	/* We support protected mode without paging using identity mapping. */
784	uCr0Mask &= ~X86_CR0_PG;
785	}
786	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
787	return false;
788
789	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
790	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
791	if ((pCtx->cr0 & uCr0Mask) != 0)
792	return false;
793
794	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
795	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
796	uCr0Mask &= ~X86_CR4_VMXE;
797	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
798	return false;
799
800	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
801	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
802	if ((pCtx->cr4 & uCr0Mask) != 0)
803	return false;
804
805	pVCpu->hm.s.fActive = true;
806	return true;
807	}
808
809	return false;
810	}
811
812
813	/**
814	* Injects an event using TRPM given a VM-entry interruption info. and related
815	* fields.
816	*
817	* @returns VBox status code.
818	* @param pVCpu The cross context virtual CPU structure.
819	* @param uEntryIntInfo The VM-entry interruption info.
820	* @param uErrCode The error code associated with the event if any.
821	* @param cbInstr The VM-entry instruction length (for software
822	* interrupts and software exceptions). Pass 0
823	* otherwise.
824	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
825	*/
826	VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
827	RTGCUINTPTR GCPtrFaultAddress)
828	{
829	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
830
831	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
832	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
833	bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
834
835	TRPMEVENT enmTrapType;
836	switch (uType)
837	{
838	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
839	enmTrapType = TRPM_HARDWARE_INT;
840	break;
841
842	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
843	enmTrapType = TRPM_SOFTWARE_INT;
844	break;
845
846	case VMX_ENTRY_INT_INFO_TYPE_NMI:
847	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
848	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
849	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
850	enmTrapType = TRPM_TRAP;
851	break;
852
853	default:
854	/* Shouldn't really happen. */
855	AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
856	break;
857	}
858
859	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
860	AssertRCReturn(rc, rc);
861
862	if (fErrCodeValid)
863	TRPMSetErrorCode(pVCpu, uErrCode);
864
865	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
866	&& uVector == X86_XCPT_PF)
867	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
868	else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
869	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
870	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
871	{
872	AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
873	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
874	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
875	TRPMSetInstrLength(pVCpu, cbInstr);
876	}
877
878	return VINF_SUCCESS;
879	}
880
881
882	/**
883	* Gets the permission bits for the specified MSR in the specified MSR bitmap.
884	*
885	* @returns VBox status code.
886	* @param pvMsrBitmap Pointer to the MSR bitmap.
887	* @param idMsr The MSR.
888	* @param penmRead Where to store the read permissions. Optional, can be
889	* NULL.
890	* @param penmWrite Where to store the write permissions. Optional, can be
891	* NULL.
892	*/
893	VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
894	PVMXMSREXITWRITE penmWrite)
895	{
896	AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER);
897
898	int32_t iBit;
899	uint8_t const pbMsrBitmap = (uint8_t )pvMsrBitmap;
900
901	/*
902	* MSR Layout:
903	* Byte index MSR range Interpreted as
904	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
905	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
906	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
907	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
908	*
909	* A bit corresponding to an MSR within the above range causes a VM-exit
910	* if the bit is 1 on executions of RDMSR/WRMSR.
911	*
912	* If an MSR falls out of the MSR range, it always cause a VM-exit.
913	*
914	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
915	*/
916	if (idMsr <= 0x00001fff)
917	iBit = idMsr;
918	else if ( idMsr >= 0xc0000000
919	&& idMsr <= 0xc0001fff)
920	{
921	iBit = (idMsr - 0xc0000000);
922	pbMsrBitmap += 0x400;
923	}
924	else
925	{
926	if (penmRead)
927	*penmRead = VMXMSREXIT_INTERCEPT_READ;
928	if (penmWrite)
929	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
930	Log(("HMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr));
931	return VINF_SUCCESS;
932	}
933
934	/* Validate the MSR bit position. */
935	Assert(iBit <= 0x1fff);
936
937	/* Get the MSR read permissions. */
938	if (penmRead)
939	{
940	if (ASMBitTest(pbMsrBitmap, iBit))
941	*penmRead = VMXMSREXIT_INTERCEPT_READ;
942	else
943	*penmRead = VMXMSREXIT_PASSTHRU_READ;
944	}
945
946	/* Get the MSR write permissions. */
947	if (penmWrite)
948	{
949	if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
950	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
951	else
952	*penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
953	}
954
955	return VINF_SUCCESS;
956	}
957
958
959	/**
960	* Gets the permission bits for the specified I/O port from the given I/O bitmaps.
961	*
962	* @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
963	* @param pvIoBitmapA Pointer to I/O bitmap A.
964	* @param pvIoBitmapB Pointer to I/O bitmap B.
965	* @param uPort The I/O port being accessed.
966	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
967	*/
968	VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort, uint8_t cbAccess)
969	{
970	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
971
972	/*
973	* If the I/O port access wraps around the 16-bit port I/O space,
974	* we must cause a VM-exit.
975	*
976	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
977	*/
978	/** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
979	* respectively are valid and do not constitute a wrap around from what I
980	* understand. Verify this later. */
981	uint32_t const uPortLast = uPort + cbAccess;
982	if (uPortLast > 0x10000)
983	return true;
984
985	/* Read the appropriate bit from the corresponding IO bitmap. */
986	void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
987	return ASMBitTest(pvIoBitmap, uPort);
988	}
989

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 75323

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