HMVMXAll.cpp@ 75249

Last change on this file since 75249 was 74696, checked in by vboxsync, 6 years ago
VMM/HMVMXAll: Comment typo.
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1	/* $Id: HMVMXAll.cpp 74696 2018-10-09 05:58:08Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27
28
29	/*********************************************************************************************************************************
30	* Global Variables *
31	*********************************************************************************************************************************/
32	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
33	/** VMX virtual-instructions and VM-exit diagnostics. */
34	static const char * const g_apszVmxVDiagDesc[] =
35	{
36	/* Internal processing errors. */
37	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
38	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
54	/* VMXON. */
55	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
75	/* VMXOFF. */
76	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
82	/* VMPTRLD. */
83	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
95	/* VMPTRST. */
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
97	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
101	/* VMCLEAR. */
102	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
103	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
112	/* VMWRITE. */
113	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
114	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
122	/* VMREAD. */
123	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
124	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
131	/* VMLAUNCH/VMRESUME. */
132	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
133	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
134	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrReadPhys , "PtrReadPhys" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
357	/* kVmxVDiag_End */
358	};
359	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
360	#undef VMXV_DIAG_DESC
361
362
363	/**
364	* Gets a copy of the VMX host MSRs that were read by HM during ring-0
365	* initialization.
366	*
367	* @return VBox status code.
368	* @param pVM The cross context VM structure.
369	* @param pVmxMsrs Where to store the VMXMSRS struct (only valid when
370	* VINF_SUCCESS is returned).
371	*
372	* @remarks Caller needs to take care not to call this function too early. Call
373	* after HM initialization is fully complete.
374	*/
375	VMM_INT_DECL(int) HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs)
376	{
377	AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
378	AssertPtrReturn(pVmxMsrs, VERR_INVALID_PARAMETER);
379	if (pVM->hm.s.vmx.fSupported)
380	{
381	*pVmxMsrs = pVM->hm.s.vmx.Msrs;
382	return VINF_SUCCESS;
383	}
384	return VERR_VMX_NOT_SUPPORTED;
385	}
386
387
388	/**
389	* Gets the specified VMX host MSR that was read by HM during ring-0
390	* initialization.
391	*
392	* @return VBox status code.
393	* @param pVM The cross context VM structure.
394	* @param idMsr The MSR.
395	* @param puValue Where to store the MSR value (only updated when VINF_SUCCESS
396	* is returned).
397	*
398	* @remarks Caller needs to take care not to call this function too early. Call
399	* after HM initialization is fully complete.
400	*/
401	VMM_INT_DECL(int) HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue)
402	{
403	AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
404	AssertPtrReturn(puValue, VERR_INVALID_PARAMETER);
405
406	if (pVM->hm.s.vmx.fSupported)
407	{
408	PCVMXMSRS pVmxMsrs = &pVM->hm.s.vmx.Msrs;
409	switch (idMsr)
410	{
411	case MSR_IA32_FEATURE_CONTROL: *puValue = pVmxMsrs->u64FeatCtrl; break;
412	case MSR_IA32_VMX_BASIC: *puValue = pVmxMsrs->u64Basic; break;
413	case MSR_IA32_VMX_PINBASED_CTLS: *puValue = pVmxMsrs->PinCtls.u; break;
414	case MSR_IA32_VMX_PROCBASED_CTLS: *puValue = pVmxMsrs->ProcCtls.u; break;
415	case MSR_IA32_VMX_PROCBASED_CTLS2: *puValue = pVmxMsrs->ProcCtls2.u; break;
416	case MSR_IA32_VMX_EXIT_CTLS: *puValue = pVmxMsrs->ExitCtls.u; break;
417	case MSR_IA32_VMX_ENTRY_CTLS: *puValue = pVmxMsrs->EntryCtls.u; break;
418	case MSR_IA32_VMX_TRUE_PINBASED_CTLS: *puValue = pVmxMsrs->TruePinCtls.u; break;
419	case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: *puValue = pVmxMsrs->TrueProcCtls.u; break;
420	case MSR_IA32_VMX_TRUE_ENTRY_CTLS: *puValue = pVmxMsrs->TrueEntryCtls.u; break;
421	case MSR_IA32_VMX_TRUE_EXIT_CTLS: *puValue = pVmxMsrs->TrueExitCtls.u; break;
422	case MSR_IA32_VMX_MISC: *puValue = pVmxMsrs->u64Misc; break;
423	case MSR_IA32_VMX_CR0_FIXED0: *puValue = pVmxMsrs->u64Cr0Fixed0; break;
424	case MSR_IA32_VMX_CR0_FIXED1: *puValue = pVmxMsrs->u64Cr0Fixed1; break;
425	case MSR_IA32_VMX_CR4_FIXED0: *puValue = pVmxMsrs->u64Cr4Fixed0; break;
426	case MSR_IA32_VMX_CR4_FIXED1: *puValue = pVmxMsrs->u64Cr4Fixed1; break;
427	case MSR_IA32_VMX_VMCS_ENUM: *puValue = pVmxMsrs->u64VmcsEnum; break;
428	case MSR_IA32_VMX_VMFUNC: *puValue = pVmxMsrs->u64VmFunc; break;
429	case MSR_IA32_VMX_EPT_VPID_CAP: *puValue = pVmxMsrs->u64EptVpidCaps; break;
430	default:
431	{
432	AssertMsgFailed(("Invalid MSR %#x\n", idMsr));
433	return VERR_NOT_FOUND;
434	}
435	}
436	return VINF_SUCCESS;
437	}
438	return VERR_VMX_NOT_SUPPORTED;
439	}
440
441
442	/**
443	* Gets the description of a VMX instruction/Vm-exit diagnostic.
444	*
445	* @returns The descriptive string.
446	* @param enmDiag The VMX diagnostic.
447	*/
448	VMM_INT_DECL(const char *) HMVmxGetDiagDesc(VMXVDIAG enmDiag)
449	{
450	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
451	return g_apszVmxVDiagDesc[enmDiag];
452	return "Unknown/invalid";
453	}
454
455
456	/**
457	* Gets the description for a VMX abort reason.
458	*
459	* @returns The descriptive string.
460	* @param enmAbort The VMX abort reason.
461	*/
462	VMM_INT_DECL(const char *) HMVmxGetAbortDesc(VMXABORT enmAbort)
463	{
464	switch (enmAbort)
465	{
466	case VMXABORT_NONE: return "VMXABORT_NONE";
467	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
468	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
469	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
470	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
471	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
472	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
473	default:
474	break;
475	}
476	return "Unknown/invalid";
477	}
478
479
480	/**
481	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
482	* VMX when unrestricted execution isn't available.
483	*
484	* @returns true if selector is suitable for VMX, otherwise
485	* false.
486	* @param pSel Pointer to the selector to check (CS).
487	* @param uStackDpl The CPL, aka the DPL of the stack segment.
488	*/
489	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
490	{
491	/*
492	* Segment must be an accessed code segment, it must be present and it must
493	* be usable.
494	* Note! These are all standard requirements and if CS holds anything else
495	* we've got buggy code somewhere!
496	*/
497	AssertCompile(X86DESCATTR_TYPE == 0xf);
498	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
499	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
500	("%#x\n", pSel->Attr.u),
501	false);
502
503	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
504	must equal SS.DPL for non-confroming segments.
505	Note! This is also a hard requirement like above. */
506	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
507	? pSel->Attr.n.u2Dpl <= uStackDpl
508	: pSel->Attr.n.u2Dpl == uStackDpl,
509	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
510	false);
511
512	/*
513	* The following two requirements are VT-x specific:
514	* - G bit must be set if any high limit bits are set.
515	* - G bit must be clear if any low limit bits are clear.
516	*/
517	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
518	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
519	return true;
520	return false;
521	}
522
523
524	/**
525	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
526	* hardware-assisted VMX when unrestricted execution isn't available.
527	*
528	* @returns true if selector is suitable for VMX, otherwise
529	* false.
530	* @param pSel Pointer to the selector to check
531	* (DS/ES/FS/GS).
532	*/
533	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
534	{
535	/*
536	* Unusable segments are OK. These days they should be marked as such, as
537	* but as an alternative we for old saved states and AMD<->VT-x migration
538	* we also treat segments with all the attributes cleared as unusable.
539	*/
540	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
541	return true;
542
543	/** @todo tighten these checks. Will require CPUM load adjusting. */
544
545	/* Segment must be accessed. */
546	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
547	{
548	/* Code segments must also be readable. */
549	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
550	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
551	{
552	/* The S bit must be set. */
553	if (pSel->Attr.n.u1DescType)
554	{
555	/* Except for conforming segments, DPL >= RPL. */
556	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
557	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
558	{
559	/* Segment must be present. */
560	if (pSel->Attr.n.u1Present)
561	{
562	/*
563	* The following two requirements are VT-x specific:
564	* - G bit must be set if any high limit bits are set.
565	* - G bit must be clear if any low limit bits are clear.
566	*/
567	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
568	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
569	return true;
570	}
571	}
572	}
573	}
574	}
575
576	return false;
577	}
578
579
580	/**
581	* Checks if the stack selector (SS) is suitable for execution using
582	* hardware-assisted VMX when unrestricted execution isn't available.
583	*
584	* @returns true if selector is suitable for VMX, otherwise
585	* false.
586	* @param pSel Pointer to the selector to check (SS).
587	*/
588	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
589	{
590	/*
591	* Unusable segments are OK. These days they should be marked as such, as
592	* but as an alternative we for old saved states and AMD<->VT-x migration
593	* we also treat segments with all the attributes cleared as unusable.
594	*/
595	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
596	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
597	return true;
598
599	/*
600	* Segment must be an accessed writable segment, it must be present.
601	* Note! These are all standard requirements and if SS holds anything else
602	* we've got buggy code somewhere!
603	*/
604	AssertCompile(X86DESCATTR_TYPE == 0xf);
605	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
606	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
607	("%#x\n", pSel->Attr.u), false);
608
609	/*
610	* DPL must equal RPL. But in real mode or soon after enabling protected
611	* mode, it might not be.
612	*/
613	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
614	{
615	/*
616	* The following two requirements are VT-x specific:
617	* - G bit must be set if any high limit bits are set.
618	* - G bit must be clear if any low limit bits are clear.
619	*/
620	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
621	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
622	return true;
623	}
624	return false;
625	}
626
627
628	/**
629	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
630	*
631	* @returns @c true if it is suitable, @c false otherwise.
632	* @param pVCpu The cross context virtual CPU structure.
633	* @param pCtx Pointer to the guest CPU context.
634	*
635	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
636	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
637	* Secondly, if additional checks are added that require more of the CPU
638	* state, make sure REM (which supplies a partial state) is updated.
639	*/
640	VMM_INT_DECL(bool) HMVmxCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
641	{
642	PVM pVM = pVCpu->CTX_SUFF(pVM);
643	Assert(HMIsEnabled(pVM));
644	Assert(!CPUMIsGuestVmxEnabled(pCtx));
645	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
646	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
647
648	pVCpu->hm.s.fActive = false;
649
650	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
651	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
652	{
653	/*
654	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
655	* guest execution feature is missing (VT-x only).
656	*/
657	if (fSupportsRealMode)
658	{
659	if (CPUMIsGuestInRealModeEx(pCtx))
660	{
661	/*
662	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
663	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
664	* and attrributes must be 0x9b for code and 0x93 for code segments.
665	* If this is not true, we cannot execute real mode as V86 and have to fall
666	* back to emulation.
667	*/
668	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
669	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
670	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
671	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
672	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
673	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
674	{
675	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
676	return false;
677	}
678	if ( (pCtx->cs.u32Limit != 0xffff)
679	\|\| (pCtx->ds.u32Limit != 0xffff)
680	\|\| (pCtx->es.u32Limit != 0xffff)
681	\|\| (pCtx->ss.u32Limit != 0xffff)
682	\|\| (pCtx->fs.u32Limit != 0xffff)
683	\|\| (pCtx->gs.u32Limit != 0xffff))
684	{
685	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
686	return false;
687	}
688	if ( (pCtx->cs.Attr.u != 0x9b)
689	\|\| (pCtx->ds.Attr.u != 0x93)
690	\|\| (pCtx->es.Attr.u != 0x93)
691	\|\| (pCtx->ss.Attr.u != 0x93)
692	\|\| (pCtx->fs.Attr.u != 0x93)
693	\|\| (pCtx->gs.Attr.u != 0x93))
694	{
695	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
696	return false;
697	}
698	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
699	}
700	else
701	{
702	/*
703	* Verify the requirements for executing code in protected mode. VT-x can't
704	* handle the CPU state right after a switch from real to protected mode
705	* (all sorts of RPL & DPL assumptions).
706	*/
707	if (pVCpu->hm.s.vmx.fWasInRealMode)
708	{
709	/** @todo If guest is in V86 mode, these checks should be different! */
710	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
711	{
712	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
713	return false;
714	}
715	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
716	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
717	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
718	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
719	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
720	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
721	{
722	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
723	return false;
724	}
725	}
726	}
727	}
728	else
729	{
730	if ( !CPUMIsGuestInLongModeEx(pCtx)
731	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
732	{
733	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
734	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
735	return false;
736
737	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
738	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
739	return false;
740
741	/*
742	* The guest is about to complete the switch to protected mode. Wait a bit longer.
743	* Windows XP; switch to protected mode; all selectors are marked not present
744	* in the hidden registers (possible recompiler bug; see load_seg_vm).
745	*/
746	/** @todo Is this supposed recompiler bug still relevant with IEM? */
747	if (pCtx->cs.Attr.n.u1Present == 0)
748	return false;
749	if (pCtx->ss.Attr.n.u1Present == 0)
750	return false;
751
752	/*
753	* Windows XP: possible same as above, but new recompiler requires new
754	* heuristics? VT-x doesn't seem to like something about the guest state and
755	* this stuff avoids it.
756	*/
757	/** @todo This check is actually wrong, it doesn't take the direction of the
758	* stack segment into account. But, it does the job for now. */
759	if (pCtx->rsp >= pCtx->ss.u32Limit)
760	return false;
761	}
762	}
763	}
764
765	if (pVM->hm.s.vmx.fEnabled)
766	{
767	uint32_t uCr0Mask;
768
769	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
770	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
771
772	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
773	uCr0Mask &= ~X86_CR0_NE;
774
775	if (fSupportsRealMode)
776	{
777	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
778	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
779	}
780	else
781	{
782	/* We support protected mode without paging using identity mapping. */
783	uCr0Mask &= ~X86_CR0_PG;
784	}
785	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
786	return false;
787
788	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
789	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
790	if ((pCtx->cr0 & uCr0Mask) != 0)
791	return false;
792
793	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
794	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
795	uCr0Mask &= ~X86_CR4_VMXE;
796	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
797	return false;
798
799	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
800	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
801	if ((pCtx->cr4 & uCr0Mask) != 0)
802	return false;
803
804	pVCpu->hm.s.fActive = true;
805	return true;
806	}
807
808	return false;
809	}
810
811
812	/**
813	* Injects an event using TRPM given a VM-entry interruption info. and related
814	* fields.
815	*
816	* @returns VBox status code.
817	* @param pVCpu The cross context virtual CPU structure.
818	* @param uEntryIntInfo The VM-entry interruption info.
819	* @param uErrCode The error code associated with the event if any.
820	* @param cbInstr The VM-entry instruction length (for software
821	* interrupts and software exceptions). Pass 0
822	* otherwise.
823	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
824	*/
825	VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
826	RTGCUINTPTR GCPtrFaultAddress)
827	{
828	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
829
830	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
831	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
832	bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
833
834	TRPMEVENT enmTrapType;
835	switch (uType)
836	{
837	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
838	enmTrapType = TRPM_HARDWARE_INT;
839	break;
840
841	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
842	enmTrapType = TRPM_SOFTWARE_INT;
843	break;
844
845	case VMX_ENTRY_INT_INFO_TYPE_NMI:
846	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
847	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
848	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
849	enmTrapType = TRPM_TRAP;
850	break;
851
852	default:
853	/* Shouldn't really happen. */
854	AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
855	break;
856	}
857
858	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
859	AssertRCReturn(rc, rc);
860
861	if (fErrCodeValid)
862	TRPMSetErrorCode(pVCpu, uErrCode);
863
864	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
865	&& uVector == X86_XCPT_PF)
866	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
867	else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
868	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
869	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
870	{
871	AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
872	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
873	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
874	TRPMSetInstrLength(pVCpu, cbInstr);
875	}
876
877	return VINF_SUCCESS;
878	}
879
880
881	/**
882	* Gets the permission bits for the specified MSR in the specified MSR bitmap.
883	*
884	* @returns VBox status code.
885	* @param pvMsrBitmap Pointer to the MSR bitmap.
886	* @param idMsr The MSR.
887	* @param penmRead Where to store the read permissions. Optional, can be
888	* NULL.
889	* @param penmWrite Where to store the write permissions. Optional, can be
890	* NULL.
891	*/
892	VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
893	PVMXMSREXITWRITE penmWrite)
894	{
895	AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER);
896
897	int32_t iBit;
898	uint8_t const pbMsrBitmap = (uint8_t )pvMsrBitmap;
899
900	/*
901	* MSR Layout:
902	* Byte index MSR range Interpreted as
903	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
904	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
905	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
906	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
907	*
908	* A bit corresponding to an MSR within the above range causes a VM-exit
909	* if the bit is 1 on executions of RDMSR/WRMSR.
910	*
911	* If an MSR falls out of the MSR range, it always cause a VM-exit.
912	*
913	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
914	*/
915	if (idMsr <= 0x00001fff)
916	iBit = idMsr;
917	else if ( idMsr >= 0xc0000000
918	&& idMsr <= 0xc0001fff)
919	{
920	iBit = (idMsr - 0xc0000000);
921	pbMsrBitmap += 0x400;
922	}
923	else
924	{
925	if (penmRead)
926	*penmRead = VMXMSREXIT_INTERCEPT_READ;
927	if (penmWrite)
928	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
929	Log(("HMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr));
930	return VINF_SUCCESS;
931	}
932
933	/* Validate the MSR bit position. */
934	Assert(iBit <= 0x1fff);
935
936	/* Get the MSR read permissions. */
937	if (penmRead)
938	{
939	if (ASMBitTest(pbMsrBitmap, iBit))
940	*penmRead = VMXMSREXIT_INTERCEPT_READ;
941	else
942	*penmRead = VMXMSREXIT_PASSTHRU_READ;
943	}
944
945	/* Get the MSR write permissions. */
946	if (penmWrite)
947	{
948	if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
949	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
950	else
951	*penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
952	}
953
954	return VINF_SUCCESS;
955	}
956
957
958	/**
959	* Gets the permission bits for the specified I/O port from the given I/O bitmaps.
960	*
961	* @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
962	* @param pvIoBitmapA Pointer to I/O bitmap A.
963	* @param pvIoBitmapB Pointer to I/O bitmap B.
964	* @param uPort The I/O port being accessed.
965	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
966	*/
967	VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort, uint8_t cbAccess)
968	{
969	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
970
971	/*
972	* If the I/O port access wraps around the 16-bit port I/O space,
973	* we must cause a VM-exit.
974	*
975	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
976	*/
977	/** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
978	* respectively are valid and do not constitute a wrap around from what I
979	* understand. Verify this later. */
980	uint32_t const uPortLast = uPort + cbAccess;
981	if (uPortLast > 0x10000)
982	return true;
983
984	/* Read the appropriate bit from the corresponding IO bitmap. */
985	void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
986	return ASMBitTest(pvIoBitmap, uPort);
987	}
988

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 75249

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