HMVMXAll.cpp@ 76763

Last change on this file since 76763 was 76722, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Fix VMLAUNCH/VMRESUME and VMPTRLD caching of the VMCS. We cache VMCS on VMPTRLD, so do not reload it again during VMLAUNCH/VMRESUME.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 55.4 KB

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1	/* $Id: HMVMXAll.cpp 76722 2019-01-09 08:15:04Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/err.h>
28
29
30	/*********************************************************************************************************************************
31	* Global Variables *
32	*********************************************************************************************************************************/
33	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
34	/** VMX virtual-instructions and VM-exit diagnostics. */
35	static const char * const g_apszVmxVDiagDesc[] =
36	{
37	/* Internal processing errors. */
38	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
55	/* VMXON. */
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
76	/* VMXOFF. */
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
83	/* VMPTRLD. */
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RevPtrReadPhys , "RevPtrReadPhys" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
97	/* VMPTRST. */
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
102	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
103	/* VMCLEAR. */
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
113	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
114	/* VMWRITE. */
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
123	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
124	/* VMREAD. */
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
132	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
133	/* VMLAUNCH/VMRESUME. */
134	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
360	/* kVmxVDiag_End */
361	};
362	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
363	#undef VMXV_DIAG_DESC
364
365
366	/**
367	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
368	*
369	* @returns The descriptive string.
370	* @param enmDiag The VMX diagnostic.
371	*/
372	VMM_INT_DECL(const char *) HMVmxGetDiagDesc(VMXVDIAG enmDiag)
373	{
374	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
375	return g_apszVmxVDiagDesc[enmDiag];
376	return "Unknown/invalid";
377	}
378
379
380	/**
381	* Gets the description for a VMX abort reason.
382	*
383	* @returns The descriptive string.
384	* @param enmAbort The VMX abort reason.
385	*/
386	VMM_INT_DECL(const char *) HMVmxGetAbortDesc(VMXABORT enmAbort)
387	{
388	switch (enmAbort)
389	{
390	case VMXABORT_NONE: return "VMXABORT_NONE";
391	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
392	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
393	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
394	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
395	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
396	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
397	default:
398	break;
399	}
400	return "Unknown/invalid";
401	}
402
403
404	/**
405	* Gets the description for a virtual VMCS state.
406	*
407	* @returns The descriptive string.
408	* @param fVmcsState The virtual-VMCS state.
409	*/
410	VMM_INT_DECL(const char *) HMVmxGetVmcsStateDesc(uint8_t fVmcsState)
411	{
412	switch (fVmcsState)
413	{
414	case VMX_V_VMCS_STATE_CLEAR: return "Clear";
415	case VMX_V_VMCS_STATE_LAUNCHED: return "Launched";
416	default: return "Unknown";
417	}
418	}
419
420
421	/**
422	* Gets the description for a VM-entry interruption information event type.
423	*
424	* @returns The descriptive string.
425	* @param uType The event type.
426	*/
427	VMM_INT_DECL(const char *) HMVmxGetEntryIntInfoTypeDesc(uint8_t uType)
428	{
429	switch (uType)
430	{
431	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
432	case VMX_ENTRY_INT_INFO_TYPE_NMI: return "NMI";
433	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
434	case VMX_ENTRY_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
435	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
436	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
437	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: return "Other Event";
438	default:
439	break;
440	}
441	return "Unknown/invalid";
442	}
443
444
445	/**
446	* Gets the description for a VM-exit interruption information event type.
447	*
448	* @returns The descriptive string.
449	* @param uType The event type.
450	*/
451	VMM_INT_DECL(const char *) HMVmxGetExitIntInfoTypeDesc(uint8_t uType)
452	{
453	switch (uType)
454	{
455	case VMX_EXIT_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
456	case VMX_EXIT_INT_INFO_TYPE_NMI: return "NMI";
457	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
458	case VMX_EXIT_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
459	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
460	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
461	default:
462	break;
463	}
464	return "Unknown/invalid";
465	}
466
467
468	/**
469	* Gets the description for an IDT-vectoring information event type.
470	*
471	* @returns The descriptive string.
472	* @param uType The event type.
473	*/
474	VMM_INT_DECL(const char *) HMVmxGetIdtVectoringInfoTypeDesc(uint8_t uType)
475	{
476	switch (uType)
477	{
478	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT: return "External Interrupt";
479	case VMX_IDT_VECTORING_INFO_TYPE_NMI: return "NMI";
480	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT: return "Hardware Exception";
481	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT: return "Software Interrupt";
482	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
483	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: return "Software Exception";
484	default:
485	break;
486	}
487	return "Unknown/invalid";
488	}
489
490
491	/**
492	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
493	* VMX when unrestricted execution isn't available.
494	*
495	* @returns true if selector is suitable for VMX, otherwise
496	* false.
497	* @param pSel Pointer to the selector to check (CS).
498	* @param uStackDpl The CPL, aka the DPL of the stack segment.
499	*/
500	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
501	{
502	/*
503	* Segment must be an accessed code segment, it must be present and it must
504	* be usable.
505	* Note! These are all standard requirements and if CS holds anything else
506	* we've got buggy code somewhere!
507	*/
508	AssertCompile(X86DESCATTR_TYPE == 0xf);
509	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
510	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
511	("%#x\n", pSel->Attr.u),
512	false);
513
514	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
515	must equal SS.DPL for non-confroming segments.
516	Note! This is also a hard requirement like above. */
517	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
518	? pSel->Attr.n.u2Dpl <= uStackDpl
519	: pSel->Attr.n.u2Dpl == uStackDpl,
520	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
521	false);
522
523	/*
524	* The following two requirements are VT-x specific:
525	* - G bit must be set if any high limit bits are set.
526	* - G bit must be clear if any low limit bits are clear.
527	*/
528	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
529	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
530	return true;
531	return false;
532	}
533
534
535	/**
536	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
537	* hardware-assisted VMX when unrestricted execution isn't available.
538	*
539	* @returns true if selector is suitable for VMX, otherwise
540	* false.
541	* @param pSel Pointer to the selector to check
542	* (DS/ES/FS/GS).
543	*/
544	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
545	{
546	/*
547	* Unusable segments are OK. These days they should be marked as such, as
548	* but as an alternative we for old saved states and AMD<->VT-x migration
549	* we also treat segments with all the attributes cleared as unusable.
550	*/
551	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
552	return true;
553
554	/** @todo tighten these checks. Will require CPUM load adjusting. */
555
556	/* Segment must be accessed. */
557	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
558	{
559	/* Code segments must also be readable. */
560	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
561	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
562	{
563	/* The S bit must be set. */
564	if (pSel->Attr.n.u1DescType)
565	{
566	/* Except for conforming segments, DPL >= RPL. */
567	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
568	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
569	{
570	/* Segment must be present. */
571	if (pSel->Attr.n.u1Present)
572	{
573	/*
574	* The following two requirements are VT-x specific:
575	* - G bit must be set if any high limit bits are set.
576	* - G bit must be clear if any low limit bits are clear.
577	*/
578	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
579	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
580	return true;
581	}
582	}
583	}
584	}
585	}
586
587	return false;
588	}
589
590
591	/**
592	* Checks if the stack selector (SS) is suitable for execution using
593	* hardware-assisted VMX when unrestricted execution isn't available.
594	*
595	* @returns true if selector is suitable for VMX, otherwise
596	* false.
597	* @param pSel Pointer to the selector to check (SS).
598	*/
599	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
600	{
601	/*
602	* Unusable segments are OK. These days they should be marked as such, as
603	* but as an alternative we for old saved states and AMD<->VT-x migration
604	* we also treat segments with all the attributes cleared as unusable.
605	*/
606	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
607	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
608	return true;
609
610	/*
611	* Segment must be an accessed writable segment, it must be present.
612	* Note! These are all standard requirements and if SS holds anything else
613	* we've got buggy code somewhere!
614	*/
615	AssertCompile(X86DESCATTR_TYPE == 0xf);
616	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
617	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
618	("%#x\n", pSel->Attr.u), false);
619
620	/*
621	* DPL must equal RPL. But in real mode or soon after enabling protected
622	* mode, it might not be.
623	*/
624	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
625	{
626	/*
627	* The following two requirements are VT-x specific:
628	* - G bit must be set if any high limit bits are set.
629	* - G bit must be clear if any low limit bits are clear.
630	*/
631	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
632	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
633	return true;
634	}
635	return false;
636	}
637
638
639	/**
640	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
641	*
642	* @returns @c true if it is suitable, @c false otherwise.
643	* @param pVCpu The cross context virtual CPU structure.
644	* @param pCtx Pointer to the guest CPU context.
645	*
646	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
647	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
648	* Secondly, if additional checks are added that require more of the CPU
649	* state, make sure REM (which supplies a partial state) is updated.
650	*/
651	VMM_INT_DECL(bool) HMVmxCanExecuteGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
652	{
653	PVM pVM = pVCpu->CTX_SUFF(pVM);
654	Assert(HMIsEnabled(pVM));
655	Assert(!CPUMIsGuestVmxEnabled(pCtx));
656	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
657	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
658
659	pVCpu->hm.s.fActive = false;
660
661	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
662	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
663	{
664	/*
665	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
666	* guest execution feature is missing (VT-x only).
667	*/
668	if (fSupportsRealMode)
669	{
670	if (CPUMIsGuestInRealModeEx(pCtx))
671	{
672	/*
673	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
674	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
675	* and attrributes must be 0x9b for code and 0x93 for code segments.
676	* If this is not true, we cannot execute real mode as V86 and have to fall
677	* back to emulation.
678	*/
679	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
680	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
681	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
682	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
683	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
684	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
685	{
686	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
687	return false;
688	}
689	if ( (pCtx->cs.u32Limit != 0xffff)
690	\|\| (pCtx->ds.u32Limit != 0xffff)
691	\|\| (pCtx->es.u32Limit != 0xffff)
692	\|\| (pCtx->ss.u32Limit != 0xffff)
693	\|\| (pCtx->fs.u32Limit != 0xffff)
694	\|\| (pCtx->gs.u32Limit != 0xffff))
695	{
696	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
697	return false;
698	}
699	if ( (pCtx->cs.Attr.u != 0x9b)
700	\|\| (pCtx->ds.Attr.u != 0x93)
701	\|\| (pCtx->es.Attr.u != 0x93)
702	\|\| (pCtx->ss.Attr.u != 0x93)
703	\|\| (pCtx->fs.Attr.u != 0x93)
704	\|\| (pCtx->gs.Attr.u != 0x93))
705	{
706	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
707	return false;
708	}
709	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
710	}
711	else
712	{
713	/*
714	* Verify the requirements for executing code in protected mode. VT-x can't
715	* handle the CPU state right after a switch from real to protected mode
716	* (all sorts of RPL & DPL assumptions).
717	*/
718	if (pVCpu->hm.s.vmx.fWasInRealMode)
719	{
720	/** @todo If guest is in V86 mode, these checks should be different! */
721	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
722	{
723	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
724	return false;
725	}
726	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
727	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
728	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
729	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
730	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
731	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
732	{
733	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
734	return false;
735	}
736	}
737	}
738	}
739	else
740	{
741	if ( !CPUMIsGuestInLongModeEx(pCtx)
742	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
743	{
744	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
745	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
746	return false;
747
748	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
749	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
750	return false;
751
752	/*
753	* The guest is about to complete the switch to protected mode. Wait a bit longer.
754	* Windows XP; switch to protected mode; all selectors are marked not present
755	* in the hidden registers (possible recompiler bug; see load_seg_vm).
756	*/
757	/** @todo Is this supposed recompiler bug still relevant with IEM? */
758	if (pCtx->cs.Attr.n.u1Present == 0)
759	return false;
760	if (pCtx->ss.Attr.n.u1Present == 0)
761	return false;
762
763	/*
764	* Windows XP: possible same as above, but new recompiler requires new
765	* heuristics? VT-x doesn't seem to like something about the guest state and
766	* this stuff avoids it.
767	*/
768	/** @todo This check is actually wrong, it doesn't take the direction of the
769	* stack segment into account. But, it does the job for now. */
770	if (pCtx->rsp >= pCtx->ss.u32Limit)
771	return false;
772	}
773	}
774	}
775
776	if (pVM->hm.s.vmx.fEnabled)
777	{
778	uint32_t uCr0Mask;
779
780	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
781	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
782
783	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
784	uCr0Mask &= ~X86_CR0_NE;
785
786	if (fSupportsRealMode)
787	{
788	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
789	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
790	}
791	else
792	{
793	/* We support protected mode without paging using identity mapping. */
794	uCr0Mask &= ~X86_CR0_PG;
795	}
796	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
797	return false;
798
799	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
800	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
801	if ((pCtx->cr0 & uCr0Mask) != 0)
802	return false;
803
804	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
805	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
806	uCr0Mask &= ~X86_CR4_VMXE;
807	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
808	return false;
809
810	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
811	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
812	if ((pCtx->cr4 & uCr0Mask) != 0)
813	return false;
814
815	pVCpu->hm.s.fActive = true;
816	return true;
817	}
818
819	return false;
820	}
821
822
823	/**
824	* Injects an event using TRPM given a VM-entry interruption info. and related
825	* fields.
826	*
827	* @returns VBox status code.
828	* @param pVCpu The cross context virtual CPU structure.
829	* @param uEntryIntInfo The VM-entry interruption info.
830	* @param uErrCode The error code associated with the event if any.
831	* @param cbInstr The VM-entry instruction length (for software
832	* interrupts and software exceptions). Pass 0
833	* otherwise.
834	* @param GCPtrFaultAddress The guest CR2 if this is a \#PF event.
835	*/
836	VMM_INT_DECL(int) HMVmxEntryIntInfoInjectTrpmEvent(PVMCPU pVCpu, uint32_t uEntryIntInfo, uint32_t uErrCode, uint32_t cbInstr,
837	RTGCUINTPTR GCPtrFaultAddress)
838	{
839	Assert(VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo));
840
841	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
842	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uEntryIntInfo);
843	bool const fErrCodeValid = VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(uEntryIntInfo);
844
845	TRPMEVENT enmTrapType;
846	switch (uType)
847	{
848	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
849	enmTrapType = TRPM_HARDWARE_INT;
850	break;
851
852	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
853	enmTrapType = TRPM_SOFTWARE_INT;
854	break;
855
856	case VMX_ENTRY_INT_INFO_TYPE_NMI:
857	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* ICEBP. */
858	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* #BP and #OF */
859	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
860	enmTrapType = TRPM_TRAP;
861	break;
862
863	default:
864	/* Shouldn't really happen. */
865	AssertMsgFailedReturn(("Invalid trap type %#x\n", uType), VERR_VMX_IPE_4);
866	break;
867	}
868
869	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
870	AssertRCReturn(rc, rc);
871
872	if (fErrCodeValid)
873	TRPMSetErrorCode(pVCpu, uErrCode);
874
875	if ( uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
876	&& uVector == X86_XCPT_PF)
877	TRPMSetFaultAddress(pVCpu, GCPtrFaultAddress);
878	else if ( uType == VMX_ENTRY_INT_INFO_TYPE_SW_INT
879	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT
880	\|\| uType == VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT)
881	{
882	AssertMsg( uType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
883	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
884	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uType));
885	TRPMSetInstrLength(pVCpu, cbInstr);
886	}
887
888	return VINF_SUCCESS;
889	}
890
891
892	/**
893	* Gets the permission bits for the specified MSR in the specified MSR bitmap.
894	*
895	* @returns VBox status code.
896	* @param pvMsrBitmap Pointer to the MSR bitmap.
897	* @param idMsr The MSR.
898	* @param penmRead Where to store the read permissions. Optional, can be
899	* NULL.
900	* @param penmWrite Where to store the write permissions. Optional, can be
901	* NULL.
902	*/
903	VMM_INT_DECL(int) HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
904	PVMXMSREXITWRITE penmWrite)
905	{
906	AssertPtrReturn(pvMsrBitmap, VERR_INVALID_PARAMETER);
907
908	int32_t iBit;
909	uint8_t const pbMsrBitmap = (uint8_t )pvMsrBitmap;
910
911	/*
912	* MSR Layout:
913	* Byte index MSR range Interpreted as
914	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
915	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
916	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
917	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
918	*
919	* A bit corresponding to an MSR within the above range causes a VM-exit
920	* if the bit is 1 on executions of RDMSR/WRMSR.
921	*
922	* If an MSR falls out of the MSR range, it always cause a VM-exit.
923	*
924	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
925	*/
926	if (idMsr <= 0x00001fff)
927	iBit = idMsr;
928	else if ( idMsr >= 0xc0000000
929	&& idMsr <= 0xc0001fff)
930	{
931	iBit = (idMsr - 0xc0000000);
932	pbMsrBitmap += 0x400;
933	}
934	else
935	{
936	if (penmRead)
937	*penmRead = VMXMSREXIT_INTERCEPT_READ;
938	if (penmWrite)
939	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
940	Log(("CPUMVmxGetMsrPermission: Warning! Out of range MSR %#RX32\n", idMsr));
941	return VINF_SUCCESS;
942	}
943
944	/* Validate the MSR bit position. */
945	Assert(iBit <= 0x1fff);
946
947	/* Get the MSR read permissions. */
948	if (penmRead)
949	{
950	if (ASMBitTest(pbMsrBitmap, iBit))
951	*penmRead = VMXMSREXIT_INTERCEPT_READ;
952	else
953	*penmRead = VMXMSREXIT_PASSTHRU_READ;
954	}
955
956	/* Get the MSR write permissions. */
957	if (penmWrite)
958	{
959	if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
960	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
961	else
962	*penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
963	}
964
965	return VINF_SUCCESS;
966	}
967
968
969	/**
970	* Gets the permission bits for the specified I/O port from the given I/O bitmaps.
971	*
972	* @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
973	* @param pvIoBitmapA Pointer to I/O bitmap A.
974	* @param pvIoBitmapB Pointer to I/O bitmap B.
975	* @param uPort The I/O port being accessed.
976	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
977	*/
978	VMM_INT_DECL(bool) HMVmxGetIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort,
979	uint8_t cbAccess)
980	{
981	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
982
983	/*
984	* If the I/O port access wraps around the 16-bit port I/O space,
985	* we must cause a VM-exit.
986	*
987	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
988	*/
989	/** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
990	* respectively are valid and do not constitute a wrap around from what I
991	* understand. Verify this later. */
992	uint32_t const uPortLast = uPort + cbAccess;
993	if (uPortLast > 0x10000)
994	return true;
995
996	/* Read the appropriate bit from the corresponding IO bitmap. */
997	void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
998	return ASMBitTest(pvIoBitmap, uPort);
999	}
1000

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 76763

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