HMVMXAll.cpp@ 78327

Last change on this file since 78327 was 78220, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 76.2 KB

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1	/* $Id: HMVMXAll.cpp 78220 2019-04-20 04:08:44Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <iprt/errcore.h>
28
29
30	/*********************************************************************************************************************************
31	* Global Variables *
32	*********************************************************************************************************************************/
33	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
34	/** VMX virtual-instructions and VM-exit diagnostics. */
35	static const char * const g_apszVmxVDiagDesc[] =
36	{
37	/* Internal processing errors. */
38	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
55	/* VMXON. */
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
76	/* VMXOFF. */
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
83	/* VMPTRLD. */
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RevPtrReadPhys , "RevPtrReadPhys" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
97	/* VMPTRST. */
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
102	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
103	/* VMCLEAR. */
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
113	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
114	/* VMWRITE. */
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
123	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
124	/* VMREAD. */
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
132	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
133	/* VMLAUNCH/VMRESUME. */
134	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
144	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrShadowVmcs , "PtrShadowVmcs" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
360	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
361	/* kVmxVDiag_End */
362	};
363	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
364	#undef VMXV_DIAG_DESC
365
366
367	/**
368	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
369	*
370	* @returns The descriptive string.
371	* @param enmDiag The VMX diagnostic.
372	*/
373	VMM_INT_DECL(const char *) HMGetVmxDiagDesc(VMXVDIAG enmDiag)
374	{
375	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
376	return g_apszVmxVDiagDesc[enmDiag];
377	return "Unknown/invalid";
378	}
379
380
381	/**
382	* Gets the description for a VMX abort reason.
383	*
384	* @returns The descriptive string.
385	* @param enmAbort The VMX abort reason.
386	*/
387	VMM_INT_DECL(const char *) HMGetVmxAbortDesc(VMXABORT enmAbort)
388	{
389	switch (enmAbort)
390	{
391	case VMXABORT_NONE: return "VMXABORT_NONE";
392	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
393	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
394	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
395	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
396	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
397	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
398	default:
399	break;
400	}
401	return "Unknown/invalid";
402	}
403
404
405	/**
406	* Gets the description for a virtual VMCS state.
407	*
408	* @returns The descriptive string.
409	* @param fVmcsState The virtual-VMCS state.
410	*/
411	VMM_INT_DECL(const char *) HMGetVmxVmcsStateDesc(uint8_t fVmcsState)
412	{
413	switch (fVmcsState)
414	{
415	case VMX_V_VMCS_LAUNCH_STATE_CLEAR: return "Clear";
416	case VMX_V_VMCS_LAUNCH_STATE_LAUNCHED: return "Launched";
417	default: return "Unknown";
418	}
419	}
420
421
422	/**
423	* Gets the description for a VM-entry interruption information event type.
424	*
425	* @returns The descriptive string.
426	* @param uType The event type.
427	*/
428	VMM_INT_DECL(const char *) HMGetVmxEntryIntInfoTypeDesc(uint8_t uType)
429	{
430	switch (uType)
431	{
432	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
433	case VMX_ENTRY_INT_INFO_TYPE_NMI: return "NMI";
434	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
435	case VMX_ENTRY_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
436	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
437	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
438	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: return "Other Event";
439	default:
440	break;
441	}
442	return "Unknown/invalid";
443	}
444
445
446	/**
447	* Gets the description for a VM-exit interruption information event type.
448	*
449	* @returns The descriptive string.
450	* @param uType The event type.
451	*/
452	VMM_INT_DECL(const char *) HMGetVmxExitIntInfoTypeDesc(uint8_t uType)
453	{
454	switch (uType)
455	{
456	case VMX_EXIT_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
457	case VMX_EXIT_INT_INFO_TYPE_NMI: return "NMI";
458	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
459	case VMX_EXIT_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
460	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
461	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
462	default:
463	break;
464	}
465	return "Unknown/invalid";
466	}
467
468
469	/**
470	* Gets the description for an IDT-vectoring information event type.
471	*
472	* @returns The descriptive string.
473	* @param uType The event type.
474	*/
475	VMM_INT_DECL(const char *) HMGetVmxIdtVectoringInfoTypeDesc(uint8_t uType)
476	{
477	switch (uType)
478	{
479	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT: return "External Interrupt";
480	case VMX_IDT_VECTORING_INFO_TYPE_NMI: return "NMI";
481	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT: return "Hardware Exception";
482	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT: return "Software Interrupt";
483	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
484	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: return "Software Exception";
485	default:
486	break;
487	}
488	return "Unknown/invalid";
489	}
490
491
492	/**
493	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
494	* VMX when unrestricted execution isn't available.
495	*
496	* @returns true if selector is suitable for VMX, otherwise
497	* false.
498	* @param pSel Pointer to the selector to check (CS).
499	* @param uStackDpl The CPL, aka the DPL of the stack segment.
500	*/
501	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
502	{
503	/*
504	* Segment must be an accessed code segment, it must be present and it must
505	* be usable.
506	* Note! These are all standard requirements and if CS holds anything else
507	* we've got buggy code somewhere!
508	*/
509	AssertCompile(X86DESCATTR_TYPE == 0xf);
510	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
511	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
512	("%#x\n", pSel->Attr.u),
513	false);
514
515	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
516	must equal SS.DPL for non-confroming segments.
517	Note! This is also a hard requirement like above. */
518	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
519	? pSel->Attr.n.u2Dpl <= uStackDpl
520	: pSel->Attr.n.u2Dpl == uStackDpl,
521	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
522	false);
523
524	/*
525	* The following two requirements are VT-x specific:
526	* - G bit must be set if any high limit bits are set.
527	* - G bit must be clear if any low limit bits are clear.
528	*/
529	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
530	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
531	return true;
532	return false;
533	}
534
535
536	/**
537	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
538	* hardware-assisted VMX when unrestricted execution isn't available.
539	*
540	* @returns true if selector is suitable for VMX, otherwise
541	* false.
542	* @param pSel Pointer to the selector to check
543	* (DS/ES/FS/GS).
544	*/
545	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
546	{
547	/*
548	* Unusable segments are OK. These days they should be marked as such, as
549	* but as an alternative we for old saved states and AMD<->VT-x migration
550	* we also treat segments with all the attributes cleared as unusable.
551	*/
552	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
553	return true;
554
555	/** @todo tighten these checks. Will require CPUM load adjusting. */
556
557	/* Segment must be accessed. */
558	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
559	{
560	/* Code segments must also be readable. */
561	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
562	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
563	{
564	/* The S bit must be set. */
565	if (pSel->Attr.n.u1DescType)
566	{
567	/* Except for conforming segments, DPL >= RPL. */
568	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
569	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
570	{
571	/* Segment must be present. */
572	if (pSel->Attr.n.u1Present)
573	{
574	/*
575	* The following two requirements are VT-x specific:
576	* - G bit must be set if any high limit bits are set.
577	* - G bit must be clear if any low limit bits are clear.
578	*/
579	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
580	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
581	return true;
582	}
583	}
584	}
585	}
586	}
587
588	return false;
589	}
590
591
592	/**
593	* Checks if the stack selector (SS) is suitable for execution using
594	* hardware-assisted VMX when unrestricted execution isn't available.
595	*
596	* @returns true if selector is suitable for VMX, otherwise
597	* false.
598	* @param pSel Pointer to the selector to check (SS).
599	*/
600	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
601	{
602	/*
603	* Unusable segments are OK. These days they should be marked as such, as
604	* but as an alternative we for old saved states and AMD<->VT-x migration
605	* we also treat segments with all the attributes cleared as unusable.
606	*/
607	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
608	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
609	return true;
610
611	/*
612	* Segment must be an accessed writable segment, it must be present.
613	* Note! These are all standard requirements and if SS holds anything else
614	* we've got buggy code somewhere!
615	*/
616	AssertCompile(X86DESCATTR_TYPE == 0xf);
617	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
618	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
619	("%#x\n", pSel->Attr.u), false);
620
621	/*
622	* DPL must equal RPL. But in real mode or soon after enabling protected
623	* mode, it might not be.
624	*/
625	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
626	{
627	/*
628	* The following two requirements are VT-x specific:
629	* - G bit must be set if any high limit bits are set.
630	* - G bit must be clear if any low limit bits are clear.
631	*/
632	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
633	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
634	return true;
635	}
636	return false;
637	}
638
639
640	/**
641	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
642	*
643	* @returns @c true if it is suitable, @c false otherwise.
644	* @param pVCpu The cross context virtual CPU structure.
645	* @param pCtx Pointer to the guest CPU context.
646	*
647	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
648	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
649	* Secondly, if additional checks are added that require more of the CPU
650	* state, make sure REM (which supplies a partial state) is updated.
651	*/
652	VMM_INT_DECL(bool) HMCanExecuteVmxGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
653	{
654	PVM pVM = pVCpu->CTX_SUFF(pVM);
655	Assert(HMIsEnabled(pVM));
656	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
657	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
658
659	pVCpu->hm.s.fActive = false;
660
661	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
662	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
663	{
664	/*
665	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
666	* guest execution feature is missing (VT-x only).
667	*/
668	if (fSupportsRealMode)
669	{
670	if (CPUMIsGuestInRealModeEx(pCtx))
671	{
672	/*
673	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
674	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
675	* and attributes must be 0x9b for code and 0x93 for code segments.
676	* If this is not true, we cannot execute real mode as V86 and have to fall
677	* back to emulation.
678	*/
679	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
680	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
681	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
682	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
683	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
684	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
685	{
686	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
687	return false;
688	}
689	if ( (pCtx->cs.u32Limit != 0xffff)
690	\|\| (pCtx->ds.u32Limit != 0xffff)
691	\|\| (pCtx->es.u32Limit != 0xffff)
692	\|\| (pCtx->ss.u32Limit != 0xffff)
693	\|\| (pCtx->fs.u32Limit != 0xffff)
694	\|\| (pCtx->gs.u32Limit != 0xffff))
695	{
696	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
697	return false;
698	}
699	if ( (pCtx->cs.Attr.u != 0x9b)
700	\|\| (pCtx->ds.Attr.u != 0x93)
701	\|\| (pCtx->es.Attr.u != 0x93)
702	\|\| (pCtx->ss.Attr.u != 0x93)
703	\|\| (pCtx->fs.Attr.u != 0x93)
704	\|\| (pCtx->gs.Attr.u != 0x93))
705	{
706	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
707	return false;
708	}
709	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
710	}
711	else
712	{
713	/*
714	* Verify the requirements for executing code in protected mode. VT-x can't
715	* handle the CPU state right after a switch from real to protected mode
716	* (all sorts of RPL & DPL assumptions).
717	*/
718	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
719	if (pVmcsInfo->fWasInRealMode)
720	{
721	if (!CPUMIsGuestInV86ModeEx(pCtx))
722	{
723	/* The guest switched to protected mode, check if the state is suitable for VT-x. */
724	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
725	{
726	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
727	return false;
728	}
729	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
730	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
731	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
732	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
733	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
734	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
735	{
736	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
737	return false;
738	}
739	}
740	else
741	{
742	/* The guest switched to V86 mode, check if the state is suitable for VT-x. */
743	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
744	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
745	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
746	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
747	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
748	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
749	{
750	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelBase);
751	return false;
752	}
753	if ( (pCtx->cs.u32Limit != 0xffff)
754	\|\| (pCtx->ds.u32Limit != 0xffff)
755	\|\| (pCtx->es.u32Limit != 0xffff)
756	\|\| (pCtx->ss.u32Limit != 0xffff)
757	\|\| (pCtx->fs.u32Limit != 0xffff)
758	\|\| (pCtx->gs.u32Limit != 0xffff))
759	{
760	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit);
761	return false;
762	}
763	if ( (pCtx->cs.Attr.u != 0xf3)
764	\|\| (pCtx->ds.Attr.u != 0xf3)
765	\|\| (pCtx->es.Attr.u != 0xf3)
766	\|\| (pCtx->ss.Attr.u != 0xf3)
767	\|\| (pCtx->fs.Attr.u != 0xf3)
768	\|\| (pCtx->gs.Attr.u != 0xf3))
769	{
770	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr);
771	return false;
772	}
773	}
774	}
775	}
776	}
777	else
778	{
779	if (!CPUMIsGuestInLongModeEx(pCtx))
780	{
781	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
782	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
783	return false;
784
785	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
786	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
787	return false;
788
789	/*
790	* The guest is about to complete the switch to protected mode. Wait a bit longer.
791	* Windows XP; switch to protected mode; all selectors are marked not present
792	* in the hidden registers (possible recompiler bug; see load_seg_vm).
793	*/
794	/** @todo Is this supposed recompiler bug still relevant with IEM? */
795	if (pCtx->cs.Attr.n.u1Present == 0)
796	return false;
797	if (pCtx->ss.Attr.n.u1Present == 0)
798	return false;
799
800	/*
801	* Windows XP: possible same as above, but new recompiler requires new
802	* heuristics? VT-x doesn't seem to like something about the guest state and
803	* this stuff avoids it.
804	*/
805	/** @todo This check is actually wrong, it doesn't take the direction of the
806	* stack segment into account. But, it does the job for now. */
807	if (pCtx->rsp >= pCtx->ss.u32Limit)
808	return false;
809	}
810	}
811	}
812
813	if (pVM->hm.s.vmx.fEnabled)
814	{
815	uint32_t uCr0Mask;
816
817	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
818	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
819
820	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
821	uCr0Mask &= ~X86_CR0_NE;
822
823	if (fSupportsRealMode)
824	{
825	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
826	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
827	}
828	else
829	{
830	/* We support protected mode without paging using identity mapping. */
831	uCr0Mask &= ~X86_CR0_PG;
832	}
833	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
834	return false;
835
836	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
837	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
838	if ((pCtx->cr0 & uCr0Mask) != 0)
839	return false;
840
841	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
842	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
843	uCr0Mask &= ~X86_CR4_VMXE;
844	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
845	return false;
846
847	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
848	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
849	if ((pCtx->cr4 & uCr0Mask) != 0)
850	return false;
851
852	pVCpu->hm.s.fActive = true;
853	return true;
854	}
855
856	return false;
857	}
858
859
860	/**
861	* Gets the read and write permission bits for an MSR in an MSR bitmap.
862	*
863	* @returns VMXMSRPM_XXX - the MSR permission.
864	* @param pvMsrBitmap Pointer to the MSR bitmap.
865	* @param idMsr The MSR to get permissions for.
866	*
867	* @sa hmR0VmxSetMsrPermission.
868	*/
869	VMM_INT_DECL(uint32_t) HMGetVmxMsrPermission(void const *pvMsrBitmap, uint32_t idMsr)
870	{
871	AssertPtrReturn(pvMsrBitmap, VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR);
872
873	uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
874
875	/*
876	* MSR Layout:
877	* Byte index MSR range Interpreted as
878	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
879	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
880	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
881	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
882	*
883	* A bit corresponding to an MSR within the above range causes a VM-exit
884	* if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
885	* the MSR range, it always cause a VM-exit.
886	*
887	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
888	*/
889	uint32_t const offBitmapRead = 0;
890	uint32_t const offBitmapWrite = 0x800;
891	uint32_t offMsr;
892	uint32_t iBit;
893	if (idMsr <= UINT32_C(0x00001fff))
894	{
895	offMsr = 0;
896	iBit = idMsr;
897	}
898	else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
899	{
900	offMsr = 0x400;
901	iBit = idMsr - UINT32_C(0xc0000000);
902	}
903	else
904	{
905	LogFunc(("Warning! Out of range MSR %#RX32\n", idMsr));
906	return VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR;
907	}
908
909	/*
910	* Get the MSR read permissions.
911	*/
912	uint32_t fRet;
913	uint32_t const offMsrRead = offBitmapRead + offMsr;
914	Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
915	if (ASMBitTest(pbMsrBitmap + offMsrRead, iBit))
916	fRet = VMXMSRPM_EXIT_RD;
917	else
918	fRet = VMXMSRPM_ALLOW_RD;
919
920	/*
921	* Get the MSR write permissions.
922	*/
923	uint32_t const offMsrWrite = offBitmapWrite + offMsr;
924	Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
925	if (ASMBitTest(pbMsrBitmap + offMsrWrite, iBit))
926	fRet \|= VMXMSRPM_EXIT_WR;
927	else
928	fRet \|= VMXMSRPM_ALLOW_WR;
929
930	Assert(VMXMSRPM_IS_FLAG_VALID(fRet));
931	return fRet;
932	}
933
934
935	/**
936	* Gets the permission bits for the specified I/O port from the given I/O bitmaps.
937	*
938	* @returns @c true if the I/O port access must cause a VM-exit, @c false otherwise.
939	* @param pvIoBitmapA Pointer to I/O bitmap A.
940	* @param pvIoBitmapB Pointer to I/O bitmap B.
941	* @param uPort The I/O port being accessed.
942	* @param cbAccess The size of the I/O access in bytes (1, 2 or 4 bytes).
943	*/
944	VMM_INT_DECL(bool) HMGetVmxIoBitmapPermission(void const pvIoBitmapA, void const pvIoBitmapB, uint16_t uPort, uint8_t cbAccess)
945	{
946	Assert(cbAccess == 1 \|\| cbAccess == 2 \|\| cbAccess == 4);
947
948	/*
949	* If the I/O port access wraps around the 16-bit port I/O space,
950	* we must cause a VM-exit.
951	*
952	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
953	*/
954	/** @todo r=ramshankar: Reading 1, 2, 4 bytes at ports 0xffff, 0xfffe and 0xfffc
955	* respectively are valid and do not constitute a wrap around from what I
956	* understand. Verify this later. */
957	uint32_t const uPortLast = uPort + cbAccess;
958	if (uPortLast > 0x10000)
959	return true;
960
961	/* Read the appropriate bit from the corresponding IO bitmap. */
962	void const *pvIoBitmap = uPort < 0x8000 ? pvIoBitmapA : pvIoBitmapB;
963	return ASMBitTest(pvIoBitmap, uPort);
964	}
965
966
967	/**
968	* Dumps the virtual VMCS state to the release log.
969	*
970	* @param pVCpu The cross context virtual CPU structure.
971	*/
972	VMM_INT_DECL(void) HMDumpHwvirtVmxState(PVMCPU pVCpu)
973	{
974	#ifndef IN_RC
975	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
976	# define HMVMX_DUMP_HOST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
977	do { \
978	LogRel((" %s%-4s = {base=%016RX64}\n", \
979	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u)); \
980	} while (0)
981	# define HMVMX_DUMP_HOST_FS_GS_TR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
982	do { \
983	LogRel((" %s%-4s = {%04x base=%016RX64}\n", \
984	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u)); \
985	} while (0)
986	# define HMVMX_DUMP_GUEST_SEGREG(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
987	do { \
988	LogRel((" %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
989	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
990	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr)); \
991	} while (0)
992	# define HMVMX_DUMP_GUEST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
993	do { \
994	LogRel((" %s%-4s = {base=%016RX64 limit=%08x}\n", \
995	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit)); \
996	} while (0)
997
998	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
999	PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1000	if (!pVmcs)
1001	{
1002	LogRel(("Virtual VMCS not allocated\n"));
1003	return;
1004	}
1005	LogRel(("GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon));
1006	LogRel(("GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs));
1007	LogRel(("GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs));
1008	LogRel(("enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag)));
1009	LogRel(("enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMGetVmxAbortDesc(pCtx->hwvirt.vmx.enmAbort)));
1010	LogRel(("uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux));
1011	LogRel(("fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode));
1012	LogRel(("fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode));
1013	LogRel(("fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents));
1014	LogRel(("fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret));
1015	LogRel(("uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick));
1016	LogRel(("uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick));
1017	LogRel(("uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick));
1018	LogRel(("offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite));
1019	LogRel(("fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking));
1020	LogRel(("VMCS cache:\n"));
1021
1022	const char *pszPrefix = " ";
1023	/* Header. */
1024	{
1025	LogRel(("%sHeader:\n", pszPrefix));
1026	LogRel((" %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId));
1027	LogRel((" %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, HMGetVmxAbortDesc(pVmcs->enmVmxAbort)));
1028	LogRel((" %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, HMGetVmxVmcsStateDesc(pVmcs->fVmcsState)));
1029	}
1030
1031	/* Control fields. */
1032	{
1033	/* 16-bit. */
1034	LogRel(("%sControl:\n", pszPrefix));
1035	LogRel((" %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid));
1036	LogRel((" %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector));
1037	LogRel((" %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex));
1038
1039	/* 32-bit. */
1040	LogRel((" %sPinCtls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls));
1041	LogRel((" %sProcCtls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls));
1042	LogRel((" %sProcCtls2 = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2));
1043	LogRel((" %sExitCtls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls));
1044	LogRel((" %sEntryCtls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls));
1045	LogRel((" %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap));
1046	LogRel((" %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask));
1047	LogRel((" %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch));
1048	LogRel((" %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount));
1049	LogRel((" %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount));
1050	LogRel((" %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount));
1051	LogRel((" %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount));
1052	LogRel((" %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo));
1053	{
1054	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
1055	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
1056	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo)));
1057	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxEntryIntInfoTypeDesc(uType)));
1058	LogRel((" %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo)));
1059	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
1060	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
1061	}
1062	LogRel((" %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode));
1063	LogRel((" %sVM-entry instruction len = %u bytes\n", pszPrefix, pVmcs->u32EntryInstrLen));
1064	LogRel((" %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold));
1065	LogRel((" %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap));
1066	LogRel((" %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow));
1067
1068	/* 64-bit. */
1069	LogRel((" %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u));
1070	LogRel((" %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u));
1071	LogRel((" %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u));
1072	LogRel((" %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u));
1073	LogRel((" %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u));
1074	LogRel((" %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u));
1075	LogRel((" %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u));
1076	LogRel((" %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u));
1077	LogRel((" %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u));
1078	LogRel((" %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u));
1079	LogRel((" %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u));
1080	LogRel((" %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u));
1081	LogRel((" %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u));
1082	LogRel((" %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u));
1083	LogRel((" %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u));
1084	LogRel((" %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u));
1085	LogRel((" %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u));
1086	LogRel((" %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u));
1087	LogRel((" %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u));
1088	LogRel((" %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u));
1089	LogRel((" %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u));
1090	LogRel((" %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u));
1091	LogRel((" %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u));
1092	LogRel((" %sENCLS-exiting bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEnclsBitmap.u));
1093	LogRel((" %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u));
1094
1095	/* Natural width. */
1096	LogRel((" %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u));
1097	LogRel((" %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u));
1098	LogRel((" %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u));
1099	LogRel((" %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u));
1100	LogRel((" %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u));
1101	LogRel((" %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u));
1102	LogRel((" %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u));
1103	LogRel((" %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u));
1104	}
1105
1106	/* Guest state. */
1107	{
1108	LogRel(("%sGuest state:\n", pszPrefix));
1109
1110	/* 16-bit. */
1111	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Cs, "cs", pszPrefix);
1112	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ss, "ss", pszPrefix);
1113	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Es, "es", pszPrefix);
1114	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ds, "ds", pszPrefix);
1115	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Fs, "fs", pszPrefix);
1116	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Gs, "gs", pszPrefix);
1117	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ldtr, "ldtr", pszPrefix);
1118	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Tr, "tr", pszPrefix);
1119	HMVMX_DUMP_GUEST_XDTR( pVmcs, Gdtr, "gdtr", pszPrefix);
1120	HMVMX_DUMP_GUEST_XDTR( pVmcs, Idtr, "idtr", pszPrefix);
1121	LogRel((" %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus));
1122	LogRel((" %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex));
1123
1124	/* 32-bit. */
1125	LogRel((" %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState));
1126	LogRel((" %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState));
1127	LogRel((" %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase));
1128	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS));
1129	LogRel((" %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer));
1130
1131	/* 64-bit. */
1132	LogRel((" %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u));
1133	LogRel((" %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u));
1134	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u));
1135	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u));
1136	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u));
1137	LogRel((" %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u));
1138	LogRel((" %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u));
1139	LogRel((" %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u));
1140	LogRel((" %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u));
1141	LogRel((" %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u));
1142
1143	/* Natural width. */
1144	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u));
1145	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u));
1146	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u));
1147	LogRel((" %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u));
1148	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u));
1149	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u));
1150	LogRel((" %srflags = %#RX64\n", pszPrefix, pVmcs->u64GuestRFlags.u));
1151	LogRel((" %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpt.u));
1152	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u));
1153	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u));
1154	}
1155
1156	/* Host state. */
1157	{
1158	LogRel(("%sHost state:\n", pszPrefix));
1159
1160	/* 16-bit. */
1161	LogRel((" %scs = %#RX16\n", pszPrefix, pVmcs->HostCs));
1162	LogRel((" %sss = %#RX16\n", pszPrefix, pVmcs->HostSs));
1163	LogRel((" %sds = %#RX16\n", pszPrefix, pVmcs->HostDs));
1164	LogRel((" %ses = %#RX16\n", pszPrefix, pVmcs->HostEs));
1165	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Fs, "fs", pszPrefix);
1166	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Gs, "gs", pszPrefix);
1167	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Tr, "tr", pszPrefix);
1168	HMVMX_DUMP_HOST_XDTR(pVmcs, Gdtr, "gdtr", pszPrefix);
1169	HMVMX_DUMP_HOST_XDTR(pVmcs, Idtr, "idtr", pszPrefix);
1170
1171	/* 32-bit. */
1172	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs));
1173
1174	/* 64-bit. */
1175	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u));
1176	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u));
1177	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u));
1178
1179	/* Natural width. */
1180	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u));
1181	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u));
1182	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u));
1183	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u));
1184	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u));
1185	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u));
1186	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u));
1187	}
1188
1189	/* Read-only fields. */
1190	{
1191	LogRel(("%sRead-only data fields:\n", pszPrefix));
1192
1193	/* 16-bit (none currently). */
1194
1195	/* 32-bit. */
1196	uint32_t const uExitReason = pVmcs->u32RoExitReason;
1197	LogRel((" %sExit reason = %u (%s)\n", pszPrefix, uExitReason, HMGetVmxExitName(uExitReason)));
1198	LogRel((" %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u));
1199	LogRel((" %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError));
1200	LogRel((" %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo));
1201	{
1202	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
1203	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
1204	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo)));
1205	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxExitIntInfoTypeDesc(uType)));
1206	LogRel((" %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo)));
1207	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
1208	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
1209	}
1210	LogRel((" %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode));
1211	LogRel((" %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo));
1212	{
1213	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
1214	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
1215	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo)));
1216	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxIdtVectoringInfoTypeDesc(uType)));
1217	LogRel((" %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo)));
1218	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo)));
1219	}
1220	LogRel((" %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode));
1221	LogRel((" %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen));
1222	LogRel((" %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo));
1223
1224	/* 64-bit. */
1225	LogRel((" %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u));
1226
1227	/* Natural width. */
1228	LogRel((" %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u));
1229	LogRel((" %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u));
1230	LogRel((" %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u));
1231	LogRel((" %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u));
1232	LogRel((" %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u));
1233	}
1234
1235	# undef HMVMX_DUMP_HOST_XDTR
1236	# undef HMVMX_DUMP_HOST_FS_GS_TR
1237	# undef HMVMX_DUMP_GUEST_SEGREG
1238	# undef HMVMX_DUMP_GUEST_XDTR
1239	#else
1240	NOREF(pVCpu);
1241	#endif /* !IN_RC */
1242	}
1243
1244
1245	/**
1246	* Gets the active (in use) VMCS info. object for the specified VCPU.
1247	*
1248	* This is either the guest or nested-guest VMCS and need not necessarily pertain to
1249	* the "current" VMCS (in the VMX definition of the term). For instance, if the
1250	* VM-entry failed due to an invalid-guest state, we may have "cleared" the VMCS
1251	* while returning to ring-3. The VMCS info. object for that VMCS would still be
1252	* active and returned so that we could dump the VMCS fields to ring-3 for
1253	* diagnostics. This function is thus only used to distinguish between the
1254	* nested-guest or guest VMCS.
1255	*
1256	* @returns The active VMCS information.
1257	* @param pVCpu The cross context virtual CPU structure.
1258	*
1259	* @thread EMT.
1260	* @remarks This function may be called with preemption or interrupts disabled!
1261	*/
1262	VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu)
1263	{
1264	if (!pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs)
1265	return &pVCpu->hm.s.vmx.VmcsInfo;
1266	return &pVCpu->hm.s.vmx.VmcsInfoNstGst;
1267	}
1268
1269
1270	/**
1271	* Converts a VMX event type into an appropriate TRPM event type.
1272	*
1273	* @returns TRPM event.
1274	* @param uIntInfo The VMX event.
1275	*/
1276	VMM_INT_DECL(TRPMEVENT) HMVmxEventToTrpmEventType(uint32_t uIntInfo)
1277	{
1278	TRPMEVENT enmTrapType;
1279	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uIntInfo);
1280	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uIntInfo);
1281
1282	switch (uType)
1283	{
1284	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
1285	enmTrapType = TRPM_HARDWARE_INT;
1286	break;
1287
1288	case VMX_ENTRY_INT_INFO_TYPE_NMI:
1289	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
1290	enmTrapType = TRPM_TRAP;
1291	break;
1292
1293	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* INT1 (ICEBP). */
1294	Assert(uVector == X86_XCPT_DB); NOREF(uVector);
1295	enmTrapType = TRPM_SOFTWARE_INT;
1296	break;
1297
1298	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* INT3 (#BP) and INTO (#OF) */
1299	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF); NOREF(uVector);
1300	enmTrapType = TRPM_SOFTWARE_INT;
1301	break;
1302
1303	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
1304	enmTrapType = TRPM_SOFTWARE_INT;
1305	break;
1306
1307	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: /* Shouldn't really happen. */
1308	default:
1309	AssertMsgFailed(("Invalid trap type %#x\n", uType));
1310	enmTrapType = TRPM_32BIT_HACK;
1311	break;
1312	}
1313
1314	return enmTrapType;
1315	}
1316
1317
1318	#ifndef IN_RC
1319	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1320	/**
1321	* Notification callback for when a VM-exit happens outside VMX R0 code (e.g. in
1322	* IEM).
1323	*
1324	* @param pVCpu The cross context virtual CPU structure.
1325	* @param pCtx Pointer to the guest-CPU context.
1326	*/
1327	VMM_INT_DECL(void) HMNotifyVmxNstGstVmexit(PVMCPU pVCpu, PCPUMCTX pCtx)
1328	{
1329	NOREF(pCtx);
1330	pVCpu->hm.s.vmx.fMergedNstGstCtls = false;
1331	}
1332	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
1333	#endif /* IN_RC */
1334

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 78327

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