HMVMXAll.cpp@ 78591

Last change on this file since 78591 was 78591, checked in by vboxsync, 6 years ago
VMM/HM, CPUM: Nested VMX: bugref:9180 Better description of virtual VMCS fields while dumping.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 74.2 KB

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1	/* $Id: HMVMXAll.cpp 78591 2019-05-20 10:03:10Z vboxsync $ */
2	/** @file
3	* HM VMX (VT-x) - All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2018-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <iprt/errcore.h>
28
29
30	/*********************************************************************************************************************************
31	* Global Variables *
32	*********************************************************************************************************************************/
33	#define VMXV_DIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
34	/** VMX virtual-instructions and VM-exit diagnostics. */
35	static const char * const g_apszVmxVDiagDesc[] =
36	{
37	/* Internal processing errors. */
38	VMXV_DIAG_DESC(kVmxVDiag_None , "None" ),
39	VMXV_DIAG_DESC(kVmxVDiag_Ipe_1 , "Ipe_1" ),
40	VMXV_DIAG_DESC(kVmxVDiag_Ipe_2 , "Ipe_2" ),
41	VMXV_DIAG_DESC(kVmxVDiag_Ipe_3 , "Ipe_3" ),
42	VMXV_DIAG_DESC(kVmxVDiag_Ipe_4 , "Ipe_4" ),
43	VMXV_DIAG_DESC(kVmxVDiag_Ipe_5 , "Ipe_5" ),
44	VMXV_DIAG_DESC(kVmxVDiag_Ipe_6 , "Ipe_6" ),
45	VMXV_DIAG_DESC(kVmxVDiag_Ipe_7 , "Ipe_7" ),
46	VMXV_DIAG_DESC(kVmxVDiag_Ipe_8 , "Ipe_8" ),
47	VMXV_DIAG_DESC(kVmxVDiag_Ipe_9 , "Ipe_9" ),
48	VMXV_DIAG_DESC(kVmxVDiag_Ipe_10 , "Ipe_10" ),
49	VMXV_DIAG_DESC(kVmxVDiag_Ipe_11 , "Ipe_11" ),
50	VMXV_DIAG_DESC(kVmxVDiag_Ipe_12 , "Ipe_12" ),
51	VMXV_DIAG_DESC(kVmxVDiag_Ipe_13 , "Ipe_13" ),
52	VMXV_DIAG_DESC(kVmxVDiag_Ipe_14 , "Ipe_14" ),
53	VMXV_DIAG_DESC(kVmxVDiag_Ipe_15 , "Ipe_15" ),
54	VMXV_DIAG_DESC(kVmxVDiag_Ipe_16 , "Ipe_16" ),
55	/* VMXON. */
56	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_A20M , "A20M" ),
57	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cpl , "Cpl" ),
58	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed0 , "Cr0Fixed0" ),
59	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr0Fixed1 , "Cr0Fixed1" ),
60	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed0 , "Cr4Fixed0" ),
61	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Cr4Fixed1 , "Cr4Fixed1" ),
62	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Intercept , "Intercept" ),
63	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_LongModeCS , "LongModeCS" ),
64	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_MsrFeatCtl , "MsrFeatCtl" ),
65	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAbnormal , "PtrAbnormal" ),
66	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrAlign , "PtrAlign" ),
67	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrMap , "PtrMap" ),
68	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrReadPhys , "PtrReadPhys" ),
69	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_PtrWidth , "PtrWidth" ),
70	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_RealOrV86Mode , "RealOrV86Mode" ),
71	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_ShadowVmcs , "ShadowVmcs" ),
72	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxAlreadyRoot , "VmxAlreadyRoot" ),
73	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_Vmxe , "Vmxe" ),
74	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmcsRevId , "VmcsRevId" ),
75	VMXV_DIAG_DESC(kVmxVDiag_Vmxon_VmxRootCpl , "VmxRootCpl" ),
76	/* VMXOFF. */
77	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Cpl , "Cpl" ),
78	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Intercept , "Intercept" ),
79	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_LongModeCS , "LongModeCS" ),
80	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_RealOrV86Mode , "RealOrV86Mode" ),
81	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_Vmxe , "Vmxe" ),
82	VMXV_DIAG_DESC(kVmxVDiag_Vmxoff_VmxRoot , "VmxRoot" ),
83	/* VMPTRLD. */
84	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_Cpl , "Cpl" ),
85	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_LongModeCS , "LongModeCS" ),
86	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAbnormal , "PtrAbnormal" ),
87	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrAlign , "PtrAlign" ),
88	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrMap , "PtrMap" ),
89	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrReadPhys , "PtrReadPhys" ),
90	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrVmxon , "PtrVmxon" ),
91	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_PtrWidth , "PtrWidth" ),
92	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RealOrV86Mode , "RealOrV86Mode" ),
93	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_RevPtrReadPhys , "RevPtrReadPhys" ),
94	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_ShadowVmcs , "ShadowVmcs" ),
95	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmcsRevId , "VmcsRevId" ),
96	VMXV_DIAG_DESC(kVmxVDiag_Vmptrld_VmxRoot , "VmxRoot" ),
97	/* VMPTRST. */
98	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_Cpl , "Cpl" ),
99	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_LongModeCS , "LongModeCS" ),
100	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_PtrMap , "PtrMap" ),
101	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_RealOrV86Mode , "RealOrV86Mode" ),
102	VMXV_DIAG_DESC(kVmxVDiag_Vmptrst_VmxRoot , "VmxRoot" ),
103	/* VMCLEAR. */
104	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_Cpl , "Cpl" ),
105	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_LongModeCS , "LongModeCS" ),
106	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAbnormal , "PtrAbnormal" ),
107	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrAlign , "PtrAlign" ),
108	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrMap , "PtrMap" ),
109	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrReadPhys , "PtrReadPhys" ),
110	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrVmxon , "PtrVmxon" ),
111	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_PtrWidth , "PtrWidth" ),
112	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_RealOrV86Mode , "RealOrV86Mode" ),
113	VMXV_DIAG_DESC(kVmxVDiag_Vmclear_VmxRoot , "VmxRoot" ),
114	/* VMWRITE. */
115	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_Cpl , "Cpl" ),
116	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldInvalid , "FieldInvalid" ),
117	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_FieldRo , "FieldRo" ),
118	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LinkPtrInvalid , "LinkPtrInvalid" ),
119	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_LongModeCS , "LongModeCS" ),
120	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrInvalid , "PtrInvalid" ),
121	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_PtrMap , "PtrMap" ),
122	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_RealOrV86Mode , "RealOrV86Mode" ),
123	VMXV_DIAG_DESC(kVmxVDiag_Vmwrite_VmxRoot , "VmxRoot" ),
124	/* VMREAD. */
125	VMXV_DIAG_DESC(kVmxVDiag_Vmread_Cpl , "Cpl" ),
126	VMXV_DIAG_DESC(kVmxVDiag_Vmread_FieldInvalid , "FieldInvalid" ),
127	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LinkPtrInvalid , "LinkPtrInvalid" ),
128	VMXV_DIAG_DESC(kVmxVDiag_Vmread_LongModeCS , "LongModeCS" ),
129	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrInvalid , "PtrInvalid" ),
130	VMXV_DIAG_DESC(kVmxVDiag_Vmread_PtrMap , "PtrMap" ),
131	VMXV_DIAG_DESC(kVmxVDiag_Vmread_RealOrV86Mode , "RealOrV86Mode" ),
132	VMXV_DIAG_DESC(kVmxVDiag_Vmread_VmxRoot , "VmxRoot" ),
133	/* INVVPID. */
134	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Cpl , "Cpl" ),
135	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_DescRsvd , "DescRsvd" ),
136	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_LongModeCS , "LongModeCS" ),
137	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_RealOrV86Mode , "RealOrV86Mode" ),
138	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_TypeInvalid , "TypeInvalid" ),
139	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidAddr , "Type0InvalidAddr" ),
140	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type0InvalidVpid , "Type0InvalidVpid" ),
141	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type1InvalidVpid , "Type1InvalidVpid" ),
142	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_Type3InvalidVpid , "Type3InvalidVpid" ),
143	VMXV_DIAG_DESC(kVmxVDiag_Invvpid_VmxRoot , "VmxRoot" ),
144	/* VMLAUNCH/VMRESUME. */
145	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess , "AddrApicAccess" ),
146	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic" ),
147	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg" ),
148	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad , "AddrEntryMsrLoad" ),
149	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad , "AddrExitMsrLoad" ),
150	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrStore , "AddrExitMsrStore" ),
151	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapA , "AddrIoBitmapA" ),
152	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrIoBitmapB , "AddrIoBitmapB" ),
153	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrMsrBitmap , "AddrMsrBitmap" ),
154	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVirtApicPage , "AddrVirtApicPage" ),
155	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmcsLinkPtr , "AddrVmcsLinkPtr" ),
156	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmreadBitmap , "AddrVmreadBitmap" ),
157	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrVmwriteBitmap , "AddrVmwriteBitmap" ),
158	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ApicRegVirt , "ApicRegVirt" ),
159	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_BlocKMovSS , "BlockMovSS" ),
160	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cpl , "Cpl" ),
161	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Cr3TargetCount , "Cr3TargetCount" ),
162	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsAllowed1 , "EntryCtlsAllowed1" ),
163	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryCtlsDisallowed0 , "EntryCtlsDisallowed0" ),
164	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLen , "EntryInstrLen" ),
165	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryInstrLenZero , "EntryInstrLenZero" ),
166	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodePe , "EntryIntInfoErrCodePe" ),
167	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec , "EntryIntInfoErrCodeVec" ),
168	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd , "EntryIntInfoTypeVecRsvd" ),
169	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd , "EntryXcptErrCodeRsvd" ),
170	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsAllowed1 , "ExitCtlsAllowed1" ),
171	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ExitCtlsDisallowed0 , "ExitCtlsDisallowed0" ),
172	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateHlt , "GuestActStateHlt" ),
173	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateRsvd , "GuestActStateRsvd" ),
174	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateShutdown , "GuestActStateShutdown" ),
175	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateSsDpl , "GuestActStateSsDpl" ),
176	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestActStateStiMovSs , "GuestActStateStiMovSs" ),
177	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed0 , "GuestCr0Fixed0" ),
178	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0Fixed1 , "GuestCr0Fixed1" ),
179	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr0PgPe , "GuestCr0PgPe" ),
180	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr3 , "GuestCr3" ),
181	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed0 , "GuestCr4Fixed0" ),
182	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestCr4Fixed1 , "GuestCr4Fixed1" ),
183	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDebugCtl , "GuestDebugCtl" ),
184	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestDr7 , "GuestDr7" ),
185	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsr , "GuestEferMsr" ),
186	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestEferMsrRsvd , "GuestEferMsrRsvd" ),
187	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrBase , "GuestGdtrBase" ),
188	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestGdtrLimit , "GuestGdtrLimit" ),
189	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ),
190	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ),
191	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ),
192	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ),
193	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ),
194	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ),
195	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ),
196	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ),
197	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ),
198	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ),
199	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ),
200	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ),
201	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPcide , "GuestPcide" ),
202	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys , "GuestPdpteCr3ReadPhys" ),
203	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte0Rsvd , "GuestPdpte0Rsvd" ),
204	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte1Rsvd , "GuestPdpte1Rsvd" ),
205	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte2Rsvd , "GuestPdpte2Rsvd" ),
206	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPdpte3Rsvd , "GuestPdpte3Rsvd" ),
207	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf , "GuestPndDbgXcptBsNoTf" ),
208	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf , "GuestPndDbgXcptBsTf" ),
209	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd , "GuestPndDbgXcptRsvd" ),
210	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPndDbgXcptRtm , "GuestPndDbgXcptRtm" ),
211	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRip , "GuestRip" ),
212	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRipRsvd , "GuestRipRsvd" ),
213	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsIf , "GuestRFlagsIf" ),
214	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsRsvd , "GuestRFlagsRsvd" ),
215	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestRFlagsVm , "GuestRFlagsVm" ),
216	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDefBig , "GuestSegAttrCsDefBig" ),
217	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs , "GuestSegAttrCsDplEqSs" ),
218	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs , "GuestSegAttrCsDplLtSs" ),
219	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsDplZero , "GuestSegAttrCsDplZero" ),
220	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsType , "GuestSegAttrCsType" ),
221	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead , "GuestSegAttrCsTypeRead" ),
222	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs , "GuestSegAttrDescTypeCs" ),
223	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs , "GuestSegAttrDescTypeDs" ),
224	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs , "GuestSegAttrDescTypeEs" ),
225	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs , "GuestSegAttrDescTypeFs" ),
226	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs , "GuestSegAttrDescTypeGs" ),
227	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs , "GuestSegAttrDescTypeSs" ),
228	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplCs , "GuestSegAttrDplRplCs" ),
229	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplDs , "GuestSegAttrDplRplDs" ),
230	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplEs , "GuestSegAttrDplRplEs" ),
231	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplFs , "GuestSegAttrDplRplFs" ),
232	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplGs , "GuestSegAttrDplRplGs" ),
233	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrDplRplSs , "GuestSegAttrDplRplSs" ),
234	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranCs , "GuestSegAttrGranCs" ),
235	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranDs , "GuestSegAttrGranDs" ),
236	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranEs , "GuestSegAttrGranEs" ),
237	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranFs , "GuestSegAttrGranFs" ),
238	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranGs , "GuestSegAttrGranGs" ),
239	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrGranSs , "GuestSegAttrGranSs" ),
240	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType , "GuestSegAttrLdtrDescType" ),
241	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrGran , "GuestSegAttrLdtrGran" ),
242	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent , "GuestSegAttrLdtrPresent" ),
243	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd , "GuestSegAttrLdtrRsvd" ),
244	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrLdtrType , "GuestSegAttrLdtrType" ),
245	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentCs , "GuestSegAttrPresentCs" ),
246	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentDs , "GuestSegAttrPresentDs" ),
247	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentEs , "GuestSegAttrPresentEs" ),
248	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentFs , "GuestSegAttrPresentFs" ),
249	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentGs , "GuestSegAttrPresentGs" ),
250	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrPresentSs , "GuestSegAttrPresentSs" ),
251	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdCs , "GuestSegAttrRsvdCs" ),
252	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdDs , "GuestSegAttrRsvdDs" ),
253	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdEs , "GuestSegAttrRsvdEs" ),
254	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdFs , "GuestSegAttrRsvdFs" ),
255	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdGs , "GuestSegAttrRsvdGs" ),
256	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrRsvdSs , "GuestSegAttrRsvdSs" ),
257	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl , "GuestSegAttrSsDplEqRpl" ),
258	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsDplZero , "GuestSegAttrSsDplZero " ),
259	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrSsType , "GuestSegAttrSsType" ),
260	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrDescType , "GuestSegAttrTrDescType" ),
261	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrGran , "GuestSegAttrTrGran" ),
262	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrPresent , "GuestSegAttrTrPresent" ),
263	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrRsvd , "GuestSegAttrTrRsvd" ),
264	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrType , "GuestSegAttrTrType" ),
265	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTrUnusable , "GuestSegAttrTrUnusable" ),
266	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs , "GuestSegAttrTypeAccCs" ),
267	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs , "GuestSegAttrTypeAccDs" ),
268	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs , "GuestSegAttrTypeAccEs" ),
269	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs , "GuestSegAttrTypeAccFs" ),
270	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs , "GuestSegAttrTypeAccGs" ),
271	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs , "GuestSegAttrTypeAccSs" ),
272	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Cs , "GuestSegAttrV86Cs" ),
273	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ds , "GuestSegAttrV86Ds" ),
274	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Es , "GuestSegAttrV86Es" ),
275	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Fs , "GuestSegAttrV86Fs" ),
276	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Gs , "GuestSegAttrV86Gs" ),
277	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegAttrV86Ss , "GuestSegAttrV86Ss" ),
278	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseCs , "GuestSegBaseCs" ),
279	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseDs , "GuestSegBaseDs" ),
280	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseEs , "GuestSegBaseEs" ),
281	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseFs , "GuestSegBaseFs" ),
282	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseGs , "GuestSegBaseGs" ),
283	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseLdtr , "GuestSegBaseLdtr" ),
284	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseSs , "GuestSegBaseSs" ),
285	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseTr , "GuestSegBaseTr" ),
286	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Cs , "GuestSegBaseV86Cs" ),
287	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ds , "GuestSegBaseV86Ds" ),
288	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Es , "GuestSegBaseV86Es" ),
289	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Fs , "GuestSegBaseV86Fs" ),
290	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Gs , "GuestSegBaseV86Gs" ),
291	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegBaseV86Ss , "GuestSegBaseV86Ss" ),
292	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Cs , "GuestSegLimitV86Cs" ),
293	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ds , "GuestSegLimitV86Ds" ),
294	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Es , "GuestSegLimitV86Es" ),
295	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Fs , "GuestSegLimitV86Fs" ),
296	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Gs , "GuestSegLimitV86Gs" ),
297	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegLimitV86Ss , "GuestSegLimitV86Ss" ),
298	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelCsSsRpl , "GuestSegSelCsSsRpl" ),
299	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelLdtr , "GuestSegSelLdtr" ),
300	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSegSelTr , "GuestSegSelTr" ),
301	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestSysenterEspEip , "GuestSysenterEspEip" ),
302	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs , "VmcsLinkPtrCurVmcs" ),
303	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys , "VmcsLinkPtrReadPhys" ),
304	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrRevId , "VmcsLinkPtrRevId" ),
305	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLinkPtrShadow , "VmcsLinkPtrShadow" ),
306	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed0 , "HostCr0Fixed0" ),
307	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr0Fixed1 , "HostCr0Fixed1" ),
308	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr3 , "HostCr3" ),
309	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed0 , "HostCr4Fixed0" ),
310	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Fixed1 , "HostCr4Fixed1" ),
311	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pae , "HostCr4Pae" ),
312	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCr4Pcide , "HostCr4Pcide" ),
313	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostCsTr , "HostCsTr" ),
314	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsr , "HostEferMsr" ),
315	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostEferMsrRsvd , "HostEferMsrRsvd" ),
316	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongMode , "HostGuestLongMode" ),
317	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostGuestLongModeNoCpu , "HostGuestLongModeNoCpu" ),
318	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostLongMode , "HostLongMode" ),
319	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostPatMsr , "HostPatMsr" ),
320	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRip , "HostRip" ),
321	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostRipRsvd , "HostRipRsvd" ),
322	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSel , "HostSel" ),
323	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSegBase , "HostSegBase" ),
324	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSs , "HostSs" ),
325	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_HostSysenterEspEip , "HostSysenterEspEip" ),
326	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_LongModeCS , "LongModeCS" ),
327	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys , "MsrBitmapPtrReadPhys" ),
328	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoad , "MsrLoad" ),
329	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadCount , "MsrLoadCount" ),
330	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
331	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRing3 , "MsrLoadRing3" ),
332	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_MsrLoadRsvd , "MsrLoadRsvd" ),
333	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_NmiWindowExit , "NmiWindowExit" ),
334	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsAllowed1 , "PinCtlsAllowed1" ),
335	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PinCtlsDisallowed0 , "PinCtlsDisallowed0" ),
336	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsAllowed1 , "ProcCtlsAllowed1" ),
337	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtlsDisallowed0 , "ProcCtlsDisallowed0" ),
338	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Allowed1 , "ProcCtls2Allowed1" ),
339	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_ProcCtls2Disallowed0 , "ProcCtls2Disallowed0" ),
340	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrInvalid , "PtrInvalid" ),
341	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_PtrShadowVmcs , "PtrShadowVmcs" ),
342	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_RealOrV86Mode , "RealOrV86Mode" ),
343	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ),
344	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ),
345	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ),
346	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ),
347	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtIntDelivery , "VirtIntDelivery" ),
348	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtNmi , "VirtNmi" ),
349	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicTprShadow , "VirtX2ApicTprShadow" ),
350	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtX2ApicVirtApic , "VirtX2ApicVirtApic" ),
351	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsClear , "VmcsClear" ),
352	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmcsLaunch , "VmcsLaunch" ),
353	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys , "VmreadBitmapPtrReadPhys" ),
354	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys , "VmwriteBitmapPtrReadPhys" ),
355	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VmxRoot , "VmxRoot" ),
356	VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Vpid , "Vpid" ),
357	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys , "HostPdpteCr3ReadPhys" ),
358	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte0Rsvd , "HostPdpte0Rsvd" ),
359	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte1Rsvd , "HostPdpte1Rsvd" ),
360	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte2Rsvd , "HostPdpte2Rsvd" ),
361	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_HostPdpte3Rsvd , "HostPdpte3Rsvd" ),
362	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoad , "MsrLoad" ),
363	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadCount , "MsrLoadCount" ),
364	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadPtrReadPhys , "MsrLoadPtrReadPhys" ),
365	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRing3 , "MsrLoadRing3" ),
366	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrLoadRsvd , "MsrLoadRsvd" ),
367	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStore , "MsrStore" ),
368	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreCount , "MsrStoreCount" ),
369	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrReadPhys , "MsrStorePtrReadPhys" ),
370	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStorePtrWritePhys , "MsrStorePtrWritePhys" ),
371	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRing3 , "MsrStoreRing3" ),
372	VMXV_DIAG_DESC(kVmxVDiag_Vmexit_MsrStoreRsvd , "MsrStoreRsvd" )
373	/* kVmxVDiag_End */
374	};
375	AssertCompile(RT_ELEMENTS(g_apszVmxVDiagDesc) == kVmxVDiag_End);
376	#undef VMXV_DIAG_DESC
377
378
379	/**
380	* Gets the descriptive name of a VMX instruction/VM-exit diagnostic code.
381	*
382	* @returns The descriptive string.
383	* @param enmDiag The VMX diagnostic.
384	*/
385	VMM_INT_DECL(const char *) HMGetVmxDiagDesc(VMXVDIAG enmDiag)
386	{
387	if (RT_LIKELY((unsigned)enmDiag < RT_ELEMENTS(g_apszVmxVDiagDesc)))
388	return g_apszVmxVDiagDesc[enmDiag];
389	return "Unknown/invalid";
390	}
391
392
393	/**
394	* Gets the description for a VMX abort reason.
395	*
396	* @returns The descriptive string.
397	* @param enmAbort The VMX abort reason.
398	*/
399	VMM_INT_DECL(const char *) HMGetVmxAbortDesc(VMXABORT enmAbort)
400	{
401	switch (enmAbort)
402	{
403	case VMXABORT_NONE: return "VMXABORT_NONE";
404	case VMXABORT_SAVE_GUEST_MSRS: return "VMXABORT_SAVE_GUEST_MSRS";
405	case VMXBOART_HOST_PDPTE: return "VMXBOART_HOST_PDPTE";
406	case VMXABORT_CURRENT_VMCS_CORRUPT: return "VMXABORT_CURRENT_VMCS_CORRUPT";
407	case VMXABORT_LOAD_HOST_MSR: return "VMXABORT_LOAD_HOST_MSR";
408	case VMXABORT_MACHINE_CHECK_XCPT: return "VMXABORT_MACHINE_CHECK_XCPT";
409	case VMXABORT_HOST_NOT_IN_LONG_MODE: return "VMXABORT_HOST_NOT_IN_LONG_MODE";
410	default:
411	break;
412	}
413	return "Unknown/invalid";
414	}
415
416
417	/**
418	* Gets the description for a virtual VMCS state.
419	*
420	* @returns The descriptive string.
421	* @param fVmcsState The virtual-VMCS state.
422	*/
423	VMM_INT_DECL(const char *) HMGetVmxVmcsStateDesc(uint8_t fVmcsState)
424	{
425	switch (fVmcsState)
426	{
427	case VMX_V_VMCS_LAUNCH_STATE_CLEAR: return "Clear";
428	case VMX_V_VMCS_LAUNCH_STATE_LAUNCHED: return "Launched";
429	default: return "Unknown";
430	}
431	}
432
433
434	/**
435	* Gets the description for a VM-entry interruption information event type.
436	*
437	* @returns The descriptive string.
438	* @param uType The event type.
439	*/
440	VMM_INT_DECL(const char *) HMGetVmxEntryIntInfoTypeDesc(uint8_t uType)
441	{
442	switch (uType)
443	{
444	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
445	case VMX_ENTRY_INT_INFO_TYPE_NMI: return "NMI";
446	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
447	case VMX_ENTRY_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
448	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
449	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
450	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: return "Other Event";
451	default:
452	break;
453	}
454	return "Unknown/invalid";
455	}
456
457
458	/**
459	* Gets the description for a VM-exit interruption information event type.
460	*
461	* @returns The descriptive string.
462	* @param uType The event type.
463	*/
464	VMM_INT_DECL(const char *) HMGetVmxExitIntInfoTypeDesc(uint8_t uType)
465	{
466	switch (uType)
467	{
468	case VMX_EXIT_INT_INFO_TYPE_EXT_INT: return "External Interrupt";
469	case VMX_EXIT_INT_INFO_TYPE_NMI: return "NMI";
470	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT: return "Hardware Exception";
471	case VMX_EXIT_INT_INFO_TYPE_SW_INT: return "Software Interrupt";
472	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
473	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: return "Software Exception";
474	default:
475	break;
476	}
477	return "Unknown/invalid";
478	}
479
480
481	/**
482	* Gets the description for an IDT-vectoring information event type.
483	*
484	* @returns The descriptive string.
485	* @param uType The event type.
486	*/
487	VMM_INT_DECL(const char *) HMGetVmxIdtVectoringInfoTypeDesc(uint8_t uType)
488	{
489	switch (uType)
490	{
491	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT: return "External Interrupt";
492	case VMX_IDT_VECTORING_INFO_TYPE_NMI: return "NMI";
493	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT: return "Hardware Exception";
494	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT: return "Software Interrupt";
495	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT: return "Priv. Software Exception";
496	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: return "Software Exception";
497	default:
498	break;
499	}
500	return "Unknown/invalid";
501	}
502
503
504	/**
505	* Checks if a code selector (CS) is suitable for execution using hardware-assisted
506	* VMX when unrestricted execution isn't available.
507	*
508	* @returns true if selector is suitable for VMX, otherwise
509	* false.
510	* @param pSel Pointer to the selector to check (CS).
511	* @param uStackDpl The CPL, aka the DPL of the stack segment.
512	*/
513	static bool hmVmxIsCodeSelectorOk(PCCPUMSELREG pSel, unsigned uStackDpl)
514	{
515	/*
516	* Segment must be an accessed code segment, it must be present and it must
517	* be usable.
518	* Note! These are all standard requirements and if CS holds anything else
519	* we've got buggy code somewhere!
520	*/
521	AssertCompile(X86DESCATTR_TYPE == 0xf);
522	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
523	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
524	("%#x\n", pSel->Attr.u),
525	false);
526
527	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
528	must equal SS.DPL for non-confroming segments.
529	Note! This is also a hard requirement like above. */
530	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
531	? pSel->Attr.n.u2Dpl <= uStackDpl
532	: pSel->Attr.n.u2Dpl == uStackDpl,
533	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
534	false);
535
536	/*
537	* The following two requirements are VT-x specific:
538	* - G bit must be set if any high limit bits are set.
539	* - G bit must be clear if any low limit bits are clear.
540	*/
541	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
542	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
543	return true;
544	return false;
545	}
546
547
548	/**
549	* Checks if a data selector (DS/ES/FS/GS) is suitable for execution using
550	* hardware-assisted VMX when unrestricted execution isn't available.
551	*
552	* @returns true if selector is suitable for VMX, otherwise
553	* false.
554	* @param pSel Pointer to the selector to check
555	* (DS/ES/FS/GS).
556	*/
557	static bool hmVmxIsDataSelectorOk(PCCPUMSELREG pSel)
558	{
559	/*
560	* Unusable segments are OK. These days they should be marked as such, as
561	* but as an alternative we for old saved states and AMD<->VT-x migration
562	* we also treat segments with all the attributes cleared as unusable.
563	*/
564	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
565	return true;
566
567	/** @todo tighten these checks. Will require CPUM load adjusting. */
568
569	/* Segment must be accessed. */
570	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
571	{
572	/* Code segments must also be readable. */
573	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
574	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
575	{
576	/* The S bit must be set. */
577	if (pSel->Attr.n.u1DescType)
578	{
579	/* Except for conforming segments, DPL >= RPL. */
580	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
581	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
582	{
583	/* Segment must be present. */
584	if (pSel->Attr.n.u1Present)
585	{
586	/*
587	* The following two requirements are VT-x specific:
588	* - G bit must be set if any high limit bits are set.
589	* - G bit must be clear if any low limit bits are clear.
590	*/
591	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
592	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
593	return true;
594	}
595	}
596	}
597	}
598	}
599
600	return false;
601	}
602
603
604	/**
605	* Checks if the stack selector (SS) is suitable for execution using
606	* hardware-assisted VMX when unrestricted execution isn't available.
607	*
608	* @returns true if selector is suitable for VMX, otherwise
609	* false.
610	* @param pSel Pointer to the selector to check (SS).
611	*/
612	static bool hmVmxIsStackSelectorOk(PCCPUMSELREG pSel)
613	{
614	/*
615	* Unusable segments are OK. These days they should be marked as such, as
616	* but as an alternative we for old saved states and AMD<->VT-x migration
617	* we also treat segments with all the attributes cleared as unusable.
618	*/
619	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
620	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
621	return true;
622
623	/*
624	* Segment must be an accessed writable segment, it must be present.
625	* Note! These are all standard requirements and if SS holds anything else
626	* we've got buggy code somewhere!
627	*/
628	AssertCompile(X86DESCATTR_TYPE == 0xf);
629	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
630	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
631	("%#x\n", pSel->Attr.u), false);
632
633	/*
634	* DPL must equal RPL. But in real mode or soon after enabling protected
635	* mode, it might not be.
636	*/
637	if (pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL))
638	{
639	/*
640	* The following two requirements are VT-x specific:
641	* - G bit must be set if any high limit bits are set.
642	* - G bit must be clear if any low limit bits are clear.
643	*/
644	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
645	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity))
646	return true;
647	}
648	return false;
649	}
650
651
652	/**
653	* Checks if the guest is in a suitable state for hardware-assisted VMX execution.
654	*
655	* @returns @c true if it is suitable, @c false otherwise.
656	* @param pVCpu The cross context virtual CPU structure.
657	* @param pCtx Pointer to the guest CPU context.
658	*
659	* @remarks @a pCtx can be a partial context and thus may not be necessarily the
660	* same as pVCpu->cpum.GstCtx! Thus don't eliminate the @a pCtx parameter.
661	* Secondly, if additional checks are added that require more of the CPU
662	* state, make sure REM (which supplies a partial state) is updated.
663	*/
664	VMM_INT_DECL(bool) HMCanExecuteVmxGuest(PVMCPU pVCpu, PCCPUMCTX pCtx)
665	{
666	PVM pVM = pVCpu->CTX_SUFF(pVM);
667	Assert(HMIsEnabled(pVM));
668	Assert( ( pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
669	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
670
671	pVCpu->hm.s.fActive = false;
672
673	bool const fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
674	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
675	{
676	/*
677	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
678	* guest execution feature is missing (VT-x only).
679	*/
680	if (fSupportsRealMode)
681	{
682	if (CPUMIsGuestInRealModeEx(pCtx))
683	{
684	/*
685	* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
686	* bases, limits, and attributes, i.e. limit must be 64K, base must be selector * 16,
687	* and attributes must be 0x9b for code and 0x93 for code segments.
688	* If this is not true, we cannot execute real mode as V86 and have to fall
689	* back to emulation.
690	*/
691	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
692	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
693	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
694	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
695	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
696	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
697	{
698	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
699	return false;
700	}
701	if ( (pCtx->cs.u32Limit != 0xffff)
702	\|\| (pCtx->ds.u32Limit != 0xffff)
703	\|\| (pCtx->es.u32Limit != 0xffff)
704	\|\| (pCtx->ss.u32Limit != 0xffff)
705	\|\| (pCtx->fs.u32Limit != 0xffff)
706	\|\| (pCtx->gs.u32Limit != 0xffff))
707	{
708	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
709	return false;
710	}
711	if ( (pCtx->cs.Attr.u != 0x9b)
712	\|\| (pCtx->ds.Attr.u != 0x93)
713	\|\| (pCtx->es.Attr.u != 0x93)
714	\|\| (pCtx->ss.Attr.u != 0x93)
715	\|\| (pCtx->fs.Attr.u != 0x93)
716	\|\| (pCtx->gs.Attr.u != 0x93))
717	{
718	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr);
719	return false;
720	}
721	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
722	}
723	else
724	{
725	/*
726	* Verify the requirements for executing code in protected mode. VT-x can't
727	* handle the CPU state right after a switch from real to protected mode
728	* (all sorts of RPL & DPL assumptions).
729	*/
730	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
731	if (pVmcsInfo->fWasInRealMode)
732	{
733	if (!CPUMIsGuestInV86ModeEx(pCtx))
734	{
735	/* The guest switched to protected mode, check if the state is suitable for VT-x. */
736	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
737	{
738	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
739	return false;
740	}
741	if ( !hmVmxIsCodeSelectorOk(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
742	\|\| !hmVmxIsDataSelectorOk(&pCtx->ds)
743	\|\| !hmVmxIsDataSelectorOk(&pCtx->es)
744	\|\| !hmVmxIsDataSelectorOk(&pCtx->fs)
745	\|\| !hmVmxIsDataSelectorOk(&pCtx->gs)
746	\|\| !hmVmxIsStackSelectorOk(&pCtx->ss))
747	{
748	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
749	return false;
750	}
751	}
752	else
753	{
754	/* The guest switched to V86 mode, check if the state is suitable for VT-x. */
755	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
756	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
757	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
758	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
759	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
760	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
761	{
762	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelBase);
763	return false;
764	}
765	if ( (pCtx->cs.u32Limit != 0xffff)
766	\|\| (pCtx->ds.u32Limit != 0xffff)
767	\|\| (pCtx->es.u32Limit != 0xffff)
768	\|\| (pCtx->ss.u32Limit != 0xffff)
769	\|\| (pCtx->fs.u32Limit != 0xffff)
770	\|\| (pCtx->gs.u32Limit != 0xffff))
771	{
772	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit);
773	return false;
774	}
775	if ( (pCtx->cs.Attr.u != 0xf3)
776	\|\| (pCtx->ds.Attr.u != 0xf3)
777	\|\| (pCtx->es.Attr.u != 0xf3)
778	\|\| (pCtx->ss.Attr.u != 0xf3)
779	\|\| (pCtx->fs.Attr.u != 0xf3)
780	\|\| (pCtx->gs.Attr.u != 0xf3))
781	{
782	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr);
783	return false;
784	}
785	}
786	}
787	}
788	}
789	else
790	{
791	if (!CPUMIsGuestInLongModeEx(pCtx))
792	{
793	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
794	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
795	return false;
796
797	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
798	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
799	return false;
800
801	/*
802	* The guest is about to complete the switch to protected mode. Wait a bit longer.
803	* Windows XP; switch to protected mode; all selectors are marked not present
804	* in the hidden registers (possible recompiler bug; see load_seg_vm).
805	*/
806	/** @todo Is this supposed recompiler bug still relevant with IEM? */
807	if (pCtx->cs.Attr.n.u1Present == 0)
808	return false;
809	if (pCtx->ss.Attr.n.u1Present == 0)
810	return false;
811
812	/*
813	* Windows XP: possible same as above, but new recompiler requires new
814	* heuristics? VT-x doesn't seem to like something about the guest state and
815	* this stuff avoids it.
816	*/
817	/** @todo This check is actually wrong, it doesn't take the direction of the
818	* stack segment into account. But, it does the job for now. */
819	if (pCtx->rsp >= pCtx->ss.u32Limit)
820	return false;
821	}
822	}
823	}
824
825	if (pVM->hm.s.vmx.fEnabled)
826	{
827	uint32_t uCr0Mask;
828
829	/* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
830	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
831
832	/* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
833	uCr0Mask &= ~X86_CR0_NE;
834
835	if (fSupportsRealMode)
836	{
837	/* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
838	uCr0Mask &= ~(X86_CR0_PG \| X86_CR0_PE);
839	}
840	else
841	{
842	/* We support protected mode without paging using identity mapping. */
843	uCr0Mask &= ~X86_CR0_PG;
844	}
845	if ((pCtx->cr0 & uCr0Mask) != uCr0Mask)
846	return false;
847
848	/* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
849	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
850	if ((pCtx->cr0 & uCr0Mask) != 0)
851	return false;
852
853	/* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
854	uCr0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
855	uCr0Mask &= ~X86_CR4_VMXE;
856	if ((pCtx->cr4 & uCr0Mask) != uCr0Mask)
857	return false;
858
859	/* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
860	uCr0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
861	if ((pCtx->cr4 & uCr0Mask) != 0)
862	return false;
863
864	pVCpu->hm.s.fActive = true;
865	return true;
866	}
867
868	return false;
869	}
870
871
872	/**
873	* Dumps the virtual VMCS state to the release log.
874	*
875	* @param pVCpu The cross context virtual CPU structure.
876	*/
877	VMM_INT_DECL(void) HMDumpHwvirtVmxState(PVMCPU pVCpu)
878	{
879	#ifndef IN_RC
880	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
881	# define HMVMX_DUMP_HOST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
882	do { \
883	LogRel((" %s%-4s = {base=%016RX64}\n", \
884	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u)); \
885	} while (0)
886	# define HMVMX_DUMP_HOST_FS_GS_TR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
887	do { \
888	LogRel((" %s%-4s = {%04x base=%016RX64}\n", \
889	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u)); \
890	} while (0)
891	# define HMVMX_DUMP_GUEST_SEGREG(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
892	do { \
893	LogRel((" %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
894	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
895	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr)); \
896	} while (0)
897	# define HMVMX_DUMP_GUEST_XDTR(a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
898	do { \
899	LogRel((" %s%-4s = {base=%016RX64 limit=%08x}\n", \
900	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit)); \
901	} while (0)
902
903	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
904	PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
905	if (!pVmcs)
906	{
907	LogRel(("Virtual VMCS not allocated\n"));
908	return;
909	}
910	LogRel(("GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon));
911	LogRel(("GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs));
912	LogRel(("GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs));
913	LogRel(("enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag)));
914	LogRel(("enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMGetVmxAbortDesc(pCtx->hwvirt.vmx.enmAbort)));
915	LogRel(("uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux));
916	LogRel(("fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode));
917	LogRel(("fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode));
918	LogRel(("fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents));
919	LogRel(("fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret));
920	LogRel(("uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick));
921	LogRel(("uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick));
922	LogRel(("uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick));
923	LogRel(("offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite));
924	LogRel(("fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking));
925	LogRel(("VMCS cache:\n"));
926
927	const char *pszPrefix = " ";
928	/* Header. */
929	{
930	LogRel(("%sHeader:\n", pszPrefix));
931	LogRel((" %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId));
932	LogRel((" %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, HMGetVmxAbortDesc(pVmcs->enmVmxAbort)));
933	LogRel((" %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, HMGetVmxVmcsStateDesc(pVmcs->fVmcsState)));
934	}
935
936	/* Control fields. */
937	{
938	/* 16-bit. */
939	LogRel(("%sControl:\n", pszPrefix));
940	LogRel((" %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid));
941	LogRel((" %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector));
942	LogRel((" %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex));
943
944	/* 32-bit. */
945	LogRel((" %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls));
946	LogRel((" %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls));
947	LogRel((" %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2));
948	LogRel((" %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls));
949	LogRel((" %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls));
950	LogRel((" %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap));
951	LogRel((" %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask));
952	LogRel((" %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch));
953	LogRel((" %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount));
954	LogRel((" %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount));
955	LogRel((" %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount));
956	LogRel((" %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount));
957	LogRel((" %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo));
958	{
959	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
960	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
961	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo)));
962	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxEntryIntInfoTypeDesc(uType)));
963	LogRel((" %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo)));
964	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
965	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
966	}
967	LogRel((" %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode));
968	LogRel((" %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen));
969	LogRel((" %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold));
970	LogRel((" %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap));
971	LogRel((" %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow));
972
973	/* 64-bit. */
974	LogRel((" %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u));
975	LogRel((" %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u));
976	LogRel((" %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u));
977	LogRel((" %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u));
978	LogRel((" %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u));
979	LogRel((" %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u));
980	LogRel((" %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u));
981	LogRel((" %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u));
982	LogRel((" %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u));
983	LogRel((" %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u));
984	LogRel((" %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u));
985	LogRel((" %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u));
986	LogRel((" %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u));
987	LogRel((" %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u));
988	LogRel((" %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u));
989	LogRel((" %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u));
990	LogRel((" %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u));
991	LogRel((" %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u));
992	LogRel((" %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u));
993	LogRel((" %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u));
994	LogRel((" %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u));
995	LogRel((" %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u));
996	LogRel((" %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u));
997	LogRel((" %sENCLS-exiting bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEnclsBitmap.u));
998	LogRel((" %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u));
999
1000	/* Natural width. */
1001	LogRel((" %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u));
1002	LogRel((" %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u));
1003	LogRel((" %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u));
1004	LogRel((" %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u));
1005	LogRel((" %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u));
1006	LogRel((" %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u));
1007	LogRel((" %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u));
1008	LogRel((" %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u));
1009	}
1010
1011	/* Guest state. */
1012	{
1013	LogRel(("%sGuest state:\n", pszPrefix));
1014
1015	/* 16-bit. */
1016	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Cs, "cs", pszPrefix);
1017	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ss, "ss", pszPrefix);
1018	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Es, "es", pszPrefix);
1019	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ds, "ds", pszPrefix);
1020	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Fs, "fs", pszPrefix);
1021	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Gs, "gs", pszPrefix);
1022	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Ldtr, "ldtr", pszPrefix);
1023	HMVMX_DUMP_GUEST_SEGREG(pVmcs, Tr, "tr", pszPrefix);
1024	HMVMX_DUMP_GUEST_XDTR( pVmcs, Gdtr, "gdtr", pszPrefix);
1025	HMVMX_DUMP_GUEST_XDTR( pVmcs, Idtr, "idtr", pszPrefix);
1026	LogRel((" %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus));
1027	LogRel((" %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex));
1028
1029	/* 32-bit. */
1030	LogRel((" %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState));
1031	LogRel((" %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState));
1032	LogRel((" %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase));
1033	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS));
1034	LogRel((" %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer));
1035
1036	/* 64-bit. */
1037	LogRel((" %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u));
1038	LogRel((" %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u));
1039	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u));
1040	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u));
1041	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u));
1042	LogRel((" %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u));
1043	LogRel((" %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u));
1044	LogRel((" %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u));
1045	LogRel((" %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u));
1046	LogRel((" %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u));
1047
1048	/* Natural width. */
1049	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u));
1050	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u));
1051	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u));
1052	LogRel((" %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u));
1053	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u));
1054	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u));
1055	LogRel((" %srflags = %#RX64\n", pszPrefix, pVmcs->u64GuestRFlags.u));
1056	LogRel((" %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpt.u));
1057	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u));
1058	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u));
1059	}
1060
1061	/* Host state. */
1062	{
1063	LogRel(("%sHost state:\n", pszPrefix));
1064
1065	/* 16-bit. */
1066	LogRel((" %scs = %#RX16\n", pszPrefix, pVmcs->HostCs));
1067	LogRel((" %sss = %#RX16\n", pszPrefix, pVmcs->HostSs));
1068	LogRel((" %sds = %#RX16\n", pszPrefix, pVmcs->HostDs));
1069	LogRel((" %ses = %#RX16\n", pszPrefix, pVmcs->HostEs));
1070	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Fs, "fs", pszPrefix);
1071	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Gs, "gs", pszPrefix);
1072	HMVMX_DUMP_HOST_FS_GS_TR(pVmcs, Tr, "tr", pszPrefix);
1073	HMVMX_DUMP_HOST_XDTR(pVmcs, Gdtr, "gdtr", pszPrefix);
1074	HMVMX_DUMP_HOST_XDTR(pVmcs, Idtr, "idtr", pszPrefix);
1075
1076	/* 32-bit. */
1077	LogRel((" %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs));
1078
1079	/* 64-bit. */
1080	LogRel((" %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u));
1081	LogRel((" %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u));
1082	LogRel((" %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u));
1083
1084	/* Natural width. */
1085	LogRel((" %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u));
1086	LogRel((" %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u));
1087	LogRel((" %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u));
1088	LogRel((" %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u));
1089	LogRel((" %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u));
1090	LogRel((" %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u));
1091	LogRel((" %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u));
1092	}
1093
1094	/* Read-only fields. */
1095	{
1096	LogRel(("%sRead-only data fields:\n", pszPrefix));
1097
1098	/* 16-bit (none currently). */
1099
1100	/* 32-bit. */
1101	uint32_t const uExitReason = pVmcs->u32RoExitReason;
1102	LogRel((" %sExit reason = %u (%s)\n", pszPrefix, uExitReason, HMGetVmxExitName(uExitReason)));
1103	LogRel((" %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u));
1104	LogRel((" %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError));
1105	LogRel((" %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo));
1106	{
1107	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
1108	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
1109	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo)));
1110	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxExitIntInfoTypeDesc(uType)));
1111	LogRel((" %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo)));
1112	LogRel((" %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo)));
1113	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo)));
1114	}
1115	LogRel((" %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode));
1116	LogRel((" %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo));
1117	{
1118	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
1119	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
1120	LogRel((" %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo)));
1121	LogRel((" %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxIdtVectoringInfoTypeDesc(uType)));
1122	LogRel((" %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo)));
1123	LogRel((" %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo)));
1124	}
1125	LogRel((" %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode));
1126	LogRel((" %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen));
1127	LogRel((" %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo));
1128
1129	/* 64-bit. */
1130	LogRel((" %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u));
1131
1132	/* Natural width. */
1133	LogRel((" %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u));
1134	LogRel((" %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u));
1135	LogRel((" %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u));
1136	LogRel((" %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u));
1137	LogRel((" %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u));
1138	}
1139
1140	# undef HMVMX_DUMP_HOST_XDTR
1141	# undef HMVMX_DUMP_HOST_FS_GS_TR
1142	# undef HMVMX_DUMP_GUEST_SEGREG
1143	# undef HMVMX_DUMP_GUEST_XDTR
1144	#else
1145	NOREF(pVCpu);
1146	#endif /* !IN_RC */
1147	}
1148
1149
1150	/**
1151	* Gets the active (in use) VMCS info. object for the specified VCPU.
1152	*
1153	* This is either the guest or nested-guest VMCS and need not necessarily pertain to
1154	* the "current" VMCS (in the VMX definition of the term). For instance, if the
1155	* VM-entry failed due to an invalid-guest state, we may have "cleared" the VMCS
1156	* while returning to ring-3. The VMCS info. object for that VMCS would still be
1157	* active and returned so that we could dump the VMCS fields to ring-3 for
1158	* diagnostics. This function is thus only used to distinguish between the
1159	* nested-guest or guest VMCS.
1160	*
1161	* @returns The active VMCS information.
1162	* @param pVCpu The cross context virtual CPU structure.
1163	*
1164	* @thread EMT.
1165	* @remarks This function may be called with preemption or interrupts disabled!
1166	*/
1167	VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu)
1168	{
1169	if (!pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs)
1170	return &pVCpu->hm.s.vmx.VmcsInfo;
1171	return &pVCpu->hm.s.vmx.VmcsInfoNstGst;
1172	}
1173
1174
1175	/**
1176	* Converts a VMX event type into an appropriate TRPM event type.
1177	*
1178	* @returns TRPM event.
1179	* @param uIntInfo The VMX event.
1180	*/
1181	VMM_INT_DECL(TRPMEVENT) HMVmxEventToTrpmEventType(uint32_t uIntInfo)
1182	{
1183	TRPMEVENT enmTrapType;
1184	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uIntInfo);
1185	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(uIntInfo);
1186
1187	switch (uType)
1188	{
1189	case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
1190	enmTrapType = TRPM_HARDWARE_INT;
1191	break;
1192
1193	case VMX_ENTRY_INT_INFO_TYPE_NMI:
1194	case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
1195	enmTrapType = TRPM_TRAP;
1196	break;
1197
1198	case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT: /* INT1 (ICEBP). */
1199	Assert(uVector == X86_XCPT_DB); NOREF(uVector);
1200	enmTrapType = TRPM_SOFTWARE_INT;
1201	break;
1202
1203	case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT: /* INT3 (#BP) and INTO (#OF) */
1204	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF); NOREF(uVector);
1205	enmTrapType = TRPM_SOFTWARE_INT;
1206	break;
1207
1208	case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
1209	enmTrapType = TRPM_SOFTWARE_INT;
1210	break;
1211
1212	case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT: /* Shouldn't really happen. */
1213	default:
1214	AssertMsgFailed(("Invalid trap type %#x\n", uType));
1215	enmTrapType = TRPM_32BIT_HACK;
1216	break;
1217	}
1218
1219	return enmTrapType;
1220	}
1221
1222
1223	#ifndef IN_RC
1224	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1225	/**
1226	* Notification callback for when a VM-exit happens outside VMX R0 code (e.g. in
1227	* IEM).
1228	*
1229	* @param pVCpu The cross context virtual CPU structure.
1230	* @param pCtx Pointer to the guest-CPU context.
1231	*
1232	* @remarks Can be called from ring-0 as well as ring-3.
1233	*/
1234	VMM_INT_DECL(void) HMNotifyVmxNstGstVmexit(PVMCPU pVCpu, PCPUMCTX pCtx)
1235	{
1236	NOREF(pCtx);
1237
1238	/*
1239	* Make sure we need to merge the nested-guest VMCS on next nested-guest
1240	* VM entry (if we VM-exit in ring-0 and continue in ring-0 till the next
1241	* nested-guest VM-entry).
1242	*/
1243	pVCpu->hm.s.vmx.fMergedNstGstCtls = false;
1244
1245	CPUMImportGuestStateOnDemand(pVCpu, CPUMCTX_EXTRN_ALL);
1246	AssertMsg(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL),
1247	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", pVCpu->cpum.GstCtx.fExtrn, CPUMCTX_EXTRN_ALL));
1248	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
1249
1250
1251	}
1252	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
1253	#endif /* IN_RC */
1254

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source: vbox/trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp@ 78591

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