VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/HWACCMAll.cpp@ 28875

Last change on this file since 28875 was 28800, checked in by vboxsync, 15 years ago

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1/* $Id: HWACCMAll.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * HWACCM - All contexts.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <VBox/hwaccm.h>
24#include <VBox/pgm.h>
25#include "HWACCMInternal.h"
26#include <VBox/vm.h>
27#include <VBox/x86.h>
28#include <VBox/hwacc_vmx.h>
29#include <VBox/hwacc_svm.h>
30#include <VBox/err.h>
31#include <VBox/log.h>
32#include <iprt/param.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35#include <iprt/string.h>
36
37/**
38 * Queues a page for invalidation
39 *
40 * @returns VBox status code.
41 * @param pVCpu The VMCPU to operate on.
42 * @param GCVirt Page to invalidate
43 */
44void hwaccmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
45{
46 /* Nothing to do if a TLB flush is already pending */
47 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
48 return;
49#if 1
50 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
51#else
52 Be very careful when activating this code!
53 if (iPage == RT_ELEMENTS(pVCpu->hwaccm.s.TlbShootdown.aPages))
54 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
55 else
56 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
57#endif
58}
59
60/**
61 * Invalidates a guest page
62 *
63 * @returns VBox status code.
64 * @param pVCpu The VMCPU to operate on.
65 * @param GCVirt Page to invalidate
66 */
67VMMDECL(int) HWACCMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
68{
69 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
70#ifdef IN_RING0
71 PVM pVM = pVCpu->CTX_SUFF(pVM);
72 if (pVM->hwaccm.s.vmx.fSupported)
73 return VMXR0InvalidatePage(pVM, pVCpu, GCVirt);
74
75 Assert(pVM->hwaccm.s.svm.fSupported);
76 return SVMR0InvalidatePage(pVM, pVCpu, GCVirt);
77#endif
78
79 hwaccmQueueInvlPage(pVCpu, GCVirt);
80 return VINF_SUCCESS;
81}
82
83/**
84 * Flushes the guest TLB
85 *
86 * @returns VBox status code.
87 * @param pVCpu The VMCPU to operate on.
88 */
89VMMDECL(int) HWACCMFlushTLB(PVMCPU pVCpu)
90{
91 LogFlow(("HWACCMFlushTLB\n"));
92
93 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
94 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBManual);
95 return VINF_SUCCESS;
96}
97
98#ifdef IN_RING0
99/**
100 * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
101 *
102 */
103static DECLCALLBACK(void) hwaccmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
104{
105 return;
106}
107
108/**
109 * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED
110 *
111 */
112void hwaccmMpPokeCpu(PVMCPU pVCpu, RTCPUID idHostCpu)
113{
114 uint32_t cWorldSwitchExit = pVCpu->hwaccm.s.cWorldSwitchExit;
115
116 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatPoke, x);
117 int rc = RTMpPokeCpu(idHostCpu);
118 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatPoke, x);
119 /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall back to a less efficient implementation (broadcast). */
120 if (rc == VERR_NOT_SUPPORTED)
121 {
122 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatSpinPoke, z);
123 /* synchronous. */
124 RTMpOnSpecific(idHostCpu, hwaccmFlushHandler, 0, 0);
125 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatSpinPoke, z);
126 }
127 else
128 {
129 if (rc == VINF_SUCCESS)
130 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatSpinPoke, z);
131 else
132 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatSpinPokeFailed, z);
133
134 /* Spin until the VCPU has switched back. */
135 while ( pVCpu->hwaccm.s.fCheckedTLBFlush
136 && cWorldSwitchExit == pVCpu->hwaccm.s.cWorldSwitchExit)
137 {
138 ASMNopPause();
139 }
140 if (rc == VINF_SUCCESS)
141 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatSpinPoke, z);
142 else
143 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatSpinPokeFailed, z);
144 }
145}
146#endif
147
148#ifndef IN_RC
149/**
150 * Invalidates a guest page on all VCPUs.
151 *
152 * @returns VBox status code.
153 * @param pVM The VM to operate on.
154 * @param GCVirt Page to invalidate
155 */
156VMMDECL(int) HWACCMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCPtr)
157{
158 VMCPUID idCurCpu = VMMGetCpuId(pVM);
159
160 STAM_COUNTER_INC(&pVM->aCpus[idCurCpu].hwaccm.s.StatFlushPage);
161
162 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
163 {
164 PVMCPU pVCpu = &pVM->aCpus[idCpu];
165
166 /* Nothing to do if a TLB flush is already pending; the VCPU should have already been poked if it were active */
167 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
168 continue;
169
170 if (pVCpu->idCpu == idCurCpu)
171 {
172 HWACCMInvalidatePage(pVCpu, GCPtr);
173 }
174 else
175 {
176 hwaccmQueueInvlPage(pVCpu, GCPtr);
177 if (pVCpu->hwaccm.s.fCheckedTLBFlush)
178 {
179 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
180#ifdef IN_RING0
181 RTCPUID idHostCpu = pVCpu->hwaccm.s.idEnteredCpu;
182 if (idHostCpu != NIL_RTCPUID)
183 hwaccmMpPokeCpu(pVCpu, idHostCpu);
184#else
185 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
186#endif
187 }
188 else
189 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageManual);
190 }
191 }
192
193 return VINF_SUCCESS;
194}
195
196
197/**
198 * Flush the TLBs of all VCPUs
199 *
200 * @returns VBox status code.
201 * @param pVM The VM to operate on.
202 */
203VMMDECL(int) HWACCMFlushTLBOnAllVCpus(PVM pVM)
204{
205 if (pVM->cCpus == 1)
206 return HWACCMFlushTLB(&pVM->aCpus[0]);
207
208 VMCPUID idThisCpu = VMMGetCpuId(pVM);
209
210 STAM_COUNTER_INC(&pVM->aCpus[idThisCpu].hwaccm.s.StatFlushTLB);
211
212 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
213 {
214 PVMCPU pVCpu = &pVM->aCpus[idCpu];
215
216 /* Nothing to do if a TLB flush is already pending; the VCPU should have already been poked if it were active */
217 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH))
218 continue;
219
220 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
221 if (idThisCpu == idCpu)
222 continue;
223
224 if (pVCpu->hwaccm.s.fCheckedTLBFlush)
225 {
226 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdownFlush);
227#ifdef IN_RING0
228 RTCPUID idHostCpu = pVCpu->hwaccm.s.idEnteredCpu;
229 if (idHostCpu != NIL_RTCPUID)
230 hwaccmMpPokeCpu(pVCpu, idHostCpu);
231#else
232 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
233#endif
234 }
235 else
236 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBManual);
237 }
238 return VINF_SUCCESS;
239}
240#endif
241
242/**
243 * Checks if nested paging is enabled
244 *
245 * @returns boolean
246 * @param pVM The VM to operate on.
247 */
248VMMDECL(bool) HWACCMIsNestedPagingActive(PVM pVM)
249{
250 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.fNestedPaging;
251}
252
253/**
254 * Return the shadow paging mode for nested paging/ept
255 *
256 * @returns shadow paging mode
257 * @param pVM The VM to operate on.
258 */
259VMMDECL(PGMMODE) HWACCMGetShwPagingMode(PVM pVM)
260{
261 Assert(HWACCMIsNestedPagingActive(pVM));
262 if (pVM->hwaccm.s.svm.fSupported)
263 return PGMMODE_NESTED;
264
265 Assert(pVM->hwaccm.s.vmx.fSupported);
266 return PGMMODE_EPT;
267}
268
269/**
270 * Invalidates a guest page by physical address
271 *
272 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
273 *
274 * @returns VBox status code.
275 * @param pVM The VM to operate on.
276 * @param GCPhys Page to invalidate
277 */
278VMMDECL(int) HWACCMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
279{
280 if (!HWACCMIsNestedPagingActive(pVM))
281 return VINF_SUCCESS;
282
283#ifdef IN_RING0
284 if (pVM->hwaccm.s.vmx.fSupported)
285 {
286 VMCPUID idThisCpu = VMMGetCpuId(pVM);
287
288 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
289 {
290 PVMCPU pVCpu = &pVM->aCpus[idCpu];
291
292 if (idThisCpu == idCpu)
293 {
294 VMXR0InvalidatePhysPage(pVM, pVCpu, GCPhys);
295 continue;
296 }
297
298 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
299 if (pVCpu->hwaccm.s.fCheckedTLBFlush)
300 {
301 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdownFlush);
302# ifdef IN_RING0
303 RTCPUID idHostCpu = pVCpu->hwaccm.s.idEnteredCpu;
304 if (idHostCpu != NIL_RTCPUID)
305 hwaccmMpPokeCpu(pVCpu, idHostCpu);
306# else
307 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
308# endif
309 }
310 else
311 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBManual);
312 }
313 return VINF_SUCCESS;
314 }
315
316 Assert(pVM->hwaccm.s.svm.fSupported);
317 /* AMD-V doesn't support invalidation with guest physical addresses; see comment in SVMR0InvalidatePhysPage. */
318 HWACCMFlushTLBOnAllVCpus(pVM);
319#else
320 HWACCMFlushTLBOnAllVCpus(pVM);
321#endif
322 return VINF_SUCCESS;
323}
324
325/**
326 * Checks if an interrupt event is currently pending.
327 *
328 * @returns Interrupt event pending state.
329 * @param pVM The VM to operate on.
330 */
331VMMDECL(bool) HWACCMHasPendingIrq(PVM pVM)
332{
333 PVMCPU pVCpu = VMMGetCpu(pVM);
334 return !!pVCpu->hwaccm.s.Event.fPending;
335}
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