VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp@ 93877

Last change on this file since 93877 was 93877, checked in by vboxsync, 3 years ago

VMM/IEM: Fixed EFlags for LOCK XADD, adding tests for it. bugref:9898
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File size: 112.6 KB
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1/* $Id: IEMAllAImplC.cpp 93877 2022-02-21 20:49:18Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in Assembly, portable C variant.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include "IEMInternal.h"
23#include <VBox/vmm/vmcc.h>
24#include <iprt/errcore.h>
25#include <iprt/x86.h>
26#include <iprt/uint128.h>
27
28
29/*********************************************************************************************************************************
30* Defined Constants And Macros *
31*********************************************************************************************************************************/
32/** @def IEM_WITHOUT_ASSEMBLY
33 * Enables all the code in this file.
34 */
35#if !defined(IEM_WITHOUT_ASSEMBLY)
36# if defined(RT_ARCH_ARM32) || defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING)
37# define IEM_WITHOUT_ASSEMBLY
38# endif
39#endif
40/* IEM_WITH_ASSEMBLY trumps IEM_WITHOUT_ASSEMBLY for tstIEMAImplAsm purposes. */
41#ifdef IEM_WITH_ASSEMBLY
42# undef IEM_WITHOUT_ASSEMBLY
43#endif
44
45/**
46 * Calculates the signed flag value given a result and it's bit width.
47 *
48 * The signed flag (SF) is a duplication of the most significant bit in the
49 * result.
50 *
51 * @returns X86_EFL_SF or 0.
52 * @param a_uResult Unsigned result value.
53 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
54 */
55#define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
56 ( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
57
58/**
59 * Calculates the zero flag value given a result.
60 *
61 * The zero flag (ZF) indicates whether the result is zero or not.
62 *
63 * @returns X86_EFL_ZF or 0.
64 * @param a_uResult Unsigned result value.
65 */
66#define X86_EFL_CALC_ZF(a_uResult) \
67 ( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
68
69/**
70 * Extracts the OF flag from a OF calculation result.
71 *
72 * These are typically used by concating with a bitcount. The problem is that
73 * 8-bit values needs shifting in the other direction than the others.
74 */
75#define X86_EFL_GET_OF_8(a_uValue) (((uint32_t)(a_uValue) << (X86_EFL_OF_BIT - 8 + 1)) & X86_EFL_OF)
76#define X86_EFL_GET_OF_16(a_uValue) ((uint32_t)((a_uValue) >> (16 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
77#define X86_EFL_GET_OF_32(a_uValue) ((uint32_t)((a_uValue) >> (32 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
78#define X86_EFL_GET_OF_64(a_uValue) ((uint32_t)((a_uValue) >> (64 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
79
80/**
81 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after arithmetic op.
82 *
83 * @returns Status bits.
84 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
85 * @param a_uResult Unsigned result value.
86 * @param a_uSrc The source value (for AF calc).
87 * @param a_uDst The original destination value (for AF calc).
88 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
89 * @param a_CfExpr Bool expression for the carry flag (CF).
90 * @param a_uOfSrc The a_uSrc value to use for overflow calculation.
91 */
92#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
93 do { \
94 uint32_t fEflTmp = *(a_pfEFlags); \
95 fEflTmp &= ~X86_EFL_STATUS_BITS; \
96 fEflTmp |= (a_CfExpr) << X86_EFL_CF_BIT; \
97 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
98 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
99 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
100 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
101 \
102 /* Overflow during ADDition happens when both inputs have the same signed \
103 bit value and the result has a different sign bit value. \
104 \
105 Since subtraction can be rewritten as addition: 2 - 1 == 2 + -1, it \
106 follows that for SUBtraction the signed bit value must differ between \
107 the two inputs and the result's signed bit diff from the first input. \
108 Note! Must xor with sign bit to convert, not do (0 - a_uSrc). \
109 \
110 See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
111 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth( ( ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
112 & RT_BIT_64(a_cBitsWidth - 1)) \
113 & ((a_uResult) ^ (a_uDst)) ); \
114 *(a_pfEFlags) = fEflTmp; \
115 } while (0)
116
117/**
118 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
119 *
120 * CF and OF are defined to be 0 by logical operations. AF on the other hand is
121 * undefined. We do not set AF, as that seems to make the most sense (which
122 * probably makes it the most wrong in real life).
123 *
124 * @returns Status bits.
125 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
126 * @param a_uResult Unsigned result value.
127 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
128 * @param a_fExtra Additional bits to set.
129 */
130#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
131 do { \
132 uint32_t fEflTmp = *(a_pfEFlags); \
133 fEflTmp &= ~X86_EFL_STATUS_BITS; \
134 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
135 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
136 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
137 fEflTmp |= (a_fExtra); \
138 *(a_pfEFlags) = fEflTmp; \
139 } while (0)
140
141
142/*********************************************************************************************************************************
143* Global Variables *
144*********************************************************************************************************************************/
145#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
146/**
147 * Parity calculation table.
148 *
149 * The generator code:
150 * @code
151 * #include <stdio.h>
152 *
153 * int main()
154 * {
155 * unsigned b;
156 * for (b = 0; b < 256; b++)
157 * {
158 * int cOnes = ( b & 1)
159 * + ((b >> 1) & 1)
160 * + ((b >> 2) & 1)
161 * + ((b >> 3) & 1)
162 * + ((b >> 4) & 1)
163 * + ((b >> 5) & 1)
164 * + ((b >> 6) & 1)
165 * + ((b >> 7) & 1);
166 * printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
167 * b,
168 * (b >> 7) & 1,
169 * (b >> 6) & 1,
170 * (b >> 5) & 1,
171 * (b >> 4) & 1,
172 * (b >> 3) & 1,
173 * (b >> 2) & 1,
174 * (b >> 1) & 1,
175 * b & 1,
176 * cOnes & 1 ? "0" : "X86_EFL_PF");
177 * }
178 * return 0;
179 * }
180 * @endcode
181 */
182static uint8_t const g_afParity[256] =
183{
184 /* 0000 = 00000000b */ X86_EFL_PF,
185 /* 0x01 = 00000001b */ 0,
186 /* 0x02 = 00000010b */ 0,
187 /* 0x03 = 00000011b */ X86_EFL_PF,
188 /* 0x04 = 00000100b */ 0,
189 /* 0x05 = 00000101b */ X86_EFL_PF,
190 /* 0x06 = 00000110b */ X86_EFL_PF,
191 /* 0x07 = 00000111b */ 0,
192 /* 0x08 = 00001000b */ 0,
193 /* 0x09 = 00001001b */ X86_EFL_PF,
194 /* 0x0a = 00001010b */ X86_EFL_PF,
195 /* 0x0b = 00001011b */ 0,
196 /* 0x0c = 00001100b */ X86_EFL_PF,
197 /* 0x0d = 00001101b */ 0,
198 /* 0x0e = 00001110b */ 0,
199 /* 0x0f = 00001111b */ X86_EFL_PF,
200 /* 0x10 = 00010000b */ 0,
201 /* 0x11 = 00010001b */ X86_EFL_PF,
202 /* 0x12 = 00010010b */ X86_EFL_PF,
203 /* 0x13 = 00010011b */ 0,
204 /* 0x14 = 00010100b */ X86_EFL_PF,
205 /* 0x15 = 00010101b */ 0,
206 /* 0x16 = 00010110b */ 0,
207 /* 0x17 = 00010111b */ X86_EFL_PF,
208 /* 0x18 = 00011000b */ X86_EFL_PF,
209 /* 0x19 = 00011001b */ 0,
210 /* 0x1a = 00011010b */ 0,
211 /* 0x1b = 00011011b */ X86_EFL_PF,
212 /* 0x1c = 00011100b */ 0,
213 /* 0x1d = 00011101b */ X86_EFL_PF,
214 /* 0x1e = 00011110b */ X86_EFL_PF,
215 /* 0x1f = 00011111b */ 0,
216 /* 0x20 = 00100000b */ 0,
217 /* 0x21 = 00100001b */ X86_EFL_PF,
218 /* 0x22 = 00100010b */ X86_EFL_PF,
219 /* 0x23 = 00100011b */ 0,
220 /* 0x24 = 00100100b */ X86_EFL_PF,
221 /* 0x25 = 00100101b */ 0,
222 /* 0x26 = 00100110b */ 0,
223 /* 0x27 = 00100111b */ X86_EFL_PF,
224 /* 0x28 = 00101000b */ X86_EFL_PF,
225 /* 0x29 = 00101001b */ 0,
226 /* 0x2a = 00101010b */ 0,
227 /* 0x2b = 00101011b */ X86_EFL_PF,
228 /* 0x2c = 00101100b */ 0,
229 /* 0x2d = 00101101b */ X86_EFL_PF,
230 /* 0x2e = 00101110b */ X86_EFL_PF,
231 /* 0x2f = 00101111b */ 0,
232 /* 0x30 = 00110000b */ X86_EFL_PF,
233 /* 0x31 = 00110001b */ 0,
234 /* 0x32 = 00110010b */ 0,
235 /* 0x33 = 00110011b */ X86_EFL_PF,
236 /* 0x34 = 00110100b */ 0,
237 /* 0x35 = 00110101b */ X86_EFL_PF,
238 /* 0x36 = 00110110b */ X86_EFL_PF,
239 /* 0x37 = 00110111b */ 0,
240 /* 0x38 = 00111000b */ 0,
241 /* 0x39 = 00111001b */ X86_EFL_PF,
242 /* 0x3a = 00111010b */ X86_EFL_PF,
243 /* 0x3b = 00111011b */ 0,
244 /* 0x3c = 00111100b */ X86_EFL_PF,
245 /* 0x3d = 00111101b */ 0,
246 /* 0x3e = 00111110b */ 0,
247 /* 0x3f = 00111111b */ X86_EFL_PF,
248 /* 0x40 = 01000000b */ 0,
249 /* 0x41 = 01000001b */ X86_EFL_PF,
250 /* 0x42 = 01000010b */ X86_EFL_PF,
251 /* 0x43 = 01000011b */ 0,
252 /* 0x44 = 01000100b */ X86_EFL_PF,
253 /* 0x45 = 01000101b */ 0,
254 /* 0x46 = 01000110b */ 0,
255 /* 0x47 = 01000111b */ X86_EFL_PF,
256 /* 0x48 = 01001000b */ X86_EFL_PF,
257 /* 0x49 = 01001001b */ 0,
258 /* 0x4a = 01001010b */ 0,
259 /* 0x4b = 01001011b */ X86_EFL_PF,
260 /* 0x4c = 01001100b */ 0,
261 /* 0x4d = 01001101b */ X86_EFL_PF,
262 /* 0x4e = 01001110b */ X86_EFL_PF,
263 /* 0x4f = 01001111b */ 0,
264 /* 0x50 = 01010000b */ X86_EFL_PF,
265 /* 0x51 = 01010001b */ 0,
266 /* 0x52 = 01010010b */ 0,
267 /* 0x53 = 01010011b */ X86_EFL_PF,
268 /* 0x54 = 01010100b */ 0,
269 /* 0x55 = 01010101b */ X86_EFL_PF,
270 /* 0x56 = 01010110b */ X86_EFL_PF,
271 /* 0x57 = 01010111b */ 0,
272 /* 0x58 = 01011000b */ 0,
273 /* 0x59 = 01011001b */ X86_EFL_PF,
274 /* 0x5a = 01011010b */ X86_EFL_PF,
275 /* 0x5b = 01011011b */ 0,
276 /* 0x5c = 01011100b */ X86_EFL_PF,
277 /* 0x5d = 01011101b */ 0,
278 /* 0x5e = 01011110b */ 0,
279 /* 0x5f = 01011111b */ X86_EFL_PF,
280 /* 0x60 = 01100000b */ X86_EFL_PF,
281 /* 0x61 = 01100001b */ 0,
282 /* 0x62 = 01100010b */ 0,
283 /* 0x63 = 01100011b */ X86_EFL_PF,
284 /* 0x64 = 01100100b */ 0,
285 /* 0x65 = 01100101b */ X86_EFL_PF,
286 /* 0x66 = 01100110b */ X86_EFL_PF,
287 /* 0x67 = 01100111b */ 0,
288 /* 0x68 = 01101000b */ 0,
289 /* 0x69 = 01101001b */ X86_EFL_PF,
290 /* 0x6a = 01101010b */ X86_EFL_PF,
291 /* 0x6b = 01101011b */ 0,
292 /* 0x6c = 01101100b */ X86_EFL_PF,
293 /* 0x6d = 01101101b */ 0,
294 /* 0x6e = 01101110b */ 0,
295 /* 0x6f = 01101111b */ X86_EFL_PF,
296 /* 0x70 = 01110000b */ 0,
297 /* 0x71 = 01110001b */ X86_EFL_PF,
298 /* 0x72 = 01110010b */ X86_EFL_PF,
299 /* 0x73 = 01110011b */ 0,
300 /* 0x74 = 01110100b */ X86_EFL_PF,
301 /* 0x75 = 01110101b */ 0,
302 /* 0x76 = 01110110b */ 0,
303 /* 0x77 = 01110111b */ X86_EFL_PF,
304 /* 0x78 = 01111000b */ X86_EFL_PF,
305 /* 0x79 = 01111001b */ 0,
306 /* 0x7a = 01111010b */ 0,
307 /* 0x7b = 01111011b */ X86_EFL_PF,
308 /* 0x7c = 01111100b */ 0,
309 /* 0x7d = 01111101b */ X86_EFL_PF,
310 /* 0x7e = 01111110b */ X86_EFL_PF,
311 /* 0x7f = 01111111b */ 0,
312 /* 0x80 = 10000000b */ 0,
313 /* 0x81 = 10000001b */ X86_EFL_PF,
314 /* 0x82 = 10000010b */ X86_EFL_PF,
315 /* 0x83 = 10000011b */ 0,
316 /* 0x84 = 10000100b */ X86_EFL_PF,
317 /* 0x85 = 10000101b */ 0,
318 /* 0x86 = 10000110b */ 0,
319 /* 0x87 = 10000111b */ X86_EFL_PF,
320 /* 0x88 = 10001000b */ X86_EFL_PF,
321 /* 0x89 = 10001001b */ 0,
322 /* 0x8a = 10001010b */ 0,
323 /* 0x8b = 10001011b */ X86_EFL_PF,
324 /* 0x8c = 10001100b */ 0,
325 /* 0x8d = 10001101b */ X86_EFL_PF,
326 /* 0x8e = 10001110b */ X86_EFL_PF,
327 /* 0x8f = 10001111b */ 0,
328 /* 0x90 = 10010000b */ X86_EFL_PF,
329 /* 0x91 = 10010001b */ 0,
330 /* 0x92 = 10010010b */ 0,
331 /* 0x93 = 10010011b */ X86_EFL_PF,
332 /* 0x94 = 10010100b */ 0,
333 /* 0x95 = 10010101b */ X86_EFL_PF,
334 /* 0x96 = 10010110b */ X86_EFL_PF,
335 /* 0x97 = 10010111b */ 0,
336 /* 0x98 = 10011000b */ 0,
337 /* 0x99 = 10011001b */ X86_EFL_PF,
338 /* 0x9a = 10011010b */ X86_EFL_PF,
339 /* 0x9b = 10011011b */ 0,
340 /* 0x9c = 10011100b */ X86_EFL_PF,
341 /* 0x9d = 10011101b */ 0,
342 /* 0x9e = 10011110b */ 0,
343 /* 0x9f = 10011111b */ X86_EFL_PF,
344 /* 0xa0 = 10100000b */ X86_EFL_PF,
345 /* 0xa1 = 10100001b */ 0,
346 /* 0xa2 = 10100010b */ 0,
347 /* 0xa3 = 10100011b */ X86_EFL_PF,
348 /* 0xa4 = 10100100b */ 0,
349 /* 0xa5 = 10100101b */ X86_EFL_PF,
350 /* 0xa6 = 10100110b */ X86_EFL_PF,
351 /* 0xa7 = 10100111b */ 0,
352 /* 0xa8 = 10101000b */ 0,
353 /* 0xa9 = 10101001b */ X86_EFL_PF,
354 /* 0xaa = 10101010b */ X86_EFL_PF,
355 /* 0xab = 10101011b */ 0,
356 /* 0xac = 10101100b */ X86_EFL_PF,
357 /* 0xad = 10101101b */ 0,
358 /* 0xae = 10101110b */ 0,
359 /* 0xaf = 10101111b */ X86_EFL_PF,
360 /* 0xb0 = 10110000b */ 0,
361 /* 0xb1 = 10110001b */ X86_EFL_PF,
362 /* 0xb2 = 10110010b */ X86_EFL_PF,
363 /* 0xb3 = 10110011b */ 0,
364 /* 0xb4 = 10110100b */ X86_EFL_PF,
365 /* 0xb5 = 10110101b */ 0,
366 /* 0xb6 = 10110110b */ 0,
367 /* 0xb7 = 10110111b */ X86_EFL_PF,
368 /* 0xb8 = 10111000b */ X86_EFL_PF,
369 /* 0xb9 = 10111001b */ 0,
370 /* 0xba = 10111010b */ 0,
371 /* 0xbb = 10111011b */ X86_EFL_PF,
372 /* 0xbc = 10111100b */ 0,
373 /* 0xbd = 10111101b */ X86_EFL_PF,
374 /* 0xbe = 10111110b */ X86_EFL_PF,
375 /* 0xbf = 10111111b */ 0,
376 /* 0xc0 = 11000000b */ X86_EFL_PF,
377 /* 0xc1 = 11000001b */ 0,
378 /* 0xc2 = 11000010b */ 0,
379 /* 0xc3 = 11000011b */ X86_EFL_PF,
380 /* 0xc4 = 11000100b */ 0,
381 /* 0xc5 = 11000101b */ X86_EFL_PF,
382 /* 0xc6 = 11000110b */ X86_EFL_PF,
383 /* 0xc7 = 11000111b */ 0,
384 /* 0xc8 = 11001000b */ 0,
385 /* 0xc9 = 11001001b */ X86_EFL_PF,
386 /* 0xca = 11001010b */ X86_EFL_PF,
387 /* 0xcb = 11001011b */ 0,
388 /* 0xcc = 11001100b */ X86_EFL_PF,
389 /* 0xcd = 11001101b */ 0,
390 /* 0xce = 11001110b */ 0,
391 /* 0xcf = 11001111b */ X86_EFL_PF,
392 /* 0xd0 = 11010000b */ 0,
393 /* 0xd1 = 11010001b */ X86_EFL_PF,
394 /* 0xd2 = 11010010b */ X86_EFL_PF,
395 /* 0xd3 = 11010011b */ 0,
396 /* 0xd4 = 11010100b */ X86_EFL_PF,
397 /* 0xd5 = 11010101b */ 0,
398 /* 0xd6 = 11010110b */ 0,
399 /* 0xd7 = 11010111b */ X86_EFL_PF,
400 /* 0xd8 = 11011000b */ X86_EFL_PF,
401 /* 0xd9 = 11011001b */ 0,
402 /* 0xda = 11011010b */ 0,
403 /* 0xdb = 11011011b */ X86_EFL_PF,
404 /* 0xdc = 11011100b */ 0,
405 /* 0xdd = 11011101b */ X86_EFL_PF,
406 /* 0xde = 11011110b */ X86_EFL_PF,
407 /* 0xdf = 11011111b */ 0,
408 /* 0xe0 = 11100000b */ 0,
409 /* 0xe1 = 11100001b */ X86_EFL_PF,
410 /* 0xe2 = 11100010b */ X86_EFL_PF,
411 /* 0xe3 = 11100011b */ 0,
412 /* 0xe4 = 11100100b */ X86_EFL_PF,
413 /* 0xe5 = 11100101b */ 0,
414 /* 0xe6 = 11100110b */ 0,
415 /* 0xe7 = 11100111b */ X86_EFL_PF,
416 /* 0xe8 = 11101000b */ X86_EFL_PF,
417 /* 0xe9 = 11101001b */ 0,
418 /* 0xea = 11101010b */ 0,
419 /* 0xeb = 11101011b */ X86_EFL_PF,
420 /* 0xec = 11101100b */ 0,
421 /* 0xed = 11101101b */ X86_EFL_PF,
422 /* 0xee = 11101110b */ X86_EFL_PF,
423 /* 0xef = 11101111b */ 0,
424 /* 0xf0 = 11110000b */ X86_EFL_PF,
425 /* 0xf1 = 11110001b */ 0,
426 /* 0xf2 = 11110010b */ 0,
427 /* 0xf3 = 11110011b */ X86_EFL_PF,
428 /* 0xf4 = 11110100b */ 0,
429 /* 0xf5 = 11110101b */ X86_EFL_PF,
430 /* 0xf6 = 11110110b */ X86_EFL_PF,
431 /* 0xf7 = 11110111b */ 0,
432 /* 0xf8 = 11111000b */ 0,
433 /* 0xf9 = 11111001b */ X86_EFL_PF,
434 /* 0xfa = 11111010b */ X86_EFL_PF,
435 /* 0xfb = 11111011b */ 0,
436 /* 0xfc = 11111100b */ X86_EFL_PF,
437 /* 0xfd = 11111101b */ 0,
438 /* 0xfe = 11111110b */ 0,
439 /* 0xff = 11111111b */ X86_EFL_PF,
440};
441#endif /* !RT_ARCH_AMD64 || IEM_WITHOUT_ASSEMBLY */
442
443
444
445/*
446 * There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
447 * it all in C is probably safer atm., optimize what's necessary later, maybe.
448 */
449#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
450
451
452/*********************************************************************************************************************************
453* Binary Operations *
454*********************************************************************************************************************************/
455
456/*
457 * ADD
458 */
459
460IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
461{
462 uint64_t uDst = *puDst;
463 uint64_t uResult = uDst + uSrc;
464 *puDst = uResult;
465 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
466}
467
468# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
469
470IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
471{
472 uint32_t uDst = *puDst;
473 uint32_t uResult = uDst + uSrc;
474 *puDst = uResult;
475 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
476}
477
478
479IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
480{
481 uint16_t uDst = *puDst;
482 uint16_t uResult = uDst + uSrc;
483 *puDst = uResult;
484 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
485}
486
487
488IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
489{
490 uint8_t uDst = *puDst;
491 uint8_t uResult = uDst + uSrc;
492 *puDst = uResult;
493 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
494}
495
496# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
497
498/*
499 * ADC
500 */
501
502IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
503{
504 if (!(*pfEFlags & X86_EFL_CF))
505 iemAImpl_add_u64(puDst, uSrc, pfEFlags);
506 else
507 {
508 uint64_t uDst = *puDst;
509 uint64_t uResult = uDst + uSrc + 1;
510 *puDst = uResult;
511 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
512 }
513}
514
515# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
516
517IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
518{
519 if (!(*pfEFlags & X86_EFL_CF))
520 iemAImpl_add_u32(puDst, uSrc, pfEFlags);
521 else
522 {
523 uint32_t uDst = *puDst;
524 uint32_t uResult = uDst + uSrc + 1;
525 *puDst = uResult;
526 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
527 }
528}
529
530
531IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
532{
533 if (!(*pfEFlags & X86_EFL_CF))
534 iemAImpl_add_u16(puDst, uSrc, pfEFlags);
535 else
536 {
537 uint16_t uDst = *puDst;
538 uint16_t uResult = uDst + uSrc + 1;
539 *puDst = uResult;
540 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
541 }
542}
543
544
545IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
546{
547 if (!(*pfEFlags & X86_EFL_CF))
548 iemAImpl_add_u8(puDst, uSrc, pfEFlags);
549 else
550 {
551 uint8_t uDst = *puDst;
552 uint8_t uResult = uDst + uSrc + 1;
553 *puDst = uResult;
554 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
555 }
556}
557
558# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
559
560/*
561 * SUB
562 */
563
564IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
565{
566 uint64_t uDst = *puDst;
567 uint64_t uResult = uDst - uSrc;
568 *puDst = uResult;
569 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
570}
571
572# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
573
574IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
575{
576 uint32_t uDst = *puDst;
577 uint32_t uResult = uDst - uSrc;
578 *puDst = uResult;
579 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
580}
581
582
583IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
584{
585 uint16_t uDst = *puDst;
586 uint16_t uResult = uDst - uSrc;
587 *puDst = uResult;
588 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
589}
590
591
592IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
593{
594 uint8_t uDst = *puDst;
595 uint8_t uResult = uDst - uSrc;
596 *puDst = uResult;
597 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
598}
599
600# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
601
602/*
603 * SBB
604 */
605
606IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
607{
608 if (!(*pfEFlags & X86_EFL_CF))
609 iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
610 else
611 {
612 uint64_t uDst = *puDst;
613 uint64_t uResult = uDst - uSrc - 1;
614 *puDst = uResult;
615 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
616 }
617}
618
619# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
620
621IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
622{
623 if (!(*pfEFlags & X86_EFL_CF))
624 iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
625 else
626 {
627 uint32_t uDst = *puDst;
628 uint32_t uResult = uDst - uSrc - 1;
629 *puDst = uResult;
630 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
631 }
632}
633
634
635IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
636{
637 if (!(*pfEFlags & X86_EFL_CF))
638 iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
639 else
640 {
641 uint16_t uDst = *puDst;
642 uint16_t uResult = uDst - uSrc - 1;
643 *puDst = uResult;
644 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
645 }
646}
647
648
649IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
650{
651 if (!(*pfEFlags & X86_EFL_CF))
652 iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
653 else
654 {
655 uint8_t uDst = *puDst;
656 uint8_t uResult = uDst - uSrc - 1;
657 *puDst = uResult;
658 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
659 }
660}
661
662# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
663
664
665/*
666 * OR
667 */
668
669IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
670{
671 uint64_t uResult = *puDst | uSrc;
672 *puDst = uResult;
673 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
674}
675
676# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
677
678IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
679{
680 uint32_t uResult = *puDst | uSrc;
681 *puDst = uResult;
682 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
683}
684
685
686IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
687{
688 uint16_t uResult = *puDst | uSrc;
689 *puDst = uResult;
690 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
691}
692
693
694IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
695{
696 uint8_t uResult = *puDst | uSrc;
697 *puDst = uResult;
698 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
699}
700
701# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
702
703/*
704 * XOR
705 */
706
707IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
708{
709 uint64_t uResult = *puDst ^ uSrc;
710 *puDst = uResult;
711 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
712}
713
714# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
715
716IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
717{
718 uint32_t uResult = *puDst ^ uSrc;
719 *puDst = uResult;
720 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
721}
722
723
724IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
725{
726 uint16_t uResult = *puDst ^ uSrc;
727 *puDst = uResult;
728 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
729}
730
731
732IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
733{
734 uint8_t uResult = *puDst ^ uSrc;
735 *puDst = uResult;
736 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
737}
738
739# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
740
741/*
742 * AND
743 */
744
745IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
746{
747 uint64_t uResult = *puDst & uSrc;
748 *puDst = uResult;
749 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
750}
751
752# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
753
754IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
755{
756 uint32_t uResult = *puDst & uSrc;
757 *puDst = uResult;
758 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
759}
760
761
762IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
763{
764 uint16_t uResult = *puDst & uSrc;
765 *puDst = uResult;
766 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
767}
768
769
770IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
771{
772 uint8_t uResult = *puDst & uSrc;
773 *puDst = uResult;
774 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
775}
776
777# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
778
779/*
780 * CMP
781 */
782
783IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
784{
785 uint64_t uDstTmp = *puDst;
786 iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
787}
788
789# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
790
791IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
792{
793 uint32_t uDstTmp = *puDst;
794 iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
795}
796
797
798IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
799{
800 uint16_t uDstTmp = *puDst;
801 iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
802}
803
804
805IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
806{
807 uint8_t uDstTmp = *puDst;
808 iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
809}
810
811# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
812
813/*
814 * TEST
815 */
816
817IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
818{
819 uint64_t uResult = *puDst & uSrc;
820 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
821}
822
823# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
824
825IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
826{
827 uint32_t uResult = *puDst & uSrc;
828 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
829}
830
831
832IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
833{
834 uint16_t uResult = *puDst & uSrc;
835 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
836}
837
838
839IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
840{
841 uint8_t uResult = *puDst & uSrc;
842 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
843}
844
845# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
846
847
848/*
849 * LOCK prefixed variants of the above
850 */
851
852/** 64-bit locked binary operand operation. */
853# define DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
854 do { \
855 uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
856 uint ## a_cBitsWidth ## _t uTmp; \
857 uint32_t fEflTmp; \
858 do \
859 { \
860 uTmp = uOld; \
861 fEflTmp = *pfEFlags; \
862 iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
863 } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
864 *pfEFlags = fEflTmp; \
865 } while (0)
866
867
868#define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
869 IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
870 uint ## a_cBitsWidth ## _t uSrc, \
871 uint32_t *pfEFlags)) \
872 { \
873 DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
874 }
875
876EMIT_LOCKED_BIN_OP(add, 64)
877EMIT_LOCKED_BIN_OP(adc, 64)
878EMIT_LOCKED_BIN_OP(sub, 64)
879EMIT_LOCKED_BIN_OP(sbb, 64)
880EMIT_LOCKED_BIN_OP(or, 64)
881EMIT_LOCKED_BIN_OP(xor, 64)
882EMIT_LOCKED_BIN_OP(and, 64)
883# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
884EMIT_LOCKED_BIN_OP(add, 32)
885EMIT_LOCKED_BIN_OP(adc, 32)
886EMIT_LOCKED_BIN_OP(sub, 32)
887EMIT_LOCKED_BIN_OP(sbb, 32)
888EMIT_LOCKED_BIN_OP(or, 32)
889EMIT_LOCKED_BIN_OP(xor, 32)
890EMIT_LOCKED_BIN_OP(and, 32)
891
892EMIT_LOCKED_BIN_OP(add, 16)
893EMIT_LOCKED_BIN_OP(adc, 16)
894EMIT_LOCKED_BIN_OP(sub, 16)
895EMIT_LOCKED_BIN_OP(sbb, 16)
896EMIT_LOCKED_BIN_OP(or, 16)
897EMIT_LOCKED_BIN_OP(xor, 16)
898EMIT_LOCKED_BIN_OP(and, 16)
899
900EMIT_LOCKED_BIN_OP(add, 8)
901EMIT_LOCKED_BIN_OP(adc, 8)
902EMIT_LOCKED_BIN_OP(sub, 8)
903EMIT_LOCKED_BIN_OP(sbb, 8)
904EMIT_LOCKED_BIN_OP(or, 8)
905EMIT_LOCKED_BIN_OP(xor, 8)
906EMIT_LOCKED_BIN_OP(and, 8)
907# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
908
909
910/*
911 * Bit operations (same signature as above).
912 */
913
914/*
915 * BT
916 */
917
918IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
919{
920 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
921 not modified by either AMD (3990x) or Intel (i9-9980HK). */
922 Assert(uSrc < 64);
923 uint64_t uDst = *puDst;
924 if (uDst & RT_BIT_64(uSrc))
925 *pfEFlags |= X86_EFL_CF;
926 else
927 *pfEFlags &= ~X86_EFL_CF;
928}
929
930# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
931
932IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
933{
934 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
935 not modified by either AMD (3990x) or Intel (i9-9980HK). */
936 Assert(uSrc < 32);
937 uint32_t uDst = *puDst;
938 if (uDst & RT_BIT_32(uSrc))
939 *pfEFlags |= X86_EFL_CF;
940 else
941 *pfEFlags &= ~X86_EFL_CF;
942}
943
944IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
945{
946 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
947 not modified by either AMD (3990x) or Intel (i9-9980HK). */
948 Assert(uSrc < 16);
949 uint16_t uDst = *puDst;
950 if (uDst & RT_BIT_32(uSrc))
951 *pfEFlags |= X86_EFL_CF;
952 else
953 *pfEFlags &= ~X86_EFL_CF;
954}
955
956# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
957
958/*
959 * BTC
960 */
961
962IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
963{
964 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
965 not modified by either AMD (3990x) or Intel (i9-9980HK). */
966 Assert(uSrc < 64);
967 uint64_t fMask = RT_BIT_64(uSrc);
968 uint64_t uDst = *puDst;
969 if (uDst & fMask)
970 {
971 uDst &= ~fMask;
972 *puDst = uDst;
973 *pfEFlags |= X86_EFL_CF;
974 }
975 else
976 {
977 uDst |= fMask;
978 *puDst = uDst;
979 *pfEFlags &= ~X86_EFL_CF;
980 }
981}
982
983# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
984
985IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
986{
987 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
988 not modified by either AMD (3990x) or Intel (i9-9980HK). */
989 Assert(uSrc < 32);
990 uint32_t fMask = RT_BIT_32(uSrc);
991 uint32_t uDst = *puDst;
992 if (uDst & fMask)
993 {
994 uDst &= ~fMask;
995 *puDst = uDst;
996 *pfEFlags |= X86_EFL_CF;
997 }
998 else
999 {
1000 uDst |= fMask;
1001 *puDst = uDst;
1002 *pfEFlags &= ~X86_EFL_CF;
1003 }
1004}
1005
1006
1007IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1008{
1009 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
1010 not modified by either AMD (3990x) or Intel (i9-9980HK). */
1011 Assert(uSrc < 16);
1012 uint16_t fMask = RT_BIT_32(uSrc);
1013 uint16_t uDst = *puDst;
1014 if (uDst & fMask)
1015 {
1016 uDst &= ~fMask;
1017 *puDst = uDst;
1018 *pfEFlags |= X86_EFL_CF;
1019 }
1020 else
1021 {
1022 uDst |= fMask;
1023 *puDst = uDst;
1024 *pfEFlags &= ~X86_EFL_CF;
1025 }
1026}
1027
1028# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1029
1030/*
1031 * BTR
1032 */
1033
1034IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1035{
1036 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1037 logical operation (AND/OR/whatever). */
1038 Assert(uSrc < 64);
1039 uint64_t fMask = RT_BIT_64(uSrc);
1040 uint64_t uDst = *puDst;
1041 if (uDst & fMask)
1042 {
1043 uDst &= ~fMask;
1044 *puDst = uDst;
1045 *pfEFlags |= X86_EFL_CF;
1046 }
1047 else
1048 *pfEFlags &= ~X86_EFL_CF;
1049}
1050
1051# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1052
1053IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1054{
1055 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1056 logical operation (AND/OR/whatever). */
1057 Assert(uSrc < 32);
1058 uint32_t fMask = RT_BIT_32(uSrc);
1059 uint32_t uDst = *puDst;
1060 if (uDst & fMask)
1061 {
1062 uDst &= ~fMask;
1063 *puDst = uDst;
1064 *pfEFlags |= X86_EFL_CF;
1065 }
1066 else
1067 *pfEFlags &= ~X86_EFL_CF;
1068}
1069
1070
1071IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1072{
1073 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1074 logical operation (AND/OR/whatever). */
1075 Assert(uSrc < 16);
1076 uint16_t fMask = RT_BIT_32(uSrc);
1077 uint16_t uDst = *puDst;
1078 if (uDst & fMask)
1079 {
1080 uDst &= ~fMask;
1081 *puDst = uDst;
1082 *pfEFlags |= X86_EFL_CF;
1083 }
1084 else
1085 *pfEFlags &= ~X86_EFL_CF;
1086}
1087
1088# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1089
1090/*
1091 * BTS
1092 */
1093
1094IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1095{
1096 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1097 logical operation (AND/OR/whatever). */
1098 Assert(uSrc < 64);
1099 uint64_t fMask = RT_BIT_64(uSrc);
1100 uint64_t uDst = *puDst;
1101 if (uDst & fMask)
1102 *pfEFlags |= X86_EFL_CF;
1103 else
1104 {
1105 uDst |= fMask;
1106 *puDst = uDst;
1107 *pfEFlags &= ~X86_EFL_CF;
1108 }
1109}
1110
1111# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1112
1113IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1114{
1115 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1116 logical operation (AND/OR/whatever). */
1117 Assert(uSrc < 32);
1118 uint32_t fMask = RT_BIT_32(uSrc);
1119 uint32_t uDst = *puDst;
1120 if (uDst & fMask)
1121 *pfEFlags |= X86_EFL_CF;
1122 else
1123 {
1124 uDst |= fMask;
1125 *puDst = uDst;
1126 *pfEFlags &= ~X86_EFL_CF;
1127 }
1128}
1129
1130
1131IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1132{
1133 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1134 logical operation (AND/OR/whatever). */
1135 Assert(uSrc < 16);
1136 uint16_t fMask = RT_BIT_32(uSrc);
1137 uint32_t uDst = *puDst;
1138 if (uDst & fMask)
1139 *pfEFlags |= X86_EFL_CF;
1140 else
1141 {
1142 uDst |= fMask;
1143 *puDst = uDst;
1144 *pfEFlags &= ~X86_EFL_CF;
1145 }
1146}
1147
1148# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1149
1150
1151EMIT_LOCKED_BIN_OP(btc, 64)
1152EMIT_LOCKED_BIN_OP(btr, 64)
1153EMIT_LOCKED_BIN_OP(bts, 64)
1154# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1155EMIT_LOCKED_BIN_OP(btc, 32)
1156EMIT_LOCKED_BIN_OP(btr, 32)
1157EMIT_LOCKED_BIN_OP(bts, 32)
1158
1159EMIT_LOCKED_BIN_OP(btc, 16)
1160EMIT_LOCKED_BIN_OP(btr, 16)
1161EMIT_LOCKED_BIN_OP(bts, 16)
1162# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1163
1164
1165/*
1166 * BSF - first (least significant) bit set
1167 */
1168
1169IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1170{
1171 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1172 /* Intel & AMD differs here. This is is the AMD behaviour. */
1173 unsigned iBit = ASMBitFirstSetU64(uSrc);
1174 if (iBit)
1175 {
1176 *puDst = iBit - 1;
1177 *pfEFlags &= ~X86_EFL_ZF;
1178 }
1179 else
1180 *pfEFlags |= X86_EFL_ZF;
1181}
1182
1183# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1184
1185IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1186{
1187 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1188 /* Intel & AMD differs here. This is is the AMD behaviour. */
1189 unsigned iBit = ASMBitFirstSetU32(uSrc);
1190 if (iBit)
1191 {
1192 *puDst = iBit - 1;
1193 *pfEFlags &= ~X86_EFL_ZF;
1194 }
1195 else
1196 *pfEFlags |= X86_EFL_ZF;
1197}
1198
1199
1200IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1201{
1202 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1203 /* Intel & AMD differs here. This is is the AMD behaviour. */
1204 unsigned iBit = ASMBitFirstSetU16(uSrc);
1205 if (iBit)
1206 {
1207 *puDst = iBit - 1;
1208 *pfEFlags &= ~X86_EFL_ZF;
1209 }
1210 else
1211 *pfEFlags |= X86_EFL_ZF;
1212}
1213
1214# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1215
1216/*
1217 * BSR - last (most significant) bit set
1218 */
1219
1220IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1221{
1222 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1223 /* Intel & AMD differs here. This is is the AMD behaviour. */
1224 unsigned iBit = ASMBitLastSetU64(uSrc);
1225 if (uSrc)
1226 {
1227 *puDst = iBit - 1;
1228 *pfEFlags &= ~X86_EFL_ZF;
1229 }
1230 else
1231 *pfEFlags |= X86_EFL_ZF;
1232}
1233
1234# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1235
1236IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1237{
1238 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1239 /* Intel & AMD differs here. This is is the AMD behaviour. */
1240 unsigned iBit = ASMBitLastSetU32(uSrc);
1241 if (uSrc)
1242 {
1243 *puDst = iBit - 1;
1244 *pfEFlags &= ~X86_EFL_ZF;
1245 }
1246 else
1247 *pfEFlags |= X86_EFL_ZF;
1248}
1249
1250
1251IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1252{
1253 /* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1254 /* Intel & AMD differs here. This is is the AMD behaviour. */
1255 unsigned iBit = ASMBitLastSetU16(uSrc);
1256 if (uSrc)
1257 {
1258 *puDst = iBit - 1;
1259 *pfEFlags &= ~X86_EFL_ZF;
1260 }
1261 else
1262 *pfEFlags |= X86_EFL_ZF;
1263}
1264
1265# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1266
1267
1268/*
1269 * XCHG
1270 */
1271
1272IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *puMem, uint64_t *puReg))
1273{
1274#if ARCH_BITS >= 64
1275 *puReg = ASMAtomicXchgU64(puMem, *puReg);
1276#else
1277 uint64_t uOldMem = *puMem;
1278 while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
1279 ASMNopPause();
1280 *puReg = uOldMem;
1281#endif
1282}
1283
1284# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1285
1286IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *puMem, uint32_t *puReg))
1287{
1288 *puReg = ASMAtomicXchgU32(puMem, *puReg);
1289}
1290
1291
1292IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *puMem, uint16_t *puReg))
1293{
1294 *puReg = ASMAtomicXchgU16(puMem, *puReg);
1295}
1296
1297
1298IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked,(uint8_t *puMem, uint8_t *puReg))
1299{
1300 *puReg = ASMAtomicXchgU8(puMem, *puReg);
1301}
1302
1303# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1304
1305
1306/* Unlocked variants for fDisregardLock mode: */
1307
1308IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *puMem, uint64_t *puReg))
1309{
1310 uint64_t const uOld = *puMem;
1311 *puMem = *puReg;
1312 *puReg = uOld;
1313}
1314
1315# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1316
1317IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *puMem, uint32_t *puReg))
1318{
1319 uint32_t const uOld = *puMem;
1320 *puMem = *puReg;
1321 *puReg = uOld;
1322}
1323
1324
1325IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *puMem, uint16_t *puReg))
1326{
1327 uint16_t const uOld = *puMem;
1328 *puMem = *puReg;
1329 *puReg = uOld;
1330}
1331
1332
1333IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked,(uint8_t *puMem, uint8_t *puReg))
1334{
1335 uint8_t const uOld = *puMem;
1336 *puMem = *puReg;
1337 *puReg = uOld;
1338}
1339
1340# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1341
1342
1343/*
1344 * XADD and LOCK XADD.
1345 */
1346
1347IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
1348{
1349 uint64_t uDst = *puDst;
1350 uint64_t uResult = uDst;
1351 iemAImpl_add_u64(&uResult, *puReg, pfEFlags);
1352 *puDst = uResult;
1353 *puReg = uDst;
1354}
1355
1356
1357IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *puDst, uint64_t *puReg, uint32_t *pfEFlags))
1358{
1359 uint64_t uOld = ASMAtomicUoReadU64(puDst);
1360 uint64_t uResult;
1361 uint32_t fEflTmp;
1362 do
1363 {
1364 uResult = uOld;
1365 fEflTmp = *pfEFlags;
1366 iemAImpl_add_u64(&uResult, *puReg, &fEflTmp);
1367 } while (!ASMAtomicCmpXchgExU64(puDst, uResult, uOld, &uOld));
1368 *puReg = uOld;
1369 *pfEFlags = fEflTmp;
1370}
1371
1372# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1373
1374IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *puDst, uint32_t *puReg, uint32_t *pfEFlags))
1375{
1376 uint32_t uDst = *puDst;
1377 uint32_t uResult = uDst;
1378 iemAImpl_add_u32(&uResult, *puReg, pfEFlags);
1379 *puDst = uResult;
1380 *puReg = uDst;
1381}
1382
1383
1384IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *puDst, uint32_t *puReg, uint32_t *pfEFlags))
1385{
1386 uint32_t uOld = ASMAtomicUoReadU32(puDst);
1387 uint32_t uResult;
1388 uint32_t fEflTmp;
1389 do
1390 {
1391 uResult = uOld;
1392 fEflTmp = *pfEFlags;
1393 iemAImpl_add_u32(&uResult, *puReg, &fEflTmp);
1394 } while (!ASMAtomicCmpXchgExU32(puDst, uResult, uOld, &uOld));
1395 *puReg = uOld;
1396 *pfEFlags = fEflTmp;
1397}
1398
1399
1400IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *puDst, uint16_t *puReg, uint32_t *pfEFlags))
1401{
1402 uint16_t uDst = *puDst;
1403 uint16_t uResult = uDst;
1404 iemAImpl_add_u16(&uResult, *puReg, pfEFlags);
1405 *puDst = uResult;
1406 *puReg = uDst;
1407}
1408
1409
1410IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *puDst, uint16_t *puReg, uint32_t *pfEFlags))
1411{
1412 uint16_t uOld = ASMAtomicUoReadU16(puDst);
1413 uint16_t uResult;
1414 uint32_t fEflTmp;
1415 do
1416 {
1417 uResult = uOld;
1418 fEflTmp = *pfEFlags;
1419 iemAImpl_add_u16(&uResult, *puReg, &fEflTmp);
1420 } while (!ASMAtomicCmpXchgExU16(puDst, uResult, uOld, &uOld));
1421 *puReg = uOld;
1422 *pfEFlags = fEflTmp;
1423}
1424
1425
1426IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8,(uint8_t *puDst, uint8_t *puReg, uint32_t *pfEFlags))
1427{
1428 uint8_t uDst = *puDst;
1429 uint8_t uResult = uDst;
1430 iemAImpl_add_u8(&uResult, *puReg, pfEFlags);
1431 *puDst = uResult;
1432 *puReg = uDst;
1433}
1434
1435
1436IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked,(uint8_t *puDst, uint8_t *puReg, uint32_t *pfEFlags))
1437{
1438 uint8_t uOld = ASMAtomicUoReadU8(puDst);
1439 uint8_t uResult;
1440 uint32_t fEflTmp;
1441 do
1442 {
1443 uResult = uOld;
1444 fEflTmp = *pfEFlags;
1445 iemAImpl_add_u8(&uResult, *puReg, &fEflTmp);
1446 } while (!ASMAtomicCmpXchgExU8(puDst, uResult, uOld, &uOld));
1447 *puReg = uOld;
1448 *pfEFlags = fEflTmp;
1449}
1450
1451# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1452#endif
1453
1454/*
1455 * CMPXCHG, CMPXCHG8B, CMPXCHG16B
1456 *
1457 * Note! We don't have non-locking/atomic cmpxchg primitives, so all cmpxchg
1458 * instructions are emulated as locked.
1459 */
1460#if defined(IEM_WITHOUT_ASSEMBLY)
1461
1462IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1463{
1464 uint8_t const uOld = *puAl;
1465 if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
1466 {
1467 Assert(*puAl == uOld);
1468 *pEFlags |= X86_EFL_ZF;
1469 }
1470 else
1471 *pEFlags &= ~X86_EFL_ZF;
1472}
1473
1474
1475IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1476{
1477 uint16_t const uOld = *puAx;
1478 if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
1479 {
1480 Assert(*puAx == uOld);
1481 *pEFlags |= X86_EFL_ZF;
1482 }
1483 else
1484 *pEFlags &= ~X86_EFL_ZF;
1485}
1486
1487
1488IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1489{
1490 uint32_t const uOld = *puEax;
1491 if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
1492 {
1493 Assert(*puEax == uOld);
1494 *pEFlags |= X86_EFL_ZF;
1495 }
1496 else
1497 *pEFlags &= ~X86_EFL_ZF;
1498}
1499
1500
1501# if ARCH_BITS == 32
1502IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
1503# else
1504IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1505# endif
1506{
1507# if ARCH_BITS == 32
1508 uint64_t const uSrcReg = *puSrcReg;
1509# endif
1510 uint64_t const uOld = *puRax;
1511 if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
1512 {
1513 Assert(*puRax == uOld);
1514 *pEFlags |= X86_EFL_ZF;
1515 }
1516 else
1517 *pEFlags &= ~X86_EFL_ZF;
1518}
1519
1520
1521IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1522 uint32_t *pEFlags))
1523{
1524 uint64_t const uNew = pu64EbxEcx->u;
1525 uint64_t const uOld = pu64EaxEdx->u;
1526 if (ASMAtomicCmpXchgExU64(pu64Dst, uNew, uOld, &pu64EaxEdx->u))
1527 {
1528 Assert(pu64EaxEdx->u == uOld);
1529 *pEFlags |= X86_EFL_ZF;
1530 }
1531 else
1532 *pEFlags &= ~X86_EFL_ZF;
1533}
1534
1535
1536# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_ARM64)
1537IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1538 uint32_t *pEFlags))
1539{
1540# ifdef VBOX_STRICT
1541 RTUINT128U const uOld = *pu128RaxRdx;
1542# endif
1543# if defined(RT_ARCH_AMD64)
1544 if (ASMAtomicCmpXchgU128v2(&pu128Dst->u, pu128RbxRcx->s.Hi, pu128RbxRcx->s.Lo, pu128RaxRdx->s.Hi, pu128RaxRdx->s.Lo,
1545 &pu128RaxRdx->u))
1546# else
1547 if (ASMAtomicCmpXchgU128(&pu128Dst->u, pu128RbxRcx->u, pu128RaxRdx->u, &pu128RaxRdx->u))
1548# endif
1549 {
1550 Assert(pu128RaxRdx->s.Lo == uOld.s.Lo && pu128RaxRdx->s.Hi == uOld.s.Hi);
1551 *pEFlags |= X86_EFL_ZF;
1552 }
1553 else
1554 *pEFlags &= ~X86_EFL_ZF;
1555}
1556# endif
1557
1558#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1559
1560# if !defined(RT_ARCH_ARM64) /** @todo may need this for unaligned accesses... */
1561IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1562 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
1563{
1564 RTUINT128U u128Tmp = *pu128Dst;
1565 if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
1566 && u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
1567 {
1568 *pu128Dst = *pu128RbxRcx;
1569 *pEFlags |= X86_EFL_ZF;
1570 }
1571 else
1572 {
1573 *pu128RaxRdx = u128Tmp;
1574 *pEFlags &= ~X86_EFL_ZF;
1575 }
1576}
1577#endif /* !RT_ARCH_ARM64 */
1578
1579#if defined(IEM_WITHOUT_ASSEMBLY)
1580
1581/* Unlocked versions mapped to the locked ones: */
1582
1583IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1584{
1585 iemAImpl_cmpxchg_u8_locked(pu8Dst, puAl, uSrcReg, pEFlags);
1586}
1587
1588
1589IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1590{
1591 iemAImpl_cmpxchg_u16_locked(pu16Dst, puAx, uSrcReg, pEFlags);
1592}
1593
1594
1595IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1596{
1597 iemAImpl_cmpxchg_u32_locked(pu32Dst, puEax, uSrcReg, pEFlags);
1598}
1599
1600
1601# if ARCH_BITS == 32
1602IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
1603{
1604 iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, puSrcReg, pEFlags);
1605}
1606# else
1607IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1608{
1609 iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, uSrcReg, pEFlags);
1610}
1611# endif
1612
1613
1614IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx, uint32_t *pEFlags))
1615{
1616 iemAImpl_cmpxchg8b_locked(pu64Dst, pu64EaxEdx, pu64EbxEcx, pEFlags);
1617}
1618
1619
1620IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1621 uint32_t *pEFlags))
1622{
1623 iemAImpl_cmpxchg16b_locked(pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
1624}
1625
1626#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1627
1628#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
1629
1630/*
1631 * MUL, IMUL, DIV and IDIV helpers.
1632 *
1633 * - The U64 versions must use 128-bit intermediates, so we need to abstract the
1634 * division step so we can select between using C operators and
1635 * RTUInt128DivRem/RTUInt128MulU64ByU64.
1636 *
1637 * - The U8 versions work returns output in AL + AH instead of xDX + xAX, with the
1638 * IDIV/DIV taking all the input in AX too. This means we have to abstract some
1639 * input loads and the result storing.
1640 */
1641
1642DECLINLINE(void) RTUInt128DivRemByU64(PRTUINT128U pQuotient, PRTUINT128U pRemainder, PCRTUINT128U pDividend, uint64_t u64Divisor)
1643{
1644# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1645 pQuotient->s.Lo = 0;
1646 pQuotient->s.Hi = 0;
1647# endif
1648 RTUINT128U Divisor;
1649 Divisor.s.Lo = u64Divisor;
1650 Divisor.s.Hi = 0;
1651 RTUInt128DivRem(pQuotient, pRemainder, pDividend, &Divisor);
1652}
1653
1654# define DIV_LOAD(a_Dividend) \
1655 a_Dividend.s.Lo = *puA, a_Dividend.s.Hi = *puD
1656# define DIV_LOAD_U8(a_Dividend) \
1657 a_Dividend.u = *puAX
1658
1659# define DIV_STORE(a_Quotient, a_uReminder) *puA = (a_Quotient), *puD = (a_uReminder)
1660# define DIV_STORE_U8(a_Quotient, a_uReminder) *puAX = (a_Quotient) | ((uint16_t)(a_uReminder) << 8)
1661
1662# define MUL_LOAD_F1() *puA
1663# define MUL_LOAD_F1_U8() ((uint8_t)*puAX)
1664
1665# define MUL_STORE(a_Result) *puA = (a_Result).s.Lo, *puD = (a_Result).s.Hi
1666# define MUL_STORE_U8(a_Result) *puAX = a_Result.u
1667
1668# define MULDIV_NEG(a_Value, a_cBitsWidth2x) \
1669 (a_Value).u = UINT ## a_cBitsWidth2x ## _C(0) - (a_Value).u
1670# define MULDIV_NEG_U128(a_Value, a_cBitsWidth2x) \
1671 RTUInt128AssignNeg(&(a_Value))
1672
1673# define MULDIV_MUL(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1674 (a_Result).u = (uint ## a_cBitsWidth2x ## _t)(a_Factor1) * (a_Factor2)
1675# define MULDIV_MUL_U128(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1676 RTUInt128MulU64ByU64(&(a_Result), a_Factor1, a_Factor2);
1677
1678# define MULDIV_MODDIV(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1679 a_Quotient.u = (a_Dividend).u / (a_uDivisor), \
1680 a_Remainder.u = (a_Dividend).u % (a_uDivisor)
1681# define MULDIV_MODDIV_U128(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1682 RTUInt128DivRemByU64(&a_Quotient, &a_Remainder, &a_Dividend, a_uDivisor)
1683
1684
1685/*
1686 * MUL
1687 */
1688# define EMIT_MUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnMul) \
1689IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth, a_Args) \
1690{ \
1691 RTUINT ## a_cBitsWidth2x ## U Result; \
1692 a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
1693 a_fnStore(Result); \
1694 \
1695 /* MUL EFLAGS according to Skylake (similar to IMUL). */ \
1696 *pfEFlags &= ~(X86_EFL_SF | X86_EFL_CF | X86_EFL_OF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF); \
1697 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1698 *pfEFlags |= X86_EFL_SF; \
1699 *pfEFlags |= g_afParity[Result.s.Lo & 0xff]; /* (Skylake behaviour) */ \
1700 if (Result.s.Hi != 0) \
1701 *pfEFlags |= X86_EFL_CF | X86_EFL_OF; \
1702 return 0; \
1703}
1704EMIT_MUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL_U128)
1705# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1706EMIT_MUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1707EMIT_MUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1708EMIT_MUL(8, 16, (uint16_t *puAX, uint8_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_MUL)
1709# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1710
1711
1712/*
1713 * IMUL
1714 */
1715# define EMIT_IMUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul) \
1716IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth,a_Args) \
1717{ \
1718 RTUINT ## a_cBitsWidth2x ## U Result; \
1719 /* The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these \
1720 flags as is. Whereas Intel skylake always clear AF and ZF and calculates \
1721 SF and PF as per the lower half of the result. */ \
1722 uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF); \
1723 \
1724 uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
1725 if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
1726 { \
1727 if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1728 { \
1729 a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1730 if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1731 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1732 } \
1733 else \
1734 { \
1735 a_fnMul(Result, uFactor1, UINT ## a_cBitsWidth ## _C(0) - uFactor2, a_cBitsWidth2x); \
1736 if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1737 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1738 a_fnNeg(Result, a_cBitsWidth2x); \
1739 } \
1740 } \
1741 else \
1742 { \
1743 if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1744 { \
1745 a_fnMul(Result, UINT ## a_cBitsWidth ## _C(0) - uFactor1, uFactor2, a_cBitsWidth2x); \
1746 if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1747 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1748 a_fnNeg(Result, a_cBitsWidth2x); \
1749 } \
1750 else \
1751 { \
1752 /*a_fnMul(Result, UINT ## a_cBitsWidth ## _C(0) - uFactor1, UINT ## a_cBitsWidth ## _C(0) - uFactor2, a_cBitsWidth2x);*/ \
1753 a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1754 if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1755 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1756 } \
1757 } \
1758 a_fnStore(Result); \
1759 if (false) \
1760 { /* Intel (skylake) flags "undefined" behaviour: */ \
1761 fEfl &= ~(X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_PF); \
1762 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1763 fEfl |= X86_EFL_SF; \
1764 fEfl |= g_afParity[Result.s.Lo & 0xff]; \
1765 } \
1766 *pfEFlags = fEfl; \
1767 return 0; \
1768}
1769/** @todo Testcase: IMUL 2 and 3 operands. */
1770EMIT_IMUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG_U128, MULDIV_MUL_U128)
1771# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1772EMIT_IMUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1773EMIT_IMUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1774EMIT_IMUL(8, 16, (uint16_t *puAX, uint8_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_NEG, MULDIV_MUL)
1775# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1776
1777
1778IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1779{
1780 uint64_t uIgn;
1781 iemAImpl_imul_u64(puDst, &uIgn, uSrc, pfEFlags);
1782}
1783
1784# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1785
1786IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1787{
1788 uint32_t uIgn;
1789 iemAImpl_imul_u32(puDst, &uIgn, uSrc, pfEFlags);
1790}
1791
1792
1793IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1794{
1795 uint16_t uIgn;
1796 iemAImpl_imul_u16(puDst, &uIgn, uSrc, pfEFlags);
1797}
1798
1799#endif
1800
1801/*
1802 * DIV
1803 */
1804# define EMIT_DIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnDivRem) \
1805IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth,a_Args) \
1806{ \
1807 /* Note! Skylake leaves all flags alone. */ \
1808 RT_NOREF_PV(pfEFlags); \
1809 \
1810 RTUINT ## a_cBitsWidth2x ## U Dividend; \
1811 a_fnLoad(Dividend); \
1812 if ( uDivisor != 0 \
1813 && Dividend.s.Hi < uDivisor) \
1814 { \
1815 RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1816 a_fnDivRem(Remainder, Quotient, Dividend, uDivisor); \
1817 a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1818 /** @todo research the undefined DIV flags. */ \
1819 return 0; \
1820 } \
1821 /* #DE */ \
1822 return -1; \
1823}
1824EMIT_DIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV_U128)
1825# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1826EMIT_DIV(32,64, (uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1827EMIT_DIV(16,32, (uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1828EMIT_DIV(8,16, (uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_MODDIV)
1829# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1830
1831
1832/*
1833 * IDIV
1834 */
1835# define EMIT_IDIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem) \
1836IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth,a_Args) \
1837{ \
1838 /* Note! Skylake leaves all flags alone. */ \
1839 RT_NOREF_PV(pfEFlags); \
1840 \
1841 /** @todo overflow checks */ \
1842 if (uDivisor != 0) \
1843 { \
1844 /* \
1845 * Convert to unsigned division. \
1846 */ \
1847 RTUINT ## a_cBitsWidth2x ## U Dividend; \
1848 a_fnLoad(Dividend); \
1849 if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi < 0) \
1850 a_fnNeg(Dividend, a_cBitsWidth2x); \
1851 \
1852 uint ## a_cBitsWidth ## _t uDivisorPositive; \
1853 if ((int ## a_cBitsWidth ## _t)uDivisor >= 0) \
1854 uDivisorPositive = uDivisor; \
1855 else \
1856 uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
1857 \
1858 RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1859 a_fnDivRem(Remainder, Quotient, Dividend, uDivisorPositive); \
1860 \
1861 /* \
1862 * Setup the result, checking for overflows. \
1863 */ \
1864 if ((int ## a_cBitsWidth ## _t)uDivisor >= 0) \
1865 { \
1866 if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi >= 0) \
1867 { \
1868 /* Positive divisor, positive dividend => result positive. */ \
1869 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1870 { \
1871 a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1872 return 0; \
1873 } \
1874 } \
1875 else \
1876 { \
1877 /* Positive divisor, positive dividend => result negative. */ \
1878 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1879 { \
1880 a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1881 return 0; \
1882 } \
1883 } \
1884 } \
1885 else \
1886 { \
1887 if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi >= 0) \
1888 { \
1889 /* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
1890 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1891 { \
1892 a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
1893 return 0; \
1894 } \
1895 } \
1896 else \
1897 { \
1898 /* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
1899 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1900 { \
1901 a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1902 return 0; \
1903 } \
1904 } \
1905 } \
1906 } \
1907 /* #DE */ \
1908 return -1; \
1909}
1910EMIT_IDIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG_U128, MULDIV_MODDIV_U128)
1911# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1912EMIT_IDIV(32,64,(uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1913EMIT_IDIV(16,32,(uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1914EMIT_IDIV(8,16,(uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_NEG, MULDIV_MODDIV)
1915# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1916
1917
1918/*********************************************************************************************************************************
1919* Unary operations. *
1920*********************************************************************************************************************************/
1921
1922/**
1923 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an INC or DEC instruction.
1924 *
1925 * CF is NOT modified for hysterical raisins (allegedly for carrying and
1926 * borrowing in arithmetic loops on intel 8008).
1927 *
1928 * @returns Status bits.
1929 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
1930 * @param a_uResult Unsigned result value.
1931 * @param a_uDst The original destination value (for AF calc).
1932 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
1933 * @param a_OfMethod 0 for INC-style, 1 for DEC-style.
1934 */
1935#define IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth, a_OfMethod) \
1936 do { \
1937 uint32_t fEflTmp = *(a_pfEFlags); \
1938 fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
1939 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
1940 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
1941 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
1942 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
1943 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth(a_OfMethod == 0 ? (((a_uDst) ^ RT_BIT_64(63)) & (a_uResult)) \
1944 : ((a_uDst) & ((a_uResult) ^ RT_BIT_64(63))) ); \
1945 *(a_pfEFlags) = fEflTmp; \
1946 } while (0)
1947
1948/*
1949 * INC
1950 */
1951
1952IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t *puDst, uint32_t *pfEFlags))
1953{
1954 uint64_t uDst = *puDst;
1955 uint64_t uResult = uDst + 1;
1956 *puDst = uResult;
1957 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 0 /*INC*/);
1958}
1959
1960# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1961
1962IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u32,(uint32_t *puDst, uint32_t *pfEFlags))
1963{
1964 uint32_t uDst = *puDst;
1965 uint32_t uResult = uDst + 1;
1966 *puDst = uResult;
1967 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 0 /*INC*/);
1968}
1969
1970
1971IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u16,(uint16_t *puDst, uint32_t *pfEFlags))
1972{
1973 uint16_t uDst = *puDst;
1974 uint16_t uResult = uDst + 1;
1975 *puDst = uResult;
1976 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 0 /*INC*/);
1977}
1978
1979IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u8,(uint8_t *puDst, uint32_t *pfEFlags))
1980{
1981 uint8_t uDst = *puDst;
1982 uint8_t uResult = uDst + 1;
1983 *puDst = uResult;
1984 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 0 /*INC*/);
1985}
1986
1987# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1988
1989
1990/*
1991 * DEC
1992 */
1993
1994IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t *puDst, uint32_t *pfEFlags))
1995{
1996 uint64_t uDst = *puDst;
1997 uint64_t uResult = uDst - 1;
1998 *puDst = uResult;
1999 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 1 /*INC*/);
2000}
2001
2002# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2003
2004IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2005{
2006 uint32_t uDst = *puDst;
2007 uint32_t uResult = uDst - 1;
2008 *puDst = uResult;
2009 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 1 /*INC*/);
2010}
2011
2012
2013IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2014{
2015 uint16_t uDst = *puDst;
2016 uint16_t uResult = uDst - 1;
2017 *puDst = uResult;
2018 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 1 /*INC*/);
2019}
2020
2021
2022IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2023{
2024 uint8_t uDst = *puDst;
2025 uint8_t uResult = uDst - 1;
2026 *puDst = uResult;
2027 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 1 /*INC*/);
2028}
2029
2030# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2031
2032
2033/*
2034 * NOT
2035 */
2036
2037IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t *puDst, uint32_t *pfEFlags))
2038{
2039 uint64_t uDst = *puDst;
2040 uint64_t uResult = ~uDst;
2041 *puDst = uResult;
2042 /* EFLAGS are not modified. */
2043 RT_NOREF_PV(pfEFlags);
2044}
2045
2046# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2047
2048IEM_DECL_IMPL_DEF(void, iemAImpl_not_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2049{
2050 uint32_t uDst = *puDst;
2051 uint32_t uResult = ~uDst;
2052 *puDst = uResult;
2053 /* EFLAGS are not modified. */
2054 RT_NOREF_PV(pfEFlags);
2055}
2056
2057IEM_DECL_IMPL_DEF(void, iemAImpl_not_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2058{
2059 uint16_t uDst = *puDst;
2060 uint16_t uResult = ~uDst;
2061 *puDst = uResult;
2062 /* EFLAGS are not modified. */
2063 RT_NOREF_PV(pfEFlags);
2064}
2065
2066IEM_DECL_IMPL_DEF(void, iemAImpl_not_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2067{
2068 uint8_t uDst = *puDst;
2069 uint8_t uResult = ~uDst;
2070 *puDst = uResult;
2071 /* EFLAGS are not modified. */
2072 RT_NOREF_PV(pfEFlags);
2073}
2074
2075# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2076
2077
2078/*
2079 * NEG
2080 */
2081
2082/**
2083 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an NEG instruction.
2084 *
2085 * @returns Status bits.
2086 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2087 * @param a_uResult Unsigned result value.
2088 * @param a_uDst The original destination value (for AF calc).
2089 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2090 */
2091#define IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth) \
2092 do { \
2093 uint32_t fEflTmp = *(a_pfEFlags); \
2094 fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
2095 fEflTmp |= ((a_uDst) != 0) << X86_EFL_CF_BIT; \
2096 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
2097 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
2098 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
2099 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
2100 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth((a_uDst) & (a_uResult)); \
2101 *(a_pfEFlags) = fEflTmp; \
2102 } while (0)
2103
2104IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t *puDst, uint32_t *pfEFlags))
2105{
2106 uint64_t uDst = *puDst;
2107 uint64_t uResult = (uint64_t)0 - uDst;
2108 *puDst = uResult;
2109 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 64);
2110}
2111
2112# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2113
2114IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2115{
2116 uint32_t uDst = *puDst;
2117 uint32_t uResult = (uint32_t)0 - uDst;
2118 *puDst = uResult;
2119 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 32);
2120}
2121
2122
2123IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2124{
2125 uint16_t uDst = *puDst;
2126 uint16_t uResult = (uint16_t)0 - uDst;
2127 *puDst = uResult;
2128 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 16);
2129}
2130
2131
2132IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2133{
2134 uint8_t uDst = *puDst;
2135 uint8_t uResult = (uint8_t)0 - uDst;
2136 *puDst = uResult;
2137 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 8);
2138}
2139
2140# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2141
2142/*
2143 * Locked variants.
2144 */
2145
2146/** Emit a function for doing a locked unary operand operation. */
2147# define EMIT_LOCKED_UNARY_OP(a_Mnemonic, a_cBitsWidth) \
2148 IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
2149 uint32_t *pfEFlags)) \
2150 { \
2151 uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
2152 uint ## a_cBitsWidth ## _t uTmp; \
2153 uint32_t fEflTmp; \
2154 do \
2155 { \
2156 uTmp = uOld; \
2157 fEflTmp = *pfEFlags; \
2158 iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, &fEflTmp); \
2159 } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
2160 *pfEFlags = fEflTmp; \
2161 }
2162
2163EMIT_LOCKED_UNARY_OP(inc, 64)
2164EMIT_LOCKED_UNARY_OP(dec, 64)
2165EMIT_LOCKED_UNARY_OP(not, 64)
2166EMIT_LOCKED_UNARY_OP(neg, 64)
2167# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2168EMIT_LOCKED_UNARY_OP(inc, 32)
2169EMIT_LOCKED_UNARY_OP(dec, 32)
2170EMIT_LOCKED_UNARY_OP(not, 32)
2171EMIT_LOCKED_UNARY_OP(neg, 32)
2172
2173EMIT_LOCKED_UNARY_OP(inc, 16)
2174EMIT_LOCKED_UNARY_OP(dec, 16)
2175EMIT_LOCKED_UNARY_OP(not, 16)
2176EMIT_LOCKED_UNARY_OP(neg, 16)
2177
2178EMIT_LOCKED_UNARY_OP(inc, 8)
2179EMIT_LOCKED_UNARY_OP(dec, 8)
2180EMIT_LOCKED_UNARY_OP(not, 8)
2181EMIT_LOCKED_UNARY_OP(neg, 8)
2182# endif
2183
2184
2185/*********************************************************************************************************************************
2186* Shifting and Rotating *
2187*********************************************************************************************************************************/
2188
2189/*
2190 * ROL
2191 */
2192
2193/**
2194 * Updates the status bits (OF and CF) for an ROL instruction.
2195 *
2196 * @returns Status bits.
2197 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2198 * @param a_uResult Unsigned result value.
2199 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2200 */
2201#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2202 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2203 it the same way as for 1 bit shifts. */ \
2204 AssertCompile(X86_EFL_CF_BIT == 0); \
2205 uint32_t fEflTmp = *(a_pfEFlags); \
2206 fEflTmp &= ~(X86_EFL_CF | X86_EFL_OF); \
2207 uint32_t const fCarry = ((a_uResult) & X86_EFL_CF); \
2208 fEflTmp |= fCarry; \
2209 fEflTmp |= (((a_uResult) >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2210 *(a_pfEFlags) = fEflTmp; \
2211 } while (0)
2212
2213IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2214{
2215 cShift &= 63;
2216 if (cShift)
2217 {
2218 uint64_t uResult = ASMRotateLeftU64(*puDst, cShift);
2219 *puDst = uResult;
2220 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 64);
2221 }
2222}
2223
2224# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2225
2226IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u32,(uint32_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2227{
2228 cShift &= 31;
2229 if (cShift)
2230 {
2231 uint32_t uResult = ASMRotateLeftU32(*puDst, cShift);
2232 *puDst = uResult;
2233 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 32);
2234 }
2235}
2236
2237
2238IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u16,(uint16_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2239{
2240 cShift &= 15;
2241 if (cShift)
2242 {
2243 uint16_t uDst = *puDst;
2244 uint16_t uResult = (uDst << cShift) | (uDst >> (16 - cShift));
2245 *puDst = uResult;
2246 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 16);
2247 }
2248}
2249
2250
2251IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u8,(uint8_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2252{
2253 cShift &= 7;
2254 if (cShift)
2255 {
2256 uint8_t uDst = *puDst;
2257 uint8_t uResult = (uDst << cShift) | (uDst >> (8 - cShift));
2258 *puDst = uResult;
2259 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 8);
2260 }
2261}
2262
2263# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2264
2265
2266/*
2267 * ROR
2268 */
2269
2270/**
2271 * Updates the status bits (OF and CF) for an ROL instruction.
2272 *
2273 * @returns Status bits.
2274 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2275 * @param a_uResult Unsigned result value.
2276 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2277 */
2278#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2279 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2280 it the same way as for 1 bit shifts. */ \
2281 AssertCompile(X86_EFL_CF_BIT == 0); \
2282 uint32_t fEflTmp = *(a_pfEFlags); \
2283 fEflTmp &= ~(X86_EFL_CF | X86_EFL_OF); \
2284 uint32_t const fCarry = ((a_uResult) >> ((a_cBitsWidth) - 1)) & X86_EFL_CF; \
2285 fEflTmp |= fCarry; \
2286 fEflTmp |= (((a_uResult) >> ((a_cBitsWidth) - 2)) ^ fCarry) << X86_EFL_OF_BIT; \
2287 *(a_pfEFlags) = fEflTmp; \
2288 } while (0)
2289
2290IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2291{
2292 cShift &= 63;
2293 if (cShift)
2294 {
2295 uint64_t const uResult = ASMRotateRightU64(*puDst, cShift);
2296 *puDst = uResult;
2297 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 64);
2298 }
2299}
2300
2301# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2302
2303IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u32,(uint32_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2304{
2305 cShift &= 31;
2306 if (cShift)
2307 {
2308 uint64_t const uResult = ASMRotateRightU32(*puDst, cShift);
2309 *puDst = uResult;
2310 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 32);
2311 }
2312}
2313
2314
2315IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u16,(uint16_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2316{
2317 cShift &= 15;
2318 if (cShift)
2319 {
2320 uint16_t uDst = *puDst;
2321 uint16_t uResult;
2322 uResult = uDst >> cShift;
2323 uResult |= uDst << (16 - cShift);
2324 *puDst = uResult;
2325 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 16);
2326 }
2327}
2328
2329
2330IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u8,(uint8_t *puDst, uint8_t cShift, uint32_t *pfEFlags))
2331{
2332 cShift &= 7;
2333 if (cShift)
2334 {
2335 uint8_t uDst = *puDst;
2336 uint8_t uResult;
2337 uResult = uDst >> cShift;
2338 uResult |= uDst << (8 - cShift);
2339 *puDst = uResult;
2340 IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 8);
2341 }
2342}
2343
2344# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2345
2346
2347/*
2348 * RCL
2349 */
2350#define EMIT_RCL(a_cBitsWidth) \
2351IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2352{ \
2353 cShift &= a_cBitsWidth - 1; \
2354 if (cShift) \
2355 { \
2356 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2357 uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2358 if (cShift > 1) \
2359 uResult |= uDst >> (a_cBitsWidth + 1 - cShift); \
2360 \
2361 uint32_t fEfl = *pfEFlags; \
2362 AssertCompile(X86_EFL_CF_BIT == 0); \
2363 uResult |= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (cShift - 1); \
2364 \
2365 *puDst = uResult; \
2366 \
2367 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2368 it the same way as for 1 bit shifts. */ \
2369 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2370 uint32_t const fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2371 fEfl |= fCarry; \
2372 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2373 *pfEFlags = fEfl; \
2374 } \
2375}
2376EMIT_RCL(64)
2377# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2378EMIT_RCL(32)
2379EMIT_RCL(16)
2380EMIT_RCL(8)
2381# endif
2382
2383
2384/*
2385 * RCR
2386 */
2387#define EMIT_RCR(a_cBitsWidth) \
2388IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ##_t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2389{ \
2390 cShift &= a_cBitsWidth - 1; \
2391 if (cShift) \
2392 { \
2393 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2394 uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2395 if (cShift > 1) \
2396 uResult |= uDst << (a_cBitsWidth + 1 - cShift); \
2397 \
2398 AssertCompile(X86_EFL_CF_BIT == 0); \
2399 uint32_t fEfl = *pfEFlags; \
2400 uResult |= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (a_cBitsWidth - cShift); \
2401 *puDst = uResult; \
2402 \
2403 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2404 it the same way as for 1 bit shifts. */ \
2405 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2406 uint32_t const fCarry = (uDst >> (cShift - 1)) & X86_EFL_CF; \
2407 fEfl |= fCarry; \
2408 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2409 *pfEFlags = fEfl; \
2410 } \
2411}
2412EMIT_RCR(64)
2413# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2414EMIT_RCR(32)
2415EMIT_RCR(16)
2416EMIT_RCR(8)
2417# endif
2418
2419
2420/*
2421 * SHL
2422 */
2423#define EMIT_SHL(a_cBitsWidth) \
2424IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2425{ \
2426 cShift &= a_cBitsWidth - 1; \
2427 if (cShift) \
2428 { \
2429 uint ## a_cBitsWidth ##_t const uDst = *puDst; \
2430 uint ## a_cBitsWidth ##_t uResult = uDst << cShift; \
2431 *puDst = uResult; \
2432 \
2433 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2434 it the same way as for 1 bit shifts. The AF bit is undefined, we \
2435 always set it to zero atm. */ \
2436 AssertCompile(X86_EFL_CF_BIT == 0); \
2437 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2438 uint32_t fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2439 fEfl |= fCarry; \
2440 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2441 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2442 fEfl |= X86_EFL_CALC_ZF(uResult); \
2443 fEfl |= g_afParity[uResult & 0xff]; \
2444 *pfEFlags = fEfl; \
2445 } \
2446}
2447EMIT_SHL(64)
2448# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2449EMIT_SHL(32)
2450EMIT_SHL(16)
2451EMIT_SHL(8)
2452# endif
2453
2454
2455/*
2456 * SHR
2457 */
2458#define EMIT_SHR(a_cBitsWidth) \
2459IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2460{ \
2461 cShift &= a_cBitsWidth - 1; \
2462 if (cShift) \
2463 { \
2464 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2465 uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2466 *puDst = uResult; \
2467 \
2468 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2469 it the same way as for 1 bit shifts. The AF bit is undefined, we \
2470 always set it to zero atm. */ \
2471 AssertCompile(X86_EFL_CF_BIT == 0); \
2472 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2473 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2474 fEfl |= (uDst >> (a_cBitsWidth - 1)) << X86_EFL_OF_BIT; \
2475 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2476 fEfl |= X86_EFL_CALC_ZF(uResult); \
2477 fEfl |= g_afParity[uResult & 0xff]; \
2478 *pfEFlags = fEfl; \
2479 } \
2480}
2481EMIT_SHR(64)
2482# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2483EMIT_SHR(32)
2484EMIT_SHR(16)
2485EMIT_SHR(8)
2486# endif
2487
2488
2489/*
2490 * SAR
2491 */
2492#define EMIT_SAR(a_cBitsWidth) \
2493IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2494{ \
2495 cShift &= a_cBitsWidth - 1; \
2496 if (cShift) \
2497 { \
2498 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2499 uint ## a_cBitsWidth ## _t uResult = (int ## a_cBitsWidth ## _t)uDst >> cShift; \
2500 *puDst = uResult; \
2501 \
2502 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2503 it the same way as for 1 bit shifts (0). The AF bit is undefined, \
2504 we always set it to zero atm. */ \
2505 AssertCompile(X86_EFL_CF_BIT == 0); \
2506 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2507 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2508 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2509 fEfl |= X86_EFL_CALC_ZF(uResult); \
2510 fEfl |= g_afParity[uResult & 0xff]; \
2511 *pfEFlags = fEfl; \
2512 } \
2513}
2514EMIT_SAR(64)
2515# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2516EMIT_SAR(32)
2517EMIT_SAR(16)
2518EMIT_SAR(8)
2519# endif
2520
2521
2522/*
2523 * SHLD
2524 */
2525#define EMIT_SHLD(a_cBitsWidth) \
2526IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2527 uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2528{ \
2529 cShift &= a_cBitsWidth - 1; \
2530 if (cShift) \
2531 { \
2532 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2533 uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2534 uResult |= uSrc >> (a_cBitsWidth - cShift); \
2535 *puDst = uResult; \
2536 \
2537 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2538 it the same way as for 1 bit shifts. The AF bit is undefined, \
2539 we always set it to zero atm. */ \
2540 AssertCompile(X86_EFL_CF_BIT == 0); \
2541 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2542 fEfl |= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2543 fEfl |= (uint32_t)((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))) << X86_EFL_OF_BIT; \
2544 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2545 fEfl |= X86_EFL_CALC_ZF(uResult); \
2546 fEfl |= g_afParity[uResult & 0xff]; \
2547 *pfEFlags = fEfl; \
2548 } \
2549}
2550EMIT_SHLD(64)
2551# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2552EMIT_SHLD(32)
2553EMIT_SHLD(16)
2554EMIT_SHLD(8)
2555# endif
2556
2557
2558/*
2559 * SHRD
2560 */
2561#define EMIT_SHRD(a_cBitsWidth) \
2562IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2563 uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2564{ \
2565 cShift &= a_cBitsWidth - 1; \
2566 if (cShift) \
2567 { \
2568 uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2569 uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2570 uResult |= uSrc << (a_cBitsWidth - cShift); \
2571 *puDst = uResult; \
2572 \
2573 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2574 it the same way as for 1 bit shifts. The AF bit is undefined, \
2575 we always set it to zero atm. */ \
2576 AssertCompile(X86_EFL_CF_BIT == 0); \
2577 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2578 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2579 fEfl |= (uint32_t)((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))) << X86_EFL_OF_BIT; \
2580 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2581 fEfl |= X86_EFL_CALC_ZF(uResult); \
2582 fEfl |= g_afParity[uResult & 0xff]; \
2583 *pfEFlags = fEfl; \
2584 } \
2585}
2586EMIT_SHRD(64)
2587# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2588EMIT_SHRD(32)
2589EMIT_SHRD(16)
2590EMIT_SHRD(8)
2591# endif
2592
2593
2594# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2595/*
2596 * BSWAP
2597 */
2598
2599IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u64,(uint64_t *puDst))
2600{
2601 *puDst = ASMByteSwapU64(*puDst);
2602}
2603
2604
2605IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u32,(uint32_t *puDst))
2606{
2607 *puDst = ASMByteSwapU32(*puDst);
2608}
2609
2610
2611/* Note! undocument, so 32-bit arg */
2612IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u16,(uint32_t *puDst))
2613{
2614 *puDst = ASMByteSwapU16((uint16_t)*puDst) | (*puDst & UINT32_C(0xffff0000));
2615}
2616
2617# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2618
2619
2620
2621# if defined(IEM_WITHOUT_ASSEMBLY)
2622
2623/*
2624 * LFENCE, SFENCE & MFENCE.
2625 */
2626
2627IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void))
2628{
2629 ASMReadFence();
2630}
2631
2632
2633IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void))
2634{
2635 ASMWriteFence();
2636}
2637
2638
2639IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void))
2640{
2641 ASMMemoryFence();
2642}
2643
2644
2645# ifndef RT_ARCH_ARM64
2646IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void))
2647{
2648 ASMMemoryFence();
2649}
2650# endif
2651
2652# endif
2653
2654#endif /* !RT_ARCH_AMD64 || IEM_WITHOUT_ASSEMBLY */
2655
2656
2657IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pfEFlags))
2658{
2659 if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
2660 {
2661 *pu16Dst &= X86_SEL_MASK_OFF_RPL;
2662 *pu16Dst |= u16Src & X86_SEL_RPL;
2663
2664 *pfEFlags |= X86_EFL_ZF;
2665 }
2666 else
2667 *pfEFlags &= ~X86_EFL_ZF;
2668}
2669
2670
2671/*********************************************************************************************************************************
2672* x87 FPU *
2673*********************************************************************************************************************************/
2674#if defined(IEM_WITHOUT_ASSEMBLY)
2675
2676IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2677{
2678 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2679 AssertReleaseFailed();
2680}
2681
2682
2683IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2684{
2685 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2686 AssertReleaseFailed();
2687}
2688
2689
2690IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2691 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2692{
2693 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2694 AssertReleaseFailed();
2695}
2696
2697
2698IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2699 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2700{
2701 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2702 AssertReleaseFailed();
2703}
2704
2705
2706IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2707 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2708{
2709 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2710 AssertReleaseFailed();
2711}
2712
2713
2714IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2715{
2716 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2717 AssertReleaseFailed();
2718}
2719
2720
2721IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2722 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2723{
2724 RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
2725 AssertReleaseFailed();
2726}
2727
2728
2729IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2730 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2731{
2732 RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
2733 AssertReleaseFailed();
2734}
2735
2736
2737IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2738 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2739{
2740 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2741 AssertReleaseFailed();
2742}
2743
2744
2745IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2746 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2747{
2748 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2749 AssertReleaseFailed();
2750 return 0;
2751}
2752
2753
2754IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2755{
2756 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2757 AssertReleaseFailed();
2758}
2759
2760
2761IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2762 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2763{
2764 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2765 AssertReleaseFailed();
2766}
2767
2768
2769IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2770 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2771{
2772 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2773 AssertReleaseFailed();
2774}
2775
2776
2777IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2778 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2779{
2780 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2781 AssertReleaseFailed();
2782}
2783
2784
2785IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2786 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2787{
2788 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2789 AssertReleaseFailed();
2790}
2791
2792
2793IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2794 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2795{
2796 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2797 AssertReleaseFailed();
2798}
2799
2800
2801IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2802 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2803{
2804 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2805 AssertReleaseFailed();
2806}
2807
2808
2809IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2810 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2811{
2812 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2813 AssertReleaseFailed();
2814}
2815
2816
2817IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2818 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2819{
2820 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2821 AssertReleaseFailed();
2822}
2823
2824
2825IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2826 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2827{
2828 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
2829 AssertReleaseFailed();
2830}
2831
2832
2833IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2834 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2835{
2836 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
2837 AssertReleaseFailed();
2838}
2839
2840
2841IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2842 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2843{
2844 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2845 AssertReleaseFailed();
2846}
2847
2848
2849IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2850 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2851{
2852 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2853 AssertReleaseFailed();
2854}
2855
2856
2857IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2858 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2859{
2860 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2861 AssertReleaseFailed();
2862}
2863
2864
2865IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2866 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2867{
2868 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2869 AssertReleaseFailed();
2870}
2871
2872
2873IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
2874{
2875 RT_NOREF(pFpuState, pFpuRes, pi16Val);
2876 AssertReleaseFailed();
2877}
2878
2879
2880IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
2881{
2882 RT_NOREF(pFpuState, pFpuRes, pi32Val);
2883 AssertReleaseFailed();
2884}
2885
2886
2887IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
2888{
2889 RT_NOREF(pFpuState, pFpuRes, pi64Val);
2890 AssertReleaseFailed();
2891}
2892
2893
2894IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2895 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2896{
2897 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2898 AssertReleaseFailed();
2899}
2900
2901
2902IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2903 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2904{
2905 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2906 AssertReleaseFailed();
2907}
2908
2909
2910IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2911 int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2912{
2913 RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2914 AssertReleaseFailed();
2915}
2916
2917
2918IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2919 int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2920{
2921 RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2922 AssertReleaseFailed();
2923}
2924
2925
2926IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2927 int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2928{
2929 RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2930 AssertReleaseFailed();
2931}
2932
2933
2934IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2935 int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2936{
2937 RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2938 AssertReleaseFailed();
2939}
2940
2941
2942IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2943 int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2944{
2945 RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2946 AssertReleaseFailed();
2947}
2948
2949
2950IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2951 int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2952{
2953 RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2954 AssertReleaseFailed();
2955}
2956
2957
2958IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2959 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2960{
2961 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2962 AssertReleaseFailed();
2963}
2964
2965
2966IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2967 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2968{
2969 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2970 AssertReleaseFailed();
2971}
2972
2973
2974IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2975 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2976{
2977 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2978 AssertReleaseFailed();
2979}
2980
2981
2982IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2983 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2984{
2985 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2986 AssertReleaseFailed();
2987}
2988
2989
2990IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
2991{
2992 RT_NOREF(pFpuState, pFpuRes, pr32Val);
2993 AssertReleaseFailed();
2994}
2995
2996
2997IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
2998{
2999 RT_NOREF(pFpuState, pFpuRes, pr64Val);
3000 AssertReleaseFailed();
3001}
3002
3003IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3004{
3005 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3006 AssertReleaseFailed();
3007}
3008
3009
3010IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3011{
3012 RT_NOREF(pFpuState, pFpuRes);
3013 AssertReleaseFailed();
3014}
3015
3016
3017IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3018{
3019 RT_NOREF(pFpuState, pFpuRes);
3020 AssertReleaseFailed();
3021}
3022
3023
3024IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3025{
3026 RT_NOREF(pFpuState, pFpuRes);
3027 AssertReleaseFailed();
3028}
3029
3030
3031IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3032{
3033 RT_NOREF(pFpuState, pFpuRes);
3034 AssertReleaseFailed();
3035}
3036
3037
3038IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3039{
3040 RT_NOREF(pFpuState, pFpuRes);
3041 AssertReleaseFailed();
3042}
3043
3044
3045IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3046{
3047 RT_NOREF(pFpuState, pFpuRes);
3048 AssertReleaseFailed();
3049}
3050
3051
3052IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3053{
3054 RT_NOREF(pFpuState, pFpuRes);
3055 AssertReleaseFailed();
3056}
3057
3058
3059IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3060 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3061{
3062 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3063 AssertReleaseFailed();
3064}
3065
3066
3067IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3068 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3069{
3070 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3071 AssertReleaseFailed();
3072}
3073
3074
3075IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3076 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3077{
3078 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3079 AssertReleaseFailed();
3080}
3081
3082
3083IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3084 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3085{
3086 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3087 AssertReleaseFailed();
3088}
3089
3090
3091IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3092 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3093{
3094 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3095 AssertReleaseFailed();
3096}
3097
3098
3099IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3100 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3101{
3102 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3103 AssertReleaseFailed();
3104}
3105
3106
3107IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3108{
3109 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3110 AssertReleaseFailed();
3111}
3112
3113
3114IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3115{
3116 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3117 AssertReleaseFailed();
3118}
3119
3120
3121IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3122 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3123{
3124 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3125 AssertReleaseFailed();
3126}
3127
3128
3129IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3130{
3131 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3132 AssertReleaseFailed();
3133}
3134
3135
3136IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3137{
3138 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3139 AssertReleaseFailed();
3140}
3141
3142
3143IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3144{
3145 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3146 AssertReleaseFailed();
3147}
3148
3149
3150IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3151 PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
3152{
3153 RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
3154 AssertReleaseFailed();
3155}
3156
3157
3158IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3159 PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
3160{
3161 RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
3162 AssertReleaseFailed();
3163}
3164
3165
3166IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3167 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
3168{
3169 RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
3170 AssertReleaseFailed();
3171}
3172
3173
3174IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3175 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3176{
3177 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3178 AssertReleaseFailed();
3179}
3180
3181
3182IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3183 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3184{
3185 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3186 AssertReleaseFailed();
3187}
3188
3189
3190IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3191 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3192{
3193 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3194 AssertReleaseFailed();
3195}
3196
3197
3198IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3199 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3200{
3201 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3202 AssertReleaseFailed();
3203}
3204
3205
3206IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3207 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3208{
3209 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3210 AssertReleaseFailed();
3211}
3212
3213
3214IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3215 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3216{
3217 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3218 AssertReleaseFailed();
3219}
3220
3221
3222IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3223{
3224 RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3225 AssertReleaseFailed();
3226}
3227
3228
3229IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3230 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3231{
3232 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3233 AssertReleaseFailed();
3234}
3235
3236
3237IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3238 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3239{
3240 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
3241 AssertReleaseFailed();
3242 return 0;
3243}
3244
3245
3246IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3247{
3248 RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3249 AssertReleaseFailed();
3250}
3251
3252
3253IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3254{
3255 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3256 AssertReleaseFailed();
3257}
3258
3259
3260IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3261 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3262{
3263 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3264 AssertReleaseFailed();
3265}
3266
3267
3268IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3269 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3270{
3271 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3272 AssertReleaseFailed();
3273}
3274
3275#endif /* IEM_WITHOUT_ASSEMBLY */
3276
3277
3278/*********************************************************************************************************************************
3279* MMX, SSE & AVX *
3280*********************************************************************************************************************************/
3281
3282IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3283{
3284 RT_NOREF(pFpuState);
3285 puDst->au32[0] = puSrc->au32[0];
3286 puDst->au32[1] = puSrc->au32[0];
3287 puDst->au32[2] = puSrc->au32[2];
3288 puDst->au32[3] = puSrc->au32[2];
3289}
3290
3291#ifdef IEM_WITH_VEX
3292
3293IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3294{
3295 pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
3296 pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
3297 pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
3298 pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
3299 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3300 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3301 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3302 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3303}
3304
3305
3306IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3307{
3308 pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
3309 pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
3310 pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
3311 pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
3312 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
3313 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
3314 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
3315 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
3316}
3317
3318#endif /* IEM_WITH_VEX */
3319
3320
3321IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3322{
3323 RT_NOREF(pFpuState);
3324 puDst->au32[0] = puSrc->au32[1];
3325 puDst->au32[1] = puSrc->au32[1];
3326 puDst->au32[2] = puSrc->au32[3];
3327 puDst->au32[3] = puSrc->au32[3];
3328}
3329
3330
3331IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
3332{
3333 RT_NOREF(pFpuState);
3334 puDst->au64[0] = uSrc;
3335 puDst->au64[1] = uSrc;
3336}
3337
3338#ifdef IEM_WITH_VEX
3339
3340IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3341{
3342 pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
3343 pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
3344 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3345 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3346}
3347
3348IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3349{
3350 pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
3351 pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
3352 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
3353 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
3354}
3355
3356#endif /* IEM_WITH_VEX */
3357
3358#ifdef IEM_WITHOUT_ASSEMBLY
3359
3360IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3361{
3362 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3363 AssertReleaseFailed();
3364}
3365
3366
3367IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3368{
3369 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3370 AssertReleaseFailed();
3371}
3372
3373
3374IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3375{
3376 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3377 AssertReleaseFailed();
3378}
3379
3380
3381IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3382{
3383 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3384 AssertReleaseFailed();
3385}
3386
3387
3388IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3389{
3390 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3391 AssertReleaseFailed();
3392}
3393
3394
3395IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3396{
3397 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3398 AssertReleaseFailed();
3399}
3400
3401
3402IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3403{
3404 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3405 AssertReleaseFailed();
3406}
3407
3408
3409IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3410{
3411 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3412 AssertReleaseFailed();
3413}
3414
3415
3416IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3417{
3418 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3419 AssertReleaseFailed();
3420
3421}
3422
3423
3424IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src))
3425{
3426 RT_NOREF(pFpuState, pu64Dst, pu128Src);
3427 AssertReleaseFailed();
3428}
3429
3430
3431IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src, uint8_t bEvil))
3432{
3433 RT_NOREF(pFpuState, pu64Dst, pu64Src, bEvil);
3434 AssertReleaseFailed();
3435}
3436
3437
3438IEM_DECL_IMPL_DEF(void, iemAImpl_pshufhw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3439{
3440 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3441 AssertReleaseFailed();
3442}
3443
3444
3445IEM_DECL_IMPL_DEF(void, iemAImpl_pshuflw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3446{
3447 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3448 AssertReleaseFailed();
3449}
3450
3451
3452IEM_DECL_IMPL_DEF(void, iemAImpl_pshufd,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3453{
3454 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3455 AssertReleaseFailed();
3456}
3457
3458/* PUNPCKHxxx */
3459
3460IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3461{
3462 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3463 AssertReleaseFailed();
3464}
3465
3466
3467IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3468{
3469 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3470 AssertReleaseFailed();
3471}
3472
3473
3474IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3475{
3476 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3477 AssertReleaseFailed();
3478}
3479
3480
3481IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3482{
3483 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3484 AssertReleaseFailed();
3485}
3486
3487
3488IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3489{
3490 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3491 AssertReleaseFailed();
3492}
3493
3494
3495IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3496{
3497 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3498 AssertReleaseFailed();
3499}
3500
3501
3502IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3503{
3504 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3505 AssertReleaseFailed();
3506}
3507
3508/* PUNPCKLxxx */
3509
3510IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3511{
3512 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3513 AssertReleaseFailed();
3514}
3515
3516
3517IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3518{
3519 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3520 AssertReleaseFailed();
3521}
3522
3523
3524IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3525{
3526 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3527 AssertReleaseFailed();
3528}
3529
3530
3531IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3532{
3533 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3534 AssertReleaseFailed();
3535}
3536
3537
3538IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3539{
3540 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3541 AssertReleaseFailed();
3542}
3543
3544
3545IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3546{
3547 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3548 AssertReleaseFailed();
3549}
3550
3551
3552IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3553{
3554 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3555 AssertReleaseFailed();
3556}
3557
3558#endif /* IEM_WITHOUT_ASSEMBLY */
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