IEMAllAImplC.cpp@ 93878

Last change on this file since 93878 was 93878, checked in by vboxsync, 3 years ago
VMM/IEM: Simplified XADD impl. bugref:9898
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1	/* $Id: IEMAllAImplC.cpp 93878 2022-02-21 20:52:59Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Implementation in Assembly, portable C variant.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include "IEMInternal.h"
23	#include <VBox/vmm/vmcc.h>
24	#include <iprt/errcore.h>
25	#include <iprt/x86.h>
26	#include <iprt/uint128.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** @def IEM_WITHOUT_ASSEMBLY
33	* Enables all the code in this file.
34	*/
35	#if !defined(IEM_WITHOUT_ASSEMBLY)
36	# if defined(RT_ARCH_ARM32) \|\| defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
37	# define IEM_WITHOUT_ASSEMBLY
38	# endif
39	#endif
40	/* IEM_WITH_ASSEMBLY trumps IEM_WITHOUT_ASSEMBLY for tstIEMAImplAsm purposes. */
41	#ifdef IEM_WITH_ASSEMBLY
42	# undef IEM_WITHOUT_ASSEMBLY
43	#endif
44
45	/**
46	* Calculates the signed flag value given a result and it's bit width.
47	*
48	* The signed flag (SF) is a duplication of the most significant bit in the
49	* result.
50	*
51	* @returns X86_EFL_SF or 0.
52	* @param a_uResult Unsigned result value.
53	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
54	*/
55	#define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
56	( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
57
58	/**
59	* Calculates the zero flag value given a result.
60	*
61	* The zero flag (ZF) indicates whether the result is zero or not.
62	*
63	* @returns X86_EFL_ZF or 0.
64	* @param a_uResult Unsigned result value.
65	*/
66	#define X86_EFL_CALC_ZF(a_uResult) \
67	( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
68
69	/**
70	* Extracts the OF flag from a OF calculation result.
71	*
72	* These are typically used by concating with a bitcount. The problem is that
73	* 8-bit values needs shifting in the other direction than the others.
74	*/
75	#define X86_EFL_GET_OF_8(a_uValue) (((uint32_t)(a_uValue) << (X86_EFL_OF_BIT - 8 + 1)) & X86_EFL_OF)
76	#define X86_EFL_GET_OF_16(a_uValue) ((uint32_t)((a_uValue) >> (16 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
77	#define X86_EFL_GET_OF_32(a_uValue) ((uint32_t)((a_uValue) >> (32 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
78	#define X86_EFL_GET_OF_64(a_uValue) ((uint32_t)((a_uValue) >> (64 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
79
80	/**
81	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) after arithmetic op.
82	*
83	* @returns Status bits.
84	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
85	* @param a_uResult Unsigned result value.
86	* @param a_uSrc The source value (for AF calc).
87	* @param a_uDst The original destination value (for AF calc).
88	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
89	* @param a_CfExpr Bool expression for the carry flag (CF).
90	* @param a_uOfSrc The a_uSrc value to use for overflow calculation.
91	*/
92	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
93	do { \
94	uint32_t fEflTmp = *(a_pfEFlags); \
95	fEflTmp &= ~X86_EFL_STATUS_BITS; \
96	fEflTmp \|= (a_CfExpr) << X86_EFL_CF_BIT; \
97	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
98	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
99	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
100	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
101	\
102	/* Overflow during ADDition happens when both inputs have the same signed \
103	bit value and the result has a different sign bit value. \
104	\
105	Since subtraction can be rewritten as addition: 2 - 1 == 2 + -1, it \
106	follows that for SUBtraction the signed bit value must differ between \
107	the two inputs and the result's signed bit diff from the first input. \
108	Note! Must xor with sign bit to convert, not do (0 - a_uSrc). \
109	\
110	See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
111	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth( ( ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
112	& RT_BIT_64(a_cBitsWidth - 1)) \
113	& ((a_uResult) ^ (a_uDst)) ); \
114	*(a_pfEFlags) = fEflTmp; \
115	} while (0)
116
117	/**
118	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
119	*
120	* CF and OF are defined to be 0 by logical operations. AF on the other hand is
121	* undefined. We do not set AF, as that seems to make the most sense (which
122	* probably makes it the most wrong in real life).
123	*
124	* @returns Status bits.
125	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
126	* @param a_uResult Unsigned result value.
127	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
128	* @param a_fExtra Additional bits to set.
129	*/
130	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
131	do { \
132	uint32_t fEflTmp = *(a_pfEFlags); \
133	fEflTmp &= ~X86_EFL_STATUS_BITS; \
134	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
135	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
136	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
137	fEflTmp \|= (a_fExtra); \
138	*(a_pfEFlags) = fEflTmp; \
139	} while (0)
140
141
142	/*********************************************************************************************************************************
143	* Global Variables *
144	*********************************************************************************************************************************/
145	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
146	/**
147	* Parity calculation table.
148	*
149	* The generator code:
150	* @code
151	* #include <stdio.h>
152	*
153	* int main()
154	* {
155	* unsigned b;
156	* for (b = 0; b < 256; b++)
157	* {
158	* int cOnes = ( b & 1)
159	* + ((b >> 1) & 1)
160	* + ((b >> 2) & 1)
161	* + ((b >> 3) & 1)
162	* + ((b >> 4) & 1)
163	* + ((b >> 5) & 1)
164	* + ((b >> 6) & 1)
165	* + ((b >> 7) & 1);
166	* printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
167	* b,
168	* (b >> 7) & 1,
169	* (b >> 6) & 1,
170	* (b >> 5) & 1,
171	* (b >> 4) & 1,
172	* (b >> 3) & 1,
173	* (b >> 2) & 1,
174	* (b >> 1) & 1,
175	* b & 1,
176	* cOnes & 1 ? "0" : "X86_EFL_PF");
177	* }
178	* return 0;
179	* }
180	* @endcode
181	*/
182	static uint8_t const g_afParity[256] =
183	{
184	/* 0000 = 00000000b */ X86_EFL_PF,
185	/* 0x01 = 00000001b */ 0,
186	/* 0x02 = 00000010b */ 0,
187	/* 0x03 = 00000011b */ X86_EFL_PF,
188	/* 0x04 = 00000100b */ 0,
189	/* 0x05 = 00000101b */ X86_EFL_PF,
190	/* 0x06 = 00000110b */ X86_EFL_PF,
191	/* 0x07 = 00000111b */ 0,
192	/* 0x08 = 00001000b */ 0,
193	/* 0x09 = 00001001b */ X86_EFL_PF,
194	/* 0x0a = 00001010b */ X86_EFL_PF,
195	/* 0x0b = 00001011b */ 0,
196	/* 0x0c = 00001100b */ X86_EFL_PF,
197	/* 0x0d = 00001101b */ 0,
198	/* 0x0e = 00001110b */ 0,
199	/* 0x0f = 00001111b */ X86_EFL_PF,
200	/* 0x10 = 00010000b */ 0,
201	/* 0x11 = 00010001b */ X86_EFL_PF,
202	/* 0x12 = 00010010b */ X86_EFL_PF,
203	/* 0x13 = 00010011b */ 0,
204	/* 0x14 = 00010100b */ X86_EFL_PF,
205	/* 0x15 = 00010101b */ 0,
206	/* 0x16 = 00010110b */ 0,
207	/* 0x17 = 00010111b */ X86_EFL_PF,
208	/* 0x18 = 00011000b */ X86_EFL_PF,
209	/* 0x19 = 00011001b */ 0,
210	/* 0x1a = 00011010b */ 0,
211	/* 0x1b = 00011011b */ X86_EFL_PF,
212	/* 0x1c = 00011100b */ 0,
213	/* 0x1d = 00011101b */ X86_EFL_PF,
214	/* 0x1e = 00011110b */ X86_EFL_PF,
215	/* 0x1f = 00011111b */ 0,
216	/* 0x20 = 00100000b */ 0,
217	/* 0x21 = 00100001b */ X86_EFL_PF,
218	/* 0x22 = 00100010b */ X86_EFL_PF,
219	/* 0x23 = 00100011b */ 0,
220	/* 0x24 = 00100100b */ X86_EFL_PF,
221	/* 0x25 = 00100101b */ 0,
222	/* 0x26 = 00100110b */ 0,
223	/* 0x27 = 00100111b */ X86_EFL_PF,
224	/* 0x28 = 00101000b */ X86_EFL_PF,
225	/* 0x29 = 00101001b */ 0,
226	/* 0x2a = 00101010b */ 0,
227	/* 0x2b = 00101011b */ X86_EFL_PF,
228	/* 0x2c = 00101100b */ 0,
229	/* 0x2d = 00101101b */ X86_EFL_PF,
230	/* 0x2e = 00101110b */ X86_EFL_PF,
231	/* 0x2f = 00101111b */ 0,
232	/* 0x30 = 00110000b */ X86_EFL_PF,
233	/* 0x31 = 00110001b */ 0,
234	/* 0x32 = 00110010b */ 0,
235	/* 0x33 = 00110011b */ X86_EFL_PF,
236	/* 0x34 = 00110100b */ 0,
237	/* 0x35 = 00110101b */ X86_EFL_PF,
238	/* 0x36 = 00110110b */ X86_EFL_PF,
239	/* 0x37 = 00110111b */ 0,
240	/* 0x38 = 00111000b */ 0,
241	/* 0x39 = 00111001b */ X86_EFL_PF,
242	/* 0x3a = 00111010b */ X86_EFL_PF,
243	/* 0x3b = 00111011b */ 0,
244	/* 0x3c = 00111100b */ X86_EFL_PF,
245	/* 0x3d = 00111101b */ 0,
246	/* 0x3e = 00111110b */ 0,
247	/* 0x3f = 00111111b */ X86_EFL_PF,
248	/* 0x40 = 01000000b */ 0,
249	/* 0x41 = 01000001b */ X86_EFL_PF,
250	/* 0x42 = 01000010b */ X86_EFL_PF,
251	/* 0x43 = 01000011b */ 0,
252	/* 0x44 = 01000100b */ X86_EFL_PF,
253	/* 0x45 = 01000101b */ 0,
254	/* 0x46 = 01000110b */ 0,
255	/* 0x47 = 01000111b */ X86_EFL_PF,
256	/* 0x48 = 01001000b */ X86_EFL_PF,
257	/* 0x49 = 01001001b */ 0,
258	/* 0x4a = 01001010b */ 0,
259	/* 0x4b = 01001011b */ X86_EFL_PF,
260	/* 0x4c = 01001100b */ 0,
261	/* 0x4d = 01001101b */ X86_EFL_PF,
262	/* 0x4e = 01001110b */ X86_EFL_PF,
263	/* 0x4f = 01001111b */ 0,
264	/* 0x50 = 01010000b */ X86_EFL_PF,
265	/* 0x51 = 01010001b */ 0,
266	/* 0x52 = 01010010b */ 0,
267	/* 0x53 = 01010011b */ X86_EFL_PF,
268	/* 0x54 = 01010100b */ 0,
269	/* 0x55 = 01010101b */ X86_EFL_PF,
270	/* 0x56 = 01010110b */ X86_EFL_PF,
271	/* 0x57 = 01010111b */ 0,
272	/* 0x58 = 01011000b */ 0,
273	/* 0x59 = 01011001b */ X86_EFL_PF,
274	/* 0x5a = 01011010b */ X86_EFL_PF,
275	/* 0x5b = 01011011b */ 0,
276	/* 0x5c = 01011100b */ X86_EFL_PF,
277	/* 0x5d = 01011101b */ 0,
278	/* 0x5e = 01011110b */ 0,
279	/* 0x5f = 01011111b */ X86_EFL_PF,
280	/* 0x60 = 01100000b */ X86_EFL_PF,
281	/* 0x61 = 01100001b */ 0,
282	/* 0x62 = 01100010b */ 0,
283	/* 0x63 = 01100011b */ X86_EFL_PF,
284	/* 0x64 = 01100100b */ 0,
285	/* 0x65 = 01100101b */ X86_EFL_PF,
286	/* 0x66 = 01100110b */ X86_EFL_PF,
287	/* 0x67 = 01100111b */ 0,
288	/* 0x68 = 01101000b */ 0,
289	/* 0x69 = 01101001b */ X86_EFL_PF,
290	/* 0x6a = 01101010b */ X86_EFL_PF,
291	/* 0x6b = 01101011b */ 0,
292	/* 0x6c = 01101100b */ X86_EFL_PF,
293	/* 0x6d = 01101101b */ 0,
294	/* 0x6e = 01101110b */ 0,
295	/* 0x6f = 01101111b */ X86_EFL_PF,
296	/* 0x70 = 01110000b */ 0,
297	/* 0x71 = 01110001b */ X86_EFL_PF,
298	/* 0x72 = 01110010b */ X86_EFL_PF,
299	/* 0x73 = 01110011b */ 0,
300	/* 0x74 = 01110100b */ X86_EFL_PF,
301	/* 0x75 = 01110101b */ 0,
302	/* 0x76 = 01110110b */ 0,
303	/* 0x77 = 01110111b */ X86_EFL_PF,
304	/* 0x78 = 01111000b */ X86_EFL_PF,
305	/* 0x79 = 01111001b */ 0,
306	/* 0x7a = 01111010b */ 0,
307	/* 0x7b = 01111011b */ X86_EFL_PF,
308	/* 0x7c = 01111100b */ 0,
309	/* 0x7d = 01111101b */ X86_EFL_PF,
310	/* 0x7e = 01111110b */ X86_EFL_PF,
311	/* 0x7f = 01111111b */ 0,
312	/* 0x80 = 10000000b */ 0,
313	/* 0x81 = 10000001b */ X86_EFL_PF,
314	/* 0x82 = 10000010b */ X86_EFL_PF,
315	/* 0x83 = 10000011b */ 0,
316	/* 0x84 = 10000100b */ X86_EFL_PF,
317	/* 0x85 = 10000101b */ 0,
318	/* 0x86 = 10000110b */ 0,
319	/* 0x87 = 10000111b */ X86_EFL_PF,
320	/* 0x88 = 10001000b */ X86_EFL_PF,
321	/* 0x89 = 10001001b */ 0,
322	/* 0x8a = 10001010b */ 0,
323	/* 0x8b = 10001011b */ X86_EFL_PF,
324	/* 0x8c = 10001100b */ 0,
325	/* 0x8d = 10001101b */ X86_EFL_PF,
326	/* 0x8e = 10001110b */ X86_EFL_PF,
327	/* 0x8f = 10001111b */ 0,
328	/* 0x90 = 10010000b */ X86_EFL_PF,
329	/* 0x91 = 10010001b */ 0,
330	/* 0x92 = 10010010b */ 0,
331	/* 0x93 = 10010011b */ X86_EFL_PF,
332	/* 0x94 = 10010100b */ 0,
333	/* 0x95 = 10010101b */ X86_EFL_PF,
334	/* 0x96 = 10010110b */ X86_EFL_PF,
335	/* 0x97 = 10010111b */ 0,
336	/* 0x98 = 10011000b */ 0,
337	/* 0x99 = 10011001b */ X86_EFL_PF,
338	/* 0x9a = 10011010b */ X86_EFL_PF,
339	/* 0x9b = 10011011b */ 0,
340	/* 0x9c = 10011100b */ X86_EFL_PF,
341	/* 0x9d = 10011101b */ 0,
342	/* 0x9e = 10011110b */ 0,
343	/* 0x9f = 10011111b */ X86_EFL_PF,
344	/* 0xa0 = 10100000b */ X86_EFL_PF,
345	/* 0xa1 = 10100001b */ 0,
346	/* 0xa2 = 10100010b */ 0,
347	/* 0xa3 = 10100011b */ X86_EFL_PF,
348	/* 0xa4 = 10100100b */ 0,
349	/* 0xa5 = 10100101b */ X86_EFL_PF,
350	/* 0xa6 = 10100110b */ X86_EFL_PF,
351	/* 0xa7 = 10100111b */ 0,
352	/* 0xa8 = 10101000b */ 0,
353	/* 0xa9 = 10101001b */ X86_EFL_PF,
354	/* 0xaa = 10101010b */ X86_EFL_PF,
355	/* 0xab = 10101011b */ 0,
356	/* 0xac = 10101100b */ X86_EFL_PF,
357	/* 0xad = 10101101b */ 0,
358	/* 0xae = 10101110b */ 0,
359	/* 0xaf = 10101111b */ X86_EFL_PF,
360	/* 0xb0 = 10110000b */ 0,
361	/* 0xb1 = 10110001b */ X86_EFL_PF,
362	/* 0xb2 = 10110010b */ X86_EFL_PF,
363	/* 0xb3 = 10110011b */ 0,
364	/* 0xb4 = 10110100b */ X86_EFL_PF,
365	/* 0xb5 = 10110101b */ 0,
366	/* 0xb6 = 10110110b */ 0,
367	/* 0xb7 = 10110111b */ X86_EFL_PF,
368	/* 0xb8 = 10111000b */ X86_EFL_PF,
369	/* 0xb9 = 10111001b */ 0,
370	/* 0xba = 10111010b */ 0,
371	/* 0xbb = 10111011b */ X86_EFL_PF,
372	/* 0xbc = 10111100b */ 0,
373	/* 0xbd = 10111101b */ X86_EFL_PF,
374	/* 0xbe = 10111110b */ X86_EFL_PF,
375	/* 0xbf = 10111111b */ 0,
376	/* 0xc0 = 11000000b */ X86_EFL_PF,
377	/* 0xc1 = 11000001b */ 0,
378	/* 0xc2 = 11000010b */ 0,
379	/* 0xc3 = 11000011b */ X86_EFL_PF,
380	/* 0xc4 = 11000100b */ 0,
381	/* 0xc5 = 11000101b */ X86_EFL_PF,
382	/* 0xc6 = 11000110b */ X86_EFL_PF,
383	/* 0xc7 = 11000111b */ 0,
384	/* 0xc8 = 11001000b */ 0,
385	/* 0xc9 = 11001001b */ X86_EFL_PF,
386	/* 0xca = 11001010b */ X86_EFL_PF,
387	/* 0xcb = 11001011b */ 0,
388	/* 0xcc = 11001100b */ X86_EFL_PF,
389	/* 0xcd = 11001101b */ 0,
390	/* 0xce = 11001110b */ 0,
391	/* 0xcf = 11001111b */ X86_EFL_PF,
392	/* 0xd0 = 11010000b */ 0,
393	/* 0xd1 = 11010001b */ X86_EFL_PF,
394	/* 0xd2 = 11010010b */ X86_EFL_PF,
395	/* 0xd3 = 11010011b */ 0,
396	/* 0xd4 = 11010100b */ X86_EFL_PF,
397	/* 0xd5 = 11010101b */ 0,
398	/* 0xd6 = 11010110b */ 0,
399	/* 0xd7 = 11010111b */ X86_EFL_PF,
400	/* 0xd8 = 11011000b */ X86_EFL_PF,
401	/* 0xd9 = 11011001b */ 0,
402	/* 0xda = 11011010b */ 0,
403	/* 0xdb = 11011011b */ X86_EFL_PF,
404	/* 0xdc = 11011100b */ 0,
405	/* 0xdd = 11011101b */ X86_EFL_PF,
406	/* 0xde = 11011110b */ X86_EFL_PF,
407	/* 0xdf = 11011111b */ 0,
408	/* 0xe0 = 11100000b */ 0,
409	/* 0xe1 = 11100001b */ X86_EFL_PF,
410	/* 0xe2 = 11100010b */ X86_EFL_PF,
411	/* 0xe3 = 11100011b */ 0,
412	/* 0xe4 = 11100100b */ X86_EFL_PF,
413	/* 0xe5 = 11100101b */ 0,
414	/* 0xe6 = 11100110b */ 0,
415	/* 0xe7 = 11100111b */ X86_EFL_PF,
416	/* 0xe8 = 11101000b */ X86_EFL_PF,
417	/* 0xe9 = 11101001b */ 0,
418	/* 0xea = 11101010b */ 0,
419	/* 0xeb = 11101011b */ X86_EFL_PF,
420	/* 0xec = 11101100b */ 0,
421	/* 0xed = 11101101b */ X86_EFL_PF,
422	/* 0xee = 11101110b */ X86_EFL_PF,
423	/* 0xef = 11101111b */ 0,
424	/* 0xf0 = 11110000b */ X86_EFL_PF,
425	/* 0xf1 = 11110001b */ 0,
426	/* 0xf2 = 11110010b */ 0,
427	/* 0xf3 = 11110011b */ X86_EFL_PF,
428	/* 0xf4 = 11110100b */ 0,
429	/* 0xf5 = 11110101b */ X86_EFL_PF,
430	/* 0xf6 = 11110110b */ X86_EFL_PF,
431	/* 0xf7 = 11110111b */ 0,
432	/* 0xf8 = 11111000b */ 0,
433	/* 0xf9 = 11111001b */ X86_EFL_PF,
434	/* 0xfa = 11111010b */ X86_EFL_PF,
435	/* 0xfb = 11111011b */ 0,
436	/* 0xfc = 11111100b */ X86_EFL_PF,
437	/* 0xfd = 11111101b */ 0,
438	/* 0xfe = 11111110b */ 0,
439	/* 0xff = 11111111b */ X86_EFL_PF,
440	};
441	#endif /* !RT_ARCH_AMD64 \|\| IEM_WITHOUT_ASSEMBLY */
442
443
444
445	/*
446	* There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
447	* it all in C is probably safer atm., optimize what's necessary later, maybe.
448	*/
449	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
450
451
452	/*********************************************************************************************************************************
453	* Binary Operations *
454	*********************************************************************************************************************************/
455
456	/*
457	* ADD
458	*/
459
460	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
461	{
462	uint64_t uDst = *puDst;
463	uint64_t uResult = uDst + uSrc;
464	*puDst = uResult;
465	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
466	}
467
468	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
469
470	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
471	{
472	uint32_t uDst = *puDst;
473	uint32_t uResult = uDst + uSrc;
474	*puDst = uResult;
475	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
476	}
477
478
479	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
480	{
481	uint16_t uDst = *puDst;
482	uint16_t uResult = uDst + uSrc;
483	*puDst = uResult;
484	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
485	}
486
487
488	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
489	{
490	uint8_t uDst = *puDst;
491	uint8_t uResult = uDst + uSrc;
492	*puDst = uResult;
493	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
494	}
495
496	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
497
498	/*
499	* ADC
500	*/
501
502	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
503	{
504	if (!(*pfEFlags & X86_EFL_CF))
505	iemAImpl_add_u64(puDst, uSrc, pfEFlags);
506	else
507	{
508	uint64_t uDst = *puDst;
509	uint64_t uResult = uDst + uSrc + 1;
510	*puDst = uResult;
511	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
512	}
513	}
514
515	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
516
517	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
518	{
519	if (!(*pfEFlags & X86_EFL_CF))
520	iemAImpl_add_u32(puDst, uSrc, pfEFlags);
521	else
522	{
523	uint32_t uDst = *puDst;
524	uint32_t uResult = uDst + uSrc + 1;
525	*puDst = uResult;
526	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
527	}
528	}
529
530
531	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
532	{
533	if (!(*pfEFlags & X86_EFL_CF))
534	iemAImpl_add_u16(puDst, uSrc, pfEFlags);
535	else
536	{
537	uint16_t uDst = *puDst;
538	uint16_t uResult = uDst + uSrc + 1;
539	*puDst = uResult;
540	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
541	}
542	}
543
544
545	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
546	{
547	if (!(*pfEFlags & X86_EFL_CF))
548	iemAImpl_add_u8(puDst, uSrc, pfEFlags);
549	else
550	{
551	uint8_t uDst = *puDst;
552	uint8_t uResult = uDst + uSrc + 1;
553	*puDst = uResult;
554	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
555	}
556	}
557
558	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
559
560	/*
561	* SUB
562	*/
563
564	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
565	{
566	uint64_t uDst = *puDst;
567	uint64_t uResult = uDst - uSrc;
568	*puDst = uResult;
569	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
570	}
571
572	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
573
574	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
575	{
576	uint32_t uDst = *puDst;
577	uint32_t uResult = uDst - uSrc;
578	*puDst = uResult;
579	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
580	}
581
582
583	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
584	{
585	uint16_t uDst = *puDst;
586	uint16_t uResult = uDst - uSrc;
587	*puDst = uResult;
588	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
589	}
590
591
592	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
593	{
594	uint8_t uDst = *puDst;
595	uint8_t uResult = uDst - uSrc;
596	*puDst = uResult;
597	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
598	}
599
600	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
601
602	/*
603	* SBB
604	*/
605
606	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
607	{
608	if (!(*pfEFlags & X86_EFL_CF))
609	iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
610	else
611	{
612	uint64_t uDst = *puDst;
613	uint64_t uResult = uDst - uSrc - 1;
614	*puDst = uResult;
615	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
616	}
617	}
618
619	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
620
621	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
622	{
623	if (!(*pfEFlags & X86_EFL_CF))
624	iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
625	else
626	{
627	uint32_t uDst = *puDst;
628	uint32_t uResult = uDst - uSrc - 1;
629	*puDst = uResult;
630	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
631	}
632	}
633
634
635	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
636	{
637	if (!(*pfEFlags & X86_EFL_CF))
638	iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
639	else
640	{
641	uint16_t uDst = *puDst;
642	uint16_t uResult = uDst - uSrc - 1;
643	*puDst = uResult;
644	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
645	}
646	}
647
648
649	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
650	{
651	if (!(*pfEFlags & X86_EFL_CF))
652	iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
653	else
654	{
655	uint8_t uDst = *puDst;
656	uint8_t uResult = uDst - uSrc - 1;
657	*puDst = uResult;
658	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
659	}
660	}
661
662	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
663
664
665	/*
666	* OR
667	*/
668
669	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
670	{
671	uint64_t uResult = *puDst \| uSrc;
672	*puDst = uResult;
673	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
674	}
675
676	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
677
678	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
679	{
680	uint32_t uResult = *puDst \| uSrc;
681	*puDst = uResult;
682	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
683	}
684
685
686	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
687	{
688	uint16_t uResult = *puDst \| uSrc;
689	*puDst = uResult;
690	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
691	}
692
693
694	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
695	{
696	uint8_t uResult = *puDst \| uSrc;
697	*puDst = uResult;
698	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
699	}
700
701	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
702
703	/*
704	* XOR
705	*/
706
707	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
708	{
709	uint64_t uResult = *puDst ^ uSrc;
710	*puDst = uResult;
711	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
712	}
713
714	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
715
716	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
717	{
718	uint32_t uResult = *puDst ^ uSrc;
719	*puDst = uResult;
720	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
721	}
722
723
724	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
725	{
726	uint16_t uResult = *puDst ^ uSrc;
727	*puDst = uResult;
728	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
729	}
730
731
732	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
733	{
734	uint8_t uResult = *puDst ^ uSrc;
735	*puDst = uResult;
736	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
737	}
738
739	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
740
741	/*
742	* AND
743	*/
744
745	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
746	{
747	uint64_t uResult = *puDst & uSrc;
748	*puDst = uResult;
749	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
750	}
751
752	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
753
754	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
755	{
756	uint32_t uResult = *puDst & uSrc;
757	*puDst = uResult;
758	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
759	}
760
761
762	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
763	{
764	uint16_t uResult = *puDst & uSrc;
765	*puDst = uResult;
766	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
767	}
768
769
770	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
771	{
772	uint8_t uResult = *puDst & uSrc;
773	*puDst = uResult;
774	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
775	}
776
777	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
778
779	/*
780	* CMP
781	*/
782
783	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
784	{
785	uint64_t uDstTmp = *puDst;
786	iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
787	}
788
789	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
790
791	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
792	{
793	uint32_t uDstTmp = *puDst;
794	iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
795	}
796
797
798	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
799	{
800	uint16_t uDstTmp = *puDst;
801	iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
802	}
803
804
805	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
806	{
807	uint8_t uDstTmp = *puDst;
808	iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
809	}
810
811	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
812
813	/*
814	* TEST
815	*/
816
817	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
818	{
819	uint64_t uResult = *puDst & uSrc;
820	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
821	}
822
823	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
824
825	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
826	{
827	uint32_t uResult = *puDst & uSrc;
828	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
829	}
830
831
832	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
833	{
834	uint16_t uResult = *puDst & uSrc;
835	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
836	}
837
838
839	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
840	{
841	uint8_t uResult = *puDst & uSrc;
842	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
843	}
844
845	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
846
847
848	/*
849	* LOCK prefixed variants of the above
850	*/
851
852	/** 64-bit locked binary operand operation. */
853	# define DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
854	do { \
855	uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
856	uint ## a_cBitsWidth ## _t uTmp; \
857	uint32_t fEflTmp; \
858	do \
859	{ \
860	uTmp = uOld; \
861	fEflTmp = *pfEFlags; \
862	iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
863	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
864	*pfEFlags = fEflTmp; \
865	} while (0)
866
867
868	#define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
869	IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
870	uint ## a_cBitsWidth ## _t uSrc, \
871	uint32_t *pfEFlags)) \
872	{ \
873	DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
874	}
875
876	EMIT_LOCKED_BIN_OP(add, 64)
877	EMIT_LOCKED_BIN_OP(adc, 64)
878	EMIT_LOCKED_BIN_OP(sub, 64)
879	EMIT_LOCKED_BIN_OP(sbb, 64)
880	EMIT_LOCKED_BIN_OP(or, 64)
881	EMIT_LOCKED_BIN_OP(xor, 64)
882	EMIT_LOCKED_BIN_OP(and, 64)
883	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
884	EMIT_LOCKED_BIN_OP(add, 32)
885	EMIT_LOCKED_BIN_OP(adc, 32)
886	EMIT_LOCKED_BIN_OP(sub, 32)
887	EMIT_LOCKED_BIN_OP(sbb, 32)
888	EMIT_LOCKED_BIN_OP(or, 32)
889	EMIT_LOCKED_BIN_OP(xor, 32)
890	EMIT_LOCKED_BIN_OP(and, 32)
891
892	EMIT_LOCKED_BIN_OP(add, 16)
893	EMIT_LOCKED_BIN_OP(adc, 16)
894	EMIT_LOCKED_BIN_OP(sub, 16)
895	EMIT_LOCKED_BIN_OP(sbb, 16)
896	EMIT_LOCKED_BIN_OP(or, 16)
897	EMIT_LOCKED_BIN_OP(xor, 16)
898	EMIT_LOCKED_BIN_OP(and, 16)
899
900	EMIT_LOCKED_BIN_OP(add, 8)
901	EMIT_LOCKED_BIN_OP(adc, 8)
902	EMIT_LOCKED_BIN_OP(sub, 8)
903	EMIT_LOCKED_BIN_OP(sbb, 8)
904	EMIT_LOCKED_BIN_OP(or, 8)
905	EMIT_LOCKED_BIN_OP(xor, 8)
906	EMIT_LOCKED_BIN_OP(and, 8)
907	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
908
909
910	/*
911	* Bit operations (same signature as above).
912	*/
913
914	/*
915	* BT
916	*/
917
918	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
919	{
920	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
921	not modified by either AMD (3990x) or Intel (i9-9980HK). */
922	Assert(uSrc < 64);
923	uint64_t uDst = *puDst;
924	if (uDst & RT_BIT_64(uSrc))
925	*pfEFlags \|= X86_EFL_CF;
926	else
927	*pfEFlags &= ~X86_EFL_CF;
928	}
929
930	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
931
932	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
933	{
934	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
935	not modified by either AMD (3990x) or Intel (i9-9980HK). */
936	Assert(uSrc < 32);
937	uint32_t uDst = *puDst;
938	if (uDst & RT_BIT_32(uSrc))
939	*pfEFlags \|= X86_EFL_CF;
940	else
941	*pfEFlags &= ~X86_EFL_CF;
942	}
943
944	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
945	{
946	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
947	not modified by either AMD (3990x) or Intel (i9-9980HK). */
948	Assert(uSrc < 16);
949	uint16_t uDst = *puDst;
950	if (uDst & RT_BIT_32(uSrc))
951	*pfEFlags \|= X86_EFL_CF;
952	else
953	*pfEFlags &= ~X86_EFL_CF;
954	}
955
956	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
957
958	/*
959	* BTC
960	*/
961
962	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
963	{
964	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
965	not modified by either AMD (3990x) or Intel (i9-9980HK). */
966	Assert(uSrc < 64);
967	uint64_t fMask = RT_BIT_64(uSrc);
968	uint64_t uDst = *puDst;
969	if (uDst & fMask)
970	{
971	uDst &= ~fMask;
972	*puDst = uDst;
973	*pfEFlags \|= X86_EFL_CF;
974	}
975	else
976	{
977	uDst \|= fMask;
978	*puDst = uDst;
979	*pfEFlags &= ~X86_EFL_CF;
980	}
981	}
982
983	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
984
985	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
986	{
987	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
988	not modified by either AMD (3990x) or Intel (i9-9980HK). */
989	Assert(uSrc < 32);
990	uint32_t fMask = RT_BIT_32(uSrc);
991	uint32_t uDst = *puDst;
992	if (uDst & fMask)
993	{
994	uDst &= ~fMask;
995	*puDst = uDst;
996	*pfEFlags \|= X86_EFL_CF;
997	}
998	else
999	{
1000	uDst \|= fMask;
1001	*puDst = uDst;
1002	*pfEFlags &= ~X86_EFL_CF;
1003	}
1004	}
1005
1006
1007	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1008	{
1009	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
1010	not modified by either AMD (3990x) or Intel (i9-9980HK). */
1011	Assert(uSrc < 16);
1012	uint16_t fMask = RT_BIT_32(uSrc);
1013	uint16_t uDst = *puDst;
1014	if (uDst & fMask)
1015	{
1016	uDst &= ~fMask;
1017	*puDst = uDst;
1018	*pfEFlags \|= X86_EFL_CF;
1019	}
1020	else
1021	{
1022	uDst \|= fMask;
1023	*puDst = uDst;
1024	*pfEFlags &= ~X86_EFL_CF;
1025	}
1026	}
1027
1028	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1029
1030	/*
1031	* BTR
1032	*/
1033
1034	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1035	{
1036	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1037	logical operation (AND/OR/whatever). */
1038	Assert(uSrc < 64);
1039	uint64_t fMask = RT_BIT_64(uSrc);
1040	uint64_t uDst = *puDst;
1041	if (uDst & fMask)
1042	{
1043	uDst &= ~fMask;
1044	*puDst = uDst;
1045	*pfEFlags \|= X86_EFL_CF;
1046	}
1047	else
1048	*pfEFlags &= ~X86_EFL_CF;
1049	}
1050
1051	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1052
1053	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1054	{
1055	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1056	logical operation (AND/OR/whatever). */
1057	Assert(uSrc < 32);
1058	uint32_t fMask = RT_BIT_32(uSrc);
1059	uint32_t uDst = *puDst;
1060	if (uDst & fMask)
1061	{
1062	uDst &= ~fMask;
1063	*puDst = uDst;
1064	*pfEFlags \|= X86_EFL_CF;
1065	}
1066	else
1067	*pfEFlags &= ~X86_EFL_CF;
1068	}
1069
1070
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1072	{
1073	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1074	logical operation (AND/OR/whatever). */
1075	Assert(uSrc < 16);
1076	uint16_t fMask = RT_BIT_32(uSrc);
1077	uint16_t uDst = *puDst;
1078	if (uDst & fMask)
1079	{
1080	uDst &= ~fMask;
1081	*puDst = uDst;
1082	*pfEFlags \|= X86_EFL_CF;
1083	}
1084	else
1085	*pfEFlags &= ~X86_EFL_CF;
1086	}
1087
1088	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1089
1090	/*
1091	* BTS
1092	*/
1093
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1095	{
1096	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1097	logical operation (AND/OR/whatever). */
1098	Assert(uSrc < 64);
1099	uint64_t fMask = RT_BIT_64(uSrc);
1100	uint64_t uDst = *puDst;
1101	if (uDst & fMask)
1102	*pfEFlags \|= X86_EFL_CF;
1103	else
1104	{
1105	uDst \|= fMask;
1106	*puDst = uDst;
1107	*pfEFlags &= ~X86_EFL_CF;
1108	}
1109	}
1110
1111	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1112
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1114	{
1115	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1116	logical operation (AND/OR/whatever). */
1117	Assert(uSrc < 32);
1118	uint32_t fMask = RT_BIT_32(uSrc);
1119	uint32_t uDst = *puDst;
1120	if (uDst & fMask)
1121	*pfEFlags \|= X86_EFL_CF;
1122	else
1123	{
1124	uDst \|= fMask;
1125	*puDst = uDst;
1126	*pfEFlags &= ~X86_EFL_CF;
1127	}
1128	}
1129
1130
1131	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1132	{
1133	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1134	logical operation (AND/OR/whatever). */
1135	Assert(uSrc < 16);
1136	uint16_t fMask = RT_BIT_32(uSrc);
1137	uint32_t uDst = *puDst;
1138	if (uDst & fMask)
1139	*pfEFlags \|= X86_EFL_CF;
1140	else
1141	{
1142	uDst \|= fMask;
1143	*puDst = uDst;
1144	*pfEFlags &= ~X86_EFL_CF;
1145	}
1146	}
1147
1148	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1149
1150
1151	EMIT_LOCKED_BIN_OP(btc, 64)
1152	EMIT_LOCKED_BIN_OP(btr, 64)
1153	EMIT_LOCKED_BIN_OP(bts, 64)
1154	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1155	EMIT_LOCKED_BIN_OP(btc, 32)
1156	EMIT_LOCKED_BIN_OP(btr, 32)
1157	EMIT_LOCKED_BIN_OP(bts, 32)
1158
1159	EMIT_LOCKED_BIN_OP(btc, 16)
1160	EMIT_LOCKED_BIN_OP(btr, 16)
1161	EMIT_LOCKED_BIN_OP(bts, 16)
1162	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1163
1164
1165	/*
1166	* BSF - first (least significant) bit set
1167	*/
1168
1169	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1170	{
1171	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1172	/* Intel & AMD differs here. This is is the AMD behaviour. */
1173	unsigned iBit = ASMBitFirstSetU64(uSrc);
1174	if (iBit)
1175	{
1176	*puDst = iBit - 1;
1177	*pfEFlags &= ~X86_EFL_ZF;
1178	}
1179	else
1180	*pfEFlags \|= X86_EFL_ZF;
1181	}
1182
1183	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1184
1185	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1186	{
1187	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1188	/* Intel & AMD differs here. This is is the AMD behaviour. */
1189	unsigned iBit = ASMBitFirstSetU32(uSrc);
1190	if (iBit)
1191	{
1192	*puDst = iBit - 1;
1193	*pfEFlags &= ~X86_EFL_ZF;
1194	}
1195	else
1196	*pfEFlags \|= X86_EFL_ZF;
1197	}
1198
1199
1200	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1201	{
1202	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1203	/* Intel & AMD differs here. This is is the AMD behaviour. */
1204	unsigned iBit = ASMBitFirstSetU16(uSrc);
1205	if (iBit)
1206	{
1207	*puDst = iBit - 1;
1208	*pfEFlags &= ~X86_EFL_ZF;
1209	}
1210	else
1211	*pfEFlags \|= X86_EFL_ZF;
1212	}
1213
1214	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1215
1216	/*
1217	* BSR - last (most significant) bit set
1218	*/
1219
1220	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1221	{
1222	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1223	/* Intel & AMD differs here. This is is the AMD behaviour. */
1224	unsigned iBit = ASMBitLastSetU64(uSrc);
1225	if (uSrc)
1226	{
1227	*puDst = iBit - 1;
1228	*pfEFlags &= ~X86_EFL_ZF;
1229	}
1230	else
1231	*pfEFlags \|= X86_EFL_ZF;
1232	}
1233
1234	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1235
1236	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1237	{
1238	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1239	/* Intel & AMD differs here. This is is the AMD behaviour. */
1240	unsigned iBit = ASMBitLastSetU32(uSrc);
1241	if (uSrc)
1242	{
1243	*puDst = iBit - 1;
1244	*pfEFlags &= ~X86_EFL_ZF;
1245	}
1246	else
1247	*pfEFlags \|= X86_EFL_ZF;
1248	}
1249
1250
1251	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1252	{
1253	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1254	/* Intel & AMD differs here. This is is the AMD behaviour. */
1255	unsigned iBit = ASMBitLastSetU16(uSrc);
1256	if (uSrc)
1257	{
1258	*puDst = iBit - 1;
1259	*pfEFlags &= ~X86_EFL_ZF;
1260	}
1261	else
1262	*pfEFlags \|= X86_EFL_ZF;
1263	}
1264
1265	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1266
1267
1268	/*
1269	* XCHG
1270	*/
1271
1272	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t puMem, uint64_t puReg))
1273	{
1274	#if ARCH_BITS >= 64
1275	puReg = ASMAtomicXchgU64(puMem, puReg);
1276	#else
1277	uint64_t uOldMem = *puMem;
1278	while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
1279	ASMNopPause();
1280	*puReg = uOldMem;
1281	#endif
1282	}
1283
1284	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1285
1286	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t puMem, uint32_t puReg))
1287	{
1288	puReg = ASMAtomicXchgU32(puMem, puReg);
1289	}
1290
1291
1292	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t puMem, uint16_t puReg))
1293	{
1294	puReg = ASMAtomicXchgU16(puMem, puReg);
1295	}
1296
1297
1298	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked,(uint8_t puMem, uint8_t puReg))
1299	{
1300	puReg = ASMAtomicXchgU8(puMem, puReg);
1301	}
1302
1303	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1304
1305
1306	/* Unlocked variants for fDisregardLock mode: */
1307
1308	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t puMem, uint64_t puReg))
1309	{
1310	uint64_t const uOld = *puMem;
1311	puMem = puReg;
1312	*puReg = uOld;
1313	}
1314
1315	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1316
1317	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t puMem, uint32_t puReg))
1318	{
1319	uint32_t const uOld = *puMem;
1320	puMem = puReg;
1321	*puReg = uOld;
1322	}
1323
1324
1325	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t puMem, uint16_t puReg))
1326	{
1327	uint16_t const uOld = *puMem;
1328	puMem = puReg;
1329	*puReg = uOld;
1330	}
1331
1332
1333	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked,(uint8_t puMem, uint8_t puReg))
1334	{
1335	uint8_t const uOld = *puMem;
1336	puMem = puReg;
1337	*puReg = uOld;
1338	}
1339
1340	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1341
1342
1343	/*
1344	* XADD and LOCK XADD.
1345	*/
1346	#define EMIT_XADD(a_cBitsWidth, a_Type) \
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth,(a_Type puDst, a_Type puReg, uint32_t *pfEFlags)) \
1348	{ \
1349	a_Type uDst = *puDst; \
1350	a_Type uResult = uDst; \
1351	iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, pfEFlags); \
1352	*puDst = uResult; \
1353	*puReg = uDst; \
1354	} \
1355	\
1356	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth ## _locked,(a_Type puDst, a_Type puReg, uint32_t *pfEFlags)) \
1357	{ \
1358	a_Type uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
1359	a_Type uResult; \
1360	uint32_t fEflTmp; \
1361	do \
1362	{ \
1363	uResult = uOld; \
1364	fEflTmp = *pfEFlags; \
1365	iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, &fEflTmp); \
1366	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uResult, uOld, &uOld)); \
1367	*puReg = uOld; \
1368	*pfEFlags = fEflTmp; \
1369	}
1370	EMIT_XADD(64, uint64_t)
1371	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1372	EMIT_XADD(32, uint32_t)
1373	EMIT_XADD(16, uint16_t)
1374	EMIT_XADD(8, uint8_t)
1375	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1376
1377	#endif
1378
1379	/*
1380	* CMPXCHG, CMPXCHG8B, CMPXCHG16B
1381	*
1382	* Note! We don't have non-locking/atomic cmpxchg primitives, so all cmpxchg
1383	* instructions are emulated as locked.
1384	*/
1385	#if defined(IEM_WITHOUT_ASSEMBLY)
1386
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1388	{
1389	uint8_t const uOld = *puAl;
1390	if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
1391	{
1392	Assert(*puAl == uOld);
1393	*pEFlags \|= X86_EFL_ZF;
1394	}
1395	else
1396	*pEFlags &= ~X86_EFL_ZF;
1397	}
1398
1399
1400	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1401	{
1402	uint16_t const uOld = *puAx;
1403	if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
1404	{
1405	Assert(*puAx == uOld);
1406	*pEFlags \|= X86_EFL_ZF;
1407	}
1408	else
1409	*pEFlags &= ~X86_EFL_ZF;
1410	}
1411
1412
1413	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1414	{
1415	uint32_t const uOld = *puEax;
1416	if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
1417	{
1418	Assert(*puEax == uOld);
1419	*pEFlags \|= X86_EFL_ZF;
1420	}
1421	else
1422	*pEFlags &= ~X86_EFL_ZF;
1423	}
1424
1425
1426	# if ARCH_BITS == 32
1427	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags))
1428	# else
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1430	# endif
1431	{
1432	# if ARCH_BITS == 32
1433	uint64_t const uSrcReg = *puSrcReg;
1434	# endif
1435	uint64_t const uOld = *puRax;
1436	if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
1437	{
1438	Assert(*puRax == uOld);
1439	*pEFlags \|= X86_EFL_ZF;
1440	}
1441	else
1442	*pEFlags &= ~X86_EFL_ZF;
1443	}
1444
1445
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1447	uint32_t *pEFlags))
1448	{
1449	uint64_t const uNew = pu64EbxEcx->u;
1450	uint64_t const uOld = pu64EaxEdx->u;
1451	if (ASMAtomicCmpXchgExU64(pu64Dst, uNew, uOld, &pu64EaxEdx->u))
1452	{
1453	Assert(pu64EaxEdx->u == uOld);
1454	*pEFlags \|= X86_EFL_ZF;
1455	}
1456	else
1457	*pEFlags &= ~X86_EFL_ZF;
1458	}
1459
1460
1461	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_ARM64)
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1463	uint32_t *pEFlags))
1464	{
1465	# ifdef VBOX_STRICT
1466	RTUINT128U const uOld = *pu128RaxRdx;
1467	# endif
1468	# if defined(RT_ARCH_AMD64)
1469	if (ASMAtomicCmpXchgU128v2(&pu128Dst->u, pu128RbxRcx->s.Hi, pu128RbxRcx->s.Lo, pu128RaxRdx->s.Hi, pu128RaxRdx->s.Lo,
1470	&pu128RaxRdx->u))
1471	# else
1472	if (ASMAtomicCmpXchgU128(&pu128Dst->u, pu128RbxRcx->u, pu128RaxRdx->u, &pu128RaxRdx->u))
1473	# endif
1474	{
1475	Assert(pu128RaxRdx->s.Lo == uOld.s.Lo && pu128RaxRdx->s.Hi == uOld.s.Hi);
1476	*pEFlags \|= X86_EFL_ZF;
1477	}
1478	else
1479	*pEFlags &= ~X86_EFL_ZF;
1480	}
1481	# endif
1482
1483	#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1484
1485	# if !defined(RT_ARCH_ARM64) /** @todo may need this for unaligned accesses... */
1486	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1487	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
1488	{
1489	RTUINT128U u128Tmp = *pu128Dst;
1490	if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
1491	&& u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
1492	{
1493	pu128Dst = pu128RbxRcx;
1494	*pEFlags \|= X86_EFL_ZF;
1495	}
1496	else
1497	{
1498	*pu128RaxRdx = u128Tmp;
1499	*pEFlags &= ~X86_EFL_ZF;
1500	}
1501	}
1502	#endif /* !RT_ARCH_ARM64 */
1503
1504	#if defined(IEM_WITHOUT_ASSEMBLY)
1505
1506	/* Unlocked versions mapped to the locked ones: */
1507
1508	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1509	{
1510	iemAImpl_cmpxchg_u8_locked(pu8Dst, puAl, uSrcReg, pEFlags);
1511	}
1512
1513
1514	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1515	{
1516	iemAImpl_cmpxchg_u16_locked(pu16Dst, puAx, uSrcReg, pEFlags);
1517	}
1518
1519
1520	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1521	{
1522	iemAImpl_cmpxchg_u32_locked(pu32Dst, puEax, uSrcReg, pEFlags);
1523	}
1524
1525
1526	# if ARCH_BITS == 32
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags))
1528	{
1529	iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, puSrcReg, pEFlags);
1530	}
1531	# else
1532	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1533	{
1534	iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, uSrcReg, pEFlags);
1535	}
1536	# endif
1537
1538
1539	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx, uint32_t pEFlags))
1540	{
1541	iemAImpl_cmpxchg8b_locked(pu64Dst, pu64EaxEdx, pu64EbxEcx, pEFlags);
1542	}
1543
1544
1545	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1546	uint32_t *pEFlags))
1547	{
1548	iemAImpl_cmpxchg16b_locked(pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
1549	}
1550
1551	#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1552
1553	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1554
1555	/*
1556	* MUL, IMUL, DIV and IDIV helpers.
1557	*
1558	* - The U64 versions must use 128-bit intermediates, so we need to abstract the
1559	* division step so we can select between using C operators and
1560	* RTUInt128DivRem/RTUInt128MulU64ByU64.
1561	*
1562	* - The U8 versions work returns output in AL + AH instead of xDX + xAX, with the
1563	* IDIV/DIV taking all the input in AX too. This means we have to abstract some
1564	* input loads and the result storing.
1565	*/
1566
1567	DECLINLINE(void) RTUInt128DivRemByU64(PRTUINT128U pQuotient, PRTUINT128U pRemainder, PCRTUINT128U pDividend, uint64_t u64Divisor)
1568	{
1569	# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1570	pQuotient->s.Lo = 0;
1571	pQuotient->s.Hi = 0;
1572	# endif
1573	RTUINT128U Divisor;
1574	Divisor.s.Lo = u64Divisor;
1575	Divisor.s.Hi = 0;
1576	RTUInt128DivRem(pQuotient, pRemainder, pDividend, &Divisor);
1577	}
1578
1579	# define DIV_LOAD(a_Dividend) \
1580	a_Dividend.s.Lo = puA, a_Dividend.s.Hi = puD
1581	# define DIV_LOAD_U8(a_Dividend) \
1582	a_Dividend.u = *puAX
1583
1584	# define DIV_STORE(a_Quotient, a_uReminder) puA = (a_Quotient), puD = (a_uReminder)
1585	# define DIV_STORE_U8(a_Quotient, a_uReminder) *puAX = (a_Quotient) \| ((uint16_t)(a_uReminder) << 8)
1586
1587	# define MUL_LOAD_F1() *puA
1588	# define MUL_LOAD_F1_U8() ((uint8_t)*puAX)
1589
1590	# define MUL_STORE(a_Result) puA = (a_Result).s.Lo, puD = (a_Result).s.Hi
1591	# define MUL_STORE_U8(a_Result) *puAX = a_Result.u
1592
1593	# define MULDIV_NEG(a_Value, a_cBitsWidth2x) \
1594	(a_Value).u = UINT ## a_cBitsWidth2x ## _C(0) - (a_Value).u
1595	# define MULDIV_NEG_U128(a_Value, a_cBitsWidth2x) \
1596	RTUInt128AssignNeg(&(a_Value))
1597
1598	# define MULDIV_MUL(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1599	(a_Result).u = (uint ## a_cBitsWidth2x ## _t)(a_Factor1) * (a_Factor2)
1600	# define MULDIV_MUL_U128(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1601	RTUInt128MulU64ByU64(&(a_Result), a_Factor1, a_Factor2);
1602
1603	# define MULDIV_MODDIV(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1604	a_Quotient.u = (a_Dividend).u / (a_uDivisor), \
1605	a_Remainder.u = (a_Dividend).u % (a_uDivisor)
1606	# define MULDIV_MODDIV_U128(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1607	RTUInt128DivRemByU64(&a_Quotient, &a_Remainder, &a_Dividend, a_uDivisor)
1608
1609
1610	/*
1611	* MUL
1612	*/
1613	# define EMIT_MUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnMul) \
1614	IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth, a_Args) \
1615	{ \
1616	RTUINT ## a_cBitsWidth2x ## U Result; \
1617	a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
1618	a_fnStore(Result); \
1619	\
1620	/* MUL EFLAGS according to Skylake (similar to IMUL). */ \
1621	*pfEFlags &= ~(X86_EFL_SF \| X86_EFL_CF \| X86_EFL_OF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_PF); \
1622	if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1623	*pfEFlags \|= X86_EFL_SF; \
1624	pfEFlags \|= g_afParity[Result.s.Lo & 0xff]; / (Skylake behaviour) */ \
1625	if (Result.s.Hi != 0) \
1626	*pfEFlags \|= X86_EFL_CF \| X86_EFL_OF; \
1627	return 0; \
1628	}
1629	EMIT_MUL(64, 128, (uint64_t puA, uint64_t puD, uint64_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL_U128)
1630	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1631	EMIT_MUL(32, 64, (uint32_t puA, uint32_t puD, uint32_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1632	EMIT_MUL(16, 32, (uint16_t puA, uint16_t puD, uint16_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1633	EMIT_MUL(8, 16, (uint16_t puAX, uint8_t uFactor, uint32_t pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_MUL)
1634	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1635
1636
1637	/*
1638	* IMUL
1639	*/
1640	# define EMIT_IMUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul) \
1641	IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth,a_Args) \
1642	{ \
1643	RTUINT ## a_cBitsWidth2x ## U Result; \
1644	/* The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these \
1645	flags as is. Whereas Intel skylake always clear AF and ZF and calculates \
1646	SF and PF as per the lower half of the result. */ \
1647	uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF \| X86_EFL_OF); \
1648	\
1649	uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
1650	if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
1651	{ \
1652	if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1653	{ \
1654	a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1655	if (Result.s.Hi != 0 \|\| Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1656	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1657	} \
1658	else \
1659	{ \
1660	a_fnMul(Result, uFactor1, UINT ## a_cBitsWidth ## _C(0) - uFactor2, a_cBitsWidth2x); \
1661	if (Result.s.Hi != 0 \|\| Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1662	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1663	a_fnNeg(Result, a_cBitsWidth2x); \
1664	} \
1665	} \
1666	else \
1667	{ \
1668	if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1669	{ \
1670	a_fnMul(Result, UINT ## a_cBitsWidth ## _C(0) - uFactor1, uFactor2, a_cBitsWidth2x); \
1671	if (Result.s.Hi != 0 \|\| Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1672	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1673	a_fnNeg(Result, a_cBitsWidth2x); \
1674	} \
1675	else \
1676	{ \
1677	/a_fnMul(Result, UINT ## a_cBitsWidth ## _C(0) - uFactor1, UINT ## a_cBitsWidth ## _C(0) - uFactor2, a_cBitsWidth2x);/ \
1678	a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1679	if (Result.s.Hi != 0 \|\| Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1680	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1681	} \
1682	} \
1683	a_fnStore(Result); \
1684	if (false) \
1685	{ /* Intel (skylake) flags "undefined" behaviour: */ \
1686	fEfl &= ~(X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_PF); \
1687	if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1688	fEfl \|= X86_EFL_SF; \
1689	fEfl \|= g_afParity[Result.s.Lo & 0xff]; \
1690	} \
1691	*pfEFlags = fEfl; \
1692	return 0; \
1693	}
1694	/** @todo Testcase: IMUL 2 and 3 operands. */
1695	EMIT_IMUL(64, 128, (uint64_t puA, uint64_t puD, uint64_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG_U128, MULDIV_MUL_U128)
1696	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1697	EMIT_IMUL(32, 64, (uint32_t puA, uint32_t puD, uint32_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1698	EMIT_IMUL(16, 32, (uint16_t puA, uint16_t puD, uint16_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1699	EMIT_IMUL(8, 16, (uint16_t puAX, uint8_t uFactor2, uint32_t pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_NEG, MULDIV_MUL)
1700	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1701
1702
1703	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1704	{
1705	uint64_t uIgn;
1706	iemAImpl_imul_u64(puDst, &uIgn, uSrc, pfEFlags);
1707	}
1708
1709	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1710
1711	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1712	{
1713	uint32_t uIgn;
1714	iemAImpl_imul_u32(puDst, &uIgn, uSrc, pfEFlags);
1715	}
1716
1717
1718	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1719	{
1720	uint16_t uIgn;
1721	iemAImpl_imul_u16(puDst, &uIgn, uSrc, pfEFlags);
1722	}
1723
1724	#endif
1725
1726	/*
1727	* DIV
1728	*/
1729	# define EMIT_DIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnDivRem) \
1730	IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth,a_Args) \
1731	{ \
1732	/* Note! Skylake leaves all flags alone. */ \
1733	RT_NOREF_PV(pfEFlags); \
1734	\
1735	RTUINT ## a_cBitsWidth2x ## U Dividend; \
1736	a_fnLoad(Dividend); \
1737	if ( uDivisor != 0 \
1738	&& Dividend.s.Hi < uDivisor) \
1739	{ \
1740	RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1741	a_fnDivRem(Remainder, Quotient, Dividend, uDivisor); \
1742	a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1743	/** @todo research the undefined DIV flags. */ \
1744	return 0; \
1745	} \
1746	/* #DE */ \
1747	return -1; \
1748	}
1749	EMIT_DIV(64,128,(uint64_t puA, uint64_t puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV_U128)
1750	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1751	EMIT_DIV(32,64, (uint32_t puA, uint32_t puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1752	EMIT_DIV(16,32, (uint16_t puA, uint16_t puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1753	EMIT_DIV(8,16, (uint16_t puAX, uint8_t uDivisor, uint32_t pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_MODDIV)
1754	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1755
1756
1757	/*
1758	* IDIV
1759	*/
1760	# define EMIT_IDIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem) \
1761	IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth,a_Args) \
1762	{ \
1763	/* Note! Skylake leaves all flags alone. */ \
1764	RT_NOREF_PV(pfEFlags); \
1765	\
1766	/** @todo overflow checks */ \
1767	if (uDivisor != 0) \
1768	{ \
1769	/* \
1770	* Convert to unsigned division. \
1771	*/ \
1772	RTUINT ## a_cBitsWidth2x ## U Dividend; \
1773	a_fnLoad(Dividend); \
1774	if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi < 0) \
1775	a_fnNeg(Dividend, a_cBitsWidth2x); \
1776	\
1777	uint ## a_cBitsWidth ## _t uDivisorPositive; \
1778	if ((int ## a_cBitsWidth ## _t)uDivisor >= 0) \
1779	uDivisorPositive = uDivisor; \
1780	else \
1781	uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
1782	\
1783	RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1784	a_fnDivRem(Remainder, Quotient, Dividend, uDivisorPositive); \
1785	\
1786	/* \
1787	* Setup the result, checking for overflows. \
1788	*/ \
1789	if ((int ## a_cBitsWidth ## _t)uDivisor >= 0) \
1790	{ \
1791	if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi >= 0) \
1792	{ \
1793	/* Positive divisor, positive dividend => result positive. */ \
1794	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1795	{ \
1796	a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1797	return 0; \
1798	} \
1799	} \
1800	else \
1801	{ \
1802	/* Positive divisor, positive dividend => result negative. */ \
1803	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1804	{ \
1805	a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1806	return 0; \
1807	} \
1808	} \
1809	} \
1810	else \
1811	{ \
1812	if ((int ## a_cBitsWidth ## _t)Dividend.s.Hi >= 0) \
1813	{ \
1814	/* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
1815	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1816	{ \
1817	a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
1818	return 0; \
1819	} \
1820	} \
1821	else \
1822	{ \
1823	/* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
1824	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1825	{ \
1826	a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1827	return 0; \
1828	} \
1829	} \
1830	} \
1831	} \
1832	/* #DE */ \
1833	return -1; \
1834	}
1835	EMIT_IDIV(64,128,(uint64_t puA, uint64_t puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG_U128, MULDIV_MODDIV_U128)
1836	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1837	EMIT_IDIV(32,64,(uint32_t puA, uint32_t puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1838	EMIT_IDIV(16,32,(uint16_t puA, uint16_t puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1839	EMIT_IDIV(8,16,(uint16_t puAX, uint8_t uDivisor, uint32_t pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_NEG, MULDIV_MODDIV)
1840	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1841
1842
1843	/*********************************************************************************************************************************
1844	* Unary operations. *
1845	*********************************************************************************************************************************/
1846
1847	/**
1848	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an INC or DEC instruction.
1849	*
1850	* CF is NOT modified for hysterical raisins (allegedly for carrying and
1851	* borrowing in arithmetic loops on intel 8008).
1852	*
1853	* @returns Status bits.
1854	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
1855	* @param a_uResult Unsigned result value.
1856	* @param a_uDst The original destination value (for AF calc).
1857	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
1858	* @param a_OfMethod 0 for INC-style, 1 for DEC-style.
1859	*/
1860	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth, a_OfMethod) \
1861	do { \
1862	uint32_t fEflTmp = *(a_pfEFlags); \
1863	fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
1864	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
1865	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
1866	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
1867	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
1868	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth(a_OfMethod == 0 ? (((a_uDst) ^ RT_BIT_64(63)) & (a_uResult)) \
1869	: ((a_uDst) & ((a_uResult) ^ RT_BIT_64(63))) ); \
1870	*(a_pfEFlags) = fEflTmp; \
1871	} while (0)
1872
1873	/*
1874	* INC
1875	*/
1876
1877	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t puDst, uint32_t pfEFlags))
1878	{
1879	uint64_t uDst = *puDst;
1880	uint64_t uResult = uDst + 1;
1881	*puDst = uResult;
1882	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 0 /INC/);
1883	}
1884
1885	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1886
1887	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u32,(uint32_t puDst, uint32_t pfEFlags))
1888	{
1889	uint32_t uDst = *puDst;
1890	uint32_t uResult = uDst + 1;
1891	*puDst = uResult;
1892	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 0 /INC/);
1893	}
1894
1895
1896	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u16,(uint16_t puDst, uint32_t pfEFlags))
1897	{
1898	uint16_t uDst = *puDst;
1899	uint16_t uResult = uDst + 1;
1900	*puDst = uResult;
1901	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 0 /INC/);
1902	}
1903
1904	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u8,(uint8_t puDst, uint32_t pfEFlags))
1905	{
1906	uint8_t uDst = *puDst;
1907	uint8_t uResult = uDst + 1;
1908	*puDst = uResult;
1909	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 0 /INC/);
1910	}
1911
1912	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1913
1914
1915	/*
1916	* DEC
1917	*/
1918
1919	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t puDst, uint32_t pfEFlags))
1920	{
1921	uint64_t uDst = *puDst;
1922	uint64_t uResult = uDst - 1;
1923	*puDst = uResult;
1924	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 1 /INC/);
1925	}
1926
1927	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1928
1929	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u32,(uint32_t puDst, uint32_t pfEFlags))
1930	{
1931	uint32_t uDst = *puDst;
1932	uint32_t uResult = uDst - 1;
1933	*puDst = uResult;
1934	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 1 /INC/);
1935	}
1936
1937
1938	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u16,(uint16_t puDst, uint32_t pfEFlags))
1939	{
1940	uint16_t uDst = *puDst;
1941	uint16_t uResult = uDst - 1;
1942	*puDst = uResult;
1943	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 1 /INC/);
1944	}
1945
1946
1947	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u8,(uint8_t puDst, uint32_t pfEFlags))
1948	{
1949	uint8_t uDst = *puDst;
1950	uint8_t uResult = uDst - 1;
1951	*puDst = uResult;
1952	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 1 /INC/);
1953	}
1954
1955	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1956
1957
1958	/*
1959	* NOT
1960	*/
1961
1962	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t puDst, uint32_t pfEFlags))
1963	{
1964	uint64_t uDst = *puDst;
1965	uint64_t uResult = ~uDst;
1966	*puDst = uResult;
1967	/* EFLAGS are not modified. */
1968	RT_NOREF_PV(pfEFlags);
1969	}
1970
1971	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1972
1973	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u32,(uint32_t puDst, uint32_t pfEFlags))
1974	{
1975	uint32_t uDst = *puDst;
1976	uint32_t uResult = ~uDst;
1977	*puDst = uResult;
1978	/* EFLAGS are not modified. */
1979	RT_NOREF_PV(pfEFlags);
1980	}
1981
1982	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u16,(uint16_t puDst, uint32_t pfEFlags))
1983	{
1984	uint16_t uDst = *puDst;
1985	uint16_t uResult = ~uDst;
1986	*puDst = uResult;
1987	/* EFLAGS are not modified. */
1988	RT_NOREF_PV(pfEFlags);
1989	}
1990
1991	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u8,(uint8_t puDst, uint32_t pfEFlags))
1992	{
1993	uint8_t uDst = *puDst;
1994	uint8_t uResult = ~uDst;
1995	*puDst = uResult;
1996	/* EFLAGS are not modified. */
1997	RT_NOREF_PV(pfEFlags);
1998	}
1999
2000	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2001
2002
2003	/*
2004	* NEG
2005	*/
2006
2007	/**
2008	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an NEG instruction.
2009	*
2010	* @returns Status bits.
2011	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2012	* @param a_uResult Unsigned result value.
2013	* @param a_uDst The original destination value (for AF calc).
2014	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2015	*/
2016	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth) \
2017	do { \
2018	uint32_t fEflTmp = *(a_pfEFlags); \
2019	fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
2020	fEflTmp \|= ((a_uDst) != 0) << X86_EFL_CF_BIT; \
2021	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
2022	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
2023	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
2024	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
2025	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth((a_uDst) & (a_uResult)); \
2026	*(a_pfEFlags) = fEflTmp; \
2027	} while (0)
2028
2029	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t puDst, uint32_t pfEFlags))
2030	{
2031	uint64_t uDst = *puDst;
2032	uint64_t uResult = (uint64_t)0 - uDst;
2033	*puDst = uResult;
2034	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 64);
2035	}
2036
2037	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2038
2039	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u32,(uint32_t puDst, uint32_t pfEFlags))
2040	{
2041	uint32_t uDst = *puDst;
2042	uint32_t uResult = (uint32_t)0 - uDst;
2043	*puDst = uResult;
2044	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 32);
2045	}
2046
2047
2048	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u16,(uint16_t puDst, uint32_t pfEFlags))
2049	{
2050	uint16_t uDst = *puDst;
2051	uint16_t uResult = (uint16_t)0 - uDst;
2052	*puDst = uResult;
2053	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 16);
2054	}
2055
2056
2057	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u8,(uint8_t puDst, uint32_t pfEFlags))
2058	{
2059	uint8_t uDst = *puDst;
2060	uint8_t uResult = (uint8_t)0 - uDst;
2061	*puDst = uResult;
2062	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 8);
2063	}
2064
2065	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2066
2067	/*
2068	* Locked variants.
2069	*/
2070
2071	/** Emit a function for doing a locked unary operand operation. */
2072	# define EMIT_LOCKED_UNARY_OP(a_Mnemonic, a_cBitsWidth) \
2073	IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
2074	uint32_t *pfEFlags)) \
2075	{ \
2076	uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
2077	uint ## a_cBitsWidth ## _t uTmp; \
2078	uint32_t fEflTmp; \
2079	do \
2080	{ \
2081	uTmp = uOld; \
2082	fEflTmp = *pfEFlags; \
2083	iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, &fEflTmp); \
2084	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
2085	*pfEFlags = fEflTmp; \
2086	}
2087
2088	EMIT_LOCKED_UNARY_OP(inc, 64)
2089	EMIT_LOCKED_UNARY_OP(dec, 64)
2090	EMIT_LOCKED_UNARY_OP(not, 64)
2091	EMIT_LOCKED_UNARY_OP(neg, 64)
2092	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2093	EMIT_LOCKED_UNARY_OP(inc, 32)
2094	EMIT_LOCKED_UNARY_OP(dec, 32)
2095	EMIT_LOCKED_UNARY_OP(not, 32)
2096	EMIT_LOCKED_UNARY_OP(neg, 32)
2097
2098	EMIT_LOCKED_UNARY_OP(inc, 16)
2099	EMIT_LOCKED_UNARY_OP(dec, 16)
2100	EMIT_LOCKED_UNARY_OP(not, 16)
2101	EMIT_LOCKED_UNARY_OP(neg, 16)
2102
2103	EMIT_LOCKED_UNARY_OP(inc, 8)
2104	EMIT_LOCKED_UNARY_OP(dec, 8)
2105	EMIT_LOCKED_UNARY_OP(not, 8)
2106	EMIT_LOCKED_UNARY_OP(neg, 8)
2107	# endif
2108
2109
2110	/*********************************************************************************************************************************
2111	* Shifting and Rotating *
2112	*********************************************************************************************************************************/
2113
2114	/*
2115	* ROL
2116	*/
2117
2118	/**
2119	* Updates the status bits (OF and CF) for an ROL instruction.
2120	*
2121	* @returns Status bits.
2122	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2123	* @param a_uResult Unsigned result value.
2124	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2125	*/
2126	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2127	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2128	it the same way as for 1 bit shifts. */ \
2129	AssertCompile(X86_EFL_CF_BIT == 0); \
2130	uint32_t fEflTmp = *(a_pfEFlags); \
2131	fEflTmp &= ~(X86_EFL_CF \| X86_EFL_OF); \
2132	uint32_t const fCarry = ((a_uResult) & X86_EFL_CF); \
2133	fEflTmp \|= fCarry; \
2134	fEflTmp \|= (((a_uResult) >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2135	*(a_pfEFlags) = fEflTmp; \
2136	} while (0)
2137
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t puDst, uint8_t cShift, uint32_t pfEFlags))
2139	{
2140	cShift &= 63;
2141	if (cShift)
2142	{
2143	uint64_t uResult = ASMRotateLeftU64(*puDst, cShift);
2144	*puDst = uResult;
2145	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 64);
2146	}
2147	}
2148
2149	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2150
2151	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u32,(uint32_t puDst, uint8_t cShift, uint32_t pfEFlags))
2152	{
2153	cShift &= 31;
2154	if (cShift)
2155	{
2156	uint32_t uResult = ASMRotateLeftU32(*puDst, cShift);
2157	*puDst = uResult;
2158	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 32);
2159	}
2160	}
2161
2162
2163	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u16,(uint16_t puDst, uint8_t cShift, uint32_t pfEFlags))
2164	{
2165	cShift &= 15;
2166	if (cShift)
2167	{
2168	uint16_t uDst = *puDst;
2169	uint16_t uResult = (uDst << cShift) \| (uDst >> (16 - cShift));
2170	*puDst = uResult;
2171	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 16);
2172	}
2173	}
2174
2175
2176	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u8,(uint8_t puDst, uint8_t cShift, uint32_t pfEFlags))
2177	{
2178	cShift &= 7;
2179	if (cShift)
2180	{
2181	uint8_t uDst = *puDst;
2182	uint8_t uResult = (uDst << cShift) \| (uDst >> (8 - cShift));
2183	*puDst = uResult;
2184	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 8);
2185	}
2186	}
2187
2188	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2189
2190
2191	/*
2192	* ROR
2193	*/
2194
2195	/**
2196	* Updates the status bits (OF and CF) for an ROL instruction.
2197	*
2198	* @returns Status bits.
2199	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2200	* @param a_uResult Unsigned result value.
2201	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2202	*/
2203	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2204	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2205	it the same way as for 1 bit shifts. */ \
2206	AssertCompile(X86_EFL_CF_BIT == 0); \
2207	uint32_t fEflTmp = *(a_pfEFlags); \
2208	fEflTmp &= ~(X86_EFL_CF \| X86_EFL_OF); \
2209	uint32_t const fCarry = ((a_uResult) >> ((a_cBitsWidth) - 1)) & X86_EFL_CF; \
2210	fEflTmp \|= fCarry; \
2211	fEflTmp \|= (((a_uResult) >> ((a_cBitsWidth) - 2)) ^ fCarry) << X86_EFL_OF_BIT; \
2212	*(a_pfEFlags) = fEflTmp; \
2213	} while (0)
2214
2215	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t puDst, uint8_t cShift, uint32_t pfEFlags))
2216	{
2217	cShift &= 63;
2218	if (cShift)
2219	{
2220	uint64_t const uResult = ASMRotateRightU64(*puDst, cShift);
2221	*puDst = uResult;
2222	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 64);
2223	}
2224	}
2225
2226	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2227
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u32,(uint32_t puDst, uint8_t cShift, uint32_t pfEFlags))
2229	{
2230	cShift &= 31;
2231	if (cShift)
2232	{
2233	uint64_t const uResult = ASMRotateRightU32(*puDst, cShift);
2234	*puDst = uResult;
2235	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 32);
2236	}
2237	}
2238
2239
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u16,(uint16_t puDst, uint8_t cShift, uint32_t pfEFlags))
2241	{
2242	cShift &= 15;
2243	if (cShift)
2244	{
2245	uint16_t uDst = *puDst;
2246	uint16_t uResult;
2247	uResult = uDst >> cShift;
2248	uResult \|= uDst << (16 - cShift);
2249	*puDst = uResult;
2250	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 16);
2251	}
2252	}
2253
2254
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u8,(uint8_t puDst, uint8_t cShift, uint32_t pfEFlags))
2256	{
2257	cShift &= 7;
2258	if (cShift)
2259	{
2260	uint8_t uDst = *puDst;
2261	uint8_t uResult;
2262	uResult = uDst >> cShift;
2263	uResult \|= uDst << (8 - cShift);
2264	*puDst = uResult;
2265	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 8);
2266	}
2267	}
2268
2269	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2270
2271
2272	/*
2273	* RCL
2274	*/
2275	#define EMIT_RCL(a_cBitsWidth) \
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2277	{ \
2278	cShift &= a_cBitsWidth - 1; \
2279	if (cShift) \
2280	{ \
2281	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2282	uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2283	if (cShift > 1) \
2284	uResult \|= uDst >> (a_cBitsWidth + 1 - cShift); \
2285	\
2286	uint32_t fEfl = *pfEFlags; \
2287	AssertCompile(X86_EFL_CF_BIT == 0); \
2288	uResult \|= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (cShift - 1); \
2289	\
2290	*puDst = uResult; \
2291	\
2292	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2293	it the same way as for 1 bit shifts. */ \
2294	fEfl &= ~(X86_EFL_CF \| X86_EFL_OF); \
2295	uint32_t const fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2296	fEfl \|= fCarry; \
2297	fEfl \|= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2298	*pfEFlags = fEfl; \
2299	} \
2300	}
2301	EMIT_RCL(64)
2302	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2303	EMIT_RCL(32)
2304	EMIT_RCL(16)
2305	EMIT_RCL(8)
2306	# endif
2307
2308
2309	/*
2310	* RCR
2311	*/
2312	#define EMIT_RCR(a_cBitsWidth) \
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ##_t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2314	{ \
2315	cShift &= a_cBitsWidth - 1; \
2316	if (cShift) \
2317	{ \
2318	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2319	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2320	if (cShift > 1) \
2321	uResult \|= uDst << (a_cBitsWidth + 1 - cShift); \
2322	\
2323	AssertCompile(X86_EFL_CF_BIT == 0); \
2324	uint32_t fEfl = *pfEFlags; \
2325	uResult \|= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (a_cBitsWidth - cShift); \
2326	*puDst = uResult; \
2327	\
2328	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2329	it the same way as for 1 bit shifts. */ \
2330	fEfl &= ~(X86_EFL_CF \| X86_EFL_OF); \
2331	uint32_t const fCarry = (uDst >> (cShift - 1)) & X86_EFL_CF; \
2332	fEfl \|= fCarry; \
2333	fEfl \|= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2334	*pfEFlags = fEfl; \
2335	} \
2336	}
2337	EMIT_RCR(64)
2338	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2339	EMIT_RCR(32)
2340	EMIT_RCR(16)
2341	EMIT_RCR(8)
2342	# endif
2343
2344
2345	/*
2346	* SHL
2347	*/
2348	#define EMIT_SHL(a_cBitsWidth) \
2349	IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2350	{ \
2351	cShift &= a_cBitsWidth - 1; \
2352	if (cShift) \
2353	{ \
2354	uint ## a_cBitsWidth ##_t const uDst = *puDst; \
2355	uint ## a_cBitsWidth ##_t uResult = uDst << cShift; \
2356	*puDst = uResult; \
2357	\
2358	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2359	it the same way as for 1 bit shifts. The AF bit is undefined, we \
2360	always set it to zero atm. */ \
2361	AssertCompile(X86_EFL_CF_BIT == 0); \
2362	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2363	uint32_t fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2364	fEfl \|= fCarry; \
2365	fEfl \|= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2366	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2367	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2368	fEfl \|= g_afParity[uResult & 0xff]; \
2369	*pfEFlags = fEfl; \
2370	} \
2371	}
2372	EMIT_SHL(64)
2373	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2374	EMIT_SHL(32)
2375	EMIT_SHL(16)
2376	EMIT_SHL(8)
2377	# endif
2378
2379
2380	/*
2381	* SHR
2382	*/
2383	#define EMIT_SHR(a_cBitsWidth) \
2384	IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2385	{ \
2386	cShift &= a_cBitsWidth - 1; \
2387	if (cShift) \
2388	{ \
2389	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2390	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2391	*puDst = uResult; \
2392	\
2393	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2394	it the same way as for 1 bit shifts. The AF bit is undefined, we \
2395	always set it to zero atm. */ \
2396	AssertCompile(X86_EFL_CF_BIT == 0); \
2397	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2398	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2399	fEfl \|= (uDst >> (a_cBitsWidth - 1)) << X86_EFL_OF_BIT; \
2400	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2401	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2402	fEfl \|= g_afParity[uResult & 0xff]; \
2403	*pfEFlags = fEfl; \
2404	} \
2405	}
2406	EMIT_SHR(64)
2407	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2408	EMIT_SHR(32)
2409	EMIT_SHR(16)
2410	EMIT_SHR(8)
2411	# endif
2412
2413
2414	/*
2415	* SAR
2416	*/
2417	#define EMIT_SAR(a_cBitsWidth) \
2418	IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2419	{ \
2420	cShift &= a_cBitsWidth - 1; \
2421	if (cShift) \
2422	{ \
2423	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2424	uint ## a_cBitsWidth ## _t uResult = (int ## a_cBitsWidth ## _t)uDst >> cShift; \
2425	*puDst = uResult; \
2426	\
2427	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2428	it the same way as for 1 bit shifts (0). The AF bit is undefined, \
2429	we always set it to zero atm. */ \
2430	AssertCompile(X86_EFL_CF_BIT == 0); \
2431	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2432	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2433	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2434	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2435	fEfl \|= g_afParity[uResult & 0xff]; \
2436	*pfEFlags = fEfl; \
2437	} \
2438	}
2439	EMIT_SAR(64)
2440	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2441	EMIT_SAR(32)
2442	EMIT_SAR(16)
2443	EMIT_SAR(8)
2444	# endif
2445
2446
2447	/*
2448	* SHLD
2449	*/
2450	#define EMIT_SHLD(a_cBitsWidth) \
2451	IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2452	uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2453	{ \
2454	cShift &= a_cBitsWidth - 1; \
2455	if (cShift) \
2456	{ \
2457	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2458	uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2459	uResult \|= uSrc >> (a_cBitsWidth - cShift); \
2460	*puDst = uResult; \
2461	\
2462	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2463	it the same way as for 1 bit shifts. The AF bit is undefined, \
2464	we always set it to zero atm. */ \
2465	AssertCompile(X86_EFL_CF_BIT == 0); \
2466	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2467	fEfl \|= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2468	fEfl \|= (uint32_t)((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))) << X86_EFL_OF_BIT; \
2469	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2470	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2471	fEfl \|= g_afParity[uResult & 0xff]; \
2472	*pfEFlags = fEfl; \
2473	} \
2474	}
2475	EMIT_SHLD(64)
2476	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2477	EMIT_SHLD(32)
2478	EMIT_SHLD(16)
2479	EMIT_SHLD(8)
2480	# endif
2481
2482
2483	/*
2484	* SHRD
2485	*/
2486	#define EMIT_SHRD(a_cBitsWidth) \
2487	IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2488	uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2489	{ \
2490	cShift &= a_cBitsWidth - 1; \
2491	if (cShift) \
2492	{ \
2493	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2494	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2495	uResult \|= uSrc << (a_cBitsWidth - cShift); \
2496	*puDst = uResult; \
2497	\
2498	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2499	it the same way as for 1 bit shifts. The AF bit is undefined, \
2500	we always set it to zero atm. */ \
2501	AssertCompile(X86_EFL_CF_BIT == 0); \
2502	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2503	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2504	fEfl \|= (uint32_t)((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))) << X86_EFL_OF_BIT; \
2505	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2506	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2507	fEfl \|= g_afParity[uResult & 0xff]; \
2508	*pfEFlags = fEfl; \
2509	} \
2510	}
2511	EMIT_SHRD(64)
2512	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2513	EMIT_SHRD(32)
2514	EMIT_SHRD(16)
2515	EMIT_SHRD(8)
2516	# endif
2517
2518
2519	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2520	/*
2521	* BSWAP
2522	*/
2523
2524	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u64,(uint64_t *puDst))
2525	{
2526	puDst = ASMByteSwapU64(puDst);
2527	}
2528
2529
2530	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u32,(uint32_t *puDst))
2531	{
2532	puDst = ASMByteSwapU32(puDst);
2533	}
2534
2535
2536	/* Note! undocument, so 32-bit arg */
2537	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u16,(uint32_t *puDst))
2538	{
2539	puDst = ASMByteSwapU16((uint16_t)puDst) \| (*puDst & UINT32_C(0xffff0000));
2540	}
2541
2542	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2543
2544
2545
2546	# if defined(IEM_WITHOUT_ASSEMBLY)
2547
2548	/*
2549	* LFENCE, SFENCE & MFENCE.
2550	*/
2551
2552	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void))
2553	{
2554	ASMReadFence();
2555	}
2556
2557
2558	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void))
2559	{
2560	ASMWriteFence();
2561	}
2562
2563
2564	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void))
2565	{
2566	ASMMemoryFence();
2567	}
2568
2569
2570	# ifndef RT_ARCH_ARM64
2571	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void))
2572	{
2573	ASMMemoryFence();
2574	}
2575	# endif
2576
2577	# endif
2578
2579	#endif /* !RT_ARCH_AMD64 \|\| IEM_WITHOUT_ASSEMBLY */
2580
2581
2582	IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t pu16Dst, uint16_t u16Src, uint32_t pfEFlags))
2583	{
2584	if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
2585	{
2586	*pu16Dst &= X86_SEL_MASK_OFF_RPL;
2587	*pu16Dst \|= u16Src & X86_SEL_RPL;
2588
2589	*pfEFlags \|= X86_EFL_ZF;
2590	}
2591	else
2592	*pfEFlags &= ~X86_EFL_ZF;
2593	}
2594
2595
2596	/*********************************************************************************************************************************
2597	* x87 FPU *
2598	*********************************************************************************************************************************/
2599	#if defined(IEM_WITHOUT_ASSEMBLY)
2600
2601	IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2602	{
2603	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2604	AssertReleaseFailed();
2605	}
2606
2607
2608	IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2609	{
2610	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2611	AssertReleaseFailed();
2612	}
2613
2614
2615	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2616	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2617	{
2618	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2619	AssertReleaseFailed();
2620	}
2621
2622
2623	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2624	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2625	{
2626	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2627	AssertReleaseFailed();
2628	}
2629
2630
2631	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2632	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2633	{
2634	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2635	AssertReleaseFailed();
2636	}
2637
2638
2639	IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2640	{
2641	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2642	AssertReleaseFailed();
2643	}
2644
2645
2646	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2647	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2648	{
2649	RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
2650	AssertReleaseFailed();
2651	}
2652
2653
2654	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2655	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2656	{
2657	RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
2658	AssertReleaseFailed();
2659	}
2660
2661
2662	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2663	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2664	{
2665	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2666	AssertReleaseFailed();
2667	}
2668
2669
2670	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2671	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2672	{
2673	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2674	AssertReleaseFailed();
2675	return 0;
2676	}
2677
2678
2679	IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2680	{
2681	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2682	AssertReleaseFailed();
2683	}
2684
2685
2686	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2687	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2688	{
2689	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2690	AssertReleaseFailed();
2691	}
2692
2693
2694	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2695	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2696	{
2697	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2698	AssertReleaseFailed();
2699	}
2700
2701
2702	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2703	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2704	{
2705	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2706	AssertReleaseFailed();
2707	}
2708
2709
2710	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2711	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2712	{
2713	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2714	AssertReleaseFailed();
2715	}
2716
2717
2718	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2719	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2720	{
2721	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2722	AssertReleaseFailed();
2723	}
2724
2725
2726	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2727	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2728	{
2729	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2730	AssertReleaseFailed();
2731	}
2732
2733
2734	IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2735	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2736	{
2737	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2738	AssertReleaseFailed();
2739	}
2740
2741
2742	IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2743	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2744	{
2745	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2746	AssertReleaseFailed();
2747	}
2748
2749
2750	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2751	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2752	{
2753	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
2754	AssertReleaseFailed();
2755	}
2756
2757
2758	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2759	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2760	{
2761	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
2762	AssertReleaseFailed();
2763	}
2764
2765
2766	IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2767	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2768	{
2769	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2770	AssertReleaseFailed();
2771	}
2772
2773
2774	IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2775	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2776	{
2777	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2778	AssertReleaseFailed();
2779	}
2780
2781
2782	IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2783	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2784	{
2785	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2786	AssertReleaseFailed();
2787	}
2788
2789
2790	IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2791	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2792	{
2793	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2794	AssertReleaseFailed();
2795	}
2796
2797
2798	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
2799	{
2800	RT_NOREF(pFpuState, pFpuRes, pi16Val);
2801	AssertReleaseFailed();
2802	}
2803
2804
2805	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
2806	{
2807	RT_NOREF(pFpuState, pFpuRes, pi32Val);
2808	AssertReleaseFailed();
2809	}
2810
2811
2812	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
2813	{
2814	RT_NOREF(pFpuState, pFpuRes, pi64Val);
2815	AssertReleaseFailed();
2816	}
2817
2818
2819	IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2820	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2821	{
2822	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2823	AssertReleaseFailed();
2824	}
2825
2826
2827	IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2828	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2829	{
2830	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2831	AssertReleaseFailed();
2832	}
2833
2834
2835	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2836	int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2837	{
2838	RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2839	AssertReleaseFailed();
2840	}
2841
2842
2843	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2844	int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2845	{
2846	RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2847	AssertReleaseFailed();
2848	}
2849
2850
2851	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2852	int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2853	{
2854	RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2855	AssertReleaseFailed();
2856	}
2857
2858
2859	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2860	int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2861	{
2862	RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2863	AssertReleaseFailed();
2864	}
2865
2866
2867	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2868	int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2869	{
2870	RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2871	AssertReleaseFailed();
2872	}
2873
2874
2875	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2876	int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2877	{
2878	RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2879	AssertReleaseFailed();
2880	}
2881
2882
2883	IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2884	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2885	{
2886	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2887	AssertReleaseFailed();
2888	}
2889
2890
2891	IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2892	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2893	{
2894	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2895	AssertReleaseFailed();
2896	}
2897
2898
2899	IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2900	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2901	{
2902	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2903	AssertReleaseFailed();
2904	}
2905
2906
2907	IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2908	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2909	{
2910	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2911	AssertReleaseFailed();
2912	}
2913
2914
2915	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
2916	{
2917	RT_NOREF(pFpuState, pFpuRes, pr32Val);
2918	AssertReleaseFailed();
2919	}
2920
2921
2922	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
2923	{
2924	RT_NOREF(pFpuState, pFpuRes, pr64Val);
2925	AssertReleaseFailed();
2926	}
2927
2928	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2929	{
2930	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2931	AssertReleaseFailed();
2932	}
2933
2934
2935	IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2936	{
2937	RT_NOREF(pFpuState, pFpuRes);
2938	AssertReleaseFailed();
2939	}
2940
2941
2942	IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2943	{
2944	RT_NOREF(pFpuState, pFpuRes);
2945	AssertReleaseFailed();
2946	}
2947
2948
2949	IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2950	{
2951	RT_NOREF(pFpuState, pFpuRes);
2952	AssertReleaseFailed();
2953	}
2954
2955
2956	IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2957	{
2958	RT_NOREF(pFpuState, pFpuRes);
2959	AssertReleaseFailed();
2960	}
2961
2962
2963	IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2964	{
2965	RT_NOREF(pFpuState, pFpuRes);
2966	AssertReleaseFailed();
2967	}
2968
2969
2970	IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2971	{
2972	RT_NOREF(pFpuState, pFpuRes);
2973	AssertReleaseFailed();
2974	}
2975
2976
2977	IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2978	{
2979	RT_NOREF(pFpuState, pFpuRes);
2980	AssertReleaseFailed();
2981	}
2982
2983
2984	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2985	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2986	{
2987	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2988	AssertReleaseFailed();
2989	}
2990
2991
2992	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2993	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2994	{
2995	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2996	AssertReleaseFailed();
2997	}
2998
2999
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3001	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3002	{
3003	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3004	AssertReleaseFailed();
3005	}
3006
3007
3008	IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3009	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3010	{
3011	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3012	AssertReleaseFailed();
3013	}
3014
3015
3016	IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3017	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3018	{
3019	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3020	AssertReleaseFailed();
3021	}
3022
3023
3024	IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3025	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3026	{
3027	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3028	AssertReleaseFailed();
3029	}
3030
3031
3032	IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3033	{
3034	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3035	AssertReleaseFailed();
3036	}
3037
3038
3039	IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3040	{
3041	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3042	AssertReleaseFailed();
3043	}
3044
3045
3046	IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3047	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3048	{
3049	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3050	AssertReleaseFailed();
3051	}
3052
3053
3054	IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3055	{
3056	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3057	AssertReleaseFailed();
3058	}
3059
3060
3061	IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3062	{
3063	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3064	AssertReleaseFailed();
3065	}
3066
3067
3068	IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3069	{
3070	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3071	AssertReleaseFailed();
3072	}
3073
3074
3075	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3076	PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
3077	{
3078	RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
3079	AssertReleaseFailed();
3080	}
3081
3082
3083	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3084	PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
3085	{
3086	RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
3087	AssertReleaseFailed();
3088	}
3089
3090
3091	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3092	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
3093	{
3094	RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
3095	AssertReleaseFailed();
3096	}
3097
3098
3099	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3100	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3101	{
3102	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3103	AssertReleaseFailed();
3104	}
3105
3106
3107	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3108	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3109	{
3110	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3111	AssertReleaseFailed();
3112	}
3113
3114
3115	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3116	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3117	{
3118	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3119	AssertReleaseFailed();
3120	}
3121
3122
3123	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3124	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3125	{
3126	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3127	AssertReleaseFailed();
3128	}
3129
3130
3131	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3132	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3133	{
3134	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3135	AssertReleaseFailed();
3136	}
3137
3138
3139	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3140	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3141	{
3142	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3143	AssertReleaseFailed();
3144	}
3145
3146
3147	IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3148	{
3149	RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3150	AssertReleaseFailed();
3151	}
3152
3153
3154	IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3155	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3156	{
3157	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3158	AssertReleaseFailed();
3159	}
3160
3161
3162	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3163	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3164	{
3165	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
3166	AssertReleaseFailed();
3167	return 0;
3168	}
3169
3170
3171	IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3172	{
3173	RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3174	AssertReleaseFailed();
3175	}
3176
3177
3178	IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3179	{
3180	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3181	AssertReleaseFailed();
3182	}
3183
3184
3185	IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3186	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3187	{
3188	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3189	AssertReleaseFailed();
3190	}
3191
3192
3193	IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3194	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3195	{
3196	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3197	AssertReleaseFailed();
3198	}
3199
3200	#endif /* IEM_WITHOUT_ASSEMBLY */
3201
3202
3203	/*********************************************************************************************************************************
3204	* MMX, SSE & AVX *
3205	*********************************************************************************************************************************/
3206
3207	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3208	{
3209	RT_NOREF(pFpuState);
3210	puDst->au32[0] = puSrc->au32[0];
3211	puDst->au32[1] = puSrc->au32[0];
3212	puDst->au32[2] = puSrc->au32[2];
3213	puDst->au32[3] = puSrc->au32[2];
3214	}
3215
3216	#ifdef IEM_WITH_VEX
3217
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3219	{
3220	pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
3221	pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
3222	pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
3223	pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
3224	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3225	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3226	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3227	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3228	}
3229
3230
3231	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3232	{
3233	pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
3234	pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
3235	pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
3236	pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
3237	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
3238	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
3239	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
3240	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
3241	}
3242
3243	#endif /* IEM_WITH_VEX */
3244
3245
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3247	{
3248	RT_NOREF(pFpuState);
3249	puDst->au32[0] = puSrc->au32[1];
3250	puDst->au32[1] = puSrc->au32[1];
3251	puDst->au32[2] = puSrc->au32[3];
3252	puDst->au32[3] = puSrc->au32[3];
3253	}
3254
3255
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
3257	{
3258	RT_NOREF(pFpuState);
3259	puDst->au64[0] = uSrc;
3260	puDst->au64[1] = uSrc;
3261	}
3262
3263	#ifdef IEM_WITH_VEX
3264
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3266	{
3267	pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
3268	pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
3269	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3270	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3271	}
3272
3273	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3274	{
3275	pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
3276	pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
3277	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
3278	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
3279	}
3280
3281	#endif /* IEM_WITH_VEX */
3282
3283	#ifdef IEM_WITHOUT_ASSEMBLY
3284
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3286	{
3287	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3288	AssertReleaseFailed();
3289	}
3290
3291
3292	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3293	{
3294	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3295	AssertReleaseFailed();
3296	}
3297
3298
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3300	{
3301	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3302	AssertReleaseFailed();
3303	}
3304
3305
3306	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3307	{
3308	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3309	AssertReleaseFailed();
3310	}
3311
3312
3313	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3314	{
3315	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3316	AssertReleaseFailed();
3317	}
3318
3319
3320	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3321	{
3322	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3323	AssertReleaseFailed();
3324	}
3325
3326
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3328	{
3329	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3330	AssertReleaseFailed();
3331	}
3332
3333
3334	IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3335	{
3336	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3337	AssertReleaseFailed();
3338	}
3339
3340
3341	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3342	{
3343	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3344	AssertReleaseFailed();
3345
3346	}
3347
3348
3349	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src))
3350	{
3351	RT_NOREF(pFpuState, pu64Dst, pu128Src);
3352	AssertReleaseFailed();
3353	}
3354
3355
3356	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil))
3357	{
3358	RT_NOREF(pFpuState, pu64Dst, pu64Src, bEvil);
3359	AssertReleaseFailed();
3360	}
3361
3362
3363	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufhw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3364	{
3365	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3366	AssertReleaseFailed();
3367	}
3368
3369
3370	IEM_DECL_IMPL_DEF(void, iemAImpl_pshuflw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3371	{
3372	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3373	AssertReleaseFailed();
3374	}
3375
3376
3377	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufd,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3378	{
3379	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3380	AssertReleaseFailed();
3381	}
3382
3383	/* PUNPCKHxxx */
3384
3385	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3386	{
3387	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3388	AssertReleaseFailed();
3389	}
3390
3391
3392	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3393	{
3394	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3395	AssertReleaseFailed();
3396	}
3397
3398
3399	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3400	{
3401	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3402	AssertReleaseFailed();
3403	}
3404
3405
3406	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3407	{
3408	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3409	AssertReleaseFailed();
3410	}
3411
3412
3413	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3414	{
3415	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3416	AssertReleaseFailed();
3417	}
3418
3419
3420	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3421	{
3422	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3423	AssertReleaseFailed();
3424	}
3425
3426
3427	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3428	{
3429	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3430	AssertReleaseFailed();
3431	}
3432
3433	/* PUNPCKLxxx */
3434
3435	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3436	{
3437	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3438	AssertReleaseFailed();
3439	}
3440
3441
3442	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3443	{
3444	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3445	AssertReleaseFailed();
3446	}
3447
3448
3449	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3450	{
3451	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3452	AssertReleaseFailed();
3453	}
3454
3455
3456	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3457	{
3458	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3459	AssertReleaseFailed();
3460	}
3461
3462
3463	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3464	{
3465	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3466	AssertReleaseFailed();
3467	}
3468
3469
3470	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3471	{
3472	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3473	AssertReleaseFailed();
3474	}
3475
3476
3477	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3478	{
3479	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3480	AssertReleaseFailed();
3481	}
3482
3483	#endif /* IEM_WITHOUT_ASSEMBLY */

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp@ 93878

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