IEMAllAImplC.cpp@ 93888

Last change on this file since 93888 was 93888, checked in by vboxsync, 3 years ago
VMM/IEM: Corrected MUL, IMUL, DIV and IDIV instruction helpers (C versions); added tests for them. bugref:9898
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1	/* $Id: IEMAllAImplC.cpp 93888 2022-02-22 15:46:53Z vboxsync $ */
2	/** @file
3	* IEM - Instruction Implementation in Assembly, portable C variant.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include "IEMInternal.h"
23	#include <VBox/vmm/vmcc.h>
24	#include <iprt/errcore.h>
25	#include <iprt/x86.h>
26	#include <iprt/uint128.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** @def IEM_WITHOUT_ASSEMBLY
33	* Enables all the code in this file.
34	*/
35	#if !defined(IEM_WITHOUT_ASSEMBLY)
36	# if defined(RT_ARCH_ARM32) \|\| defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
37	# define IEM_WITHOUT_ASSEMBLY
38	# endif
39	#endif
40	/* IEM_WITH_ASSEMBLY trumps IEM_WITHOUT_ASSEMBLY for tstIEMAImplAsm purposes. */
41	#ifdef IEM_WITH_ASSEMBLY
42	# undef IEM_WITHOUT_ASSEMBLY
43	#endif
44
45	/**
46	* Calculates the signed flag value given a result and it's bit width.
47	*
48	* The signed flag (SF) is a duplication of the most significant bit in the
49	* result.
50	*
51	* @returns X86_EFL_SF or 0.
52	* @param a_uResult Unsigned result value.
53	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
54	*/
55	#define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
56	( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
57
58	/**
59	* Calculates the zero flag value given a result.
60	*
61	* The zero flag (ZF) indicates whether the result is zero or not.
62	*
63	* @returns X86_EFL_ZF or 0.
64	* @param a_uResult Unsigned result value.
65	*/
66	#define X86_EFL_CALC_ZF(a_uResult) \
67	( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
68
69	/**
70	* Extracts the OF flag from a OF calculation result.
71	*
72	* These are typically used by concating with a bitcount. The problem is that
73	* 8-bit values needs shifting in the other direction than the others.
74	*/
75	#define X86_EFL_GET_OF_8(a_uValue) (((uint32_t)(a_uValue) << (X86_EFL_OF_BIT - 8 + 1)) & X86_EFL_OF)
76	#define X86_EFL_GET_OF_16(a_uValue) ((uint32_t)((a_uValue) >> (16 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
77	#define X86_EFL_GET_OF_32(a_uValue) ((uint32_t)((a_uValue) >> (32 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
78	#define X86_EFL_GET_OF_64(a_uValue) ((uint32_t)((a_uValue) >> (64 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
79
80	/**
81	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) after arithmetic op.
82	*
83	* @returns Status bits.
84	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
85	* @param a_uResult Unsigned result value.
86	* @param a_uSrc The source value (for AF calc).
87	* @param a_uDst The original destination value (for AF calc).
88	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
89	* @param a_CfExpr Bool expression for the carry flag (CF).
90	* @param a_uSrcOf The a_uSrc value to use for overflow calculation.
91	*/
92	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
93	do { \
94	uint32_t fEflTmp = *(a_pfEFlags); \
95	fEflTmp &= ~X86_EFL_STATUS_BITS; \
96	fEflTmp \|= (a_CfExpr) << X86_EFL_CF_BIT; \
97	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
98	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
99	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
100	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
101	\
102	/* Overflow during ADDition happens when both inputs have the same signed \
103	bit value and the result has a different sign bit value. \
104	\
105	Since subtraction can be rewritten as addition: 2 - 1 == 2 + -1, it \
106	follows that for SUBtraction the signed bit value must differ between \
107	the two inputs and the result's signed bit diff from the first input. \
108	Note! Must xor with sign bit to convert, not do (0 - a_uSrc). \
109	\
110	See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
111	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth( ( ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
112	& RT_BIT_64(a_cBitsWidth - 1)) \
113	& ((a_uResult) ^ (a_uDst)) ); \
114	*(a_pfEFlags) = fEflTmp; \
115	} while (0)
116
117	/**
118	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
119	*
120	* CF and OF are defined to be 0 by logical operations. AF on the other hand is
121	* undefined. We do not set AF, as that seems to make the most sense (which
122	* probably makes it the most wrong in real life).
123	*
124	* @returns Status bits.
125	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
126	* @param a_uResult Unsigned result value.
127	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
128	* @param a_fExtra Additional bits to set.
129	*/
130	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
131	do { \
132	uint32_t fEflTmp = *(a_pfEFlags); \
133	fEflTmp &= ~X86_EFL_STATUS_BITS; \
134	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
135	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
136	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
137	fEflTmp \|= (a_fExtra); \
138	*(a_pfEFlags) = fEflTmp; \
139	} while (0)
140
141
142	/*********************************************************************************************************************************
143	* Global Variables *
144	*********************************************************************************************************************************/
145	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
146	/**
147	* Parity calculation table.
148	*
149	* The generator code:
150	* @code
151	* #include <stdio.h>
152	*
153	* int main()
154	* {
155	* unsigned b;
156	* for (b = 0; b < 256; b++)
157	* {
158	* int cOnes = ( b & 1)
159	* + ((b >> 1) & 1)
160	* + ((b >> 2) & 1)
161	* + ((b >> 3) & 1)
162	* + ((b >> 4) & 1)
163	* + ((b >> 5) & 1)
164	* + ((b >> 6) & 1)
165	* + ((b >> 7) & 1);
166	* printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
167	* b,
168	* (b >> 7) & 1,
169	* (b >> 6) & 1,
170	* (b >> 5) & 1,
171	* (b >> 4) & 1,
172	* (b >> 3) & 1,
173	* (b >> 2) & 1,
174	* (b >> 1) & 1,
175	* b & 1,
176	* cOnes & 1 ? "0" : "X86_EFL_PF");
177	* }
178	* return 0;
179	* }
180	* @endcode
181	*/
182	static uint8_t const g_afParity[256] =
183	{
184	/* 0000 = 00000000b */ X86_EFL_PF,
185	/* 0x01 = 00000001b */ 0,
186	/* 0x02 = 00000010b */ 0,
187	/* 0x03 = 00000011b */ X86_EFL_PF,
188	/* 0x04 = 00000100b */ 0,
189	/* 0x05 = 00000101b */ X86_EFL_PF,
190	/* 0x06 = 00000110b */ X86_EFL_PF,
191	/* 0x07 = 00000111b */ 0,
192	/* 0x08 = 00001000b */ 0,
193	/* 0x09 = 00001001b */ X86_EFL_PF,
194	/* 0x0a = 00001010b */ X86_EFL_PF,
195	/* 0x0b = 00001011b */ 0,
196	/* 0x0c = 00001100b */ X86_EFL_PF,
197	/* 0x0d = 00001101b */ 0,
198	/* 0x0e = 00001110b */ 0,
199	/* 0x0f = 00001111b */ X86_EFL_PF,
200	/* 0x10 = 00010000b */ 0,
201	/* 0x11 = 00010001b */ X86_EFL_PF,
202	/* 0x12 = 00010010b */ X86_EFL_PF,
203	/* 0x13 = 00010011b */ 0,
204	/* 0x14 = 00010100b */ X86_EFL_PF,
205	/* 0x15 = 00010101b */ 0,
206	/* 0x16 = 00010110b */ 0,
207	/* 0x17 = 00010111b */ X86_EFL_PF,
208	/* 0x18 = 00011000b */ X86_EFL_PF,
209	/* 0x19 = 00011001b */ 0,
210	/* 0x1a = 00011010b */ 0,
211	/* 0x1b = 00011011b */ X86_EFL_PF,
212	/* 0x1c = 00011100b */ 0,
213	/* 0x1d = 00011101b */ X86_EFL_PF,
214	/* 0x1e = 00011110b */ X86_EFL_PF,
215	/* 0x1f = 00011111b */ 0,
216	/* 0x20 = 00100000b */ 0,
217	/* 0x21 = 00100001b */ X86_EFL_PF,
218	/* 0x22 = 00100010b */ X86_EFL_PF,
219	/* 0x23 = 00100011b */ 0,
220	/* 0x24 = 00100100b */ X86_EFL_PF,
221	/* 0x25 = 00100101b */ 0,
222	/* 0x26 = 00100110b */ 0,
223	/* 0x27 = 00100111b */ X86_EFL_PF,
224	/* 0x28 = 00101000b */ X86_EFL_PF,
225	/* 0x29 = 00101001b */ 0,
226	/* 0x2a = 00101010b */ 0,
227	/* 0x2b = 00101011b */ X86_EFL_PF,
228	/* 0x2c = 00101100b */ 0,
229	/* 0x2d = 00101101b */ X86_EFL_PF,
230	/* 0x2e = 00101110b */ X86_EFL_PF,
231	/* 0x2f = 00101111b */ 0,
232	/* 0x30 = 00110000b */ X86_EFL_PF,
233	/* 0x31 = 00110001b */ 0,
234	/* 0x32 = 00110010b */ 0,
235	/* 0x33 = 00110011b */ X86_EFL_PF,
236	/* 0x34 = 00110100b */ 0,
237	/* 0x35 = 00110101b */ X86_EFL_PF,
238	/* 0x36 = 00110110b */ X86_EFL_PF,
239	/* 0x37 = 00110111b */ 0,
240	/* 0x38 = 00111000b */ 0,
241	/* 0x39 = 00111001b */ X86_EFL_PF,
242	/* 0x3a = 00111010b */ X86_EFL_PF,
243	/* 0x3b = 00111011b */ 0,
244	/* 0x3c = 00111100b */ X86_EFL_PF,
245	/* 0x3d = 00111101b */ 0,
246	/* 0x3e = 00111110b */ 0,
247	/* 0x3f = 00111111b */ X86_EFL_PF,
248	/* 0x40 = 01000000b */ 0,
249	/* 0x41 = 01000001b */ X86_EFL_PF,
250	/* 0x42 = 01000010b */ X86_EFL_PF,
251	/* 0x43 = 01000011b */ 0,
252	/* 0x44 = 01000100b */ X86_EFL_PF,
253	/* 0x45 = 01000101b */ 0,
254	/* 0x46 = 01000110b */ 0,
255	/* 0x47 = 01000111b */ X86_EFL_PF,
256	/* 0x48 = 01001000b */ X86_EFL_PF,
257	/* 0x49 = 01001001b */ 0,
258	/* 0x4a = 01001010b */ 0,
259	/* 0x4b = 01001011b */ X86_EFL_PF,
260	/* 0x4c = 01001100b */ 0,
261	/* 0x4d = 01001101b */ X86_EFL_PF,
262	/* 0x4e = 01001110b */ X86_EFL_PF,
263	/* 0x4f = 01001111b */ 0,
264	/* 0x50 = 01010000b */ X86_EFL_PF,
265	/* 0x51 = 01010001b */ 0,
266	/* 0x52 = 01010010b */ 0,
267	/* 0x53 = 01010011b */ X86_EFL_PF,
268	/* 0x54 = 01010100b */ 0,
269	/* 0x55 = 01010101b */ X86_EFL_PF,
270	/* 0x56 = 01010110b */ X86_EFL_PF,
271	/* 0x57 = 01010111b */ 0,
272	/* 0x58 = 01011000b */ 0,
273	/* 0x59 = 01011001b */ X86_EFL_PF,
274	/* 0x5a = 01011010b */ X86_EFL_PF,
275	/* 0x5b = 01011011b */ 0,
276	/* 0x5c = 01011100b */ X86_EFL_PF,
277	/* 0x5d = 01011101b */ 0,
278	/* 0x5e = 01011110b */ 0,
279	/* 0x5f = 01011111b */ X86_EFL_PF,
280	/* 0x60 = 01100000b */ X86_EFL_PF,
281	/* 0x61 = 01100001b */ 0,
282	/* 0x62 = 01100010b */ 0,
283	/* 0x63 = 01100011b */ X86_EFL_PF,
284	/* 0x64 = 01100100b */ 0,
285	/* 0x65 = 01100101b */ X86_EFL_PF,
286	/* 0x66 = 01100110b */ X86_EFL_PF,
287	/* 0x67 = 01100111b */ 0,
288	/* 0x68 = 01101000b */ 0,
289	/* 0x69 = 01101001b */ X86_EFL_PF,
290	/* 0x6a = 01101010b */ X86_EFL_PF,
291	/* 0x6b = 01101011b */ 0,
292	/* 0x6c = 01101100b */ X86_EFL_PF,
293	/* 0x6d = 01101101b */ 0,
294	/* 0x6e = 01101110b */ 0,
295	/* 0x6f = 01101111b */ X86_EFL_PF,
296	/* 0x70 = 01110000b */ 0,
297	/* 0x71 = 01110001b */ X86_EFL_PF,
298	/* 0x72 = 01110010b */ X86_EFL_PF,
299	/* 0x73 = 01110011b */ 0,
300	/* 0x74 = 01110100b */ X86_EFL_PF,
301	/* 0x75 = 01110101b */ 0,
302	/* 0x76 = 01110110b */ 0,
303	/* 0x77 = 01110111b */ X86_EFL_PF,
304	/* 0x78 = 01111000b */ X86_EFL_PF,
305	/* 0x79 = 01111001b */ 0,
306	/* 0x7a = 01111010b */ 0,
307	/* 0x7b = 01111011b */ X86_EFL_PF,
308	/* 0x7c = 01111100b */ 0,
309	/* 0x7d = 01111101b */ X86_EFL_PF,
310	/* 0x7e = 01111110b */ X86_EFL_PF,
311	/* 0x7f = 01111111b */ 0,
312	/* 0x80 = 10000000b */ 0,
313	/* 0x81 = 10000001b */ X86_EFL_PF,
314	/* 0x82 = 10000010b */ X86_EFL_PF,
315	/* 0x83 = 10000011b */ 0,
316	/* 0x84 = 10000100b */ X86_EFL_PF,
317	/* 0x85 = 10000101b */ 0,
318	/* 0x86 = 10000110b */ 0,
319	/* 0x87 = 10000111b */ X86_EFL_PF,
320	/* 0x88 = 10001000b */ X86_EFL_PF,
321	/* 0x89 = 10001001b */ 0,
322	/* 0x8a = 10001010b */ 0,
323	/* 0x8b = 10001011b */ X86_EFL_PF,
324	/* 0x8c = 10001100b */ 0,
325	/* 0x8d = 10001101b */ X86_EFL_PF,
326	/* 0x8e = 10001110b */ X86_EFL_PF,
327	/* 0x8f = 10001111b */ 0,
328	/* 0x90 = 10010000b */ X86_EFL_PF,
329	/* 0x91 = 10010001b */ 0,
330	/* 0x92 = 10010010b */ 0,
331	/* 0x93 = 10010011b */ X86_EFL_PF,
332	/* 0x94 = 10010100b */ 0,
333	/* 0x95 = 10010101b */ X86_EFL_PF,
334	/* 0x96 = 10010110b */ X86_EFL_PF,
335	/* 0x97 = 10010111b */ 0,
336	/* 0x98 = 10011000b */ 0,
337	/* 0x99 = 10011001b */ X86_EFL_PF,
338	/* 0x9a = 10011010b */ X86_EFL_PF,
339	/* 0x9b = 10011011b */ 0,
340	/* 0x9c = 10011100b */ X86_EFL_PF,
341	/* 0x9d = 10011101b */ 0,
342	/* 0x9e = 10011110b */ 0,
343	/* 0x9f = 10011111b */ X86_EFL_PF,
344	/* 0xa0 = 10100000b */ X86_EFL_PF,
345	/* 0xa1 = 10100001b */ 0,
346	/* 0xa2 = 10100010b */ 0,
347	/* 0xa3 = 10100011b */ X86_EFL_PF,
348	/* 0xa4 = 10100100b */ 0,
349	/* 0xa5 = 10100101b */ X86_EFL_PF,
350	/* 0xa6 = 10100110b */ X86_EFL_PF,
351	/* 0xa7 = 10100111b */ 0,
352	/* 0xa8 = 10101000b */ 0,
353	/* 0xa9 = 10101001b */ X86_EFL_PF,
354	/* 0xaa = 10101010b */ X86_EFL_PF,
355	/* 0xab = 10101011b */ 0,
356	/* 0xac = 10101100b */ X86_EFL_PF,
357	/* 0xad = 10101101b */ 0,
358	/* 0xae = 10101110b */ 0,
359	/* 0xaf = 10101111b */ X86_EFL_PF,
360	/* 0xb0 = 10110000b */ 0,
361	/* 0xb1 = 10110001b */ X86_EFL_PF,
362	/* 0xb2 = 10110010b */ X86_EFL_PF,
363	/* 0xb3 = 10110011b */ 0,
364	/* 0xb4 = 10110100b */ X86_EFL_PF,
365	/* 0xb5 = 10110101b */ 0,
366	/* 0xb6 = 10110110b */ 0,
367	/* 0xb7 = 10110111b */ X86_EFL_PF,
368	/* 0xb8 = 10111000b */ X86_EFL_PF,
369	/* 0xb9 = 10111001b */ 0,
370	/* 0xba = 10111010b */ 0,
371	/* 0xbb = 10111011b */ X86_EFL_PF,
372	/* 0xbc = 10111100b */ 0,
373	/* 0xbd = 10111101b */ X86_EFL_PF,
374	/* 0xbe = 10111110b */ X86_EFL_PF,
375	/* 0xbf = 10111111b */ 0,
376	/* 0xc0 = 11000000b */ X86_EFL_PF,
377	/* 0xc1 = 11000001b */ 0,
378	/* 0xc2 = 11000010b */ 0,
379	/* 0xc3 = 11000011b */ X86_EFL_PF,
380	/* 0xc4 = 11000100b */ 0,
381	/* 0xc5 = 11000101b */ X86_EFL_PF,
382	/* 0xc6 = 11000110b */ X86_EFL_PF,
383	/* 0xc7 = 11000111b */ 0,
384	/* 0xc8 = 11001000b */ 0,
385	/* 0xc9 = 11001001b */ X86_EFL_PF,
386	/* 0xca = 11001010b */ X86_EFL_PF,
387	/* 0xcb = 11001011b */ 0,
388	/* 0xcc = 11001100b */ X86_EFL_PF,
389	/* 0xcd = 11001101b */ 0,
390	/* 0xce = 11001110b */ 0,
391	/* 0xcf = 11001111b */ X86_EFL_PF,
392	/* 0xd0 = 11010000b */ 0,
393	/* 0xd1 = 11010001b */ X86_EFL_PF,
394	/* 0xd2 = 11010010b */ X86_EFL_PF,
395	/* 0xd3 = 11010011b */ 0,
396	/* 0xd4 = 11010100b */ X86_EFL_PF,
397	/* 0xd5 = 11010101b */ 0,
398	/* 0xd6 = 11010110b */ 0,
399	/* 0xd7 = 11010111b */ X86_EFL_PF,
400	/* 0xd8 = 11011000b */ X86_EFL_PF,
401	/* 0xd9 = 11011001b */ 0,
402	/* 0xda = 11011010b */ 0,
403	/* 0xdb = 11011011b */ X86_EFL_PF,
404	/* 0xdc = 11011100b */ 0,
405	/* 0xdd = 11011101b */ X86_EFL_PF,
406	/* 0xde = 11011110b */ X86_EFL_PF,
407	/* 0xdf = 11011111b */ 0,
408	/* 0xe0 = 11100000b */ 0,
409	/* 0xe1 = 11100001b */ X86_EFL_PF,
410	/* 0xe2 = 11100010b */ X86_EFL_PF,
411	/* 0xe3 = 11100011b */ 0,
412	/* 0xe4 = 11100100b */ X86_EFL_PF,
413	/* 0xe5 = 11100101b */ 0,
414	/* 0xe6 = 11100110b */ 0,
415	/* 0xe7 = 11100111b */ X86_EFL_PF,
416	/* 0xe8 = 11101000b */ X86_EFL_PF,
417	/* 0xe9 = 11101001b */ 0,
418	/* 0xea = 11101010b */ 0,
419	/* 0xeb = 11101011b */ X86_EFL_PF,
420	/* 0xec = 11101100b */ 0,
421	/* 0xed = 11101101b */ X86_EFL_PF,
422	/* 0xee = 11101110b */ X86_EFL_PF,
423	/* 0xef = 11101111b */ 0,
424	/* 0xf0 = 11110000b */ X86_EFL_PF,
425	/* 0xf1 = 11110001b */ 0,
426	/* 0xf2 = 11110010b */ 0,
427	/* 0xf3 = 11110011b */ X86_EFL_PF,
428	/* 0xf4 = 11110100b */ 0,
429	/* 0xf5 = 11110101b */ X86_EFL_PF,
430	/* 0xf6 = 11110110b */ X86_EFL_PF,
431	/* 0xf7 = 11110111b */ 0,
432	/* 0xf8 = 11111000b */ 0,
433	/* 0xf9 = 11111001b */ X86_EFL_PF,
434	/* 0xfa = 11111010b */ X86_EFL_PF,
435	/* 0xfb = 11111011b */ 0,
436	/* 0xfc = 11111100b */ X86_EFL_PF,
437	/* 0xfd = 11111101b */ 0,
438	/* 0xfe = 11111110b */ 0,
439	/* 0xff = 11111111b */ X86_EFL_PF,
440	};
441	#endif /* !RT_ARCH_AMD64 \|\| IEM_WITHOUT_ASSEMBLY */
442
443
444
445	/*
446	* There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
447	* it all in C is probably safer atm., optimize what's necessary later, maybe.
448	*/
449	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
450
451
452	/*********************************************************************************************************************************
453	* Binary Operations *
454	*********************************************************************************************************************************/
455
456	/*
457	* ADD
458	*/
459
460	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
461	{
462	uint64_t uDst = *puDst;
463	uint64_t uResult = uDst + uSrc;
464	*puDst = uResult;
465	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
466	}
467
468	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
469
470	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
471	{
472	uint32_t uDst = *puDst;
473	uint32_t uResult = uDst + uSrc;
474	*puDst = uResult;
475	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
476	}
477
478
479	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
480	{
481	uint16_t uDst = *puDst;
482	uint16_t uResult = uDst + uSrc;
483	*puDst = uResult;
484	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
485	}
486
487
488	IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
489	{
490	uint8_t uDst = *puDst;
491	uint8_t uResult = uDst + uSrc;
492	*puDst = uResult;
493	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
494	}
495
496	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
497
498	/*
499	* ADC
500	*/
501
502	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
503	{
504	if (!(*pfEFlags & X86_EFL_CF))
505	iemAImpl_add_u64(puDst, uSrc, pfEFlags);
506	else
507	{
508	uint64_t uDst = *puDst;
509	uint64_t uResult = uDst + uSrc + 1;
510	*puDst = uResult;
511	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
512	}
513	}
514
515	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
516
517	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
518	{
519	if (!(*pfEFlags & X86_EFL_CF))
520	iemAImpl_add_u32(puDst, uSrc, pfEFlags);
521	else
522	{
523	uint32_t uDst = *puDst;
524	uint32_t uResult = uDst + uSrc + 1;
525	*puDst = uResult;
526	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
527	}
528	}
529
530
531	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
532	{
533	if (!(*pfEFlags & X86_EFL_CF))
534	iemAImpl_add_u16(puDst, uSrc, pfEFlags);
535	else
536	{
537	uint16_t uDst = *puDst;
538	uint16_t uResult = uDst + uSrc + 1;
539	*puDst = uResult;
540	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
541	}
542	}
543
544
545	IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
546	{
547	if (!(*pfEFlags & X86_EFL_CF))
548	iemAImpl_add_u8(puDst, uSrc, pfEFlags);
549	else
550	{
551	uint8_t uDst = *puDst;
552	uint8_t uResult = uDst + uSrc + 1;
553	*puDst = uResult;
554	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
555	}
556	}
557
558	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
559
560	/*
561	* SUB
562	*/
563
564	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
565	{
566	uint64_t uDst = *puDst;
567	uint64_t uResult = uDst - uSrc;
568	*puDst = uResult;
569	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
570	}
571
572	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
573
574	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
575	{
576	uint32_t uDst = *puDst;
577	uint32_t uResult = uDst - uSrc;
578	*puDst = uResult;
579	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
580	}
581
582
583	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
584	{
585	uint16_t uDst = *puDst;
586	uint16_t uResult = uDst - uSrc;
587	*puDst = uResult;
588	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
589	}
590
591
592	IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
593	{
594	uint8_t uDst = *puDst;
595	uint8_t uResult = uDst - uSrc;
596	*puDst = uResult;
597	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
598	}
599
600	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
601
602	/*
603	* SBB
604	*/
605
606	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
607	{
608	if (!(*pfEFlags & X86_EFL_CF))
609	iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
610	else
611	{
612	uint64_t uDst = *puDst;
613	uint64_t uResult = uDst - uSrc - 1;
614	*puDst = uResult;
615	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
616	}
617	}
618
619	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
620
621	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
622	{
623	if (!(*pfEFlags & X86_EFL_CF))
624	iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
625	else
626	{
627	uint32_t uDst = *puDst;
628	uint32_t uResult = uDst - uSrc - 1;
629	*puDst = uResult;
630	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
631	}
632	}
633
634
635	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
636	{
637	if (!(*pfEFlags & X86_EFL_CF))
638	iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
639	else
640	{
641	uint16_t uDst = *puDst;
642	uint16_t uResult = uDst - uSrc - 1;
643	*puDst = uResult;
644	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
645	}
646	}
647
648
649	IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
650	{
651	if (!(*pfEFlags & X86_EFL_CF))
652	iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
653	else
654	{
655	uint8_t uDst = *puDst;
656	uint8_t uResult = uDst - uSrc - 1;
657	*puDst = uResult;
658	IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
659	}
660	}
661
662	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
663
664
665	/*
666	* OR
667	*/
668
669	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
670	{
671	uint64_t uResult = *puDst \| uSrc;
672	*puDst = uResult;
673	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
674	}
675
676	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
677
678	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
679	{
680	uint32_t uResult = *puDst \| uSrc;
681	*puDst = uResult;
682	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
683	}
684
685
686	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
687	{
688	uint16_t uResult = *puDst \| uSrc;
689	*puDst = uResult;
690	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
691	}
692
693
694	IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
695	{
696	uint8_t uResult = *puDst \| uSrc;
697	*puDst = uResult;
698	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
699	}
700
701	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
702
703	/*
704	* XOR
705	*/
706
707	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
708	{
709	uint64_t uResult = *puDst ^ uSrc;
710	*puDst = uResult;
711	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
712	}
713
714	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
715
716	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
717	{
718	uint32_t uResult = *puDst ^ uSrc;
719	*puDst = uResult;
720	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
721	}
722
723
724	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
725	{
726	uint16_t uResult = *puDst ^ uSrc;
727	*puDst = uResult;
728	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
729	}
730
731
732	IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
733	{
734	uint8_t uResult = *puDst ^ uSrc;
735	*puDst = uResult;
736	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
737	}
738
739	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
740
741	/*
742	* AND
743	*/
744
745	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
746	{
747	uint64_t uResult = *puDst & uSrc;
748	*puDst = uResult;
749	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
750	}
751
752	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
753
754	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
755	{
756	uint32_t uResult = *puDst & uSrc;
757	*puDst = uResult;
758	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
759	}
760
761
762	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
763	{
764	uint16_t uResult = *puDst & uSrc;
765	*puDst = uResult;
766	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
767	}
768
769
770	IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
771	{
772	uint8_t uResult = *puDst & uSrc;
773	*puDst = uResult;
774	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
775	}
776
777	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
778
779	/*
780	* CMP
781	*/
782
783	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
784	{
785	uint64_t uDstTmp = *puDst;
786	iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
787	}
788
789	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
790
791	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
792	{
793	uint32_t uDstTmp = *puDst;
794	iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
795	}
796
797
798	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
799	{
800	uint16_t uDstTmp = *puDst;
801	iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
802	}
803
804
805	IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
806	{
807	uint8_t uDstTmp = *puDst;
808	iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
809	}
810
811	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
812
813	/*
814	* TEST
815	*/
816
817	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
818	{
819	uint64_t uResult = *puDst & uSrc;
820	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
821	}
822
823	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
824
825	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
826	{
827	uint32_t uResult = *puDst & uSrc;
828	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
829	}
830
831
832	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
833	{
834	uint16_t uResult = *puDst & uSrc;
835	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
836	}
837
838
839	IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t puDst, uint8_t uSrc, uint32_t pfEFlags))
840	{
841	uint8_t uResult = *puDst & uSrc;
842	IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
843	}
844
845	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
846
847
848	/*
849	* LOCK prefixed variants of the above
850	*/
851
852	/** 64-bit locked binary operand operation. */
853	# define DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
854	do { \
855	uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
856	uint ## a_cBitsWidth ## _t uTmp; \
857	uint32_t fEflTmp; \
858	do \
859	{ \
860	uTmp = uOld; \
861	fEflTmp = *pfEFlags; \
862	iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
863	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
864	*pfEFlags = fEflTmp; \
865	} while (0)
866
867
868	#define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
869	IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
870	uint ## a_cBitsWidth ## _t uSrc, \
871	uint32_t *pfEFlags)) \
872	{ \
873	DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
874	}
875
876	EMIT_LOCKED_BIN_OP(add, 64)
877	EMIT_LOCKED_BIN_OP(adc, 64)
878	EMIT_LOCKED_BIN_OP(sub, 64)
879	EMIT_LOCKED_BIN_OP(sbb, 64)
880	EMIT_LOCKED_BIN_OP(or, 64)
881	EMIT_LOCKED_BIN_OP(xor, 64)
882	EMIT_LOCKED_BIN_OP(and, 64)
883	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
884	EMIT_LOCKED_BIN_OP(add, 32)
885	EMIT_LOCKED_BIN_OP(adc, 32)
886	EMIT_LOCKED_BIN_OP(sub, 32)
887	EMIT_LOCKED_BIN_OP(sbb, 32)
888	EMIT_LOCKED_BIN_OP(or, 32)
889	EMIT_LOCKED_BIN_OP(xor, 32)
890	EMIT_LOCKED_BIN_OP(and, 32)
891
892	EMIT_LOCKED_BIN_OP(add, 16)
893	EMIT_LOCKED_BIN_OP(adc, 16)
894	EMIT_LOCKED_BIN_OP(sub, 16)
895	EMIT_LOCKED_BIN_OP(sbb, 16)
896	EMIT_LOCKED_BIN_OP(or, 16)
897	EMIT_LOCKED_BIN_OP(xor, 16)
898	EMIT_LOCKED_BIN_OP(and, 16)
899
900	EMIT_LOCKED_BIN_OP(add, 8)
901	EMIT_LOCKED_BIN_OP(adc, 8)
902	EMIT_LOCKED_BIN_OP(sub, 8)
903	EMIT_LOCKED_BIN_OP(sbb, 8)
904	EMIT_LOCKED_BIN_OP(or, 8)
905	EMIT_LOCKED_BIN_OP(xor, 8)
906	EMIT_LOCKED_BIN_OP(and, 8)
907	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
908
909
910	/*
911	* Bit operations (same signature as above).
912	*/
913
914	/*
915	* BT
916	*/
917
918	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
919	{
920	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
921	not modified by either AMD (3990x) or Intel (i9-9980HK). */
922	Assert(uSrc < 64);
923	uint64_t uDst = *puDst;
924	if (uDst & RT_BIT_64(uSrc))
925	*pfEFlags \|= X86_EFL_CF;
926	else
927	*pfEFlags &= ~X86_EFL_CF;
928	}
929
930	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
931
932	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
933	{
934	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
935	not modified by either AMD (3990x) or Intel (i9-9980HK). */
936	Assert(uSrc < 32);
937	uint32_t uDst = *puDst;
938	if (uDst & RT_BIT_32(uSrc))
939	*pfEFlags \|= X86_EFL_CF;
940	else
941	*pfEFlags &= ~X86_EFL_CF;
942	}
943
944	IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
945	{
946	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
947	not modified by either AMD (3990x) or Intel (i9-9980HK). */
948	Assert(uSrc < 16);
949	uint16_t uDst = *puDst;
950	if (uDst & RT_BIT_32(uSrc))
951	*pfEFlags \|= X86_EFL_CF;
952	else
953	*pfEFlags &= ~X86_EFL_CF;
954	}
955
956	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
957
958	/*
959	* BTC
960	*/
961
962	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
963	{
964	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
965	not modified by either AMD (3990x) or Intel (i9-9980HK). */
966	Assert(uSrc < 64);
967	uint64_t fMask = RT_BIT_64(uSrc);
968	uint64_t uDst = *puDst;
969	if (uDst & fMask)
970	{
971	uDst &= ~fMask;
972	*puDst = uDst;
973	*pfEFlags \|= X86_EFL_CF;
974	}
975	else
976	{
977	uDst \|= fMask;
978	*puDst = uDst;
979	*pfEFlags &= ~X86_EFL_CF;
980	}
981	}
982
983	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
984
985	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
986	{
987	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
988	not modified by either AMD (3990x) or Intel (i9-9980HK). */
989	Assert(uSrc < 32);
990	uint32_t fMask = RT_BIT_32(uSrc);
991	uint32_t uDst = *puDst;
992	if (uDst & fMask)
993	{
994	uDst &= ~fMask;
995	*puDst = uDst;
996	*pfEFlags \|= X86_EFL_CF;
997	}
998	else
999	{
1000	uDst \|= fMask;
1001	*puDst = uDst;
1002	*pfEFlags &= ~X86_EFL_CF;
1003	}
1004	}
1005
1006
1007	IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1008	{
1009	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
1010	not modified by either AMD (3990x) or Intel (i9-9980HK). */
1011	Assert(uSrc < 16);
1012	uint16_t fMask = RT_BIT_32(uSrc);
1013	uint16_t uDst = *puDst;
1014	if (uDst & fMask)
1015	{
1016	uDst &= ~fMask;
1017	*puDst = uDst;
1018	*pfEFlags \|= X86_EFL_CF;
1019	}
1020	else
1021	{
1022	uDst \|= fMask;
1023	*puDst = uDst;
1024	*pfEFlags &= ~X86_EFL_CF;
1025	}
1026	}
1027
1028	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1029
1030	/*
1031	* BTR
1032	*/
1033
1034	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1035	{
1036	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1037	logical operation (AND/OR/whatever). */
1038	Assert(uSrc < 64);
1039	uint64_t fMask = RT_BIT_64(uSrc);
1040	uint64_t uDst = *puDst;
1041	if (uDst & fMask)
1042	{
1043	uDst &= ~fMask;
1044	*puDst = uDst;
1045	*pfEFlags \|= X86_EFL_CF;
1046	}
1047	else
1048	*pfEFlags &= ~X86_EFL_CF;
1049	}
1050
1051	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1052
1053	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1054	{
1055	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1056	logical operation (AND/OR/whatever). */
1057	Assert(uSrc < 32);
1058	uint32_t fMask = RT_BIT_32(uSrc);
1059	uint32_t uDst = *puDst;
1060	if (uDst & fMask)
1061	{
1062	uDst &= ~fMask;
1063	*puDst = uDst;
1064	*pfEFlags \|= X86_EFL_CF;
1065	}
1066	else
1067	*pfEFlags &= ~X86_EFL_CF;
1068	}
1069
1070
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1072	{
1073	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1074	logical operation (AND/OR/whatever). */
1075	Assert(uSrc < 16);
1076	uint16_t fMask = RT_BIT_32(uSrc);
1077	uint16_t uDst = *puDst;
1078	if (uDst & fMask)
1079	{
1080	uDst &= ~fMask;
1081	*puDst = uDst;
1082	*pfEFlags \|= X86_EFL_CF;
1083	}
1084	else
1085	*pfEFlags &= ~X86_EFL_CF;
1086	}
1087
1088	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1089
1090	/*
1091	* BTS
1092	*/
1093
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1095	{
1096	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1097	logical operation (AND/OR/whatever). */
1098	Assert(uSrc < 64);
1099	uint64_t fMask = RT_BIT_64(uSrc);
1100	uint64_t uDst = *puDst;
1101	if (uDst & fMask)
1102	*pfEFlags \|= X86_EFL_CF;
1103	else
1104	{
1105	uDst \|= fMask;
1106	*puDst = uDst;
1107	*pfEFlags &= ~X86_EFL_CF;
1108	}
1109	}
1110
1111	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1112
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1114	{
1115	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1116	logical operation (AND/OR/whatever). */
1117	Assert(uSrc < 32);
1118	uint32_t fMask = RT_BIT_32(uSrc);
1119	uint32_t uDst = *puDst;
1120	if (uDst & fMask)
1121	*pfEFlags \|= X86_EFL_CF;
1122	else
1123	{
1124	uDst \|= fMask;
1125	*puDst = uDst;
1126	*pfEFlags &= ~X86_EFL_CF;
1127	}
1128	}
1129
1130
1131	IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1132	{
1133	/* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1134	logical operation (AND/OR/whatever). */
1135	Assert(uSrc < 16);
1136	uint16_t fMask = RT_BIT_32(uSrc);
1137	uint32_t uDst = *puDst;
1138	if (uDst & fMask)
1139	*pfEFlags \|= X86_EFL_CF;
1140	else
1141	{
1142	uDst \|= fMask;
1143	*puDst = uDst;
1144	*pfEFlags &= ~X86_EFL_CF;
1145	}
1146	}
1147
1148	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1149
1150
1151	EMIT_LOCKED_BIN_OP(btc, 64)
1152	EMIT_LOCKED_BIN_OP(btr, 64)
1153	EMIT_LOCKED_BIN_OP(bts, 64)
1154	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1155	EMIT_LOCKED_BIN_OP(btc, 32)
1156	EMIT_LOCKED_BIN_OP(btr, 32)
1157	EMIT_LOCKED_BIN_OP(bts, 32)
1158
1159	EMIT_LOCKED_BIN_OP(btc, 16)
1160	EMIT_LOCKED_BIN_OP(btr, 16)
1161	EMIT_LOCKED_BIN_OP(bts, 16)
1162	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1163
1164
1165	/*
1166	* BSF - first (least significant) bit set
1167	*/
1168
1169	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1170	{
1171	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1172	/* Intel & AMD differs here. This is is the AMD behaviour. */
1173	unsigned iBit = ASMBitFirstSetU64(uSrc);
1174	if (iBit)
1175	{
1176	*puDst = iBit - 1;
1177	*pfEFlags &= ~X86_EFL_ZF;
1178	}
1179	else
1180	*pfEFlags \|= X86_EFL_ZF;
1181	}
1182
1183	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1184
1185	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1186	{
1187	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1188	/* Intel & AMD differs here. This is is the AMD behaviour. */
1189	unsigned iBit = ASMBitFirstSetU32(uSrc);
1190	if (iBit)
1191	{
1192	*puDst = iBit - 1;
1193	*pfEFlags &= ~X86_EFL_ZF;
1194	}
1195	else
1196	*pfEFlags \|= X86_EFL_ZF;
1197	}
1198
1199
1200	IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1201	{
1202	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1203	/* Intel & AMD differs here. This is is the AMD behaviour. */
1204	unsigned iBit = ASMBitFirstSetU16(uSrc);
1205	if (iBit)
1206	{
1207	*puDst = iBit - 1;
1208	*pfEFlags &= ~X86_EFL_ZF;
1209	}
1210	else
1211	*pfEFlags \|= X86_EFL_ZF;
1212	}
1213
1214	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1215
1216	/*
1217	* BSR - last (most significant) bit set
1218	*/
1219
1220	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1221	{
1222	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1223	/* Intel & AMD differs here. This is is the AMD behaviour. */
1224	unsigned iBit = ASMBitLastSetU64(uSrc);
1225	if (uSrc)
1226	{
1227	*puDst = iBit - 1;
1228	*pfEFlags &= ~X86_EFL_ZF;
1229	}
1230	else
1231	*pfEFlags \|= X86_EFL_ZF;
1232	}
1233
1234	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1235
1236	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1237	{
1238	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1239	/* Intel & AMD differs here. This is is the AMD behaviour. */
1240	unsigned iBit = ASMBitLastSetU32(uSrc);
1241	if (uSrc)
1242	{
1243	*puDst = iBit - 1;
1244	*pfEFlags &= ~X86_EFL_ZF;
1245	}
1246	else
1247	*pfEFlags \|= X86_EFL_ZF;
1248	}
1249
1250
1251	IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1252	{
1253	/* Note! "undefined" flags: OF, SF, AF, PF, CF. */
1254	/* Intel & AMD differs here. This is is the AMD behaviour. */
1255	unsigned iBit = ASMBitLastSetU16(uSrc);
1256	if (uSrc)
1257	{
1258	*puDst = iBit - 1;
1259	*pfEFlags &= ~X86_EFL_ZF;
1260	}
1261	else
1262	*pfEFlags \|= X86_EFL_ZF;
1263	}
1264
1265	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1266
1267
1268	/*
1269	* XCHG
1270	*/
1271
1272	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t puMem, uint64_t puReg))
1273	{
1274	#if ARCH_BITS >= 64
1275	puReg = ASMAtomicXchgU64(puMem, puReg);
1276	#else
1277	uint64_t uOldMem = *puMem;
1278	while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
1279	ASMNopPause();
1280	*puReg = uOldMem;
1281	#endif
1282	}
1283
1284	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1285
1286	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t puMem, uint32_t puReg))
1287	{
1288	puReg = ASMAtomicXchgU32(puMem, puReg);
1289	}
1290
1291
1292	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t puMem, uint16_t puReg))
1293	{
1294	puReg = ASMAtomicXchgU16(puMem, puReg);
1295	}
1296
1297
1298	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked,(uint8_t puMem, uint8_t puReg))
1299	{
1300	puReg = ASMAtomicXchgU8(puMem, puReg);
1301	}
1302
1303	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1304
1305
1306	/* Unlocked variants for fDisregardLock mode: */
1307
1308	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t puMem, uint64_t puReg))
1309	{
1310	uint64_t const uOld = *puMem;
1311	puMem = puReg;
1312	*puReg = uOld;
1313	}
1314
1315	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1316
1317	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t puMem, uint32_t puReg))
1318	{
1319	uint32_t const uOld = *puMem;
1320	puMem = puReg;
1321	*puReg = uOld;
1322	}
1323
1324
1325	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t puMem, uint16_t puReg))
1326	{
1327	uint16_t const uOld = *puMem;
1328	puMem = puReg;
1329	*puReg = uOld;
1330	}
1331
1332
1333	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked,(uint8_t puMem, uint8_t puReg))
1334	{
1335	uint8_t const uOld = *puMem;
1336	puMem = puReg;
1337	*puReg = uOld;
1338	}
1339
1340	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1341
1342
1343	/*
1344	* XADD and LOCK XADD.
1345	*/
1346	#define EMIT_XADD(a_cBitsWidth, a_Type) \
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth,(a_Type puDst, a_Type puReg, uint32_t *pfEFlags)) \
1348	{ \
1349	a_Type uDst = *puDst; \
1350	a_Type uResult = uDst; \
1351	iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, pfEFlags); \
1352	*puDst = uResult; \
1353	*puReg = uDst; \
1354	} \
1355	\
1356	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth ## _locked,(a_Type puDst, a_Type puReg, uint32_t *pfEFlags)) \
1357	{ \
1358	a_Type uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
1359	a_Type uResult; \
1360	uint32_t fEflTmp; \
1361	do \
1362	{ \
1363	uResult = uOld; \
1364	fEflTmp = *pfEFlags; \
1365	iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, &fEflTmp); \
1366	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uResult, uOld, &uOld)); \
1367	*puReg = uOld; \
1368	*pfEFlags = fEflTmp; \
1369	}
1370	EMIT_XADD(64, uint64_t)
1371	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1372	EMIT_XADD(32, uint32_t)
1373	EMIT_XADD(16, uint16_t)
1374	EMIT_XADD(8, uint8_t)
1375	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1376
1377	#endif
1378
1379	/*
1380	* CMPXCHG, CMPXCHG8B, CMPXCHG16B
1381	*
1382	* Note! We don't have non-locking/atomic cmpxchg primitives, so all cmpxchg
1383	* instructions are emulated as locked.
1384	*/
1385	#if defined(IEM_WITHOUT_ASSEMBLY)
1386
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1388	{
1389	uint8_t uOld = *puAl;
1390	if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
1391	Assert(*puAl == uOld);
1392	iemAImpl_cmp_u8(&uOld, *puAl, pEFlags);
1393	}
1394
1395
1396	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1397	{
1398	uint16_t uOld = *puAx;
1399	if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
1400	Assert(*puAx == uOld);
1401	iemAImpl_cmp_u16(&uOld, *puAx, pEFlags);
1402	}
1403
1404
1405	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1406	{
1407	uint32_t uOld = *puEax;
1408	if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
1409	Assert(*puEax == uOld);
1410	iemAImpl_cmp_u32(&uOld, *puEax, pEFlags);
1411	}
1412
1413
1414	# if ARCH_BITS == 32
1415	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags))
1416	# else
1417	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1418	# endif
1419	{
1420	# if ARCH_BITS == 32
1421	uint64_t const uSrcReg = *puSrcReg;
1422	# endif
1423	uint64_t uOld = *puRax;
1424	if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
1425	Assert(*puRax == uOld);
1426	iemAImpl_cmp_u64(&uOld, *puRax, pEFlags);
1427	}
1428
1429
1430	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1431	uint32_t *pEFlags))
1432	{
1433	uint64_t const uNew = pu64EbxEcx->u;
1434	uint64_t const uOld = pu64EaxEdx->u;
1435	if (ASMAtomicCmpXchgExU64(pu64Dst, uNew, uOld, &pu64EaxEdx->u))
1436	{
1437	Assert(pu64EaxEdx->u == uOld);
1438	*pEFlags \|= X86_EFL_ZF;
1439	}
1440	else
1441	*pEFlags &= ~X86_EFL_ZF;
1442	}
1443
1444
1445	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_ARM64)
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1447	uint32_t *pEFlags))
1448	{
1449	# ifdef VBOX_STRICT
1450	RTUINT128U const uOld = *pu128RaxRdx;
1451	# endif
1452	# if defined(RT_ARCH_AMD64)
1453	if (ASMAtomicCmpXchgU128v2(&pu128Dst->u, pu128RbxRcx->s.Hi, pu128RbxRcx->s.Lo, pu128RaxRdx->s.Hi, pu128RaxRdx->s.Lo,
1454	&pu128RaxRdx->u))
1455	# else
1456	if (ASMAtomicCmpXchgU128(&pu128Dst->u, pu128RbxRcx->u, pu128RaxRdx->u, &pu128RaxRdx->u))
1457	# endif
1458	{
1459	Assert(pu128RaxRdx->s.Lo == uOld.s.Lo && pu128RaxRdx->s.Hi == uOld.s.Hi);
1460	*pEFlags \|= X86_EFL_ZF;
1461	}
1462	else
1463	*pEFlags &= ~X86_EFL_ZF;
1464	}
1465	# endif
1466
1467	#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1468
1469	# if !defined(RT_ARCH_ARM64) /** @todo may need this for unaligned accesses... */
1470	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1471	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
1472	{
1473	RTUINT128U u128Tmp = *pu128Dst;
1474	if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
1475	&& u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
1476	{
1477	pu128Dst = pu128RbxRcx;
1478	*pEFlags \|= X86_EFL_ZF;
1479	}
1480	else
1481	{
1482	*pu128RaxRdx = u128Tmp;
1483	*pEFlags &= ~X86_EFL_ZF;
1484	}
1485	}
1486	#endif /* !RT_ARCH_ARM64 */
1487
1488	#if defined(IEM_WITHOUT_ASSEMBLY)
1489
1490	/* Unlocked versions mapped to the locked ones: */
1491
1492	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1493	{
1494	iemAImpl_cmpxchg_u8_locked(pu8Dst, puAl, uSrcReg, pEFlags);
1495	}
1496
1497
1498	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1499	{
1500	iemAImpl_cmpxchg_u16_locked(pu16Dst, puAx, uSrcReg, pEFlags);
1501	}
1502
1503
1504	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1505	{
1506	iemAImpl_cmpxchg_u32_locked(pu32Dst, puEax, uSrcReg, pEFlags);
1507	}
1508
1509
1510	# if ARCH_BITS == 32
1511	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags))
1512	{
1513	iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, puSrcReg, pEFlags);
1514	}
1515	# else
1516	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1517	{
1518	iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, uSrcReg, pEFlags);
1519	}
1520	# endif
1521
1522
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx, uint32_t pEFlags))
1524	{
1525	iemAImpl_cmpxchg8b_locked(pu64Dst, pu64EaxEdx, pu64EbxEcx, pEFlags);
1526	}
1527
1528
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1530	uint32_t *pEFlags))
1531	{
1532	iemAImpl_cmpxchg16b_locked(pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
1533	}
1534
1535	#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1536
1537	#if !defined(RT_ARCH_AMD64) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1538
1539	/*
1540	* MUL, IMUL, DIV and IDIV helpers.
1541	*
1542	* - The U64 versions must use 128-bit intermediates, so we need to abstract the
1543	* division step so we can select between using C operators and
1544	* RTUInt128DivRem/RTUInt128MulU64ByU64.
1545	*
1546	* - The U8 versions work returns output in AL + AH instead of xDX + xAX, with the
1547	* IDIV/DIV taking all the input in AX too. This means we have to abstract some
1548	* input loads and the result storing.
1549	*/
1550
1551	DECLINLINE(void) RTUInt128DivRemByU64(PRTUINT128U pQuotient, PRTUINT128U pRemainder, PCRTUINT128U pDividend, uint64_t u64Divisor)
1552	{
1553	# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1554	pQuotient->s.Lo = 0;
1555	pQuotient->s.Hi = 0;
1556	# endif
1557	RTUINT128U Divisor;
1558	Divisor.s.Lo = u64Divisor;
1559	Divisor.s.Hi = 0;
1560	RTUInt128DivRem(pQuotient, pRemainder, pDividend, &Divisor);
1561	}
1562
1563	# define DIV_LOAD(a_Dividend) \
1564	a_Dividend.s.Lo = puA, a_Dividend.s.Hi = puD
1565	# define DIV_LOAD_U8(a_Dividend) \
1566	a_Dividend.u = *puAX
1567
1568	# define DIV_STORE(a_Quotient, a_uReminder) puA = (a_Quotient), puD = (a_uReminder)
1569	# define DIV_STORE_U8(a_Quotient, a_uReminder) *puAX = (uint8_t)(a_Quotient) \| ((uint16_t)(a_uReminder) << 8)
1570
1571	# define MUL_LOAD_F1() *puA
1572	# define MUL_LOAD_F1_U8() ((uint8_t)*puAX)
1573
1574	# define MUL_STORE(a_Result) puA = (a_Result).s.Lo, puD = (a_Result).s.Hi
1575	# define MUL_STORE_U8(a_Result) *puAX = a_Result.u
1576
1577	# define MULDIV_NEG(a_Value, a_cBitsWidth2x) \
1578	(a_Value).u = UINT ## a_cBitsWidth2x ## _C(0) - (a_Value).u
1579	# define MULDIV_NEG_U128(a_Value, a_cBitsWidth2x) \
1580	RTUInt128AssignNeg(&(a_Value))
1581
1582	# define MULDIV_MUL(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1583	(a_Result).u = (uint ## a_cBitsWidth2x ## _t)(a_Factor1) * (a_Factor2)
1584	# define MULDIV_MUL_U128(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1585	RTUInt128MulU64ByU64(&(a_Result), a_Factor1, a_Factor2);
1586
1587	# define MULDIV_MODDIV(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1588	a_Quotient.u = (a_Dividend).u / (a_uDivisor), \
1589	a_Remainder.u = (a_Dividend).u % (a_uDivisor)
1590	# define MULDIV_MODDIV_U128(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1591	RTUInt128DivRemByU64(&a_Quotient, &a_Remainder, &a_Dividend, a_uDivisor)
1592
1593
1594	/*
1595	* MUL
1596	*/
1597	# define EMIT_MUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnMul) \
1598	IEM_DECL_IMPL_DEF(int, iemAImpl_mul_u ## a_cBitsWidth, a_Args) \
1599	{ \
1600	RTUINT ## a_cBitsWidth2x ## U Result; \
1601	a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
1602	a_fnStore(Result); \
1603	\
1604	/* MUL EFLAGS according to Skylake (similar to IMUL). */ \
1605	uint32_t fEfl = *pfEFlags & ~(X86_EFL_SF \| X86_EFL_CF \| X86_EFL_OF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_PF); \
1606	if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1607	fEfl \|= X86_EFL_SF; \
1608	fEfl \|= g_afParity[Result.s.Lo & 0xff]; /* (Skylake behaviour) */ \
1609	if (Result.s.Hi != 0) \
1610	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1611	*pfEFlags = fEfl; \
1612	return 0; \
1613	}
1614	EMIT_MUL(64, 128, (uint64_t puA, uint64_t puD, uint64_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL_U128)
1615	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1616	EMIT_MUL(32, 64, (uint32_t puA, uint32_t puD, uint32_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1617	EMIT_MUL(16, 32, (uint16_t puA, uint16_t puD, uint16_t uFactor, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1618	EMIT_MUL(8, 16, (uint16_t puAX, uint8_t uFactor, uint32_t pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_MUL)
1619	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1620
1621
1622	/*
1623	* IMUL
1624	*/
1625	# define EMIT_IMUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul) \
1626	IEM_DECL_IMPL_DEF(int, iemAImpl_imul_u ## a_cBitsWidth,a_Args) \
1627	{ \
1628	RTUINT ## a_cBitsWidth2x ## U Result; \
1629	/* The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these \
1630	flags as is - at least for the two op version. Whereas Intel skylake \
1631	always clear AF and ZF and calculates SF and PF as per the lower half \
1632	of the result. */ \
1633	uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF \| X86_EFL_OF); \
1634	\
1635	uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
1636	if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
1637	{ \
1638	if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1639	{ \
1640	a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1641	if (Result.s.Hi != 0 \|\| Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1642	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1643	} \
1644	else \
1645	{ \
1646	uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
1647	a_fnMul(Result, uFactor1, uPositiveFactor2, a_cBitsWidth2x); \
1648	if (Result.s.Hi != 0 \|\| Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1649	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1650	a_fnNeg(Result, a_cBitsWidth2x); \
1651	} \
1652	} \
1653	else \
1654	{ \
1655	if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1656	{ \
1657	uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
1658	a_fnMul(Result, uPositiveFactor1, uFactor2, a_cBitsWidth2x); \
1659	if (Result.s.Hi != 0 \|\| Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1660	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1661	a_fnNeg(Result, a_cBitsWidth2x); \
1662	} \
1663	else \
1664	{ \
1665	uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
1666	uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
1667	a_fnMul(Result, uPositiveFactor1, uPositiveFactor2, a_cBitsWidth2x); \
1668	if (Result.s.Hi != 0 \|\| Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1669	fEfl \|= X86_EFL_CF \| X86_EFL_OF; \
1670	} \
1671	} \
1672	a_fnStore(Result); \
1673	if (false) \
1674	{ /* Intel (skylake) flags "undefined" behaviour: */ \
1675	fEfl &= ~(X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_PF); \
1676	if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1677	fEfl \|= X86_EFL_SF; \
1678	fEfl \|= g_afParity[Result.s.Lo & 0xff]; \
1679	} \
1680	*pfEFlags = fEfl; \
1681	return 0; \
1682	}
1683	/** @todo Testcase: IMUL 2 and 3 operands. */
1684	EMIT_IMUL(64, 128, (uint64_t puA, uint64_t puD, uint64_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG_U128, MULDIV_MUL_U128)
1685	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1686	EMIT_IMUL(32, 64, (uint32_t puA, uint32_t puD, uint32_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1687	EMIT_IMUL(16, 32, (uint16_t puA, uint16_t puD, uint16_t uFactor2, uint32_t *pfEFlags), MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1688	EMIT_IMUL(8, 16, (uint16_t puAX, uint8_t uFactor2, uint32_t pfEFlags), MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_NEG, MULDIV_MUL)
1689	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1690
1691
1692	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u64,(uint64_t puDst, uint64_t uSrc, uint32_t pfEFlags))
1693	{
1694	uint64_t uIgn;
1695	iemAImpl_imul_u64(puDst, &uIgn, uSrc, pfEFlags);
1696	}
1697
1698	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1699
1700	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u32,(uint32_t puDst, uint32_t uSrc, uint32_t pfEFlags))
1701	{
1702	uint32_t uIgn;
1703	iemAImpl_imul_u32(puDst, &uIgn, uSrc, pfEFlags);
1704	}
1705
1706
1707	IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u16,(uint16_t puDst, uint16_t uSrc, uint32_t pfEFlags))
1708	{
1709	uint16_t uIgn;
1710	iemAImpl_imul_u16(puDst, &uIgn, uSrc, pfEFlags);
1711	}
1712
1713	#endif
1714
1715	/*
1716	* DIV
1717	*/
1718	# define EMIT_DIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnDivRem) \
1719	IEM_DECL_IMPL_DEF(int, iemAImpl_div_u ## a_cBitsWidth,a_Args) \
1720	{ \
1721	/* Note! Skylake leaves all flags alone. */ \
1722	RT_NOREF_PV(pfEFlags); \
1723	\
1724	RTUINT ## a_cBitsWidth2x ## U Dividend; \
1725	a_fnLoad(Dividend); \
1726	if ( uDivisor != 0 \
1727	&& Dividend.s.Hi < uDivisor) \
1728	{ \
1729	RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1730	a_fnDivRem(Quotient, Remainder, Dividend, uDivisor); \
1731	a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1732	/** @todo research the undefined DIV flags. */ \
1733	return 0; \
1734	} \
1735	/* #DE */ \
1736	return -1; \
1737	}
1738	EMIT_DIV(64,128,(uint64_t puA, uint64_t puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV_U128)
1739	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1740	EMIT_DIV(32,64, (uint32_t puA, uint32_t puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1741	EMIT_DIV(16,32, (uint16_t puA, uint16_t puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1742	EMIT_DIV(8,16, (uint16_t puAX, uint8_t uDivisor, uint32_t pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_MODDIV)
1743	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1744
1745
1746	/*
1747	* IDIV
1748	*/
1749	# define EMIT_IDIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem) \
1750	IEM_DECL_IMPL_DEF(int, iemAImpl_idiv_u ## a_cBitsWidth,a_Args) \
1751	{ \
1752	/* Note! Skylake leaves all flags alone. */ \
1753	RT_NOREF_PV(pfEFlags); \
1754	\
1755	/** @todo overflow checks */ \
1756	if (uDivisor != 0) \
1757	{ \
1758	/* \
1759	* Convert to unsigned division. \
1760	*/ \
1761	RTUINT ## a_cBitsWidth2x ## U Dividend; \
1762	a_fnLoad(Dividend); \
1763	bool const fSignedDividend = RT_BOOL(Dividend.s.Hi & RT_BIT_64(a_cBitsWidth - 1)); \
1764	if (fSignedDividend) \
1765	a_fnNeg(Dividend, a_cBitsWidth2x); \
1766	\
1767	uint ## a_cBitsWidth ## _t uDivisorPositive; \
1768	if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
1769	uDivisorPositive = uDivisor; \
1770	else \
1771	uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
1772	\
1773	RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1774	a_fnDivRem(Quotient, Remainder, Dividend, uDivisorPositive); \
1775	\
1776	/* \
1777	* Setup the result, checking for overflows. \
1778	*/ \
1779	if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
1780	{ \
1781	if (!fSignedDividend) \
1782	{ \
1783	/* Positive divisor, positive dividend => result positive. */ \
1784	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1785	{ \
1786	a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1787	return 0; \
1788	} \
1789	} \
1790	else \
1791	{ \
1792	/* Positive divisor, negative dividend => result negative. */ \
1793	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1794	{ \
1795	a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1796	return 0; \
1797	} \
1798	} \
1799	} \
1800	else \
1801	{ \
1802	if (!fSignedDividend) \
1803	{ \
1804	/* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
1805	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1806	{ \
1807	a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
1808	return 0; \
1809	} \
1810	} \
1811	else \
1812	{ \
1813	/* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
1814	if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1815	{ \
1816	a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1817	return 0; \
1818	} \
1819	} \
1820	} \
1821	} \
1822	/* #DE */ \
1823	return -1; \
1824	}
1825	EMIT_IDIV(64,128,(uint64_t puA, uint64_t puD, uint64_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG_U128, MULDIV_MODDIV_U128)
1826	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1827	EMIT_IDIV(32,64,(uint32_t puA, uint32_t puD, uint32_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1828	EMIT_IDIV(16,32,(uint16_t puA, uint16_t puD, uint16_t uDivisor, uint32_t *pfEFlags), DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1829	EMIT_IDIV(8,16,(uint16_t puAX, uint8_t uDivisor, uint32_t pfEFlags), DIV_LOAD_U8, DIV_STORE_U8, MULDIV_NEG, MULDIV_MODDIV)
1830	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1831
1832
1833	/*********************************************************************************************************************************
1834	* Unary operations. *
1835	*********************************************************************************************************************************/
1836
1837	/**
1838	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an INC or DEC instruction.
1839	*
1840	* CF is NOT modified for hysterical raisins (allegedly for carrying and
1841	* borrowing in arithmetic loops on intel 8008).
1842	*
1843	* @returns Status bits.
1844	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
1845	* @param a_uResult Unsigned result value.
1846	* @param a_uDst The original destination value (for AF calc).
1847	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
1848	* @param a_OfMethod 0 for INC-style, 1 for DEC-style.
1849	*/
1850	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth, a_OfMethod) \
1851	do { \
1852	uint32_t fEflTmp = *(a_pfEFlags); \
1853	fEflTmp &= ~X86_EFL_STATUS_BITS \| X86_EFL_CF; \
1854	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
1855	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
1856	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
1857	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
1858	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth(a_OfMethod == 0 ? (((a_uDst) ^ RT_BIT_64(a_cBitsWidth - 1)) & (a_uResult)) \
1859	: ((a_uDst) & ((a_uResult) ^ RT_BIT_64(a_cBitsWidth - 1))) ); \
1860	*(a_pfEFlags) = fEflTmp; \
1861	} while (0)
1862
1863	/*
1864	* INC
1865	*/
1866
1867	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t puDst, uint32_t pfEFlags))
1868	{
1869	uint64_t uDst = *puDst;
1870	uint64_t uResult = uDst + 1;
1871	*puDst = uResult;
1872	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 0 /INC/);
1873	}
1874
1875	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1876
1877	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u32,(uint32_t puDst, uint32_t pfEFlags))
1878	{
1879	uint32_t uDst = *puDst;
1880	uint32_t uResult = uDst + 1;
1881	*puDst = uResult;
1882	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 0 /INC/);
1883	}
1884
1885
1886	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u16,(uint16_t puDst, uint32_t pfEFlags))
1887	{
1888	uint16_t uDst = *puDst;
1889	uint16_t uResult = uDst + 1;
1890	*puDst = uResult;
1891	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 0 /INC/);
1892	}
1893
1894	IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u8,(uint8_t puDst, uint32_t pfEFlags))
1895	{
1896	uint8_t uDst = *puDst;
1897	uint8_t uResult = uDst + 1;
1898	*puDst = uResult;
1899	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 0 /INC/);
1900	}
1901
1902	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1903
1904
1905	/*
1906	* DEC
1907	*/
1908
1909	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t puDst, uint32_t pfEFlags))
1910	{
1911	uint64_t uDst = *puDst;
1912	uint64_t uResult = uDst - 1;
1913	*puDst = uResult;
1914	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 1 /INC/);
1915	}
1916
1917	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1918
1919	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u32,(uint32_t puDst, uint32_t pfEFlags))
1920	{
1921	uint32_t uDst = *puDst;
1922	uint32_t uResult = uDst - 1;
1923	*puDst = uResult;
1924	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 1 /INC/);
1925	}
1926
1927
1928	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u16,(uint16_t puDst, uint32_t pfEFlags))
1929	{
1930	uint16_t uDst = *puDst;
1931	uint16_t uResult = uDst - 1;
1932	*puDst = uResult;
1933	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 1 /INC/);
1934	}
1935
1936
1937	IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u8,(uint8_t puDst, uint32_t pfEFlags))
1938	{
1939	uint8_t uDst = *puDst;
1940	uint8_t uResult = uDst - 1;
1941	*puDst = uResult;
1942	IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 1 /INC/);
1943	}
1944
1945	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1946
1947
1948	/*
1949	* NOT
1950	*/
1951
1952	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t puDst, uint32_t pfEFlags))
1953	{
1954	uint64_t uDst = *puDst;
1955	uint64_t uResult = ~uDst;
1956	*puDst = uResult;
1957	/* EFLAGS are not modified. */
1958	RT_NOREF_PV(pfEFlags);
1959	}
1960
1961	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
1962
1963	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u32,(uint32_t puDst, uint32_t pfEFlags))
1964	{
1965	uint32_t uDst = *puDst;
1966	uint32_t uResult = ~uDst;
1967	*puDst = uResult;
1968	/* EFLAGS are not modified. */
1969	RT_NOREF_PV(pfEFlags);
1970	}
1971
1972	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u16,(uint16_t puDst, uint32_t pfEFlags))
1973	{
1974	uint16_t uDst = *puDst;
1975	uint16_t uResult = ~uDst;
1976	*puDst = uResult;
1977	/* EFLAGS are not modified. */
1978	RT_NOREF_PV(pfEFlags);
1979	}
1980
1981	IEM_DECL_IMPL_DEF(void, iemAImpl_not_u8,(uint8_t puDst, uint32_t pfEFlags))
1982	{
1983	uint8_t uDst = *puDst;
1984	uint8_t uResult = ~uDst;
1985	*puDst = uResult;
1986	/* EFLAGS are not modified. */
1987	RT_NOREF_PV(pfEFlags);
1988	}
1989
1990	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
1991
1992
1993	/*
1994	* NEG
1995	*/
1996
1997	/**
1998	* Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an NEG instruction.
1999	*
2000	* @returns Status bits.
2001	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2002	* @param a_uResult Unsigned result value.
2003	* @param a_uDst The original destination value (for AF calc).
2004	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2005	*/
2006	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth) \
2007	do { \
2008	uint32_t fEflTmp = *(a_pfEFlags); \
2009	fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
2010	fEflTmp \|= ((a_uDst) != 0) << X86_EFL_CF_BIT; \
2011	fEflTmp \|= g_afParity[(a_uResult) & 0xff]; \
2012	fEflTmp \|= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
2013	fEflTmp \|= X86_EFL_CALC_ZF(a_uResult); \
2014	fEflTmp \|= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
2015	fEflTmp \|= X86_EFL_GET_OF_ ## a_cBitsWidth((a_uDst) & (a_uResult)); \
2016	*(a_pfEFlags) = fEflTmp; \
2017	} while (0)
2018
2019	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t puDst, uint32_t pfEFlags))
2020	{
2021	uint64_t uDst = *puDst;
2022	uint64_t uResult = (uint64_t)0 - uDst;
2023	*puDst = uResult;
2024	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 64);
2025	}
2026
2027	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2028
2029	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u32,(uint32_t puDst, uint32_t pfEFlags))
2030	{
2031	uint32_t uDst = *puDst;
2032	uint32_t uResult = (uint32_t)0 - uDst;
2033	*puDst = uResult;
2034	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 32);
2035	}
2036
2037
2038	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u16,(uint16_t puDst, uint32_t pfEFlags))
2039	{
2040	uint16_t uDst = *puDst;
2041	uint16_t uResult = (uint16_t)0 - uDst;
2042	*puDst = uResult;
2043	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 16);
2044	}
2045
2046
2047	IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u8,(uint8_t puDst, uint32_t pfEFlags))
2048	{
2049	uint8_t uDst = *puDst;
2050	uint8_t uResult = (uint8_t)0 - uDst;
2051	*puDst = uResult;
2052	IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 8);
2053	}
2054
2055	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2056
2057	/*
2058	* Locked variants.
2059	*/
2060
2061	/** Emit a function for doing a locked unary operand operation. */
2062	# define EMIT_LOCKED_UNARY_OP(a_Mnemonic, a_cBitsWidth) \
2063	IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
2064	uint32_t *pfEFlags)) \
2065	{ \
2066	uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
2067	uint ## a_cBitsWidth ## _t uTmp; \
2068	uint32_t fEflTmp; \
2069	do \
2070	{ \
2071	uTmp = uOld; \
2072	fEflTmp = *pfEFlags; \
2073	iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, &fEflTmp); \
2074	} while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
2075	*pfEFlags = fEflTmp; \
2076	}
2077
2078	EMIT_LOCKED_UNARY_OP(inc, 64)
2079	EMIT_LOCKED_UNARY_OP(dec, 64)
2080	EMIT_LOCKED_UNARY_OP(not, 64)
2081	EMIT_LOCKED_UNARY_OP(neg, 64)
2082	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2083	EMIT_LOCKED_UNARY_OP(inc, 32)
2084	EMIT_LOCKED_UNARY_OP(dec, 32)
2085	EMIT_LOCKED_UNARY_OP(not, 32)
2086	EMIT_LOCKED_UNARY_OP(neg, 32)
2087
2088	EMIT_LOCKED_UNARY_OP(inc, 16)
2089	EMIT_LOCKED_UNARY_OP(dec, 16)
2090	EMIT_LOCKED_UNARY_OP(not, 16)
2091	EMIT_LOCKED_UNARY_OP(neg, 16)
2092
2093	EMIT_LOCKED_UNARY_OP(inc, 8)
2094	EMIT_LOCKED_UNARY_OP(dec, 8)
2095	EMIT_LOCKED_UNARY_OP(not, 8)
2096	EMIT_LOCKED_UNARY_OP(neg, 8)
2097	# endif
2098
2099
2100	/*********************************************************************************************************************************
2101	* Shifting and Rotating *
2102	*********************************************************************************************************************************/
2103
2104	/*
2105	* ROL
2106	*/
2107
2108	/**
2109	* Updates the status bits (OF and CF) for an ROL instruction.
2110	*
2111	* @returns Status bits.
2112	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2113	* @param a_uResult Unsigned result value.
2114	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2115	*/
2116	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2117	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2118	it the same way as for 1 bit shifts. */ \
2119	AssertCompile(X86_EFL_CF_BIT == 0); \
2120	uint32_t fEflTmp = *(a_pfEFlags); \
2121	fEflTmp &= ~(X86_EFL_CF \| X86_EFL_OF); \
2122	uint32_t const fCarry = ((a_uResult) & X86_EFL_CF); \
2123	fEflTmp \|= fCarry; \
2124	fEflTmp \|= (((a_uResult) >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2125	*(a_pfEFlags) = fEflTmp; \
2126	} while (0)
2127
2128	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u64,(uint64_t puDst, uint8_t cShift, uint32_t pfEFlags))
2129	{
2130	cShift &= 63;
2131	if (cShift)
2132	{
2133	uint64_t uResult = ASMRotateLeftU64(*puDst, cShift);
2134	*puDst = uResult;
2135	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 64);
2136	}
2137	}
2138
2139	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2140
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u32,(uint32_t puDst, uint8_t cShift, uint32_t pfEFlags))
2142	{
2143	cShift &= 31;
2144	if (cShift)
2145	{
2146	uint32_t uResult = ASMRotateLeftU32(*puDst, cShift);
2147	*puDst = uResult;
2148	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 32);
2149	}
2150	}
2151
2152
2153	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u16,(uint16_t puDst, uint8_t cShift, uint32_t pfEFlags))
2154	{
2155	cShift &= 15;
2156	if (cShift)
2157	{
2158	uint16_t uDst = *puDst;
2159	uint16_t uResult = (uDst << cShift) \| (uDst >> (16 - cShift));
2160	*puDst = uResult;
2161	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 16);
2162	}
2163	}
2164
2165
2166	IEM_DECL_IMPL_DEF(void, iemAImpl_rol_u8,(uint8_t puDst, uint8_t cShift, uint32_t pfEFlags))
2167	{
2168	cShift &= 7;
2169	if (cShift)
2170	{
2171	uint8_t uDst = *puDst;
2172	uint8_t uResult = (uDst << cShift) \| (uDst >> (8 - cShift));
2173	*puDst = uResult;
2174	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROL(pfEFlags, uResult, 8);
2175	}
2176	}
2177
2178	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2179
2180
2181	/*
2182	* ROR
2183	*/
2184
2185	/**
2186	* Updates the status bits (OF and CF) for an ROL instruction.
2187	*
2188	* @returns Status bits.
2189	* @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2190	* @param a_uResult Unsigned result value.
2191	* @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2192	*/
2193	#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(a_pfEFlags, a_uResult, a_cBitsWidth) do { \
2194	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2195	it the same way as for 1 bit shifts. */ \
2196	AssertCompile(X86_EFL_CF_BIT == 0); \
2197	uint32_t fEflTmp = *(a_pfEFlags); \
2198	fEflTmp &= ~(X86_EFL_CF \| X86_EFL_OF); \
2199	uint32_t const fCarry = ((a_uResult) >> ((a_cBitsWidth) - 1)) & X86_EFL_CF; \
2200	fEflTmp \|= fCarry; \
2201	fEflTmp \|= ((((a_uResult) >> ((a_cBitsWidth) - 2)) ^ fCarry) & 1) << X86_EFL_OF_BIT; \
2202	*(a_pfEFlags) = fEflTmp; \
2203	} while (0)
2204
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u64,(uint64_t puDst, uint8_t cShift, uint32_t pfEFlags))
2206	{
2207	cShift &= 63;
2208	if (cShift)
2209	{
2210	uint64_t const uResult = ASMRotateRightU64(*puDst, cShift);
2211	*puDst = uResult;
2212	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 64);
2213	}
2214	}
2215
2216	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2217
2218	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u32,(uint32_t puDst, uint8_t cShift, uint32_t pfEFlags))
2219	{
2220	cShift &= 31;
2221	if (cShift)
2222	{
2223	uint64_t const uResult = ASMRotateRightU32(*puDst, cShift);
2224	*puDst = uResult;
2225	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 32);
2226	}
2227	}
2228
2229
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u16,(uint16_t puDst, uint8_t cShift, uint32_t pfEFlags))
2231	{
2232	cShift &= 15;
2233	if (cShift)
2234	{
2235	uint16_t uDst = *puDst;
2236	uint16_t uResult;
2237	uResult = uDst >> cShift;
2238	uResult \|= uDst << (16 - cShift);
2239	*puDst = uResult;
2240	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 16);
2241	}
2242	}
2243
2244
2245	IEM_DECL_IMPL_DEF(void, iemAImpl_ror_u8,(uint8_t puDst, uint8_t cShift, uint32_t pfEFlags))
2246	{
2247	cShift &= 7;
2248	if (cShift)
2249	{
2250	uint8_t uDst = *puDst;
2251	uint8_t uResult;
2252	uResult = uDst >> cShift;
2253	uResult \|= uDst << (8 - cShift);
2254	*puDst = uResult;
2255	IEM_EFL_UPDATE_STATUS_BITS_FOR_ROR(pfEFlags, uResult, 8);
2256	}
2257	}
2258
2259	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2260
2261
2262	/*
2263	* RCL
2264	*/
2265	#define EMIT_RCL(a_cBitsWidth) \
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_rcl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2267	{ \
2268	cShift &= a_cBitsWidth - 1; \
2269	if (cShift) \
2270	{ \
2271	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2272	uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2273	if (cShift > 1) \
2274	uResult \|= uDst >> (a_cBitsWidth + 1 - cShift); \
2275	\
2276	uint32_t fEfl = *pfEFlags; \
2277	AssertCompile(X86_EFL_CF_BIT == 0); \
2278	uResult \|= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (cShift - 1); \
2279	\
2280	*puDst = uResult; \
2281	\
2282	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2283	it the same way as for 1 bit shifts. */ \
2284	fEfl &= ~(X86_EFL_CF \| X86_EFL_OF); \
2285	uint32_t const fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2286	fEfl \|= fCarry; \
2287	fEfl \|= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2288	*pfEFlags = fEfl; \
2289	} \
2290	}
2291	EMIT_RCL(64)
2292	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2293	EMIT_RCL(32)
2294	EMIT_RCL(16)
2295	EMIT_RCL(8)
2296	# endif
2297
2298
2299	/*
2300	* RCR
2301	*/
2302	#define EMIT_RCR(a_cBitsWidth) \
2303	IEM_DECL_IMPL_DEF(void, iemAImpl_rcr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ##_t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2304	{ \
2305	cShift &= a_cBitsWidth - 1; \
2306	if (cShift) \
2307	{ \
2308	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2309	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2310	if (cShift > 1) \
2311	uResult \|= uDst << (a_cBitsWidth + 1 - cShift); \
2312	\
2313	AssertCompile(X86_EFL_CF_BIT == 0); \
2314	uint32_t fEfl = *pfEFlags; \
2315	uResult \|= (uint ## a_cBitsWidth ## _t)(fEfl & X86_EFL_CF) << (a_cBitsWidth - cShift); \
2316	*puDst = uResult; \
2317	\
2318	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2319	it the same way as for 1 bit shifts. */ \
2320	fEfl &= ~(X86_EFL_CF \| X86_EFL_OF); \
2321	uint32_t const fCarry = (uDst >> (cShift - 1)) & X86_EFL_CF; \
2322	fEfl \|= fCarry; \
2323	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth(uResult ^ (uResult << 1)); /* XOR two most signficant bits of the result */ \
2324	*pfEFlags = fEfl; \
2325	} \
2326	}
2327	EMIT_RCR(64)
2328	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2329	EMIT_RCR(32)
2330	EMIT_RCR(16)
2331	EMIT_RCR(8)
2332	# endif
2333
2334
2335	/*
2336	* SHL
2337	*/
2338	#define EMIT_SHL(a_cBitsWidth) \
2339	IEM_DECL_IMPL_DEF(void, iemAImpl_shl_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2340	{ \
2341	cShift &= a_cBitsWidth - 1; \
2342	if (cShift) \
2343	{ \
2344	uint ## a_cBitsWidth ##_t const uDst = *puDst; \
2345	uint ## a_cBitsWidth ##_t uResult = uDst << cShift; \
2346	*puDst = uResult; \
2347	\
2348	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2349	it the same way as for 1 bit shifts. The AF bit is undefined, but
2350	AMD 3990x sets it unconditionally so we do the same. */ \
2351	AssertCompile(X86_EFL_CF_BIT == 0); \
2352	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2353	uint32_t fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2354	fEfl \|= fCarry; \
2355	fEfl \|= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2356	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2357	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2358	fEfl \|= g_afParity[uResult & 0xff]; \
2359	fEfl \|= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
2360	*pfEFlags = fEfl; \
2361	} \
2362	}
2363	EMIT_SHL(64)
2364	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2365	EMIT_SHL(32)
2366	EMIT_SHL(16)
2367	EMIT_SHL(8)
2368	# endif
2369
2370
2371	/*
2372	* SHR
2373	*/
2374	#define EMIT_SHR(a_cBitsWidth) \
2375	IEM_DECL_IMPL_DEF(void, iemAImpl_shr_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2376	{ \
2377	cShift &= a_cBitsWidth - 1; \
2378	if (cShift) \
2379	{ \
2380	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2381	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2382	*puDst = uResult; \
2383	\
2384	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2385	it the same way as for 1 bit shifts. The AF bit is undefined, but \
2386	AMD 3990x sets it unconditionally so we do the same. */ \
2387	AssertCompile(X86_EFL_CF_BIT == 0); \
2388	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2389	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2390	if (cShift == 1) /* AMD 3990x does this too, even if only intel documents this. */ \
2391	fEfl \|= (uDst >> (a_cBitsWidth - 1)) << X86_EFL_OF_BIT; \
2392	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2393	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2394	fEfl \|= g_afParity[uResult & 0xff]; \
2395	fEfl \|= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
2396	*pfEFlags = fEfl; \
2397	} \
2398	}
2399	EMIT_SHR(64)
2400	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2401	EMIT_SHR(32)
2402	EMIT_SHR(16)
2403	EMIT_SHR(8)
2404	# endif
2405
2406
2407	/*
2408	* SAR
2409	*/
2410	#define EMIT_SAR(a_cBitsWidth) \
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_sar_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t puDst, uint8_t cShift, uint32_t pfEFlags)) \
2412	{ \
2413	cShift &= a_cBitsWidth - 1; \
2414	if (cShift) \
2415	{ \
2416	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2417	uint ## a_cBitsWidth ## _t uResult = (int ## a_cBitsWidth ## _t)uDst >> cShift; \
2418	*puDst = uResult; \
2419	\
2420	/* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2421	it the same way as for 1 bit shifts (0). The AF bit is undefined, but \
2422	AMD 3990x sets it unconditionally so we do the same. The OF flag is \
2423	zero because the result never differs from the input. */ \
2424	AssertCompile(X86_EFL_CF_BIT == 0); \
2425	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2426	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2427	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2428	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2429	fEfl \|= g_afParity[uResult & 0xff]; \
2430	fEfl \|= X86_EFL_AF; /* AMD 3990x sets it unconditionally */ \
2431	*pfEFlags = fEfl; \
2432	} \
2433	}
2434	EMIT_SAR(64)
2435	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2436	EMIT_SAR(32)
2437	EMIT_SAR(16)
2438	EMIT_SAR(8)
2439	# endif
2440
2441
2442	/*
2443	* SHLD
2444	*/
2445	#define EMIT_SHLD(a_cBitsWidth) \
2446	IEM_DECL_IMPL_DEF(void, iemAImpl_shld_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2447	uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2448	{ \
2449	cShift &= a_cBitsWidth - 1; \
2450	if (cShift) \
2451	{ \
2452	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2453	uint ## a_cBitsWidth ## _t uResult = uDst << cShift; \
2454	uResult \|= uSrc >> (a_cBitsWidth - cShift); \
2455	*puDst = uResult; \
2456	\
2457	/* Calc EFLAGS. CF is the last bit shifted out of puDst. The OF flag \
2458	indicates a sign change for a single shift, whereas intel documents \
2459	setting it to zero for higher shift counts and AMD just says it's \
2460	undefined, however AMD x3990 sets it according to the last sub-shift. \
2461	On AMD x3990 the AF flag is always set. */ \
2462	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2463	if (true /AMD/) \
2464	{ \
2465	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst << (cShift - 1)) ^ uResult); /* Set according to last shift. */ \
2466	fEfl \|= X86_EFL_AF; \
2467	} \
2468	else \
2469	{ \
2470	if (cShift == 1) \
2471	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst ^ uResult)); \
2472	fEfl \|= X86_EFL_AF; /* ? */ \
2473	} \
2474	AssertCompile(X86_EFL_CF_BIT == 0); \
2475	fEfl \|= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; /* CF = last bit shifted out */ \
2476	fEfl \|= g_afParity[uResult & 0xff]; \
2477	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2478	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2479	*pfEFlags = fEfl; \
2480	} \
2481	}
2482	EMIT_SHLD(64)
2483	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2484	EMIT_SHLD(32)
2485	EMIT_SHLD(16)
2486	# endif
2487
2488
2489	/*
2490	* SHRD
2491	*/
2492	#define EMIT_SHRD(a_cBitsWidth) \
2493	IEM_DECL_IMPL_DEF(void, iemAImpl_shrd_u ## a_cBitsWidth,(uint ## a_cBitsWidth ## _t *puDst, \
2494	uint ## a_cBitsWidth ## _t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2495	{ \
2496	cShift &= a_cBitsWidth - 1; \
2497	if (cShift) \
2498	{ \
2499	uint ## a_cBitsWidth ## _t const uDst = *puDst; \
2500	uint ## a_cBitsWidth ## _t uResult = uDst >> cShift; \
2501	uResult \|= uSrc << (a_cBitsWidth - cShift); \
2502	*puDst = uResult; \
2503	\
2504	/* Calc EFLAGS. CF is the last bit shifted out of puDst. The OF flag \
2505	indicates a sign change for a single shift, whereas intel documents \
2506	setting it to zero for higher shift counts and AMD just says it's \
2507	undefined, however AMD x3990 sets it according to the last sub-shift. \
2508	On AMD x3990 the AF flag is always set. */ \
2509	uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2510	if (true /AMD/) \
2511	{ \
2512	if (cShift > 1) /* Set according to last shift. */ \
2513	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth((uSrc << (a_cBitsWidth - cShift + 1)) ^ uResult); \
2514	else \
2515	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ uResult); \
2516	fEfl \|= X86_EFL_AF; \
2517	} \
2518	else \
2519	{ \
2520	if (cShift == 1) \
2521	fEfl \|= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst >> (a_cBitsWidth - 1)) ^ (uint32_t)(uResult >> (a_cBitsWidth - 1))); \
2522	fEfl \|= X86_EFL_AF; /* ? */ \
2523	} \
2524	AssertCompile(X86_EFL_CF_BIT == 0); \
2525	fEfl \|= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2526	fEfl \|= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2527	fEfl \|= X86_EFL_CALC_ZF(uResult); \
2528	fEfl \|= g_afParity[uResult & 0xff]; \
2529	*pfEFlags = fEfl; \
2530	} \
2531	}
2532	EMIT_SHRD(64)
2533	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2534	EMIT_SHRD(32)
2535	EMIT_SHRD(16)
2536	# endif
2537
2538
2539	# if !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY)
2540	/*
2541	* BSWAP
2542	*/
2543
2544	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u64,(uint64_t *puDst))
2545	{
2546	puDst = ASMByteSwapU64(puDst);
2547	}
2548
2549
2550	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u32,(uint32_t *puDst))
2551	{
2552	puDst = ASMByteSwapU32(puDst);
2553	}
2554
2555
2556	/* Note! undocument, so 32-bit arg */
2557	IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u16,(uint32_t *puDst))
2558	{
2559	puDst = ASMByteSwapU16((uint16_t)puDst) \| (*puDst & UINT32_C(0xffff0000));
2560	}
2561
2562	# endif /* !defined(RT_ARCH_X86) \|\| defined(IEM_WITHOUT_ASSEMBLY) */
2563
2564
2565
2566	# if defined(IEM_WITHOUT_ASSEMBLY)
2567
2568	/*
2569	* LFENCE, SFENCE & MFENCE.
2570	*/
2571
2572	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void))
2573	{
2574	ASMReadFence();
2575	}
2576
2577
2578	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void))
2579	{
2580	ASMWriteFence();
2581	}
2582
2583
2584	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void))
2585	{
2586	ASMMemoryFence();
2587	}
2588
2589
2590	# ifndef RT_ARCH_ARM64
2591	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void))
2592	{
2593	ASMMemoryFence();
2594	}
2595	# endif
2596
2597	# endif
2598
2599	#endif /* !RT_ARCH_AMD64 \|\| IEM_WITHOUT_ASSEMBLY */
2600
2601
2602	IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t pu16Dst, uint16_t u16Src, uint32_t pfEFlags))
2603	{
2604	if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
2605	{
2606	*pu16Dst &= X86_SEL_MASK_OFF_RPL;
2607	*pu16Dst \|= u16Src & X86_SEL_RPL;
2608
2609	*pfEFlags \|= X86_EFL_ZF;
2610	}
2611	else
2612	*pfEFlags &= ~X86_EFL_ZF;
2613	}
2614
2615
2616	/*********************************************************************************************************************************
2617	* x87 FPU *
2618	*********************************************************************************************************************************/
2619	#if defined(IEM_WITHOUT_ASSEMBLY)
2620
2621	IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2622	{
2623	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2624	AssertReleaseFailed();
2625	}
2626
2627
2628	IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2629	{
2630	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2631	AssertReleaseFailed();
2632	}
2633
2634
2635	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2636	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2637	{
2638	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2639	AssertReleaseFailed();
2640	}
2641
2642
2643	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2644	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2645	{
2646	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2647	AssertReleaseFailed();
2648	}
2649
2650
2651	IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2652	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2653	{
2654	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2655	AssertReleaseFailed();
2656	}
2657
2658
2659	IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2660	{
2661	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2662	AssertReleaseFailed();
2663	}
2664
2665
2666	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2667	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2668	{
2669	RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
2670	AssertReleaseFailed();
2671	}
2672
2673
2674	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2675	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2676	{
2677	RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
2678	AssertReleaseFailed();
2679	}
2680
2681
2682	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2683	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2684	{
2685	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2686	AssertReleaseFailed();
2687	}
2688
2689
2690	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2691	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2692	{
2693	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
2694	AssertReleaseFailed();
2695	return 0;
2696	}
2697
2698
2699	IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2700	{
2701	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2702	AssertReleaseFailed();
2703	}
2704
2705
2706	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2707	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2708	{
2709	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2710	AssertReleaseFailed();
2711	}
2712
2713
2714	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2715	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2716	{
2717	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2718	AssertReleaseFailed();
2719	}
2720
2721
2722	IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2723	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2724	{
2725	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2726	AssertReleaseFailed();
2727	}
2728
2729
2730	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2731	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2732	{
2733	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2734	AssertReleaseFailed();
2735	}
2736
2737
2738	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2739	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2740	{
2741	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2742	AssertReleaseFailed();
2743	}
2744
2745
2746	IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2747	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2748	{
2749	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2750	AssertReleaseFailed();
2751	}
2752
2753
2754	IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2755	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2756	{
2757	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2758	AssertReleaseFailed();
2759	}
2760
2761
2762	IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2763	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2764	{
2765	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2766	AssertReleaseFailed();
2767	}
2768
2769
2770	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2771	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2772	{
2773	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
2774	AssertReleaseFailed();
2775	}
2776
2777
2778	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2779	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2780	{
2781	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
2782	AssertReleaseFailed();
2783	}
2784
2785
2786	IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2787	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2788	{
2789	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2790	AssertReleaseFailed();
2791	}
2792
2793
2794	IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2795	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2796	{
2797	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2798	AssertReleaseFailed();
2799	}
2800
2801
2802	IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2803	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2804	{
2805	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2806	AssertReleaseFailed();
2807	}
2808
2809
2810	IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2811	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2812	{
2813	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2814	AssertReleaseFailed();
2815	}
2816
2817
2818	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
2819	{
2820	RT_NOREF(pFpuState, pFpuRes, pi16Val);
2821	AssertReleaseFailed();
2822	}
2823
2824
2825	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
2826	{
2827	RT_NOREF(pFpuState, pFpuRes, pi32Val);
2828	AssertReleaseFailed();
2829	}
2830
2831
2832	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
2833	{
2834	RT_NOREF(pFpuState, pFpuRes, pi64Val);
2835	AssertReleaseFailed();
2836	}
2837
2838
2839	IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2840	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2841	{
2842	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2843	AssertReleaseFailed();
2844	}
2845
2846
2847	IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2848	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2849	{
2850	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2851	AssertReleaseFailed();
2852	}
2853
2854
2855	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2856	int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2857	{
2858	RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2859	AssertReleaseFailed();
2860	}
2861
2862
2863	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2864	int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2865	{
2866	RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2867	AssertReleaseFailed();
2868	}
2869
2870
2871	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2872	int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2873	{
2874	RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2875	AssertReleaseFailed();
2876	}
2877
2878
2879	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2880	int16_t *pi16Val, PCRTFLOAT80U pr80Val))
2881	{
2882	RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
2883	AssertReleaseFailed();
2884	}
2885
2886
2887	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2888	int32_t *pi32Val, PCRTFLOAT80U pr80Val))
2889	{
2890	RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
2891	AssertReleaseFailed();
2892	}
2893
2894
2895	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2896	int64_t *pi64Val, PCRTFLOAT80U pr80Val))
2897	{
2898	RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
2899	AssertReleaseFailed();
2900	}
2901
2902
2903	IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2904	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2905	{
2906	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2907	AssertReleaseFailed();
2908	}
2909
2910
2911	IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2912	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2913	{
2914	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2915	AssertReleaseFailed();
2916	}
2917
2918
2919	IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2920	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
2921	{
2922	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
2923	AssertReleaseFailed();
2924	}
2925
2926
2927	IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2928	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
2929	{
2930	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
2931	AssertReleaseFailed();
2932	}
2933
2934
2935	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
2936	{
2937	RT_NOREF(pFpuState, pFpuRes, pr32Val);
2938	AssertReleaseFailed();
2939	}
2940
2941
2942	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
2943	{
2944	RT_NOREF(pFpuState, pFpuRes, pr64Val);
2945	AssertReleaseFailed();
2946	}
2947
2948	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2949	{
2950	RT_NOREF(pFpuState, pFpuRes, pr80Val);
2951	AssertReleaseFailed();
2952	}
2953
2954
2955	IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2956	{
2957	RT_NOREF(pFpuState, pFpuRes);
2958	AssertReleaseFailed();
2959	}
2960
2961
2962	IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2963	{
2964	RT_NOREF(pFpuState, pFpuRes);
2965	AssertReleaseFailed();
2966	}
2967
2968
2969	IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2970	{
2971	RT_NOREF(pFpuState, pFpuRes);
2972	AssertReleaseFailed();
2973	}
2974
2975
2976	IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2977	{
2978	RT_NOREF(pFpuState, pFpuRes);
2979	AssertReleaseFailed();
2980	}
2981
2982
2983	IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2984	{
2985	RT_NOREF(pFpuState, pFpuRes);
2986	AssertReleaseFailed();
2987	}
2988
2989
2990	IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2991	{
2992	RT_NOREF(pFpuState, pFpuRes);
2993	AssertReleaseFailed();
2994	}
2995
2996
2997	IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
2998	{
2999	RT_NOREF(pFpuState, pFpuRes);
3000	AssertReleaseFailed();
3001	}
3002
3003
3004	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3005	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3006	{
3007	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3008	AssertReleaseFailed();
3009	}
3010
3011
3012	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3013	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3014	{
3015	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3016	AssertReleaseFailed();
3017	}
3018
3019
3020	IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3021	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3022	{
3023	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3024	AssertReleaseFailed();
3025	}
3026
3027
3028	IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3029	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3030	{
3031	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3032	AssertReleaseFailed();
3033	}
3034
3035
3036	IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3037	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3038	{
3039	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3040	AssertReleaseFailed();
3041	}
3042
3043
3044	IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3045	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3046	{
3047	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3048	AssertReleaseFailed();
3049	}
3050
3051
3052	IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3053	{
3054	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3055	AssertReleaseFailed();
3056	}
3057
3058
3059	IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3060	{
3061	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3062	AssertReleaseFailed();
3063	}
3064
3065
3066	IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3067	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3068	{
3069	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3070	AssertReleaseFailed();
3071	}
3072
3073
3074	IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3075	{
3076	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3077	AssertReleaseFailed();
3078	}
3079
3080
3081	IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3082	{
3083	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3084	AssertReleaseFailed();
3085	}
3086
3087
3088	IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3089	{
3090	RT_NOREF(pFpuState, pFpuRes, pr80Val);
3091	AssertReleaseFailed();
3092	}
3093
3094
3095	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3096	PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
3097	{
3098	RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
3099	AssertReleaseFailed();
3100	}
3101
3102
3103	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3104	PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
3105	{
3106	RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
3107	AssertReleaseFailed();
3108	}
3109
3110
3111	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3112	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
3113	{
3114	RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
3115	AssertReleaseFailed();
3116	}
3117
3118
3119	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3120	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3121	{
3122	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3123	AssertReleaseFailed();
3124	}
3125
3126
3127	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3128	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3129	{
3130	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3131	AssertReleaseFailed();
3132	}
3133
3134
3135	IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3136	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3137	{
3138	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3139	AssertReleaseFailed();
3140	}
3141
3142
3143	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3144	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3145	{
3146	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3147	AssertReleaseFailed();
3148	}
3149
3150
3151	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3152	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3153	{
3154	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3155	AssertReleaseFailed();
3156	}
3157
3158
3159	IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3160	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3161	{
3162	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3163	AssertReleaseFailed();
3164	}
3165
3166
3167	IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3168	{
3169	RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3170	AssertReleaseFailed();
3171	}
3172
3173
3174	IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3175	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3176	{
3177	RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3178	AssertReleaseFailed();
3179	}
3180
3181
3182	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3183	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3184	{
3185	RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
3186	AssertReleaseFailed();
3187	return 0;
3188	}
3189
3190
3191	IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3192	{
3193	RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3194	AssertReleaseFailed();
3195	}
3196
3197
3198	IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3199	{
3200	RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3201	AssertReleaseFailed();
3202	}
3203
3204
3205	IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3206	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3207	{
3208	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3209	AssertReleaseFailed();
3210	}
3211
3212
3213	IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3214	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3215	{
3216	RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3217	AssertReleaseFailed();
3218	}
3219
3220	#endif /* IEM_WITHOUT_ASSEMBLY */
3221
3222
3223	/*********************************************************************************************************************************
3224	* MMX, SSE & AVX *
3225	*********************************************************************************************************************************/
3226
3227	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3228	{
3229	RT_NOREF(pFpuState);
3230	puDst->au32[0] = puSrc->au32[0];
3231	puDst->au32[1] = puSrc->au32[0];
3232	puDst->au32[2] = puSrc->au32[2];
3233	puDst->au32[3] = puSrc->au32[2];
3234	}
3235
3236	#ifdef IEM_WITH_VEX
3237
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3239	{
3240	pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
3241	pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
3242	pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
3243	pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
3244	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3245	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3246	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3247	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3248	}
3249
3250
3251	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3252	{
3253	pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
3254	pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
3255	pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
3256	pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
3257	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
3258	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
3259	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
3260	pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
3261	}
3262
3263	#endif /* IEM_WITH_VEX */
3264
3265
3266	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3267	{
3268	RT_NOREF(pFpuState);
3269	puDst->au32[0] = puSrc->au32[1];
3270	puDst->au32[1] = puSrc->au32[1];
3271	puDst->au32[2] = puSrc->au32[3];
3272	puDst->au32[3] = puSrc->au32[3];
3273	}
3274
3275
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
3277	{
3278	RT_NOREF(pFpuState);
3279	puDst->au64[0] = uSrc;
3280	puDst->au64[1] = uSrc;
3281	}
3282
3283	#ifdef IEM_WITH_VEX
3284
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3286	{
3287	pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
3288	pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
3289	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3290	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3291	}
3292
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3294	{
3295	pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
3296	pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
3297	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
3298	pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
3299	}
3300
3301	#endif /* IEM_WITH_VEX */
3302
3303	#ifdef IEM_WITHOUT_ASSEMBLY
3304
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3306	{
3307	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3308	AssertReleaseFailed();
3309	}
3310
3311
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3313	{
3314	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3315	AssertReleaseFailed();
3316	}
3317
3318
3319	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3320	{
3321	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3322	AssertReleaseFailed();
3323	}
3324
3325
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3327	{
3328	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3329	AssertReleaseFailed();
3330	}
3331
3332
3333	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3334	{
3335	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3336	AssertReleaseFailed();
3337	}
3338
3339
3340	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3341	{
3342	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3343	AssertReleaseFailed();
3344	}
3345
3346
3347	IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3348	{
3349	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3350	AssertReleaseFailed();
3351	}
3352
3353
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3355	{
3356	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3357	AssertReleaseFailed();
3358	}
3359
3360
3361	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3362	{
3363	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3364	AssertReleaseFailed();
3365
3366	}
3367
3368
3369	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src))
3370	{
3371	RT_NOREF(pFpuState, pu64Dst, pu128Src);
3372	AssertReleaseFailed();
3373	}
3374
3375
3376	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil))
3377	{
3378	RT_NOREF(pFpuState, pu64Dst, pu64Src, bEvil);
3379	AssertReleaseFailed();
3380	}
3381
3382
3383	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufhw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3384	{
3385	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3386	AssertReleaseFailed();
3387	}
3388
3389
3390	IEM_DECL_IMPL_DEF(void, iemAImpl_pshuflw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3391	{
3392	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3393	AssertReleaseFailed();
3394	}
3395
3396
3397	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufd,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3398	{
3399	RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3400	AssertReleaseFailed();
3401	}
3402
3403	/* PUNPCKHxxx */
3404
3405	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3406	{
3407	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3408	AssertReleaseFailed();
3409	}
3410
3411
3412	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3413	{
3414	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3415	AssertReleaseFailed();
3416	}
3417
3418
3419	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3420	{
3421	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3422	AssertReleaseFailed();
3423	}
3424
3425
3426	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3427	{
3428	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3429	AssertReleaseFailed();
3430	}
3431
3432
3433	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src))
3434	{
3435	RT_NOREF(pFpuState, pu64Dst, pu64Src);
3436	AssertReleaseFailed();
3437	}
3438
3439
3440	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3441	{
3442	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3443	AssertReleaseFailed();
3444	}
3445
3446
3447	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3448	{
3449	RT_NOREF(pFpuState, pu128Dst, pu128Src);
3450	AssertReleaseFailed();
3451	}
3452
3453	/* PUNPCKLxxx */
3454
3455	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3456	{
3457	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3458	AssertReleaseFailed();
3459	}
3460
3461
3462	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3463	{
3464	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3465	AssertReleaseFailed();
3466	}
3467
3468
3469	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3470	{
3471	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3472	AssertReleaseFailed();
3473	}
3474
3475
3476	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3477	{
3478	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3479	AssertReleaseFailed();
3480	}
3481
3482
3483	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src))
3484	{
3485	RT_NOREF(pFpuState, pu64Dst, pu32Src);
3486	AssertReleaseFailed();
3487	}
3488
3489
3490	IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3491	{
3492	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3493	AssertReleaseFailed();
3494	}
3495
3496
3497	IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3498	{
3499	RT_NOREF(pFpuState, pu128Dst, pu64Src);
3500	AssertReleaseFailed();
3501	}
3502
3503	#endif /* IEM_WITHOUT_ASSEMBLY */

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp@ 93888

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