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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp@ 94261

Last change on this file since 94261 was 94261, checked in by vboxsync, 3 years ago

iprt/types.h,VMM,ValKit,IPRT: Dropped the bit counts in member prefixes in the RTFLOATxxU types and added a RTFLOAT32U. Added some fld [mem] tests. bugref:9898
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1/* $Id: IEMAllAImplC.cpp 94261 2022-03-16 01:34:29Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in Assembly, portable C variant.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include "IEMInternal.h"
23#include <VBox/vmm/vmcc.h>
24#include <iprt/errcore.h>
25#include <iprt/x86.h>
26#include <iprt/uint128.h>
27
28
29/*********************************************************************************************************************************
30* Defined Constants And Macros *
31*********************************************************************************************************************************/
32/** @def IEM_WITHOUT_ASSEMBLY
33 * Enables all the code in this file.
34 */
35#if !defined(IEM_WITHOUT_ASSEMBLY)
36# if defined(RT_ARCH_ARM32) || defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING)
37# define IEM_WITHOUT_ASSEMBLY
38# endif
39#endif
40/* IEM_WITH_ASSEMBLY trumps IEM_WITHOUT_ASSEMBLY for tstIEMAImplAsm purposes. */
41#ifdef IEM_WITH_ASSEMBLY
42# undef IEM_WITHOUT_ASSEMBLY
43#endif
44
45/**
46 * Calculates the signed flag value given a result and it's bit width.
47 *
48 * The signed flag (SF) is a duplication of the most significant bit in the
49 * result.
50 *
51 * @returns X86_EFL_SF or 0.
52 * @param a_uResult Unsigned result value.
53 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
54 */
55#define X86_EFL_CALC_SF(a_uResult, a_cBitsWidth) \
56 ( (uint32_t)((a_uResult) >> ((a_cBitsWidth) - X86_EFL_SF_BIT - 1)) & X86_EFL_SF )
57
58/**
59 * Calculates the zero flag value given a result.
60 *
61 * The zero flag (ZF) indicates whether the result is zero or not.
62 *
63 * @returns X86_EFL_ZF or 0.
64 * @param a_uResult Unsigned result value.
65 */
66#define X86_EFL_CALC_ZF(a_uResult) \
67 ( (uint32_t)((a_uResult) == 0) << X86_EFL_ZF_BIT )
68
69/**
70 * Extracts the OF flag from a OF calculation result.
71 *
72 * These are typically used by concating with a bitcount. The problem is that
73 * 8-bit values needs shifting in the other direction than the others.
74 */
75#define X86_EFL_GET_OF_8(a_uValue) (((uint32_t)(a_uValue) << (X86_EFL_OF_BIT - 8 + 1)) & X86_EFL_OF)
76#define X86_EFL_GET_OF_16(a_uValue) ((uint32_t)((a_uValue) >> (16 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
77#define X86_EFL_GET_OF_32(a_uValue) ((uint32_t)((a_uValue) >> (32 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
78#define X86_EFL_GET_OF_64(a_uValue) ((uint32_t)((a_uValue) >> (64 - X86_EFL_OF_BIT - 1)) & X86_EFL_OF)
79
80/**
81 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after arithmetic op.
82 *
83 * @returns Status bits.
84 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
85 * @param a_uResult Unsigned result value.
86 * @param a_uSrc The source value (for AF calc).
87 * @param a_uDst The original destination value (for AF calc).
88 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
89 * @param a_CfExpr Bool expression for the carry flag (CF).
90 * @param a_uSrcOf The a_uSrc value to use for overflow calculation.
91 */
92#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
93 do { \
94 uint32_t fEflTmp = *(a_pfEFlags); \
95 fEflTmp &= ~X86_EFL_STATUS_BITS; \
96 fEflTmp |= (a_CfExpr) << X86_EFL_CF_BIT; \
97 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
98 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
99 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
100 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
101 \
102 /* Overflow during ADDition happens when both inputs have the same signed \
103 bit value and the result has a different sign bit value. \
104 \
105 Since subtraction can be rewritten as addition: 2 - 1 == 2 + -1, it \
106 follows that for SUBtraction the signed bit value must differ between \
107 the two inputs and the result's signed bit diff from the first input. \
108 Note! Must xor with sign bit to convert, not do (0 - a_uSrc). \
109 \
110 See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
111 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth( ( ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
112 & RT_BIT_64(a_cBitsWidth - 1)) \
113 & ((a_uResult) ^ (a_uDst)) ); \
114 *(a_pfEFlags) = fEflTmp; \
115 } while (0)
116
117/**
118 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) after a logical op.
119 *
120 * CF and OF are defined to be 0 by logical operations. AF on the other hand is
121 * undefined. We do not set AF, as that seems to make the most sense (which
122 * probably makes it the most wrong in real life).
123 *
124 * @returns Status bits.
125 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
126 * @param a_uResult Unsigned result value.
127 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
128 * @param a_fExtra Additional bits to set.
129 */
130#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
131 do { \
132 uint32_t fEflTmp = *(a_pfEFlags); \
133 fEflTmp &= ~X86_EFL_STATUS_BITS; \
134 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
135 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
136 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
137 fEflTmp |= (a_fExtra); \
138 *(a_pfEFlags) = fEflTmp; \
139 } while (0)
140
141
142/*********************************************************************************************************************************
143* Global Variables *
144*********************************************************************************************************************************/
145/**
146 * Parity calculation table.
147 *
148 * This is also used by iemAllAImpl.asm.
149 *
150 * The generator code:
151 * @code
152 * #include <stdio.h>
153 *
154 * int main()
155 * {
156 * unsigned b;
157 * for (b = 0; b < 256; b++)
158 * {
159 * int cOnes = ( b & 1)
160 * + ((b >> 1) & 1)
161 * + ((b >> 2) & 1)
162 * + ((b >> 3) & 1)
163 * + ((b >> 4) & 1)
164 * + ((b >> 5) & 1)
165 * + ((b >> 6) & 1)
166 * + ((b >> 7) & 1);
167 * printf(" /" "* %#04x = %u%u%u%u%u%u%u%ub *" "/ %s,\n",
168 * b,
169 * (b >> 7) & 1,
170 * (b >> 6) & 1,
171 * (b >> 5) & 1,
172 * (b >> 4) & 1,
173 * (b >> 3) & 1,
174 * (b >> 2) & 1,
175 * (b >> 1) & 1,
176 * b & 1,
177 * cOnes & 1 ? "0" : "X86_EFL_PF");
178 * }
179 * return 0;
180 * }
181 * @endcode
182 */
183uint8_t const g_afParity[256] =
184{
185 /* 0000 = 00000000b */ X86_EFL_PF,
186 /* 0x01 = 00000001b */ 0,
187 /* 0x02 = 00000010b */ 0,
188 /* 0x03 = 00000011b */ X86_EFL_PF,
189 /* 0x04 = 00000100b */ 0,
190 /* 0x05 = 00000101b */ X86_EFL_PF,
191 /* 0x06 = 00000110b */ X86_EFL_PF,
192 /* 0x07 = 00000111b */ 0,
193 /* 0x08 = 00001000b */ 0,
194 /* 0x09 = 00001001b */ X86_EFL_PF,
195 /* 0x0a = 00001010b */ X86_EFL_PF,
196 /* 0x0b = 00001011b */ 0,
197 /* 0x0c = 00001100b */ X86_EFL_PF,
198 /* 0x0d = 00001101b */ 0,
199 /* 0x0e = 00001110b */ 0,
200 /* 0x0f = 00001111b */ X86_EFL_PF,
201 /* 0x10 = 00010000b */ 0,
202 /* 0x11 = 00010001b */ X86_EFL_PF,
203 /* 0x12 = 00010010b */ X86_EFL_PF,
204 /* 0x13 = 00010011b */ 0,
205 /* 0x14 = 00010100b */ X86_EFL_PF,
206 /* 0x15 = 00010101b */ 0,
207 /* 0x16 = 00010110b */ 0,
208 /* 0x17 = 00010111b */ X86_EFL_PF,
209 /* 0x18 = 00011000b */ X86_EFL_PF,
210 /* 0x19 = 00011001b */ 0,
211 /* 0x1a = 00011010b */ 0,
212 /* 0x1b = 00011011b */ X86_EFL_PF,
213 /* 0x1c = 00011100b */ 0,
214 /* 0x1d = 00011101b */ X86_EFL_PF,
215 /* 0x1e = 00011110b */ X86_EFL_PF,
216 /* 0x1f = 00011111b */ 0,
217 /* 0x20 = 00100000b */ 0,
218 /* 0x21 = 00100001b */ X86_EFL_PF,
219 /* 0x22 = 00100010b */ X86_EFL_PF,
220 /* 0x23 = 00100011b */ 0,
221 /* 0x24 = 00100100b */ X86_EFL_PF,
222 /* 0x25 = 00100101b */ 0,
223 /* 0x26 = 00100110b */ 0,
224 /* 0x27 = 00100111b */ X86_EFL_PF,
225 /* 0x28 = 00101000b */ X86_EFL_PF,
226 /* 0x29 = 00101001b */ 0,
227 /* 0x2a = 00101010b */ 0,
228 /* 0x2b = 00101011b */ X86_EFL_PF,
229 /* 0x2c = 00101100b */ 0,
230 /* 0x2d = 00101101b */ X86_EFL_PF,
231 /* 0x2e = 00101110b */ X86_EFL_PF,
232 /* 0x2f = 00101111b */ 0,
233 /* 0x30 = 00110000b */ X86_EFL_PF,
234 /* 0x31 = 00110001b */ 0,
235 /* 0x32 = 00110010b */ 0,
236 /* 0x33 = 00110011b */ X86_EFL_PF,
237 /* 0x34 = 00110100b */ 0,
238 /* 0x35 = 00110101b */ X86_EFL_PF,
239 /* 0x36 = 00110110b */ X86_EFL_PF,
240 /* 0x37 = 00110111b */ 0,
241 /* 0x38 = 00111000b */ 0,
242 /* 0x39 = 00111001b */ X86_EFL_PF,
243 /* 0x3a = 00111010b */ X86_EFL_PF,
244 /* 0x3b = 00111011b */ 0,
245 /* 0x3c = 00111100b */ X86_EFL_PF,
246 /* 0x3d = 00111101b */ 0,
247 /* 0x3e = 00111110b */ 0,
248 /* 0x3f = 00111111b */ X86_EFL_PF,
249 /* 0x40 = 01000000b */ 0,
250 /* 0x41 = 01000001b */ X86_EFL_PF,
251 /* 0x42 = 01000010b */ X86_EFL_PF,
252 /* 0x43 = 01000011b */ 0,
253 /* 0x44 = 01000100b */ X86_EFL_PF,
254 /* 0x45 = 01000101b */ 0,
255 /* 0x46 = 01000110b */ 0,
256 /* 0x47 = 01000111b */ X86_EFL_PF,
257 /* 0x48 = 01001000b */ X86_EFL_PF,
258 /* 0x49 = 01001001b */ 0,
259 /* 0x4a = 01001010b */ 0,
260 /* 0x4b = 01001011b */ X86_EFL_PF,
261 /* 0x4c = 01001100b */ 0,
262 /* 0x4d = 01001101b */ X86_EFL_PF,
263 /* 0x4e = 01001110b */ X86_EFL_PF,
264 /* 0x4f = 01001111b */ 0,
265 /* 0x50 = 01010000b */ X86_EFL_PF,
266 /* 0x51 = 01010001b */ 0,
267 /* 0x52 = 01010010b */ 0,
268 /* 0x53 = 01010011b */ X86_EFL_PF,
269 /* 0x54 = 01010100b */ 0,
270 /* 0x55 = 01010101b */ X86_EFL_PF,
271 /* 0x56 = 01010110b */ X86_EFL_PF,
272 /* 0x57 = 01010111b */ 0,
273 /* 0x58 = 01011000b */ 0,
274 /* 0x59 = 01011001b */ X86_EFL_PF,
275 /* 0x5a = 01011010b */ X86_EFL_PF,
276 /* 0x5b = 01011011b */ 0,
277 /* 0x5c = 01011100b */ X86_EFL_PF,
278 /* 0x5d = 01011101b */ 0,
279 /* 0x5e = 01011110b */ 0,
280 /* 0x5f = 01011111b */ X86_EFL_PF,
281 /* 0x60 = 01100000b */ X86_EFL_PF,
282 /* 0x61 = 01100001b */ 0,
283 /* 0x62 = 01100010b */ 0,
284 /* 0x63 = 01100011b */ X86_EFL_PF,
285 /* 0x64 = 01100100b */ 0,
286 /* 0x65 = 01100101b */ X86_EFL_PF,
287 /* 0x66 = 01100110b */ X86_EFL_PF,
288 /* 0x67 = 01100111b */ 0,
289 /* 0x68 = 01101000b */ 0,
290 /* 0x69 = 01101001b */ X86_EFL_PF,
291 /* 0x6a = 01101010b */ X86_EFL_PF,
292 /* 0x6b = 01101011b */ 0,
293 /* 0x6c = 01101100b */ X86_EFL_PF,
294 /* 0x6d = 01101101b */ 0,
295 /* 0x6e = 01101110b */ 0,
296 /* 0x6f = 01101111b */ X86_EFL_PF,
297 /* 0x70 = 01110000b */ 0,
298 /* 0x71 = 01110001b */ X86_EFL_PF,
299 /* 0x72 = 01110010b */ X86_EFL_PF,
300 /* 0x73 = 01110011b */ 0,
301 /* 0x74 = 01110100b */ X86_EFL_PF,
302 /* 0x75 = 01110101b */ 0,
303 /* 0x76 = 01110110b */ 0,
304 /* 0x77 = 01110111b */ X86_EFL_PF,
305 /* 0x78 = 01111000b */ X86_EFL_PF,
306 /* 0x79 = 01111001b */ 0,
307 /* 0x7a = 01111010b */ 0,
308 /* 0x7b = 01111011b */ X86_EFL_PF,
309 /* 0x7c = 01111100b */ 0,
310 /* 0x7d = 01111101b */ X86_EFL_PF,
311 /* 0x7e = 01111110b */ X86_EFL_PF,
312 /* 0x7f = 01111111b */ 0,
313 /* 0x80 = 10000000b */ 0,
314 /* 0x81 = 10000001b */ X86_EFL_PF,
315 /* 0x82 = 10000010b */ X86_EFL_PF,
316 /* 0x83 = 10000011b */ 0,
317 /* 0x84 = 10000100b */ X86_EFL_PF,
318 /* 0x85 = 10000101b */ 0,
319 /* 0x86 = 10000110b */ 0,
320 /* 0x87 = 10000111b */ X86_EFL_PF,
321 /* 0x88 = 10001000b */ X86_EFL_PF,
322 /* 0x89 = 10001001b */ 0,
323 /* 0x8a = 10001010b */ 0,
324 /* 0x8b = 10001011b */ X86_EFL_PF,
325 /* 0x8c = 10001100b */ 0,
326 /* 0x8d = 10001101b */ X86_EFL_PF,
327 /* 0x8e = 10001110b */ X86_EFL_PF,
328 /* 0x8f = 10001111b */ 0,
329 /* 0x90 = 10010000b */ X86_EFL_PF,
330 /* 0x91 = 10010001b */ 0,
331 /* 0x92 = 10010010b */ 0,
332 /* 0x93 = 10010011b */ X86_EFL_PF,
333 /* 0x94 = 10010100b */ 0,
334 /* 0x95 = 10010101b */ X86_EFL_PF,
335 /* 0x96 = 10010110b */ X86_EFL_PF,
336 /* 0x97 = 10010111b */ 0,
337 /* 0x98 = 10011000b */ 0,
338 /* 0x99 = 10011001b */ X86_EFL_PF,
339 /* 0x9a = 10011010b */ X86_EFL_PF,
340 /* 0x9b = 10011011b */ 0,
341 /* 0x9c = 10011100b */ X86_EFL_PF,
342 /* 0x9d = 10011101b */ 0,
343 /* 0x9e = 10011110b */ 0,
344 /* 0x9f = 10011111b */ X86_EFL_PF,
345 /* 0xa0 = 10100000b */ X86_EFL_PF,
346 /* 0xa1 = 10100001b */ 0,
347 /* 0xa2 = 10100010b */ 0,
348 /* 0xa3 = 10100011b */ X86_EFL_PF,
349 /* 0xa4 = 10100100b */ 0,
350 /* 0xa5 = 10100101b */ X86_EFL_PF,
351 /* 0xa6 = 10100110b */ X86_EFL_PF,
352 /* 0xa7 = 10100111b */ 0,
353 /* 0xa8 = 10101000b */ 0,
354 /* 0xa9 = 10101001b */ X86_EFL_PF,
355 /* 0xaa = 10101010b */ X86_EFL_PF,
356 /* 0xab = 10101011b */ 0,
357 /* 0xac = 10101100b */ X86_EFL_PF,
358 /* 0xad = 10101101b */ 0,
359 /* 0xae = 10101110b */ 0,
360 /* 0xaf = 10101111b */ X86_EFL_PF,
361 /* 0xb0 = 10110000b */ 0,
362 /* 0xb1 = 10110001b */ X86_EFL_PF,
363 /* 0xb2 = 10110010b */ X86_EFL_PF,
364 /* 0xb3 = 10110011b */ 0,
365 /* 0xb4 = 10110100b */ X86_EFL_PF,
366 /* 0xb5 = 10110101b */ 0,
367 /* 0xb6 = 10110110b */ 0,
368 /* 0xb7 = 10110111b */ X86_EFL_PF,
369 /* 0xb8 = 10111000b */ X86_EFL_PF,
370 /* 0xb9 = 10111001b */ 0,
371 /* 0xba = 10111010b */ 0,
372 /* 0xbb = 10111011b */ X86_EFL_PF,
373 /* 0xbc = 10111100b */ 0,
374 /* 0xbd = 10111101b */ X86_EFL_PF,
375 /* 0xbe = 10111110b */ X86_EFL_PF,
376 /* 0xbf = 10111111b */ 0,
377 /* 0xc0 = 11000000b */ X86_EFL_PF,
378 /* 0xc1 = 11000001b */ 0,
379 /* 0xc2 = 11000010b */ 0,
380 /* 0xc3 = 11000011b */ X86_EFL_PF,
381 /* 0xc4 = 11000100b */ 0,
382 /* 0xc5 = 11000101b */ X86_EFL_PF,
383 /* 0xc6 = 11000110b */ X86_EFL_PF,
384 /* 0xc7 = 11000111b */ 0,
385 /* 0xc8 = 11001000b */ 0,
386 /* 0xc9 = 11001001b */ X86_EFL_PF,
387 /* 0xca = 11001010b */ X86_EFL_PF,
388 /* 0xcb = 11001011b */ 0,
389 /* 0xcc = 11001100b */ X86_EFL_PF,
390 /* 0xcd = 11001101b */ 0,
391 /* 0xce = 11001110b */ 0,
392 /* 0xcf = 11001111b */ X86_EFL_PF,
393 /* 0xd0 = 11010000b */ 0,
394 /* 0xd1 = 11010001b */ X86_EFL_PF,
395 /* 0xd2 = 11010010b */ X86_EFL_PF,
396 /* 0xd3 = 11010011b */ 0,
397 /* 0xd4 = 11010100b */ X86_EFL_PF,
398 /* 0xd5 = 11010101b */ 0,
399 /* 0xd6 = 11010110b */ 0,
400 /* 0xd7 = 11010111b */ X86_EFL_PF,
401 /* 0xd8 = 11011000b */ X86_EFL_PF,
402 /* 0xd9 = 11011001b */ 0,
403 /* 0xda = 11011010b */ 0,
404 /* 0xdb = 11011011b */ X86_EFL_PF,
405 /* 0xdc = 11011100b */ 0,
406 /* 0xdd = 11011101b */ X86_EFL_PF,
407 /* 0xde = 11011110b */ X86_EFL_PF,
408 /* 0xdf = 11011111b */ 0,
409 /* 0xe0 = 11100000b */ 0,
410 /* 0xe1 = 11100001b */ X86_EFL_PF,
411 /* 0xe2 = 11100010b */ X86_EFL_PF,
412 /* 0xe3 = 11100011b */ 0,
413 /* 0xe4 = 11100100b */ X86_EFL_PF,
414 /* 0xe5 = 11100101b */ 0,
415 /* 0xe6 = 11100110b */ 0,
416 /* 0xe7 = 11100111b */ X86_EFL_PF,
417 /* 0xe8 = 11101000b */ X86_EFL_PF,
418 /* 0xe9 = 11101001b */ 0,
419 /* 0xea = 11101010b */ 0,
420 /* 0xeb = 11101011b */ X86_EFL_PF,
421 /* 0xec = 11101100b */ 0,
422 /* 0xed = 11101101b */ X86_EFL_PF,
423 /* 0xee = 11101110b */ X86_EFL_PF,
424 /* 0xef = 11101111b */ 0,
425 /* 0xf0 = 11110000b */ X86_EFL_PF,
426 /* 0xf1 = 11110001b */ 0,
427 /* 0xf2 = 11110010b */ 0,
428 /* 0xf3 = 11110011b */ X86_EFL_PF,
429 /* 0xf4 = 11110100b */ 0,
430 /* 0xf5 = 11110101b */ X86_EFL_PF,
431 /* 0xf6 = 11110110b */ X86_EFL_PF,
432 /* 0xf7 = 11110111b */ 0,
433 /* 0xf8 = 11111000b */ 0,
434 /* 0xf9 = 11111001b */ X86_EFL_PF,
435 /* 0xfa = 11111010b */ X86_EFL_PF,
436 /* 0xfb = 11111011b */ 0,
437 /* 0xfc = 11111100b */ X86_EFL_PF,
438 /* 0xfd = 11111101b */ 0,
439 /* 0xfe = 11111110b */ 0,
440 /* 0xff = 11111111b */ X86_EFL_PF,
441};
442
443
444/*
445 * There are a few 64-bit on 32-bit things we'd rather do in C. Actually, doing
446 * it all in C is probably safer atm., optimize what's necessary later, maybe.
447 */
448#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
449
450
451/*********************************************************************************************************************************
452* Binary Operations *
453*********************************************************************************************************************************/
454
455/*
456 * ADD
457 */
458
459IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
460{
461 uint64_t uDst = *puDst;
462 uint64_t uResult = uDst + uSrc;
463 *puDst = uResult;
464 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
465}
466
467# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
468
469IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
470{
471 uint32_t uDst = *puDst;
472 uint32_t uResult = uDst + uSrc;
473 *puDst = uResult;
474 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
475}
476
477
478IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
479{
480 uint16_t uDst = *puDst;
481 uint16_t uResult = uDst + uSrc;
482 *puDst = uResult;
483 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
484}
485
486
487IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
488{
489 uint8_t uDst = *puDst;
490 uint8_t uResult = uDst + uSrc;
491 *puDst = uResult;
492 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
493}
494
495# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
496
497/*
498 * ADC
499 */
500
501IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
502{
503 if (!(*pfEFlags & X86_EFL_CF))
504 iemAImpl_add_u64(puDst, uSrc, pfEFlags);
505 else
506 {
507 uint64_t uDst = *puDst;
508 uint64_t uResult = uDst + uSrc + 1;
509 *puDst = uResult;
510 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
511 }
512}
513
514# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
515
516IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
517{
518 if (!(*pfEFlags & X86_EFL_CF))
519 iemAImpl_add_u32(puDst, uSrc, pfEFlags);
520 else
521 {
522 uint32_t uDst = *puDst;
523 uint32_t uResult = uDst + uSrc + 1;
524 *puDst = uResult;
525 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
526 }
527}
528
529
530IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
531{
532 if (!(*pfEFlags & X86_EFL_CF))
533 iemAImpl_add_u16(puDst, uSrc, pfEFlags);
534 else
535 {
536 uint16_t uDst = *puDst;
537 uint16_t uResult = uDst + uSrc + 1;
538 *puDst = uResult;
539 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
540 }
541}
542
543
544IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
545{
546 if (!(*pfEFlags & X86_EFL_CF))
547 iemAImpl_add_u8(puDst, uSrc, pfEFlags);
548 else
549 {
550 uint8_t uDst = *puDst;
551 uint8_t uResult = uDst + uSrc + 1;
552 *puDst = uResult;
553 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
554 }
555}
556
557# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
558
559/*
560 * SUB
561 */
562
563IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
564{
565 uint64_t uDst = *puDst;
566 uint64_t uResult = uDst - uSrc;
567 *puDst = uResult;
568 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
569}
570
571# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
572
573IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
574{
575 uint32_t uDst = *puDst;
576 uint32_t uResult = uDst - uSrc;
577 *puDst = uResult;
578 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
579}
580
581
582IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
583{
584 uint16_t uDst = *puDst;
585 uint16_t uResult = uDst - uSrc;
586 *puDst = uResult;
587 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
588}
589
590
591IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
592{
593 uint8_t uDst = *puDst;
594 uint8_t uResult = uDst - uSrc;
595 *puDst = uResult;
596 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
597}
598
599# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
600
601/*
602 * SBB
603 */
604
605IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
606{
607 if (!(*pfEFlags & X86_EFL_CF))
608 iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
609 else
610 {
611 uint64_t uDst = *puDst;
612 uint64_t uResult = uDst - uSrc - 1;
613 *puDst = uResult;
614 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
615 }
616}
617
618# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
619
620IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
621{
622 if (!(*pfEFlags & X86_EFL_CF))
623 iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
624 else
625 {
626 uint32_t uDst = *puDst;
627 uint32_t uResult = uDst - uSrc - 1;
628 *puDst = uResult;
629 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
630 }
631}
632
633
634IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
635{
636 if (!(*pfEFlags & X86_EFL_CF))
637 iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
638 else
639 {
640 uint16_t uDst = *puDst;
641 uint16_t uResult = uDst - uSrc - 1;
642 *puDst = uResult;
643 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
644 }
645}
646
647
648IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
649{
650 if (!(*pfEFlags & X86_EFL_CF))
651 iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
652 else
653 {
654 uint8_t uDst = *puDst;
655 uint8_t uResult = uDst - uSrc - 1;
656 *puDst = uResult;
657 IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
658 }
659}
660
661# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
662
663
664/*
665 * OR
666 */
667
668IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
669{
670 uint64_t uResult = *puDst | uSrc;
671 *puDst = uResult;
672 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
673}
674
675# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
676
677IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
678{
679 uint32_t uResult = *puDst | uSrc;
680 *puDst = uResult;
681 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
682}
683
684
685IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
686{
687 uint16_t uResult = *puDst | uSrc;
688 *puDst = uResult;
689 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
690}
691
692
693IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
694{
695 uint8_t uResult = *puDst | uSrc;
696 *puDst = uResult;
697 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
698}
699
700# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
701
702/*
703 * XOR
704 */
705
706IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
707{
708 uint64_t uResult = *puDst ^ uSrc;
709 *puDst = uResult;
710 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
711}
712
713# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
714
715IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
716{
717 uint32_t uResult = *puDst ^ uSrc;
718 *puDst = uResult;
719 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
720}
721
722
723IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
724{
725 uint16_t uResult = *puDst ^ uSrc;
726 *puDst = uResult;
727 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
728}
729
730
731IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
732{
733 uint8_t uResult = *puDst ^ uSrc;
734 *puDst = uResult;
735 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
736}
737
738# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
739
740/*
741 * AND
742 */
743
744IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
745{
746 uint64_t uResult = *puDst & uSrc;
747 *puDst = uResult;
748 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
749}
750
751# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
752
753IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
754{
755 uint32_t uResult = *puDst & uSrc;
756 *puDst = uResult;
757 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
758}
759
760
761IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
762{
763 uint16_t uResult = *puDst & uSrc;
764 *puDst = uResult;
765 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
766}
767
768
769IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
770{
771 uint8_t uResult = *puDst & uSrc;
772 *puDst = uResult;
773 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
774}
775
776# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
777
778/*
779 * CMP
780 */
781
782IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
783{
784 uint64_t uDstTmp = *puDst;
785 iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
786}
787
788# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
789
790IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
791{
792 uint32_t uDstTmp = *puDst;
793 iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
794}
795
796
797IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
798{
799 uint16_t uDstTmp = *puDst;
800 iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
801}
802
803
804IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
805{
806 uint8_t uDstTmp = *puDst;
807 iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
808}
809
810# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
811
812/*
813 * TEST
814 */
815
816IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
817{
818 uint64_t uResult = *puDst & uSrc;
819 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 64, 0);
820}
821
822# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
823
824IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
825{
826 uint32_t uResult = *puDst & uSrc;
827 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 32, 0);
828}
829
830
831IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
832{
833 uint16_t uResult = *puDst & uSrc;
834 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 16, 0);
835}
836
837
838IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
839{
840 uint8_t uResult = *puDst & uSrc;
841 IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGIC(pfEFlags, uResult, 8, 0);
842}
843
844# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
845
846
847/*
848 * LOCK prefixed variants of the above
849 */
850
851/** 64-bit locked binary operand operation. */
852# define DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
853 do { \
854 uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
855 uint ## a_cBitsWidth ## _t uTmp; \
856 uint32_t fEflTmp; \
857 do \
858 { \
859 uTmp = uOld; \
860 fEflTmp = *pfEFlags; \
861 iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
862 } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
863 *pfEFlags = fEflTmp; \
864 } while (0)
865
866
867#define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
868 IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
869 uint ## a_cBitsWidth ## _t uSrc, \
870 uint32_t *pfEFlags)) \
871 { \
872 DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
873 }
874
875EMIT_LOCKED_BIN_OP(add, 64)
876EMIT_LOCKED_BIN_OP(adc, 64)
877EMIT_LOCKED_BIN_OP(sub, 64)
878EMIT_LOCKED_BIN_OP(sbb, 64)
879EMIT_LOCKED_BIN_OP(or, 64)
880EMIT_LOCKED_BIN_OP(xor, 64)
881EMIT_LOCKED_BIN_OP(and, 64)
882# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
883EMIT_LOCKED_BIN_OP(add, 32)
884EMIT_LOCKED_BIN_OP(adc, 32)
885EMIT_LOCKED_BIN_OP(sub, 32)
886EMIT_LOCKED_BIN_OP(sbb, 32)
887EMIT_LOCKED_BIN_OP(or, 32)
888EMIT_LOCKED_BIN_OP(xor, 32)
889EMIT_LOCKED_BIN_OP(and, 32)
890
891EMIT_LOCKED_BIN_OP(add, 16)
892EMIT_LOCKED_BIN_OP(adc, 16)
893EMIT_LOCKED_BIN_OP(sub, 16)
894EMIT_LOCKED_BIN_OP(sbb, 16)
895EMIT_LOCKED_BIN_OP(or, 16)
896EMIT_LOCKED_BIN_OP(xor, 16)
897EMIT_LOCKED_BIN_OP(and, 16)
898
899EMIT_LOCKED_BIN_OP(add, 8)
900EMIT_LOCKED_BIN_OP(adc, 8)
901EMIT_LOCKED_BIN_OP(sub, 8)
902EMIT_LOCKED_BIN_OP(sbb, 8)
903EMIT_LOCKED_BIN_OP(or, 8)
904EMIT_LOCKED_BIN_OP(xor, 8)
905EMIT_LOCKED_BIN_OP(and, 8)
906# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
907
908
909/*
910 * Bit operations (same signature as above).
911 */
912
913/*
914 * BT
915 */
916
917IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
918{
919 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
920 not modified by either AMD (3990x) or Intel (i9-9980HK). */
921 Assert(uSrc < 64);
922 uint64_t uDst = *puDst;
923 if (uDst & RT_BIT_64(uSrc))
924 *pfEFlags |= X86_EFL_CF;
925 else
926 *pfEFlags &= ~X86_EFL_CF;
927}
928
929# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
930
931IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
932{
933 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
934 not modified by either AMD (3990x) or Intel (i9-9980HK). */
935 Assert(uSrc < 32);
936 uint32_t uDst = *puDst;
937 if (uDst & RT_BIT_32(uSrc))
938 *pfEFlags |= X86_EFL_CF;
939 else
940 *pfEFlags &= ~X86_EFL_CF;
941}
942
943IEM_DECL_IMPL_DEF(void, iemAImpl_bt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
944{
945 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
946 not modified by either AMD (3990x) or Intel (i9-9980HK). */
947 Assert(uSrc < 16);
948 uint16_t uDst = *puDst;
949 if (uDst & RT_BIT_32(uSrc))
950 *pfEFlags |= X86_EFL_CF;
951 else
952 *pfEFlags &= ~X86_EFL_CF;
953}
954
955# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
956
957/*
958 * BTC
959 */
960
961IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
962{
963 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
964 not modified by either AMD (3990x) or Intel (i9-9980HK). */
965 Assert(uSrc < 64);
966 uint64_t fMask = RT_BIT_64(uSrc);
967 uint64_t uDst = *puDst;
968 if (uDst & fMask)
969 {
970 uDst &= ~fMask;
971 *puDst = uDst;
972 *pfEFlags |= X86_EFL_CF;
973 }
974 else
975 {
976 uDst |= fMask;
977 *puDst = uDst;
978 *pfEFlags &= ~X86_EFL_CF;
979 }
980}
981
982# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
983
984IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
985{
986 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
987 not modified by either AMD (3990x) or Intel (i9-9980HK). */
988 Assert(uSrc < 32);
989 uint32_t fMask = RT_BIT_32(uSrc);
990 uint32_t uDst = *puDst;
991 if (uDst & fMask)
992 {
993 uDst &= ~fMask;
994 *puDst = uDst;
995 *pfEFlags |= X86_EFL_CF;
996 }
997 else
998 {
999 uDst |= fMask;
1000 *puDst = uDst;
1001 *pfEFlags &= ~X86_EFL_CF;
1002 }
1003}
1004
1005
1006IEM_DECL_IMPL_DEF(void, iemAImpl_btc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1007{
1008 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. However, it seems they're
1009 not modified by either AMD (3990x) or Intel (i9-9980HK). */
1010 Assert(uSrc < 16);
1011 uint16_t fMask = RT_BIT_32(uSrc);
1012 uint16_t uDst = *puDst;
1013 if (uDst & fMask)
1014 {
1015 uDst &= ~fMask;
1016 *puDst = uDst;
1017 *pfEFlags |= X86_EFL_CF;
1018 }
1019 else
1020 {
1021 uDst |= fMask;
1022 *puDst = uDst;
1023 *pfEFlags &= ~X86_EFL_CF;
1024 }
1025}
1026
1027# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1028
1029/*
1030 * BTR
1031 */
1032
1033IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1034{
1035 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1036 logical operation (AND/OR/whatever). */
1037 Assert(uSrc < 64);
1038 uint64_t fMask = RT_BIT_64(uSrc);
1039 uint64_t uDst = *puDst;
1040 if (uDst & fMask)
1041 {
1042 uDst &= ~fMask;
1043 *puDst = uDst;
1044 *pfEFlags |= X86_EFL_CF;
1045 }
1046 else
1047 *pfEFlags &= ~X86_EFL_CF;
1048}
1049
1050# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1051
1052IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1053{
1054 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1055 logical operation (AND/OR/whatever). */
1056 Assert(uSrc < 32);
1057 uint32_t fMask = RT_BIT_32(uSrc);
1058 uint32_t uDst = *puDst;
1059 if (uDst & fMask)
1060 {
1061 uDst &= ~fMask;
1062 *puDst = uDst;
1063 *pfEFlags |= X86_EFL_CF;
1064 }
1065 else
1066 *pfEFlags &= ~X86_EFL_CF;
1067}
1068
1069
1070IEM_DECL_IMPL_DEF(void, iemAImpl_btr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1071{
1072 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1073 logical operation (AND/OR/whatever). */
1074 Assert(uSrc < 16);
1075 uint16_t fMask = RT_BIT_32(uSrc);
1076 uint16_t uDst = *puDst;
1077 if (uDst & fMask)
1078 {
1079 uDst &= ~fMask;
1080 *puDst = uDst;
1081 *pfEFlags |= X86_EFL_CF;
1082 }
1083 else
1084 *pfEFlags &= ~X86_EFL_CF;
1085}
1086
1087# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1088
1089/*
1090 * BTS
1091 */
1092
1093IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1094{
1095 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1096 logical operation (AND/OR/whatever). */
1097 Assert(uSrc < 64);
1098 uint64_t fMask = RT_BIT_64(uSrc);
1099 uint64_t uDst = *puDst;
1100 if (uDst & fMask)
1101 *pfEFlags |= X86_EFL_CF;
1102 else
1103 {
1104 uDst |= fMask;
1105 *puDst = uDst;
1106 *pfEFlags &= ~X86_EFL_CF;
1107 }
1108}
1109
1110# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1111
1112IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1113{
1114 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1115 logical operation (AND/OR/whatever). */
1116 Assert(uSrc < 32);
1117 uint32_t fMask = RT_BIT_32(uSrc);
1118 uint32_t uDst = *puDst;
1119 if (uDst & fMask)
1120 *pfEFlags |= X86_EFL_CF;
1121 else
1122 {
1123 uDst |= fMask;
1124 *puDst = uDst;
1125 *pfEFlags &= ~X86_EFL_CF;
1126 }
1127}
1128
1129
1130IEM_DECL_IMPL_DEF(void, iemAImpl_bts_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1131{
1132 /* Note! "undefined" flags: OF, SF, ZF, AF, PF. We set them as after an
1133 logical operation (AND/OR/whatever). */
1134 Assert(uSrc < 16);
1135 uint16_t fMask = RT_BIT_32(uSrc);
1136 uint32_t uDst = *puDst;
1137 if (uDst & fMask)
1138 *pfEFlags |= X86_EFL_CF;
1139 else
1140 {
1141 uDst |= fMask;
1142 *puDst = uDst;
1143 *pfEFlags &= ~X86_EFL_CF;
1144 }
1145}
1146
1147# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1148
1149
1150EMIT_LOCKED_BIN_OP(btc, 64)
1151EMIT_LOCKED_BIN_OP(btr, 64)
1152EMIT_LOCKED_BIN_OP(bts, 64)
1153# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1154EMIT_LOCKED_BIN_OP(btc, 32)
1155EMIT_LOCKED_BIN_OP(btr, 32)
1156EMIT_LOCKED_BIN_OP(bts, 32)
1157
1158EMIT_LOCKED_BIN_OP(btc, 16)
1159EMIT_LOCKED_BIN_OP(btr, 16)
1160EMIT_LOCKED_BIN_OP(bts, 16)
1161# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1162
1163
1164/*
1165 * Helpers for BSR and BSF.
1166 *
1167 * Note! "undefined" flags: OF, SF, AF, PF, CF.
1168 * Intel behavior modelled on 10980xe, AMD on 3990X. Other marchs may
1169 * produce different result (see https://www.sandpile.org/x86/flags.htm),
1170 * but we restrict ourselves to emulating these recent marchs.
1171 */
1172#define SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlag, a_iBit) do { \
1173 unsigned iBit = (a_iBit); \
1174 uint32_t fEfl = *pfEFlags & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
1175 if (iBit) \
1176 { \
1177 *puDst = --iBit; \
1178 fEfl |= g_afParity[iBit]; \
1179 } \
1180 else \
1181 fEfl |= X86_EFL_ZF | X86_EFL_PF; \
1182 *pfEFlags = fEfl; \
1183 } while (0)
1184#define SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlag, a_iBit) do { \
1185 unsigned const iBit = (a_iBit); \
1186 if (iBit) \
1187 { \
1188 *puDst = iBit - 1; \
1189 *pfEFlags &= ~X86_EFL_ZF; \
1190 } \
1191 else \
1192 *pfEFlags |= X86_EFL_ZF; \
1193 } while (0)
1194
1195
1196/*
1197 * BSF - first (least significant) bit set
1198 */
1199IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1200{
1201 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
1202}
1203
1204IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1205{
1206 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
1207}
1208
1209IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1210{
1211 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
1212}
1213
1214# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1215
1216IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1217{
1218 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
1219}
1220
1221IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1222{
1223 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
1224}
1225
1226IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1227{
1228 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
1229}
1230
1231
1232IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1233{
1234 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
1235}
1236
1237IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1238{
1239 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
1240}
1241
1242IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1243{
1244 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
1245}
1246
1247# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1248
1249
1250/*
1251 * BSR - last (most significant) bit set
1252 */
1253IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1254{
1255 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
1256}
1257
1258IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1259{
1260 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
1261}
1262
1263IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
1264{
1265 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
1266}
1267
1268# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1269
1270IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1271{
1272 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
1273}
1274
1275IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1276{
1277 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
1278}
1279
1280IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
1281{
1282 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
1283}
1284
1285
1286IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1287{
1288 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
1289}
1290
1291IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1292{
1293 SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
1294}
1295
1296IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
1297{
1298 SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
1299}
1300
1301# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1302
1303
1304/*
1305 * XCHG
1306 */
1307
1308IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *puMem, uint64_t *puReg))
1309{
1310#if ARCH_BITS >= 64
1311 *puReg = ASMAtomicXchgU64(puMem, *puReg);
1312#else
1313 uint64_t uOldMem = *puMem;
1314 while (!ASMAtomicCmpXchgExU64(puMem, *puReg, uOldMem, &uOldMem))
1315 ASMNopPause();
1316 *puReg = uOldMem;
1317#endif
1318}
1319
1320# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1321
1322IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *puMem, uint32_t *puReg))
1323{
1324 *puReg = ASMAtomicXchgU32(puMem, *puReg);
1325}
1326
1327
1328IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *puMem, uint16_t *puReg))
1329{
1330 *puReg = ASMAtomicXchgU16(puMem, *puReg);
1331}
1332
1333
1334IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked,(uint8_t *puMem, uint8_t *puReg))
1335{
1336 *puReg = ASMAtomicXchgU8(puMem, *puReg);
1337}
1338
1339# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1340
1341
1342/* Unlocked variants for fDisregardLock mode: */
1343
1344IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *puMem, uint64_t *puReg))
1345{
1346 uint64_t const uOld = *puMem;
1347 *puMem = *puReg;
1348 *puReg = uOld;
1349}
1350
1351# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1352
1353IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *puMem, uint32_t *puReg))
1354{
1355 uint32_t const uOld = *puMem;
1356 *puMem = *puReg;
1357 *puReg = uOld;
1358}
1359
1360
1361IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *puMem, uint16_t *puReg))
1362{
1363 uint16_t const uOld = *puMem;
1364 *puMem = *puReg;
1365 *puReg = uOld;
1366}
1367
1368
1369IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked,(uint8_t *puMem, uint8_t *puReg))
1370{
1371 uint8_t const uOld = *puMem;
1372 *puMem = *puReg;
1373 *puReg = uOld;
1374}
1375
1376# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1377
1378
1379/*
1380 * XADD and LOCK XADD.
1381 */
1382#define EMIT_XADD(a_cBitsWidth, a_Type) \
1383IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth,(a_Type *puDst, a_Type *puReg, uint32_t *pfEFlags)) \
1384{ \
1385 a_Type uDst = *puDst; \
1386 a_Type uResult = uDst; \
1387 iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, pfEFlags); \
1388 *puDst = uResult; \
1389 *puReg = uDst; \
1390} \
1391\
1392IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u ## a_cBitsWidth ## _locked,(a_Type *puDst, a_Type *puReg, uint32_t *pfEFlags)) \
1393{ \
1394 a_Type uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
1395 a_Type uResult; \
1396 uint32_t fEflTmp; \
1397 do \
1398 { \
1399 uResult = uOld; \
1400 fEflTmp = *pfEFlags; \
1401 iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, &fEflTmp); \
1402 } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uResult, uOld, &uOld)); \
1403 *puReg = uOld; \
1404 *pfEFlags = fEflTmp; \
1405}
1406EMIT_XADD(64, uint64_t)
1407# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1408EMIT_XADD(32, uint32_t)
1409EMIT_XADD(16, uint16_t)
1410EMIT_XADD(8, uint8_t)
1411# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1412
1413#endif
1414
1415/*
1416 * CMPXCHG, CMPXCHG8B, CMPXCHG16B
1417 *
1418 * Note! We don't have non-locking/atomic cmpxchg primitives, so all cmpxchg
1419 * instructions are emulated as locked.
1420 */
1421#if defined(IEM_WITHOUT_ASSEMBLY)
1422
1423IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1424{
1425 uint8_t uOld = *puAl;
1426 if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
1427 Assert(*puAl == uOld);
1428 iemAImpl_cmp_u8(&uOld, *puAl, pEFlags);
1429}
1430
1431
1432IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1433{
1434 uint16_t uOld = *puAx;
1435 if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
1436 Assert(*puAx == uOld);
1437 iemAImpl_cmp_u16(&uOld, *puAx, pEFlags);
1438}
1439
1440
1441IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1442{
1443 uint32_t uOld = *puEax;
1444 if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
1445 Assert(*puEax == uOld);
1446 iemAImpl_cmp_u32(&uOld, *puEax, pEFlags);
1447}
1448
1449
1450# if ARCH_BITS == 32
1451IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
1452# else
1453IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1454# endif
1455{
1456# if ARCH_BITS == 32
1457 uint64_t const uSrcReg = *puSrcReg;
1458# endif
1459 uint64_t uOld = *puRax;
1460 if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
1461 Assert(*puRax == uOld);
1462 iemAImpl_cmp_u64(&uOld, *puRax, pEFlags);
1463}
1464
1465
1466IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1467 uint32_t *pEFlags))
1468{
1469 uint64_t const uNew = pu64EbxEcx->u;
1470 uint64_t const uOld = pu64EaxEdx->u;
1471 if (ASMAtomicCmpXchgExU64(pu64Dst, uNew, uOld, &pu64EaxEdx->u))
1472 {
1473 Assert(pu64EaxEdx->u == uOld);
1474 *pEFlags |= X86_EFL_ZF;
1475 }
1476 else
1477 *pEFlags &= ~X86_EFL_ZF;
1478}
1479
1480
1481# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_ARM64)
1482IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1483 uint32_t *pEFlags))
1484{
1485# ifdef VBOX_STRICT
1486 RTUINT128U const uOld = *pu128RaxRdx;
1487# endif
1488# if defined(RT_ARCH_AMD64)
1489 if (ASMAtomicCmpXchgU128v2(&pu128Dst->u, pu128RbxRcx->s.Hi, pu128RbxRcx->s.Lo, pu128RaxRdx->s.Hi, pu128RaxRdx->s.Lo,
1490 &pu128RaxRdx->u))
1491# else
1492 if (ASMAtomicCmpXchgU128(&pu128Dst->u, pu128RbxRcx->u, pu128RaxRdx->u, &pu128RaxRdx->u))
1493# endif
1494 {
1495 Assert(pu128RaxRdx->s.Lo == uOld.s.Lo && pu128RaxRdx->s.Hi == uOld.s.Hi);
1496 *pEFlags |= X86_EFL_ZF;
1497 }
1498 else
1499 *pEFlags &= ~X86_EFL_ZF;
1500}
1501# endif
1502
1503#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1504
1505# if !defined(RT_ARCH_ARM64) /** @todo may need this for unaligned accesses... */
1506IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1507 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags))
1508{
1509 RTUINT128U u128Tmp = *pu128Dst;
1510 if ( u128Tmp.s.Lo == pu128RaxRdx->s.Lo
1511 && u128Tmp.s.Hi == pu128RaxRdx->s.Hi)
1512 {
1513 *pu128Dst = *pu128RbxRcx;
1514 *pEFlags |= X86_EFL_ZF;
1515 }
1516 else
1517 {
1518 *pu128RaxRdx = u128Tmp;
1519 *pEFlags &= ~X86_EFL_ZF;
1520 }
1521}
1522#endif /* !RT_ARCH_ARM64 */
1523
1524#if defined(IEM_WITHOUT_ASSEMBLY)
1525
1526/* Unlocked versions mapped to the locked ones: */
1527
1528IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags))
1529{
1530 iemAImpl_cmpxchg_u8_locked(pu8Dst, puAl, uSrcReg, pEFlags);
1531}
1532
1533
1534IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags))
1535{
1536 iemAImpl_cmpxchg_u16_locked(pu16Dst, puAx, uSrcReg, pEFlags);
1537}
1538
1539
1540IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags))
1541{
1542 iemAImpl_cmpxchg_u32_locked(pu32Dst, puEax, uSrcReg, pEFlags);
1543}
1544
1545
1546# if ARCH_BITS == 32
1547IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags))
1548{
1549 iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, puSrcReg, pEFlags);
1550}
1551# else
1552IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags))
1553{
1554 iemAImpl_cmpxchg_u64_locked(pu64Dst, puRax, uSrcReg, pEFlags);
1555}
1556# endif
1557
1558
1559IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx, uint32_t *pEFlags))
1560{
1561 iemAImpl_cmpxchg8b_locked(pu64Dst, pu64EaxEdx, pu64EbxEcx, pEFlags);
1562}
1563
1564
1565IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1566 uint32_t *pEFlags))
1567{
1568 iemAImpl_cmpxchg16b_locked(pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
1569}
1570
1571#endif /* defined(IEM_WITHOUT_ASSEMBLY) */
1572
1573#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
1574
1575/*
1576 * MUL, IMUL, DIV and IDIV helpers.
1577 *
1578 * - The U64 versions must use 128-bit intermediates, so we need to abstract the
1579 * division step so we can select between using C operators and
1580 * RTUInt128DivRem/RTUInt128MulU64ByU64.
1581 *
1582 * - The U8 versions work returns output in AL + AH instead of xDX + xAX, with the
1583 * IDIV/DIV taking all the input in AX too. This means we have to abstract some
1584 * input loads and the result storing.
1585 */
1586
1587DECLINLINE(void) RTUInt128DivRemByU64(PRTUINT128U pQuotient, PRTUINT128U pRemainder, PCRTUINT128U pDividend, uint64_t u64Divisor)
1588{
1589# ifdef __GNUC__ /* GCC maybe really annoying in function. */
1590 pQuotient->s.Lo = 0;
1591 pQuotient->s.Hi = 0;
1592# endif
1593 RTUINT128U Divisor;
1594 Divisor.s.Lo = u64Divisor;
1595 Divisor.s.Hi = 0;
1596 RTUInt128DivRem(pQuotient, pRemainder, pDividend, &Divisor);
1597}
1598
1599# define DIV_LOAD(a_Dividend) \
1600 a_Dividend.s.Lo = *puA, a_Dividend.s.Hi = *puD
1601# define DIV_LOAD_U8(a_Dividend) \
1602 a_Dividend.u = *puAX
1603
1604# define DIV_STORE(a_Quotient, a_uReminder) *puA = (a_Quotient), *puD = (a_uReminder)
1605# define DIV_STORE_U8(a_Quotient, a_uReminder) *puAX = (uint8_t)(a_Quotient) | ((uint16_t)(a_uReminder) << 8)
1606
1607# define MUL_LOAD_F1() *puA
1608# define MUL_LOAD_F1_U8() ((uint8_t)*puAX)
1609
1610# define MUL_STORE(a_Result) *puA = (a_Result).s.Lo, *puD = (a_Result).s.Hi
1611# define MUL_STORE_U8(a_Result) *puAX = a_Result.u
1612
1613# define MULDIV_NEG(a_Value, a_cBitsWidth2x) \
1614 (a_Value).u = UINT ## a_cBitsWidth2x ## _C(0) - (a_Value).u
1615# define MULDIV_NEG_U128(a_Value, a_cBitsWidth2x) \
1616 RTUInt128AssignNeg(&(a_Value))
1617
1618# define MULDIV_MUL(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1619 (a_Result).u = (uint ## a_cBitsWidth2x ## _t)(a_Factor1) * (a_Factor2)
1620# define MULDIV_MUL_U128(a_Result, a_Factor1, a_Factor2, a_cBitsWidth2x) \
1621 RTUInt128MulU64ByU64(&(a_Result), a_Factor1, a_Factor2);
1622
1623# define MULDIV_MODDIV(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1624 a_Quotient.u = (a_Dividend).u / (a_uDivisor), \
1625 a_Remainder.u = (a_Dividend).u % (a_uDivisor)
1626# define MULDIV_MODDIV_U128(a_Quotient, a_Remainder, a_Dividend, a_uDivisor) \
1627 RTUInt128DivRemByU64(&a_Quotient, &a_Remainder, &a_Dividend, a_uDivisor)
1628
1629
1630/*
1631 * MUL
1632 */
1633# define EMIT_MUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul, a_Suffix, a_fIntelFlags) \
1634IEM_DECL_IMPL_DEF(int, RT_CONCAT3(iemAImpl_mul_u,a_cBitsWidth,a_Suffix), a_Args) \
1635{ \
1636 RTUINT ## a_cBitsWidth2x ## U Result; \
1637 a_fnMul(Result, a_fnLoadF1(), uFactor, a_cBitsWidth2x); \
1638 a_fnStore(Result); \
1639 \
1640 /* Calc EFLAGS: */ \
1641 uint32_t fEfl = *pfEFlags; \
1642 if (a_fIntelFlags) \
1643 { /* Intel: 6700K and 10980XE behavior */ \
1644 fEfl &= ~(X86_EFL_SF | X86_EFL_CF | X86_EFL_OF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF); \
1645 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1646 fEfl |= X86_EFL_SF; \
1647 fEfl |= g_afParity[Result.s.Lo & 0xff]; \
1648 if (Result.s.Hi != 0) \
1649 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1650 } \
1651 else \
1652 { /* AMD: 3990X */ \
1653 if (Result.s.Hi != 0) \
1654 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1655 else \
1656 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
1657 } \
1658 *pfEFlags = fEfl; \
1659 return 0; \
1660} \
1661
1662# define EMIT_MUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul) \
1663 EMIT_MUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul, RT_NOTHING, 1) \
1664 EMIT_MUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul, _intel, 1) \
1665 EMIT_MUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnMul, _amd, 0) \
1666
1667# ifndef DOXYGEN_RUNNING /* this totally confuses doxygen for some reason */
1668EMIT_MUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
1669 MUL_LOAD_F1, MUL_STORE, MULDIV_MUL_U128)
1670# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1671EMIT_MUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
1672 MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1673EMIT_MUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor, uint32_t *pfEFlags), (puA, puD, uFactor, pfEFlags),
1674 MUL_LOAD_F1, MUL_STORE, MULDIV_MUL)
1675EMIT_MUL(8, 16, (uint16_t *puAX, uint8_t uFactor, uint32_t *pfEFlags), (puAX, uFactor, pfEFlags),
1676 MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_MUL)
1677# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1678# endif /* !DOXYGEN_RUNNING */
1679
1680
1681/*
1682 * IMUL
1683 *
1684 * The SF, ZF, AF and PF flags are "undefined". AMD (3990x) leaves these
1685 * flags as is. Whereas Intel skylake (6700K and 10980X (Cascade Lake)) always
1686 * clear AF and ZF and calculates SF and PF as per the lower half of the result.
1687 */
1688# define EMIT_IMUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul, \
1689 a_Suffix, a_fIntelFlags) \
1690IEM_DECL_IMPL_DEF(int, RT_CONCAT3(iemAImpl_imul_u,a_cBitsWidth,a_Suffix),a_Args) \
1691{ \
1692 RTUINT ## a_cBitsWidth2x ## U Result; \
1693 uint32_t fEfl = *pfEFlags & ~(X86_EFL_CF | X86_EFL_OF); \
1694 \
1695 uint ## a_cBitsWidth ## _t const uFactor1 = a_fnLoadF1(); \
1696 if (!(uFactor1 & RT_BIT_64(a_cBitsWidth - 1))) \
1697 { \
1698 if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1699 { \
1700 a_fnMul(Result, uFactor1, uFactor2, a_cBitsWidth2x); \
1701 if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1702 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1703 } \
1704 else \
1705 { \
1706 uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
1707 a_fnMul(Result, uFactor1, uPositiveFactor2, a_cBitsWidth2x); \
1708 if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1709 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1710 a_fnNeg(Result, a_cBitsWidth2x); \
1711 } \
1712 } \
1713 else \
1714 { \
1715 if (!(uFactor2 & RT_BIT_64(a_cBitsWidth - 1))) \
1716 { \
1717 uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
1718 a_fnMul(Result, uPositiveFactor1, uFactor2, a_cBitsWidth2x); \
1719 if (Result.s.Hi != 0 || Result.s.Lo > RT_BIT_64(a_cBitsWidth - 1)) \
1720 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1721 a_fnNeg(Result, a_cBitsWidth2x); \
1722 } \
1723 else \
1724 { \
1725 uint ## a_cBitsWidth ## _t const uPositiveFactor1 = UINT ## a_cBitsWidth ## _C(0) - uFactor1; \
1726 uint ## a_cBitsWidth ## _t const uPositiveFactor2 = UINT ## a_cBitsWidth ## _C(0) - uFactor2; \
1727 a_fnMul(Result, uPositiveFactor1, uPositiveFactor2, a_cBitsWidth2x); \
1728 if (Result.s.Hi != 0 || Result.s.Lo >= RT_BIT_64(a_cBitsWidth - 1)) \
1729 fEfl |= X86_EFL_CF | X86_EFL_OF; \
1730 } \
1731 } \
1732 a_fnStore(Result); \
1733 \
1734 if (a_fIntelFlags) \
1735 { \
1736 fEfl &= ~(X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_PF); \
1737 if (Result.s.Lo & RT_BIT_64(a_cBitsWidth - 1)) \
1738 fEfl |= X86_EFL_SF; \
1739 fEfl |= g_afParity[Result.s.Lo & 0xff]; \
1740 } \
1741 *pfEFlags = fEfl; \
1742 return 0; \
1743}
1744# define EMIT_IMUL(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul) \
1745 EMIT_IMUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul, RT_NOTHING, 1) \
1746 EMIT_IMUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul, _intel, 1) \
1747 EMIT_IMUL_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoadF1, a_fnStore, a_fnNeg, a_fnMul, _amd, 0)
1748
1749# ifndef DOXYGEN_RUNNING /* this totally confuses doxygen for some reason */
1750EMIT_IMUL(64, 128, (uint64_t *puA, uint64_t *puD, uint64_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
1751 MUL_LOAD_F1, MUL_STORE, MULDIV_NEG_U128, MULDIV_MUL_U128)
1752# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1753EMIT_IMUL(32, 64, (uint32_t *puA, uint32_t *puD, uint32_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
1754 MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1755EMIT_IMUL(16, 32, (uint16_t *puA, uint16_t *puD, uint16_t uFactor2, uint32_t *pfEFlags), (puA, puD, uFactor2, pfEFlags),
1756 MUL_LOAD_F1, MUL_STORE, MULDIV_NEG, MULDIV_MUL)
1757EMIT_IMUL(8, 16, (uint16_t *puAX, uint8_t uFactor2, uint32_t *pfEFlags), (puAX, uFactor2, pfEFlags),
1758 MUL_LOAD_F1_U8, MUL_STORE_U8, MULDIV_NEG, MULDIV_MUL)
1759# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1760# endif /* !DOXYGEN_RUNNING */
1761
1762
1763/*
1764 * IMUL with two operands are mapped onto the three operand variant, ignoring
1765 * the high part of the product.
1766 */
1767# define EMIT_IMUL_TWO(a_cBits, a_uType) \
1768IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
1769{ \
1770 a_uType uIgn; \
1771 iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, pfEFlags); \
1772} \
1773\
1774IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _intel,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
1775{ \
1776 a_uType uIgn; \
1777 iemAImpl_imul_u ## a_cBits ## _intel(puDst, &uIgn, uSrc, pfEFlags); \
1778} \
1779\
1780IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _amd,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
1781{ \
1782 a_uType uIgn; \
1783 iemAImpl_imul_u ## a_cBits ## _amd(puDst, &uIgn, uSrc, pfEFlags); \
1784}
1785
1786EMIT_IMUL_TWO(64, uint64_t)
1787# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1788EMIT_IMUL_TWO(32, uint32_t)
1789EMIT_IMUL_TWO(16, uint16_t)
1790# endif
1791
1792
1793/*
1794 * DIV
1795 */
1796# define EMIT_DIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem, \
1797 a_Suffix, a_fIntelFlags) \
1798IEM_DECL_IMPL_DEF(int, RT_CONCAT3(iemAImpl_div_u,a_cBitsWidth,a_Suffix),a_Args) \
1799{ \
1800 RTUINT ## a_cBitsWidth2x ## U Dividend; \
1801 a_fnLoad(Dividend); \
1802 if ( uDivisor != 0 \
1803 && Dividend.s.Hi < uDivisor) \
1804 { \
1805 RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1806 a_fnDivRem(Quotient, Remainder, Dividend, uDivisor); \
1807 a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1808 \
1809 /* Calc EFLAGS: Intel 6700K and 10980XE leaves them alone. AMD 3990X sets AF and clears PF, ZF and SF. */ \
1810 if (!a_fIntelFlags) \
1811 *pfEFlags = (*pfEFlags & ~(X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF)) | X86_EFL_AF; \
1812 return 0; \
1813 } \
1814 /* #DE */ \
1815 return -1; \
1816}
1817# define EMIT_DIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem) \
1818 EMIT_DIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem, RT_NOTHING, 1) \
1819 EMIT_DIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem, _intel, 1) \
1820 EMIT_DIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnDivRem, _amd, 0)
1821
1822# ifndef DOXYGEN_RUNNING /* this totally confuses doxygen for some reason */
1823EMIT_DIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1824 DIV_LOAD, DIV_STORE, MULDIV_MODDIV_U128)
1825# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1826EMIT_DIV(32,64, (uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1827 DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1828EMIT_DIV(16,32, (uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1829 DIV_LOAD, DIV_STORE, MULDIV_MODDIV)
1830EMIT_DIV(8,16, (uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), (puAX, uDivisor, pfEFlags),
1831 DIV_LOAD_U8, DIV_STORE_U8, MULDIV_MODDIV)
1832# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1833# endif /* !DOXYGEN_RUNNING */
1834
1835
1836/*
1837 * IDIV
1838 *
1839 * EFLAGS are ignored and left as-is by Intel 6700K and 10980XE. AMD 3990X will
1840 * set AF and clear PF, ZF and SF just like it does for DIV.
1841 *
1842 */
1843# define EMIT_IDIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem, \
1844 a_Suffix, a_fIntelFlags) \
1845IEM_DECL_IMPL_DEF(int, RT_CONCAT3(iemAImpl_idiv_u,a_cBitsWidth,a_Suffix),a_Args) \
1846{ \
1847 /* Note! Skylake leaves all flags alone. */ \
1848 \
1849 /** @todo overflow checks */ \
1850 if (uDivisor != 0) \
1851 { \
1852 /* \
1853 * Convert to unsigned division. \
1854 */ \
1855 RTUINT ## a_cBitsWidth2x ## U Dividend; \
1856 a_fnLoad(Dividend); \
1857 bool const fSignedDividend = RT_BOOL(Dividend.s.Hi & RT_BIT_64(a_cBitsWidth - 1)); \
1858 if (fSignedDividend) \
1859 a_fnNeg(Dividend, a_cBitsWidth2x); \
1860 \
1861 uint ## a_cBitsWidth ## _t uDivisorPositive; \
1862 if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
1863 uDivisorPositive = uDivisor; \
1864 else \
1865 uDivisorPositive = UINT ## a_cBitsWidth ## _C(0) - uDivisor; \
1866 \
1867 RTUINT ## a_cBitsWidth2x ## U Remainder, Quotient; \
1868 a_fnDivRem(Quotient, Remainder, Dividend, uDivisorPositive); \
1869 \
1870 /* \
1871 * Setup the result, checking for overflows. \
1872 */ \
1873 if (!(uDivisor & RT_BIT_64(a_cBitsWidth - 1))) \
1874 { \
1875 if (!fSignedDividend) \
1876 { \
1877 /* Positive divisor, positive dividend => result positive. */ \
1878 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1879 { \
1880 a_fnStore(Quotient.s.Lo, Remainder.s.Lo); \
1881 if (!a_fIntelFlags) \
1882 *pfEFlags = (*pfEFlags & ~(X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF)) | X86_EFL_AF; \
1883 return 0; \
1884 } \
1885 } \
1886 else \
1887 { \
1888 /* Positive divisor, negative dividend => result negative. */ \
1889 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1890 { \
1891 a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1892 if (!a_fIntelFlags) \
1893 *pfEFlags = (*pfEFlags & ~(X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF)) | X86_EFL_AF; \
1894 return 0; \
1895 } \
1896 } \
1897 } \
1898 else \
1899 { \
1900 if (!fSignedDividend) \
1901 { \
1902 /* Negative divisor, positive dividend => negative quotient, positive remainder. */ \
1903 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= RT_BIT_64(a_cBitsWidth - 1)) \
1904 { \
1905 a_fnStore(UINT ## a_cBitsWidth ## _C(0) - Quotient.s.Lo, Remainder.s.Lo); \
1906 if (!a_fIntelFlags) \
1907 *pfEFlags = (*pfEFlags & ~(X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF)) | X86_EFL_AF; \
1908 return 0; \
1909 } \
1910 } \
1911 else \
1912 { \
1913 /* Negative divisor, negative dividend => positive quotient, negative remainder. */ \
1914 if (Quotient.s.Hi == 0 && Quotient.s.Lo <= (uint ## a_cBitsWidth ## _t)INT ## a_cBitsWidth ## _MAX) \
1915 { \
1916 a_fnStore(Quotient.s.Lo, UINT ## a_cBitsWidth ## _C(0) - Remainder.s.Lo); \
1917 if (!a_fIntelFlags) \
1918 *pfEFlags = (*pfEFlags & ~(X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF)) | X86_EFL_AF; \
1919 return 0; \
1920 } \
1921 } \
1922 } \
1923 } \
1924 /* #DE */ \
1925 return -1; \
1926}
1927# define EMIT_IDIV(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem) \
1928 EMIT_IDIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem, RT_NOTHING, 1) \
1929 EMIT_IDIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem, _intel, 1) \
1930 EMIT_IDIV_INNER(a_cBitsWidth, a_cBitsWidth2x, a_Args, a_CallArgs, a_fnLoad, a_fnStore, a_fnNeg, a_fnDivRem, _amd, 0)
1931
1932# ifndef DOXYGEN_RUNNING /* this totally confuses doxygen for some reason */
1933EMIT_IDIV(64,128,(uint64_t *puA, uint64_t *puD, uint64_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1934 DIV_LOAD, DIV_STORE, MULDIV_NEG_U128, MULDIV_MODDIV_U128)
1935# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1936EMIT_IDIV(32,64,(uint32_t *puA, uint32_t *puD, uint32_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1937 DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1938EMIT_IDIV(16,32,(uint16_t *puA, uint16_t *puD, uint16_t uDivisor, uint32_t *pfEFlags), (puA, puD, uDivisor, pfEFlags),
1939 DIV_LOAD, DIV_STORE, MULDIV_NEG, MULDIV_MODDIV)
1940EMIT_IDIV(8,16,(uint16_t *puAX, uint8_t uDivisor, uint32_t *pfEFlags), (puAX, uDivisor, pfEFlags),
1941 DIV_LOAD_U8, DIV_STORE_U8, MULDIV_NEG, MULDIV_MODDIV)
1942# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
1943# endif /* !DOXYGEN_RUNNING */
1944
1945
1946/*********************************************************************************************************************************
1947* Unary operations. *
1948*********************************************************************************************************************************/
1949
1950/** @def IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC
1951 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an INC or DEC instruction.
1952 *
1953 * CF is NOT modified for hysterical raisins (allegedly for carrying and
1954 * borrowing in arithmetic loops on intel 8008).
1955 *
1956 * @returns Status bits.
1957 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
1958 * @param a_uResult Unsigned result value.
1959 * @param a_uDst The original destination value (for AF calc).
1960 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
1961 * @param a_OfMethod 0 for INC-style, 1 for DEC-style.
1962 */
1963#define IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth, a_OfMethod) \
1964 do { \
1965 uint32_t fEflTmp = *(a_pfEFlags); \
1966 fEflTmp &= ~X86_EFL_STATUS_BITS | X86_EFL_CF; \
1967 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
1968 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
1969 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
1970 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
1971 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth(a_OfMethod == 0 ? (((a_uDst) ^ RT_BIT_64(a_cBitsWidth - 1)) & (a_uResult)) \
1972 : ((a_uDst) & ((a_uResult) ^ RT_BIT_64(a_cBitsWidth - 1))) ); \
1973 *(a_pfEFlags) = fEflTmp; \
1974 } while (0)
1975
1976/*
1977 * INC
1978 */
1979
1980IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u64,(uint64_t *puDst, uint32_t *pfEFlags))
1981{
1982 uint64_t uDst = *puDst;
1983 uint64_t uResult = uDst + 1;
1984 *puDst = uResult;
1985 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 0 /*INC*/);
1986}
1987
1988# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
1989
1990IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u32,(uint32_t *puDst, uint32_t *pfEFlags))
1991{
1992 uint32_t uDst = *puDst;
1993 uint32_t uResult = uDst + 1;
1994 *puDst = uResult;
1995 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 0 /*INC*/);
1996}
1997
1998
1999IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2000{
2001 uint16_t uDst = *puDst;
2002 uint16_t uResult = uDst + 1;
2003 *puDst = uResult;
2004 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 0 /*INC*/);
2005}
2006
2007IEM_DECL_IMPL_DEF(void, iemAImpl_inc_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2008{
2009 uint8_t uDst = *puDst;
2010 uint8_t uResult = uDst + 1;
2011 *puDst = uResult;
2012 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 0 /*INC*/);
2013}
2014
2015# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2016
2017
2018/*
2019 * DEC
2020 */
2021
2022IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u64,(uint64_t *puDst, uint32_t *pfEFlags))
2023{
2024 uint64_t uDst = *puDst;
2025 uint64_t uResult = uDst - 1;
2026 *puDst = uResult;
2027 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 64, 1 /*INC*/);
2028}
2029
2030# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2031
2032IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2033{
2034 uint32_t uDst = *puDst;
2035 uint32_t uResult = uDst - 1;
2036 *puDst = uResult;
2037 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 32, 1 /*INC*/);
2038}
2039
2040
2041IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2042{
2043 uint16_t uDst = *puDst;
2044 uint16_t uResult = uDst - 1;
2045 *puDst = uResult;
2046 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 16, 1 /*INC*/);
2047}
2048
2049
2050IEM_DECL_IMPL_DEF(void, iemAImpl_dec_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2051{
2052 uint8_t uDst = *puDst;
2053 uint8_t uResult = uDst - 1;
2054 *puDst = uResult;
2055 IEM_EFL_UPDATE_STATUS_BITS_FOR_INC_DEC(pfEFlags, uResult, uDst, 8, 1 /*INC*/);
2056}
2057
2058# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2059
2060
2061/*
2062 * NOT
2063 */
2064
2065IEM_DECL_IMPL_DEF(void, iemAImpl_not_u64,(uint64_t *puDst, uint32_t *pfEFlags))
2066{
2067 uint64_t uDst = *puDst;
2068 uint64_t uResult = ~uDst;
2069 *puDst = uResult;
2070 /* EFLAGS are not modified. */
2071 RT_NOREF_PV(pfEFlags);
2072}
2073
2074# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2075
2076IEM_DECL_IMPL_DEF(void, iemAImpl_not_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2077{
2078 uint32_t uDst = *puDst;
2079 uint32_t uResult = ~uDst;
2080 *puDst = uResult;
2081 /* EFLAGS are not modified. */
2082 RT_NOREF_PV(pfEFlags);
2083}
2084
2085IEM_DECL_IMPL_DEF(void, iemAImpl_not_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2086{
2087 uint16_t uDst = *puDst;
2088 uint16_t uResult = ~uDst;
2089 *puDst = uResult;
2090 /* EFLAGS are not modified. */
2091 RT_NOREF_PV(pfEFlags);
2092}
2093
2094IEM_DECL_IMPL_DEF(void, iemAImpl_not_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2095{
2096 uint8_t uDst = *puDst;
2097 uint8_t uResult = ~uDst;
2098 *puDst = uResult;
2099 /* EFLAGS are not modified. */
2100 RT_NOREF_PV(pfEFlags);
2101}
2102
2103# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2104
2105
2106/*
2107 * NEG
2108 */
2109
2110/**
2111 * Updates the status bits (CF, PF, AF, ZF, SF, and OF) for an NEG instruction.
2112 *
2113 * @returns Status bits.
2114 * @param a_pfEFlags Pointer to the 32-bit EFLAGS value to update.
2115 * @param a_uResult Unsigned result value.
2116 * @param a_uDst The original destination value (for AF calc).
2117 * @param a_cBitsWidth The width of the result (8, 16, 32, 64).
2118 */
2119#define IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(a_pfEFlags, a_uResult, a_uDst, a_cBitsWidth) \
2120 do { \
2121 uint32_t fEflTmp = *(a_pfEFlags); \
2122 fEflTmp &= ~X86_EFL_STATUS_BITS & ~X86_EFL_CF; \
2123 fEflTmp |= ((a_uDst) != 0) << X86_EFL_CF_BIT; \
2124 fEflTmp |= g_afParity[(a_uResult) & 0xff]; \
2125 fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
2126 fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
2127 fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
2128 fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth((a_uDst) & (a_uResult)); \
2129 *(a_pfEFlags) = fEflTmp; \
2130 } while (0)
2131
2132IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u64,(uint64_t *puDst, uint32_t *pfEFlags))
2133{
2134 uint64_t uDst = *puDst;
2135 uint64_t uResult = (uint64_t)0 - uDst;
2136 *puDst = uResult;
2137 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 64);
2138}
2139
2140# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2141
2142IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u32,(uint32_t *puDst, uint32_t *pfEFlags))
2143{
2144 uint32_t uDst = *puDst;
2145 uint32_t uResult = (uint32_t)0 - uDst;
2146 *puDst = uResult;
2147 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 32);
2148}
2149
2150
2151IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u16,(uint16_t *puDst, uint32_t *pfEFlags))
2152{
2153 uint16_t uDst = *puDst;
2154 uint16_t uResult = (uint16_t)0 - uDst;
2155 *puDst = uResult;
2156 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 16);
2157}
2158
2159
2160IEM_DECL_IMPL_DEF(void, iemAImpl_neg_u8,(uint8_t *puDst, uint32_t *pfEFlags))
2161{
2162 uint8_t uDst = *puDst;
2163 uint8_t uResult = (uint8_t)0 - uDst;
2164 *puDst = uResult;
2165 IEM_EFL_UPDATE_STATUS_BITS_FOR_NEG(pfEFlags, uResult, uDst, 8);
2166}
2167
2168# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2169
2170/*
2171 * Locked variants.
2172 */
2173
2174/** Emit a function for doing a locked unary operand operation. */
2175# define EMIT_LOCKED_UNARY_OP(a_Mnemonic, a_cBitsWidth) \
2176 IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ## _locked,(uint ## a_cBitsWidth ## _t *puDst, \
2177 uint32_t *pfEFlags)) \
2178 { \
2179 uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
2180 uint ## a_cBitsWidth ## _t uTmp; \
2181 uint32_t fEflTmp; \
2182 do \
2183 { \
2184 uTmp = uOld; \
2185 fEflTmp = *pfEFlags; \
2186 iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, &fEflTmp); \
2187 } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
2188 *pfEFlags = fEflTmp; \
2189 }
2190
2191EMIT_LOCKED_UNARY_OP(inc, 64)
2192EMIT_LOCKED_UNARY_OP(dec, 64)
2193EMIT_LOCKED_UNARY_OP(not, 64)
2194EMIT_LOCKED_UNARY_OP(neg, 64)
2195# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2196EMIT_LOCKED_UNARY_OP(inc, 32)
2197EMIT_LOCKED_UNARY_OP(dec, 32)
2198EMIT_LOCKED_UNARY_OP(not, 32)
2199EMIT_LOCKED_UNARY_OP(neg, 32)
2200
2201EMIT_LOCKED_UNARY_OP(inc, 16)
2202EMIT_LOCKED_UNARY_OP(dec, 16)
2203EMIT_LOCKED_UNARY_OP(not, 16)
2204EMIT_LOCKED_UNARY_OP(neg, 16)
2205
2206EMIT_LOCKED_UNARY_OP(inc, 8)
2207EMIT_LOCKED_UNARY_OP(dec, 8)
2208EMIT_LOCKED_UNARY_OP(not, 8)
2209EMIT_LOCKED_UNARY_OP(neg, 8)
2210# endif
2211
2212#endif /* !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY) */
2213
2214
2215/*********************************************************************************************************************************
2216* Shifting and Rotating *
2217*********************************************************************************************************************************/
2218
2219/*
2220 * ROL
2221 */
2222#define EMIT_ROL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags, a_fnHlp) \
2223IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rol_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2224{ \
2225 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2226 if (cShift) \
2227 { \
2228 if (a_cBitsWidth < 32) \
2229 cShift &= a_cBitsWidth - 1; \
2230 a_uType const uDst = *puDst; \
2231 a_uType const uResult = a_fnHlp(uDst, cShift); \
2232 *puDst = uResult; \
2233 \
2234 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2235 it the same way as for 1 bit shifts. */ \
2236 AssertCompile(X86_EFL_CF_BIT == 0); \
2237 uint32_t fEfl = *pfEFlags; \
2238 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2239 uint32_t const fCarry = (uResult & X86_EFL_CF); \
2240 fEfl |= fCarry; \
2241 if (!a_fIntelFlags) /* AMD 3990X: According to the last sub-shift: */ \
2242 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; \
2243 else /* Intel 10980XE: According to the first sub-shift: */ \
2244 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uDst << 1)); \
2245 *pfEFlags = fEfl; \
2246 } \
2247}
2248
2249#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2250EMIT_ROL(64, uint64_t, RT_NOTHING, 1, ASMRotateLeftU64)
2251#endif
2252EMIT_ROL(64, uint64_t, _intel, 1, ASMRotateLeftU64)
2253EMIT_ROL(64, uint64_t, _amd, 0, ASMRotateLeftU64)
2254
2255#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2256EMIT_ROL(32, uint32_t, RT_NOTHING, 1, ASMRotateLeftU32)
2257#endif
2258EMIT_ROL(32, uint32_t, _intel, 1, ASMRotateLeftU32)
2259EMIT_ROL(32, uint32_t, _amd, 0, ASMRotateLeftU32)
2260
2261DECL_FORCE_INLINE(uint16_t) iemAImpl_rol_u16_hlp(uint16_t uValue, uint8_t cShift)
2262{
2263 return (uValue << cShift) | (uValue >> (16 - cShift));
2264}
2265#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2266EMIT_ROL(16, uint16_t, RT_NOTHING, 1, iemAImpl_rol_u16_hlp)
2267#endif
2268EMIT_ROL(16, uint16_t, _intel, 1, iemAImpl_rol_u16_hlp)
2269EMIT_ROL(16, uint16_t, _amd, 0, iemAImpl_rol_u16_hlp)
2270
2271DECL_FORCE_INLINE(uint8_t) iemAImpl_rol_u8_hlp(uint8_t uValue, uint8_t cShift)
2272{
2273 return (uValue << cShift) | (uValue >> (8 - cShift));
2274}
2275#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2276EMIT_ROL(8, uint8_t, RT_NOTHING, 1, iemAImpl_rol_u8_hlp)
2277#endif
2278EMIT_ROL(8, uint8_t, _intel, 1, iemAImpl_rol_u8_hlp)
2279EMIT_ROL(8, uint8_t, _amd, 0, iemAImpl_rol_u8_hlp)
2280
2281
2282/*
2283 * ROR
2284 */
2285#define EMIT_ROR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags, a_fnHlp) \
2286IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_ror_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2287{ \
2288 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2289 if (cShift) \
2290 { \
2291 if (a_cBitsWidth < 32) \
2292 cShift &= a_cBitsWidth - 1; \
2293 a_uType const uDst = *puDst; \
2294 a_uType const uResult = a_fnHlp(uDst, cShift); \
2295 *puDst = uResult; \
2296 \
2297 /* Calc EFLAGS: */ \
2298 AssertCompile(X86_EFL_CF_BIT == 0); \
2299 uint32_t fEfl = *pfEFlags; \
2300 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2301 uint32_t const fCarry = (uResult >> ((a_cBitsWidth) - 1)) & X86_EFL_CF; \
2302 fEfl |= fCarry; \
2303 if (!a_fIntelFlags) /* AMD 3990X: According to the last sub-shift: */ \
2304 fEfl |= (((uResult >> ((a_cBitsWidth) - 2)) ^ fCarry) & 1) << X86_EFL_OF_BIT; \
2305 else /* Intel 10980XE: According to the first sub-shift: */ \
2306 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uDst << (a_cBitsWidth - 1))); \
2307 *pfEFlags = fEfl; \
2308 } \
2309}
2310
2311#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2312EMIT_ROR(64, uint64_t, RT_NOTHING, 1, ASMRotateRightU64)
2313#endif
2314EMIT_ROR(64, uint64_t, _intel, 1, ASMRotateRightU64)
2315EMIT_ROR(64, uint64_t, _amd, 0, ASMRotateRightU64)
2316
2317#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2318EMIT_ROR(32, uint32_t, RT_NOTHING, 1, ASMRotateRightU32)
2319#endif
2320EMIT_ROR(32, uint32_t, _intel, 1, ASMRotateRightU32)
2321EMIT_ROR(32, uint32_t, _amd, 0, ASMRotateRightU32)
2322
2323DECL_FORCE_INLINE(uint16_t) iemAImpl_ror_u16_hlp(uint16_t uValue, uint8_t cShift)
2324{
2325 return (uValue >> cShift) | (uValue << (16 - cShift));
2326}
2327#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2328EMIT_ROR(16, uint16_t, RT_NOTHING, 1, iemAImpl_ror_u16_hlp)
2329#endif
2330EMIT_ROR(16, uint16_t, _intel, 1, iemAImpl_ror_u16_hlp)
2331EMIT_ROR(16, uint16_t, _amd, 0, iemAImpl_ror_u16_hlp)
2332
2333DECL_FORCE_INLINE(uint8_t) iemAImpl_ror_u8_hlp(uint8_t uValue, uint8_t cShift)
2334{
2335 return (uValue >> cShift) | (uValue << (8 - cShift));
2336}
2337#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2338EMIT_ROR(8, uint8_t, RT_NOTHING, 1, iemAImpl_ror_u8_hlp)
2339#endif
2340EMIT_ROR(8, uint8_t, _intel, 1, iemAImpl_ror_u8_hlp)
2341EMIT_ROR(8, uint8_t, _amd, 0, iemAImpl_ror_u8_hlp)
2342
2343
2344/*
2345 * RCL
2346 */
2347#define EMIT_RCL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2348IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcl_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2349{ \
2350 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2351 if (a_cBitsWidth < 32 && a_fIntelFlags) \
2352 cShift %= a_cBitsWidth + 1; \
2353 if (cShift) \
2354 { \
2355 if (a_cBitsWidth < 32 && !a_fIntelFlags) \
2356 cShift %= a_cBitsWidth + 1; \
2357 a_uType const uDst = *puDst; \
2358 a_uType uResult = uDst << cShift; \
2359 if (cShift > 1) \
2360 uResult |= uDst >> (a_cBitsWidth + 1 - cShift); \
2361 \
2362 AssertCompile(X86_EFL_CF_BIT == 0); \
2363 uint32_t fEfl = *pfEFlags; \
2364 uint32_t fInCarry = fEfl & X86_EFL_CF; \
2365 uResult |= (a_uType)fInCarry << (cShift - 1); \
2366 \
2367 *puDst = uResult; \
2368 \
2369 /* Calc EFLAGS. */ \
2370 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2371 uint32_t const fOutCarry = a_cBitsWidth >= 32 || a_fIntelFlags || cShift \
2372 ? (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF : fInCarry; \
2373 fEfl |= fOutCarry; \
2374 if (!a_fIntelFlags) /* AMD 3990X: According to the last sub-shift: */ \
2375 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fOutCarry) << X86_EFL_OF_BIT; \
2376 else /* Intel 10980XE: According to the first sub-shift: */ \
2377 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uDst << 1)); \
2378 *pfEFlags = fEfl; \
2379 } \
2380}
2381
2382#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2383EMIT_RCL(64, uint64_t, RT_NOTHING, 1)
2384#endif
2385EMIT_RCL(64, uint64_t, _intel, 1)
2386EMIT_RCL(64, uint64_t, _amd, 0)
2387
2388#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2389EMIT_RCL(32, uint32_t, RT_NOTHING, 1)
2390#endif
2391EMIT_RCL(32, uint32_t, _intel, 1)
2392EMIT_RCL(32, uint32_t, _amd, 0)
2393
2394#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2395EMIT_RCL(16, uint16_t, RT_NOTHING, 1)
2396#endif
2397EMIT_RCL(16, uint16_t, _intel, 1)
2398EMIT_RCL(16, uint16_t, _amd, 0)
2399
2400#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2401EMIT_RCL(8, uint8_t, RT_NOTHING, 1)
2402#endif
2403EMIT_RCL(8, uint8_t, _intel, 1)
2404EMIT_RCL(8, uint8_t, _amd, 0)
2405
2406
2407/*
2408 * RCR
2409 */
2410#define EMIT_RCR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2411IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_rcr_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2412{ \
2413 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2414 if (a_cBitsWidth < 32 && a_fIntelFlags) \
2415 cShift %= a_cBitsWidth + 1; \
2416 if (cShift) \
2417 { \
2418 if (a_cBitsWidth < 32 && !a_fIntelFlags) \
2419 cShift %= a_cBitsWidth + 1; \
2420 a_uType const uDst = *puDst; \
2421 a_uType uResult = uDst >> cShift; \
2422 if (cShift > 1) \
2423 uResult |= uDst << (a_cBitsWidth + 1 - cShift); \
2424 \
2425 AssertCompile(X86_EFL_CF_BIT == 0); \
2426 uint32_t fEfl = *pfEFlags; \
2427 uint32_t fInCarry = fEfl & X86_EFL_CF; \
2428 uResult |= (a_uType)fInCarry << (a_cBitsWidth - cShift); \
2429 *puDst = uResult; \
2430 \
2431 /* Calc EFLAGS. The OF bit is undefined if cShift > 1, we implement \
2432 it the same way as for 1 bit shifts. */ \
2433 fEfl &= ~(X86_EFL_CF | X86_EFL_OF); \
2434 uint32_t const fOutCarry = a_cBitsWidth >= 32 || a_fIntelFlags || cShift \
2435 ? (uDst >> (cShift - 1)) & X86_EFL_CF : fInCarry; \
2436 fEfl |= fOutCarry; \
2437 if (!a_fIntelFlags) /* AMD 3990X: XOR two most signficant bits of the result: */ \
2438 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uResult ^ (uResult << 1)); \
2439 else /* Intel 10980XE: same as AMD, but only for the first sub-shift: */ \
2440 fEfl |= (fInCarry ^ (uint32_t)(uDst >> (a_cBitsWidth - 1))) << X86_EFL_OF_BIT; \
2441 *pfEFlags = fEfl; \
2442 } \
2443}
2444
2445#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2446EMIT_RCR(64, uint64_t, RT_NOTHING, 1)
2447#endif
2448EMIT_RCR(64, uint64_t, _intel, 1)
2449EMIT_RCR(64, uint64_t, _amd, 0)
2450
2451#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2452EMIT_RCR(32, uint32_t, RT_NOTHING, 1)
2453#endif
2454EMIT_RCR(32, uint32_t, _intel, 1)
2455EMIT_RCR(32, uint32_t, _amd, 0)
2456
2457#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2458EMIT_RCR(16, uint16_t, RT_NOTHING, 1)
2459#endif
2460EMIT_RCR(16, uint16_t, _intel, 1)
2461EMIT_RCR(16, uint16_t, _amd, 0)
2462
2463#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2464EMIT_RCR(8, uint8_t, RT_NOTHING, 1)
2465#endif
2466EMIT_RCR(8, uint8_t, _intel, 1)
2467EMIT_RCR(8, uint8_t, _amd, 0)
2468
2469
2470/*
2471 * SHL
2472 */
2473#define EMIT_SHL(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2474IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shl_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2475{ \
2476 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2477 if (cShift) \
2478 { \
2479 a_uType const uDst = *puDst; \
2480 a_uType uResult = uDst << cShift; \
2481 *puDst = uResult; \
2482 \
2483 /* Calc EFLAGS. */ \
2484 AssertCompile(X86_EFL_CF_BIT == 0); \
2485 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2486 uint32_t fCarry = (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; \
2487 fEfl |= fCarry; \
2488 if (!a_fIntelFlags) \
2489 fEfl |= ((uResult >> (a_cBitsWidth - 1)) ^ fCarry) << X86_EFL_OF_BIT; /* AMD 3990X: Last shift result. */ \
2490 else \
2491 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uDst << 1)); /* Intel 10980XE: First shift result. */ \
2492 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2493 fEfl |= X86_EFL_CALC_ZF(uResult); \
2494 fEfl |= g_afParity[uResult & 0xff]; \
2495 if (!a_fIntelFlags) \
2496 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \
2497 *pfEFlags = fEfl; \
2498 } \
2499}
2500
2501#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2502EMIT_SHL(64, uint64_t, RT_NOTHING, 1)
2503#endif
2504EMIT_SHL(64, uint64_t, _intel, 1)
2505EMIT_SHL(64, uint64_t, _amd, 0)
2506
2507#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2508EMIT_SHL(32, uint32_t, RT_NOTHING, 1)
2509#endif
2510EMIT_SHL(32, uint32_t, _intel, 1)
2511EMIT_SHL(32, uint32_t, _amd, 0)
2512
2513#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2514EMIT_SHL(16, uint16_t, RT_NOTHING, 1)
2515#endif
2516EMIT_SHL(16, uint16_t, _intel, 1)
2517EMIT_SHL(16, uint16_t, _amd, 0)
2518
2519#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2520EMIT_SHL(8, uint8_t, RT_NOTHING, 1)
2521#endif
2522EMIT_SHL(8, uint8_t, _intel, 1)
2523EMIT_SHL(8, uint8_t, _amd, 0)
2524
2525
2526/*
2527 * SHR
2528 */
2529#define EMIT_SHR(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2530IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shr_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2531{ \
2532 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2533 if (cShift) \
2534 { \
2535 a_uType const uDst = *puDst; \
2536 a_uType uResult = uDst >> cShift; \
2537 *puDst = uResult; \
2538 \
2539 /* Calc EFLAGS. */ \
2540 AssertCompile(X86_EFL_CF_BIT == 0); \
2541 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2542 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2543 if (a_fIntelFlags || cShift == 1) /* AMD 3990x does what intel documents; Intel 10980XE does this for all shift counts. */ \
2544 fEfl |= (uDst >> (a_cBitsWidth - 1)) << X86_EFL_OF_BIT; \
2545 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2546 fEfl |= X86_EFL_CALC_ZF(uResult); \
2547 fEfl |= g_afParity[uResult & 0xff]; \
2548 if (!a_fIntelFlags) \
2549 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \
2550 *pfEFlags = fEfl; \
2551 } \
2552}
2553
2554#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2555EMIT_SHR(64, uint64_t, RT_NOTHING, 1)
2556#endif
2557EMIT_SHR(64, uint64_t, _intel, 1)
2558EMIT_SHR(64, uint64_t, _amd, 0)
2559
2560#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2561EMIT_SHR(32, uint32_t, RT_NOTHING, 1)
2562#endif
2563EMIT_SHR(32, uint32_t, _intel, 1)
2564EMIT_SHR(32, uint32_t, _amd, 0)
2565
2566#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2567EMIT_SHR(16, uint16_t, RT_NOTHING, 1)
2568#endif
2569EMIT_SHR(16, uint16_t, _intel, 1)
2570EMIT_SHR(16, uint16_t, _amd, 0)
2571
2572#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2573EMIT_SHR(8, uint8_t, RT_NOTHING, 1)
2574#endif
2575EMIT_SHR(8, uint8_t, _intel, 1)
2576EMIT_SHR(8, uint8_t, _amd, 0)
2577
2578
2579/*
2580 * SAR
2581 */
2582#define EMIT_SAR(a_cBitsWidth, a_uType, a_iType, a_Suffix, a_fIntelFlags) \
2583IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_sar_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, uint8_t cShift, uint32_t *pfEFlags)) \
2584{ \
2585 cShift &= a_cBitsWidth >= 32 ? a_cBitsWidth - 1 : 31; \
2586 if (cShift) \
2587 { \
2588 a_iType const iDst = (a_iType)*puDst; \
2589 a_uType uResult = iDst >> cShift; \
2590 *puDst = uResult; \
2591 \
2592 /* Calc EFLAGS. \
2593 Note! The OF flag is always zero because the result never differs from the input. */ \
2594 AssertCompile(X86_EFL_CF_BIT == 0); \
2595 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2596 fEfl |= (iDst >> (cShift - 1)) & X86_EFL_CF; \
2597 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2598 fEfl |= X86_EFL_CALC_ZF(uResult); \
2599 fEfl |= g_afParity[uResult & 0xff]; \
2600 if (!a_fIntelFlags) \
2601 fEfl |= X86_EFL_AF; /* AMD 3990x sets it unconditionally, Intel 10980XE does the oposite */ \
2602 *pfEFlags = fEfl; \
2603 } \
2604}
2605
2606#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2607EMIT_SAR(64, uint64_t, int64_t, RT_NOTHING, 1)
2608#endif
2609EMIT_SAR(64, uint64_t, int64_t, _intel, 1)
2610EMIT_SAR(64, uint64_t, int64_t, _amd, 0)
2611
2612#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2613EMIT_SAR(32, uint32_t, int32_t, RT_NOTHING, 1)
2614#endif
2615EMIT_SAR(32, uint32_t, int32_t, _intel, 1)
2616EMIT_SAR(32, uint32_t, int32_t, _amd, 0)
2617
2618#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2619EMIT_SAR(16, uint16_t, int16_t, RT_NOTHING, 1)
2620#endif
2621EMIT_SAR(16, uint16_t, int16_t, _intel, 1)
2622EMIT_SAR(16, uint16_t, int16_t, _amd, 0)
2623
2624#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2625EMIT_SAR(8, uint8_t, int8_t, RT_NOTHING, 1)
2626#endif
2627EMIT_SAR(8, uint8_t, int8_t, _intel, 1)
2628EMIT_SAR(8, uint8_t, int8_t, _amd, 0)
2629
2630
2631/*
2632 * SHLD
2633 *
2634 * - CF is the last bit shifted out of puDst.
2635 * - AF is always cleared by Intel 10980XE.
2636 * - AF is always set by AMD 3990X.
2637 * - OF is set according to the first shift on Intel 10980XE, it seems.
2638 * - OF is set according to the last sub-shift on AMD 3990X.
2639 * - ZF, SF and PF are calculated according to the result by both vendors.
2640 *
2641 * For 16-bit shifts the count mask isn't 15, but 31, and the CPU will
2642 * pick either the source register or the destination register for input bits
2643 * when going beyond 16. According to https://www.sandpile.org/x86/flags.htm
2644 * intel has changed behaviour here several times. We implement what current
2645 * skylake based does for now, we can extend this later as needed.
2646 */
2647#define EMIT_SHLD(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2648IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shld_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, a_uType uSrc, uint8_t cShift, \
2649 uint32_t *pfEFlags)) \
2650{ \
2651 cShift &= a_cBitsWidth - 1; \
2652 if (cShift) \
2653 { \
2654 a_uType const uDst = *puDst; \
2655 a_uType uResult = uDst << cShift; \
2656 uResult |= uSrc >> (a_cBitsWidth - cShift); \
2657 *puDst = uResult; \
2658 \
2659 /* CALC EFLAGS: */ \
2660 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2661 if (a_fIntelFlags) \
2662 /* Intel 6700K & 10980XE: Set according to the first shift. AF always cleared. */ \
2663 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uDst << 1)); \
2664 else \
2665 { /* AMD 3990X: Set according to last shift. AF always set. */ \
2666 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uDst << (cShift - 1)) ^ uResult); \
2667 fEfl |= X86_EFL_AF; \
2668 } \
2669 AssertCompile(X86_EFL_CF_BIT == 0); \
2670 fEfl |= (uDst >> (a_cBitsWidth - cShift)) & X86_EFL_CF; /* CF = last bit shifted out */ \
2671 fEfl |= g_afParity[uResult & 0xff]; \
2672 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2673 fEfl |= X86_EFL_CALC_ZF(uResult); \
2674 *pfEFlags = fEfl; \
2675 } \
2676}
2677
2678#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2679EMIT_SHLD(64, uint64_t, RT_NOTHING, 1)
2680#endif
2681EMIT_SHLD(64, uint64_t, _intel, 1)
2682EMIT_SHLD(64, uint64_t, _amd, 0)
2683
2684#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2685EMIT_SHLD(32, uint32_t, RT_NOTHING, 1)
2686#endif
2687EMIT_SHLD(32, uint32_t, _intel, 1)
2688EMIT_SHLD(32, uint32_t, _amd, 0)
2689
2690#define EMIT_SHLD_16(a_Suffix, a_fIntelFlags) \
2691IEM_DECL_IMPL_DEF(void, RT_CONCAT(iemAImpl_shld_u16,a_Suffix),(uint16_t *puDst, uint16_t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2692{ \
2693 cShift &= 31; \
2694 if (cShift) \
2695 { \
2696 uint16_t const uDst = *puDst; \
2697 uint64_t const uTmp = a_fIntelFlags \
2698 ? ((uint64_t)uDst << 32) | ((uint32_t)uSrc << 16) | uDst \
2699 : ((uint64_t)uDst << 32) | ((uint32_t)uSrc << 16) | uSrc; \
2700 uint16_t const uResult = (uint16_t)((uTmp << cShift) >> 32); \
2701 *puDst = uResult; \
2702 \
2703 /* CALC EFLAGS: */ \
2704 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2705 AssertCompile(X86_EFL_CF_BIT == 0); \
2706 if (a_fIntelFlags) \
2707 { \
2708 fEfl |= (uTmp >> (48 - cShift)) & X86_EFL_CF; /* CF = last bit shifted out of the combined operand */ \
2709 /* Intel 6700K & 10980XE: OF is et according to the first shift. AF always cleared. */ \
2710 fEfl |= X86_EFL_GET_OF_16(uDst ^ (uDst << 1)); \
2711 } \
2712 else \
2713 { \
2714 /* AMD 3990X: OF is set according to last shift, with some weirdness. AF always set. CF = last bit shifted out of uDst. */ \
2715 if (cShift < 16) \
2716 { \
2717 fEfl |= (uDst >> (16 - cShift)) & X86_EFL_CF; \
2718 fEfl |= X86_EFL_GET_OF_16((uDst << (cShift - 1)) ^ uResult); \
2719 } \
2720 else \
2721 { \
2722 if (cShift == 16) \
2723 fEfl |= uDst & X86_EFL_CF; \
2724 fEfl |= X86_EFL_GET_OF_16((uDst << (cShift - 1)) ^ 0); \
2725 } \
2726 fEfl |= X86_EFL_AF; \
2727 } \
2728 fEfl |= g_afParity[uResult & 0xff]; \
2729 fEfl |= X86_EFL_CALC_SF(uResult, 16); \
2730 fEfl |= X86_EFL_CALC_ZF(uResult); \
2731 *pfEFlags = fEfl; \
2732 } \
2733}
2734
2735#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2736EMIT_SHLD_16(RT_NOTHING, 1)
2737#endif
2738EMIT_SHLD_16(_intel, 1)
2739EMIT_SHLD_16(_amd, 0)
2740
2741
2742/*
2743 * SHRD
2744 *
2745 * EFLAGS behaviour seems to be the same as with SHLD:
2746 * - CF is the last bit shifted out of puDst.
2747 * - AF is always cleared by Intel 10980XE.
2748 * - AF is always set by AMD 3990X.
2749 * - OF is set according to the first shift on Intel 10980XE, it seems.
2750 * - OF is set according to the last sub-shift on AMD 3990X.
2751 * - ZF, SF and PF are calculated according to the result by both vendors.
2752 *
2753 * For 16-bit shifts the count mask isn't 15, but 31, and the CPU will
2754 * pick either the source register or the destination register for input bits
2755 * when going beyond 16. According to https://www.sandpile.org/x86/flags.htm
2756 * intel has changed behaviour here several times. We implement what current
2757 * skylake based does for now, we can extend this later as needed.
2758 */
2759#define EMIT_SHRD(a_cBitsWidth, a_uType, a_Suffix, a_fIntelFlags) \
2760IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_shrd_u,a_cBitsWidth,a_Suffix),(a_uType *puDst, a_uType uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2761{ \
2762 cShift &= a_cBitsWidth - 1; \
2763 if (cShift) \
2764 { \
2765 a_uType const uDst = *puDst; \
2766 a_uType uResult = uDst >> cShift; \
2767 uResult |= uSrc << (a_cBitsWidth - cShift); \
2768 *puDst = uResult; \
2769 \
2770 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2771 AssertCompile(X86_EFL_CF_BIT == 0); \
2772 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2773 if (a_fIntelFlags) \
2774 /* Intel 6700K & 10980XE: Set according to the first shift. AF always cleared. */ \
2775 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ (uSrc << (a_cBitsWidth - 1))); \
2776 else \
2777 { /* AMD 3990X: Set according to last shift. AF always set. */ \
2778 if (cShift > 1) /* Set according to last shift. */ \
2779 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth((uSrc << (a_cBitsWidth - cShift + 1)) ^ uResult); \
2780 else \
2781 fEfl |= X86_EFL_GET_OF_ ## a_cBitsWidth(uDst ^ uResult); \
2782 fEfl |= X86_EFL_AF; \
2783 } \
2784 fEfl |= X86_EFL_CALC_SF(uResult, a_cBitsWidth); \
2785 fEfl |= X86_EFL_CALC_ZF(uResult); \
2786 fEfl |= g_afParity[uResult & 0xff]; \
2787 *pfEFlags = fEfl; \
2788 } \
2789}
2790
2791#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2792EMIT_SHRD(64, uint64_t, RT_NOTHING, 1)
2793#endif
2794EMIT_SHRD(64, uint64_t, _intel, 1)
2795EMIT_SHRD(64, uint64_t, _amd, 0)
2796
2797#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2798EMIT_SHRD(32, uint32_t, RT_NOTHING, 1)
2799#endif
2800EMIT_SHRD(32, uint32_t, _intel, 1)
2801EMIT_SHRD(32, uint32_t, _amd, 0)
2802
2803#define EMIT_SHRD_16(a_Suffix, a_fIntelFlags) \
2804IEM_DECL_IMPL_DEF(void, RT_CONCAT(iemAImpl_shrd_u16,a_Suffix),(uint16_t *puDst, uint16_t uSrc, uint8_t cShift, uint32_t *pfEFlags)) \
2805{ \
2806 cShift &= 31; \
2807 if (cShift) \
2808 { \
2809 uint16_t const uDst = *puDst; \
2810 uint64_t const uTmp = a_fIntelFlags \
2811 ? uDst | ((uint32_t)uSrc << 16) | ((uint64_t)uDst << 32) \
2812 : uDst | ((uint32_t)uSrc << 16) | ((uint64_t)uSrc << 32); \
2813 uint16_t const uResult = (uint16_t)(uTmp >> cShift); \
2814 *puDst = uResult; \
2815 \
2816 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; \
2817 AssertCompile(X86_EFL_CF_BIT == 0); \
2818 if (a_fIntelFlags) \
2819 { \
2820 /* Intel 10980XE: The CF is the last shifted out of the combined uTmp operand. */ \
2821 fEfl |= (uTmp >> (cShift - 1)) & X86_EFL_CF; \
2822 /* Intel 6700K & 10980XE: Set according to the first shift. AF always cleared. */ \
2823 fEfl |= X86_EFL_GET_OF_16(uDst ^ (uSrc << 15)); \
2824 } \
2825 else \
2826 { \
2827 /* AMD 3990X: CF flag seems to be last bit shifted out of uDst, not the combined uSrc:uSrc:uDst operand. */ \
2828 fEfl |= (uDst >> (cShift - 1)) & X86_EFL_CF; \
2829 /* AMD 3990X: Set according to last shift. AF always set. */ \
2830 if (cShift > 1) /* Set according to last shift. */ \
2831 fEfl |= X86_EFL_GET_OF_16((uint16_t)(uTmp >> (cShift - 1)) ^ uResult); \
2832 else \
2833 fEfl |= X86_EFL_GET_OF_16(uDst ^ uResult); \
2834 fEfl |= X86_EFL_AF; \
2835 } \
2836 fEfl |= X86_EFL_CALC_SF(uResult, 16); \
2837 fEfl |= X86_EFL_CALC_ZF(uResult); \
2838 fEfl |= g_afParity[uResult & 0xff]; \
2839 *pfEFlags = fEfl; \
2840 } \
2841}
2842
2843#if (!defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)) || defined(IEM_WITHOUT_ASSEMBLY)
2844EMIT_SHRD_16(RT_NOTHING, 1)
2845#endif
2846EMIT_SHRD_16(_intel, 1)
2847EMIT_SHRD_16(_amd, 0)
2848
2849
2850#if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
2851
2852# if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
2853/*
2854 * BSWAP
2855 */
2856
2857IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u64,(uint64_t *puDst))
2858{
2859 *puDst = ASMByteSwapU64(*puDst);
2860}
2861
2862
2863IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u32,(uint32_t *puDst))
2864{
2865 *puDst = ASMByteSwapU32(*puDst);
2866}
2867
2868
2869/* Note! undocument, so 32-bit arg */
2870IEM_DECL_IMPL_DEF(void, iemAImpl_bswap_u16,(uint32_t *puDst))
2871{
2872#if 0
2873 *(uint16_t *)puDst = ASMByteSwapU16(*(uint16_t *)puDst);
2874#else
2875 /* This is the behaviour AMD 3990x (64-bit mode): */
2876 *(uint16_t *)puDst = 0;
2877#endif
2878}
2879
2880# endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
2881
2882
2883
2884# if defined(IEM_WITHOUT_ASSEMBLY)
2885
2886/*
2887 * LFENCE, SFENCE & MFENCE.
2888 */
2889
2890IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void))
2891{
2892 ASMReadFence();
2893}
2894
2895
2896IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void))
2897{
2898 ASMWriteFence();
2899}
2900
2901
2902IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void))
2903{
2904 ASMMemoryFence();
2905}
2906
2907
2908# ifndef RT_ARCH_ARM64
2909IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void))
2910{
2911 ASMMemoryFence();
2912}
2913# endif
2914
2915# endif
2916
2917#endif /* !RT_ARCH_AMD64 || IEM_WITHOUT_ASSEMBLY */
2918
2919
2920IEM_DECL_IMPL_DEF(void, iemAImpl_arpl,(uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pfEFlags))
2921{
2922 if ((*pu16Dst & X86_SEL_RPL) < (u16Src & X86_SEL_RPL))
2923 {
2924 *pu16Dst &= X86_SEL_MASK_OFF_RPL;
2925 *pu16Dst |= u16Src & X86_SEL_RPL;
2926
2927 *pfEFlags |= X86_EFL_ZF;
2928 }
2929 else
2930 *pfEFlags &= ~X86_EFL_ZF;
2931}
2932
2933
2934/*********************************************************************************************************************************
2935* x87 FPU *
2936*********************************************************************************************************************************/
2937#if defined(IEM_WITHOUT_ASSEMBLY)
2938
2939IEM_DECL_IMPL_DEF(void, iemAImpl_f2xm1_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2940{
2941 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2942 AssertReleaseFailed();
2943}
2944
2945
2946IEM_DECL_IMPL_DEF(void, iemAImpl_fabs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2947{
2948 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2949 AssertReleaseFailed();
2950}
2951
2952
2953IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2954 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2955{
2956 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
2957 AssertReleaseFailed();
2958}
2959
2960
2961IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2962 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2963{
2964 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
2965 AssertReleaseFailed();
2966}
2967
2968
2969IEM_DECL_IMPL_DEF(void, iemAImpl_fadd_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2970 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
2971{
2972 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
2973 AssertReleaseFailed();
2974}
2975
2976
2977IEM_DECL_IMPL_DEF(void, iemAImpl_fchs_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
2978{
2979 RT_NOREF(pFpuState, pFpuRes, pr80Val);
2980 AssertReleaseFailed();
2981}
2982
2983
2984IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r32,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2985 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
2986{
2987 RT_NOREF(pFpuState, pFSW, pr80Val1, pr32Val2);
2988 AssertReleaseFailed();
2989}
2990
2991
2992IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2993 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
2994{
2995 RT_NOREF(pFpuState, pFSW, pr80Val1, pr64Val2);
2996 AssertReleaseFailed();
2997}
2998
2999
3000IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3001 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3002{
3003 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3004 AssertReleaseFailed();
3005}
3006
3007
3008IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fcomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3009 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3010{
3011 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3012 AssertReleaseFailed();
3013 return 0;
3014}
3015
3016
3017IEM_DECL_IMPL_DEF(void, iemAImpl_fcos_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3018{
3019 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3020 AssertReleaseFailed();
3021}
3022
3023
3024IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3025 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3026{
3027 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3028 AssertReleaseFailed();
3029}
3030
3031
3032IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3033 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3034{
3035 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3036 AssertReleaseFailed();
3037}
3038
3039
3040IEM_DECL_IMPL_DEF(void, iemAImpl_fdiv_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3041 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3042{
3043 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3044 AssertReleaseFailed();
3045}
3046
3047
3048IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3049 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3050{
3051 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3052 AssertReleaseFailed();
3053}
3054
3055
3056IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3057 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3058{
3059 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3060 AssertReleaseFailed();
3061}
3062
3063
3064IEM_DECL_IMPL_DEF(void, iemAImpl_fdivr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3065 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3066{
3067 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3068 AssertReleaseFailed();
3069}
3070
3071
3072IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3073 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3074{
3075 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3076 AssertReleaseFailed();
3077}
3078
3079
3080IEM_DECL_IMPL_DEF(void, iemAImpl_fiadd_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3081 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3082{
3083 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3084 AssertReleaseFailed();
3085}
3086
3087
3088IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3089 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3090{
3091 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi16Val2);
3092 AssertReleaseFailed();
3093}
3094
3095
3096IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3097 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3098{
3099 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pi32Val2);
3100 AssertReleaseFailed();
3101}
3102
3103
3104IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3105 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3106{
3107 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3108 AssertReleaseFailed();
3109}
3110
3111
3112IEM_DECL_IMPL_DEF(void, iemAImpl_fidiv_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3113 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3114{
3115 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3116 AssertReleaseFailed();
3117}
3118
3119
3120IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3121 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3122{
3123 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3124 AssertReleaseFailed();
3125}
3126
3127
3128IEM_DECL_IMPL_DEF(void, iemAImpl_fidivr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3129 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3130{
3131 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3132 AssertReleaseFailed();
3133}
3134
3135
3136IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val))
3137{
3138 RT_NOREF(pFpuState, pFpuRes, pi16Val);
3139 AssertReleaseFailed();
3140}
3141
3142
3143IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val))
3144{
3145 RT_NOREF(pFpuState, pFpuRes, pi32Val);
3146 AssertReleaseFailed();
3147}
3148
3149
3150IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val))
3151{
3152 RT_NOREF(pFpuState, pFpuRes, pi64Val);
3153 AssertReleaseFailed();
3154}
3155
3156
3157IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3158 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3159{
3160 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3161 AssertReleaseFailed();
3162}
3163
3164
3165IEM_DECL_IMPL_DEF(void, iemAImpl_fimul_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3166 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3167{
3168 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3169 AssertReleaseFailed();
3170}
3171
3172
3173IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3174 int16_t *pi16Val, PCRTFLOAT80U pr80Val))
3175{
3176 RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
3177 AssertReleaseFailed();
3178}
3179
3180
3181IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3182 int32_t *pi32Val, PCRTFLOAT80U pr80Val))
3183{
3184 RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
3185 AssertReleaseFailed();
3186}
3187
3188
3189IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3190 int64_t *pi64Val, PCRTFLOAT80U pr80Val))
3191{
3192 RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
3193 AssertReleaseFailed();
3194}
3195
3196
3197IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3198 int16_t *pi16Val, PCRTFLOAT80U pr80Val))
3199{
3200 RT_NOREF(pFpuState, pu16FSW, pi16Val, pr80Val);
3201 AssertReleaseFailed();
3202}
3203
3204
3205IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3206 int32_t *pi32Val, PCRTFLOAT80U pr80Val))
3207{
3208 RT_NOREF(pFpuState, pu16FSW, pi32Val, pr80Val);
3209 AssertReleaseFailed();
3210}
3211
3212
3213IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3214 int64_t *pi64Val, PCRTFLOAT80U pr80Val))
3215{
3216 RT_NOREF(pFpuState, pu16FSW, pi64Val, pr80Val);
3217 AssertReleaseFailed();
3218}
3219
3220
3221IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3222 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3223{
3224 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3225 AssertReleaseFailed();
3226}
3227
3228
3229IEM_DECL_IMPL_DEF(void, iemAImpl_fisub_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3230 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3231{
3232 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3233 AssertReleaseFailed();
3234}
3235
3236
3237IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3238 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2))
3239{
3240 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi16Val2);
3241 AssertReleaseFailed();
3242}
3243
3244
3245IEM_DECL_IMPL_DEF(void, iemAImpl_fisubr_r80_by_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3246 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2))
3247{
3248 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pi32Val2);
3249 AssertReleaseFailed();
3250}
3251
3252
3253IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val))
3254{
3255 RT_NOREF(pFpuState, pFpuRes, pr32Val);
3256 AssertReleaseFailed();
3257}
3258
3259
3260IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val))
3261{
3262 RT_NOREF(pFpuState, pFpuRes, pr64Val);
3263 AssertReleaseFailed();
3264}
3265
3266IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3267{
3268 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3269 AssertReleaseFailed();
3270}
3271
3272
3273IEM_DECL_IMPL_DEF(void, iemAImpl_fld1,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3274{
3275 pFpuRes->r80Result.sj64.fSign = 0;
3276 pFpuRes->r80Result.sj64.uExponent = 0 + 16383;
3277 pFpuRes->r80Result.sj64.fInteger = 1;
3278 pFpuRes->r80Result.sj64.uFraction = 0;
3279
3280 /*
3281 * FPU status word:
3282 * - TOP is irrelevant, but we must match x86 assembly version.
3283 * - C1 is always cleared as we don't have any stack overflows.
3284 * - C0, C2, and C3 are undefined and Intel 10980XE does not touch them.
3285 */
3286 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3));
3287}
3288
3289
3290IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2e,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3291{
3292 pFpuRes->r80Result.sj64.fSign = 0;
3293 pFpuRes->r80Result.sj64.uExponent = 0 + 16383;
3294 pFpuRes->r80Result.sj64.fInteger = 1;
3295 pFpuRes->r80Result.sj64.uFraction = (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST
3296 || (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_UP
3297 ? UINT64_C(0x38aa3b295c17f0bc) : UINT64_C(0x38aa3b295c17f0bb);
3298 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3299}
3300
3301
3302IEM_DECL_IMPL_DEF(void, iemAImpl_fldl2t,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3303{
3304 pFpuRes->r80Result.sj64.fSign = 0;
3305 pFpuRes->r80Result.sj64.uExponent = 1 + 16383;
3306 pFpuRes->r80Result.sj64.fInteger = 1;
3307 pFpuRes->r80Result.sj64.uFraction = (pFpuState->FCW & X86_FCW_RC_MASK) != X86_FCW_RC_UP
3308 ? UINT64_C(0x549a784bcd1b8afe) : UINT64_C(0x549a784bcd1b8aff);
3309 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3310}
3311
3312
3313IEM_DECL_IMPL_DEF(void, iemAImpl_fldlg2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3314{
3315 pFpuRes->r80Result.sj64.fSign = 0;
3316 pFpuRes->r80Result.sj64.uExponent = -2 + 16383;
3317 pFpuRes->r80Result.sj64.fInteger = 1;
3318 pFpuRes->r80Result.sj64.uFraction = (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST
3319 || (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_UP
3320 ? UINT64_C(0x1a209a84fbcff799) : UINT64_C(0x1a209a84fbcff798);
3321 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3322}
3323
3324
3325IEM_DECL_IMPL_DEF(void, iemAImpl_fldln2,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3326{
3327 pFpuRes->r80Result.sj64.fSign = 0;
3328 pFpuRes->r80Result.sj64.uExponent = -1 + 16383;
3329 pFpuRes->r80Result.sj64.fInteger = 1;
3330 pFpuRes->r80Result.sj64.uFraction = (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST
3331 || (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_UP
3332 ? UINT64_C(0x317217f7d1cf79ac) : UINT64_C(0x317217f7d1cf79ab);
3333 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3334}
3335
3336
3337IEM_DECL_IMPL_DEF(void, iemAImpl_fldpi,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3338{
3339 pFpuRes->r80Result.sj64.fSign = 0;
3340 pFpuRes->r80Result.sj64.uExponent = 1 + 16383;
3341 pFpuRes->r80Result.sj64.fInteger = 1;
3342 pFpuRes->r80Result.sj64.uFraction = (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_NEAREST
3343 || (pFpuState->FCW & X86_FCW_RC_MASK) == X86_FCW_RC_UP
3344 ? UINT64_C(0x490fdaa22168c235) : UINT64_C(0x490fdaa22168c234);
3345 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3346}
3347
3348
3349IEM_DECL_IMPL_DEF(void, iemAImpl_fldz,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes))
3350{
3351 pFpuRes->r80Result.sj64.fSign = 0;
3352 pFpuRes->r80Result.sj64.uExponent = 0;
3353 pFpuRes->r80Result.sj64.fInteger = 0;
3354 pFpuRes->r80Result.sj64.uFraction = 0;
3355 pFpuRes->FSW = (7 << X86_FSW_TOP_SHIFT) | (pFpuState->FSW & (X86_FSW_C0 | X86_FSW_C2 | X86_FSW_C3)); /* see iemAImpl_fld1 */
3356}
3357
3358
3359IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3360 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3361{
3362 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3363 AssertReleaseFailed();
3364}
3365
3366
3367IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3368 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3369{
3370 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3371 AssertReleaseFailed();
3372}
3373
3374
3375IEM_DECL_IMPL_DEF(void, iemAImpl_fmul_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3376 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3377{
3378 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3379 AssertReleaseFailed();
3380}
3381
3382
3383IEM_DECL_IMPL_DEF(void, iemAImpl_fpatan_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3384 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3385{
3386 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3387 AssertReleaseFailed();
3388}
3389
3390
3391IEM_DECL_IMPL_DEF(void, iemAImpl_fprem_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3392 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3393{
3394 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3395 AssertReleaseFailed();
3396}
3397
3398
3399IEM_DECL_IMPL_DEF(void, iemAImpl_fprem1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3400 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3401{
3402 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3403 AssertReleaseFailed();
3404}
3405
3406
3407IEM_DECL_IMPL_DEF(void, iemAImpl_fptan_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3408{
3409 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3410 AssertReleaseFailed();
3411}
3412
3413
3414IEM_DECL_IMPL_DEF(void, iemAImpl_frndint_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3415{
3416 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3417 AssertReleaseFailed();
3418}
3419
3420
3421IEM_DECL_IMPL_DEF(void, iemAImpl_fscale_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3422 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3423{
3424 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3425 AssertReleaseFailed();
3426}
3427
3428
3429IEM_DECL_IMPL_DEF(void, iemAImpl_fsin_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3430{
3431 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3432 AssertReleaseFailed();
3433}
3434
3435
3436IEM_DECL_IMPL_DEF(void, iemAImpl_fsincos_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3437{
3438 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3439 AssertReleaseFailed();
3440}
3441
3442
3443IEM_DECL_IMPL_DEF(void, iemAImpl_fsqrt_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val))
3444{
3445 RT_NOREF(pFpuState, pFpuRes, pr80Val);
3446 AssertReleaseFailed();
3447}
3448
3449
3450IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3451 PRTFLOAT32U pr32Dst, PCRTFLOAT80U pr80Src))
3452{
3453 RT_NOREF(pFpuState, pu16FSW, pr32Dst, pr80Src);
3454 AssertReleaseFailed();
3455}
3456
3457
3458IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3459 PRTFLOAT64U pr64Dst, PCRTFLOAT80U pr80Src))
3460{
3461 RT_NOREF(pFpuState, pu16FSW, pr64Dst, pr80Src);
3462 AssertReleaseFailed();
3463}
3464
3465
3466IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3467 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src))
3468{
3469 RT_NOREF(pFpuState, pu16FSW, pr80Dst, pr80Src);
3470 AssertReleaseFailed();
3471}
3472
3473
3474IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3475 PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src))
3476{
3477 RT_NOREF(pFpuState, pu16FSW, pd80Dst, pr80Src);
3478 AssertReleaseFailed();
3479}
3480
3481
3482IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3483 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3484{
3485 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3486 AssertReleaseFailed();
3487}
3488
3489
3490IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3491 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3492{
3493 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3494 AssertReleaseFailed();
3495}
3496
3497
3498IEM_DECL_IMPL_DEF(void, iemAImpl_fsub_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3499 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3500{
3501 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3502 AssertReleaseFailed();
3503}
3504
3505
3506IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3507 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2))
3508{
3509 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr32Val2);
3510 AssertReleaseFailed();
3511}
3512
3513
3514IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3515 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2))
3516{
3517 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr64Val2);
3518 AssertReleaseFailed();
3519}
3520
3521
3522IEM_DECL_IMPL_DEF(void, iemAImpl_fsubr_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3523 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3524{
3525 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3526 AssertReleaseFailed();
3527}
3528
3529
3530IEM_DECL_IMPL_DEF(void, iemAImpl_ftst_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3531{
3532 RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3533 AssertReleaseFailed();
3534}
3535
3536
3537IEM_DECL_IMPL_DEF(void, iemAImpl_fucom_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3538 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3539{
3540 RT_NOREF(pFpuState, pFSW, pr80Val1, pr80Val2);
3541 AssertReleaseFailed();
3542}
3543
3544
3545IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_fucomi_r80_by_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3546 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3547{
3548 RT_NOREF(pFpuState, pu16Fsw, pr80Val1, pr80Val2);
3549 AssertReleaseFailed();
3550 return 0;
3551}
3552
3553
3554IEM_DECL_IMPL_DEF(void, iemAImpl_fxam_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val))
3555{
3556 RT_NOREF(pFpuState, pu16Fsw, pr80Val);
3557 AssertReleaseFailed();
3558}
3559
3560
3561IEM_DECL_IMPL_DEF(void, iemAImpl_fxtract_r80_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo, PCRTFLOAT80U pr80Val))
3562{
3563 RT_NOREF(pFpuState, pFpuResTwo, pr80Val);
3564 AssertReleaseFailed();
3565}
3566
3567
3568IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2x_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3569 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3570{
3571 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3572 AssertReleaseFailed();
3573}
3574
3575
3576IEM_DECL_IMPL_DEF(void, iemAImpl_fyl2xp1_r80_by_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3577 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2))
3578{
3579 RT_NOREF(pFpuState, pFpuRes, pr80Val1, pr80Val2);
3580 AssertReleaseFailed();
3581}
3582
3583#endif /* IEM_WITHOUT_ASSEMBLY */
3584
3585
3586/*********************************************************************************************************************************
3587* MMX, SSE & AVX *
3588*********************************************************************************************************************************/
3589
3590IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3591{
3592 RT_NOREF(pFpuState);
3593 puDst->au32[0] = puSrc->au32[0];
3594 puDst->au32[1] = puSrc->au32[0];
3595 puDst->au32[2] = puSrc->au32[2];
3596 puDst->au32[3] = puSrc->au32[2];
3597}
3598
3599#ifdef IEM_WITH_VEX
3600
3601IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3602{
3603 pXState->x87.aXMM[iYRegDst].au32[0] = pXState->x87.aXMM[iYRegSrc].au32[0];
3604 pXState->x87.aXMM[iYRegDst].au32[1] = pXState->x87.aXMM[iYRegSrc].au32[0];
3605 pXState->x87.aXMM[iYRegDst].au32[2] = pXState->x87.aXMM[iYRegSrc].au32[2];
3606 pXState->x87.aXMM[iYRegDst].au32[3] = pXState->x87.aXMM[iYRegSrc].au32[2];
3607 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3608 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[0];
3609 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3610 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au32[2];
3611}
3612
3613
3614IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3615{
3616 pXState->x87.aXMM[iYRegDst].au32[0] = pSrc->au32[0];
3617 pXState->x87.aXMM[iYRegDst].au32[1] = pSrc->au32[0];
3618 pXState->x87.aXMM[iYRegDst].au32[2] = pSrc->au32[2];
3619 pXState->x87.aXMM[iYRegDst].au32[3] = pSrc->au32[2];
3620 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[0] = pSrc->au32[4];
3621 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[1] = pSrc->au32[4];
3622 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[2] = pSrc->au32[6];
3623 pXState->u.YmmHi.aYmmHi[iYRegDst].au32[3] = pSrc->au32[6];
3624}
3625
3626#endif /* IEM_WITH_VEX */
3627
3628
3629IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc))
3630{
3631 RT_NOREF(pFpuState);
3632 puDst->au32[0] = puSrc->au32[1];
3633 puDst->au32[1] = puSrc->au32[1];
3634 puDst->au32[2] = puSrc->au32[3];
3635 puDst->au32[3] = puSrc->au32[3];
3636}
3637
3638
3639IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc))
3640{
3641 RT_NOREF(pFpuState);
3642 puDst->au64[0] = uSrc;
3643 puDst->au64[1] = uSrc;
3644}
3645
3646#ifdef IEM_WITH_VEX
3647
3648IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc))
3649{
3650 pXState->x87.aXMM[iYRegDst].au64[0] = pXState->x87.aXMM[iYRegSrc].au64[0];
3651 pXState->x87.aXMM[iYRegDst].au64[1] = pXState->x87.aXMM[iYRegSrc].au64[0];
3652 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3653 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pXState->u.YmmHi.aYmmHi[iYRegSrc].au64[0];
3654}
3655
3656IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc))
3657{
3658 pXState->x87.aXMM[iYRegDst].au64[0] = pSrc->au64[0];
3659 pXState->x87.aXMM[iYRegDst].au64[1] = pSrc->au64[0];
3660 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[0] = pSrc->au64[2];
3661 pXState->u.YmmHi.aYmmHi[iYRegDst].au64[1] = pSrc->au64[2];
3662}
3663
3664#endif /* IEM_WITH_VEX */
3665
3666#ifdef IEM_WITHOUT_ASSEMBLY
3667
3668IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3669{
3670 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3671 AssertReleaseFailed();
3672}
3673
3674
3675IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqb_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3676{
3677 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3678 AssertReleaseFailed();
3679}
3680
3681
3682IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3683{
3684 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3685 AssertReleaseFailed();
3686}
3687
3688
3689IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3690{
3691 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3692 AssertReleaseFailed();
3693}
3694
3695
3696IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3697{
3698 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3699 AssertReleaseFailed();
3700}
3701
3702
3703IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpeqd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3704{
3705 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3706 AssertReleaseFailed();
3707}
3708
3709
3710IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3711{
3712 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3713 AssertReleaseFailed();
3714}
3715
3716
3717IEM_DECL_IMPL_DEF(void, iemAImpl_pxor_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3718{
3719 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3720 AssertReleaseFailed();
3721}
3722
3723
3724IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3725{
3726 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3727 AssertReleaseFailed();
3728
3729}
3730
3731
3732IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src))
3733{
3734 RT_NOREF(pFpuState, pu64Dst, pu128Src);
3735 AssertReleaseFailed();
3736}
3737
3738
3739IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src, uint8_t bEvil))
3740{
3741 RT_NOREF(pFpuState, pu64Dst, pu64Src, bEvil);
3742 AssertReleaseFailed();
3743}
3744
3745
3746IEM_DECL_IMPL_DEF(void, iemAImpl_pshufhw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3747{
3748 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3749 AssertReleaseFailed();
3750}
3751
3752
3753IEM_DECL_IMPL_DEF(void, iemAImpl_pshuflw,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3754{
3755 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3756 AssertReleaseFailed();
3757}
3758
3759
3760IEM_DECL_IMPL_DEF(void, iemAImpl_pshufd,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src, uint8_t bEvil))
3761{
3762 RT_NOREF(pFpuState, pu128Dst, pu128Src, bEvil);
3763 AssertReleaseFailed();
3764}
3765
3766/* PUNPCKHxxx */
3767
3768IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3769{
3770 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3771 AssertReleaseFailed();
3772}
3773
3774
3775IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3776{
3777 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3778 AssertReleaseFailed();
3779}
3780
3781
3782IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3783{
3784 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3785 AssertReleaseFailed();
3786}
3787
3788
3789IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3790{
3791 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3792 AssertReleaseFailed();
3793}
3794
3795
3796IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint64_t const *pu64Src))
3797{
3798 RT_NOREF(pFpuState, pu64Dst, pu64Src);
3799 AssertReleaseFailed();
3800}
3801
3802
3803IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3804{
3805 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3806 AssertReleaseFailed();
3807}
3808
3809
3810IEM_DECL_IMPL_DEF(void, iemAImpl_punpckhqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src))
3811{
3812 RT_NOREF(pFpuState, pu128Dst, pu128Src);
3813 AssertReleaseFailed();
3814}
3815
3816/* PUNPCKLxxx */
3817
3818IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3819{
3820 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3821 AssertReleaseFailed();
3822}
3823
3824
3825IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklbw_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3826{
3827 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3828 AssertReleaseFailed();
3829}
3830
3831
3832IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3833{
3834 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3835 AssertReleaseFailed();
3836}
3837
3838
3839IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklwd_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3840{
3841 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3842 AssertReleaseFailed();
3843}
3844
3845
3846IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u64,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, uint32_t const *pu32Src))
3847{
3848 RT_NOREF(pFpuState, pu64Dst, pu32Src);
3849 AssertReleaseFailed();
3850}
3851
3852
3853IEM_DECL_IMPL_DEF(void, iemAImpl_punpckldq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3854{
3855 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3856 AssertReleaseFailed();
3857}
3858
3859
3860IEM_DECL_IMPL_DEF(void, iemAImpl_punpcklqdq_u128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src))
3861{
3862 RT_NOREF(pFpuState, pu128Dst, pu64Src);
3863 AssertReleaseFailed();
3864}
3865
3866#endif /* IEM_WITHOUT_ASSEMBLY */
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