VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h@ 74578

Last change on this file since 74578 was 74573, checked in by vboxsync, 7 years ago

IEM: LAR/LSL must work with system descriptors, too.
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1/* $Id: IEMAllCImpl.cpp.h 74573 2018-10-02 09:34:42Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#include "IEMAllCImplSvmInstr.cpp.h"
19#include "IEMAllCImplVmxInstr.cpp.h"
20
21
22/** @name Misc Helpers
23 * @{
24 */
25
26
27/**
28 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
29 *
30 * @returns Strict VBox status code.
31 *
32 * @param pVCpu The cross context virtual CPU structure of the calling thread.
33 * @param u16Port The port number.
34 * @param cbOperand The operand size.
35 */
36static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbOperand)
37{
38 /* The TSS bits we're interested in are the same on 386 and AMD64. */
39 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
40 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
41 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
42 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
43
44 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
45
46 /*
47 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
48 */
49 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
50 if (RT_UNLIKELY( pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
51 && pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
52 {
53 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
54 u16Port, cbOperand, pVCpu->cpum.GstCtx.tr.Attr.n.u4Type, pVCpu->cpum.GstCtx.tr.Attr.u));
55 return iemRaiseGeneralProtectionFault0(pVCpu);
56 }
57
58 /*
59 * Read the bitmap offset (may #PF).
60 */
61 uint16_t offBitmap;
62 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
63 pVCpu->cpum.GstCtx.tr.u64Base + RT_UOFFSETOF(X86TSS64, offIoBitmap));
64 if (rcStrict != VINF_SUCCESS)
65 {
66 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
67 return rcStrict;
68 }
69
70 /*
71 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
72 * describes the CPU actually reading two bytes regardless of whether the
73 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
74 */
75 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
76 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
77 * for instance sizeof(X86TSS32). */
78 if (offFirstBit + 1 > pVCpu->cpum.GstCtx.tr.u32Limit) /* the limit is inclusive */
79 {
80 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
81 offFirstBit, pVCpu->cpum.GstCtx.tr.u32Limit));
82 return iemRaiseGeneralProtectionFault0(pVCpu);
83 }
84
85 /*
86 * Read the necessary bits.
87 */
88 /** @todo Test the assertion in the intel manual that the CPU reads two
89 * bytes. The question is how this works wrt to #PF and #GP on the
90 * 2nd byte when it's not required. */
91 uint16_t bmBytes = UINT16_MAX;
92 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base + offFirstBit);
93 if (rcStrict != VINF_SUCCESS)
94 {
95 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
96 return rcStrict;
97 }
98
99 /*
100 * Perform the check.
101 */
102 uint16_t fPortMask = (1 << cbOperand) - 1;
103 bmBytes >>= (u16Port & 7);
104 if (bmBytes & fPortMask)
105 {
106 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
107 u16Port, cbOperand, bmBytes, fPortMask));
108 return iemRaiseGeneralProtectionFault0(pVCpu);
109 }
110
111 return VINF_SUCCESS;
112}
113
114
115/**
116 * Checks if we are allowed to access the given I/O port, raising the
117 * appropriate exceptions if we aren't (or if the I/O bitmap is not
118 * accessible).
119 *
120 * @returns Strict VBox status code.
121 *
122 * @param pVCpu The cross context virtual CPU structure of the calling thread.
123 * @param u16Port The port number.
124 * @param cbOperand The operand size.
125 */
126DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbOperand)
127{
128 X86EFLAGS Efl;
129 Efl.u = IEMMISC_GET_EFL(pVCpu);
130 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
131 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
132 || Efl.Bits.u1VM) )
133 return iemHlpCheckPortIOPermissionBitmap(pVCpu, u16Port, cbOperand);
134 return VINF_SUCCESS;
135}
136
137
138#if 0
139/**
140 * Calculates the parity bit.
141 *
142 * @returns true if the bit is set, false if not.
143 * @param u8Result The least significant byte of the result.
144 */
145static bool iemHlpCalcParityFlag(uint8_t u8Result)
146{
147 /*
148 * Parity is set if the number of bits in the least significant byte of
149 * the result is even.
150 */
151 uint8_t cBits;
152 cBits = u8Result & 1; /* 0 */
153 u8Result >>= 1;
154 cBits += u8Result & 1;
155 u8Result >>= 1;
156 cBits += u8Result & 1;
157 u8Result >>= 1;
158 cBits += u8Result & 1;
159 u8Result >>= 1;
160 cBits += u8Result & 1; /* 4 */
161 u8Result >>= 1;
162 cBits += u8Result & 1;
163 u8Result >>= 1;
164 cBits += u8Result & 1;
165 u8Result >>= 1;
166 cBits += u8Result & 1;
167 return !(cBits & 1);
168}
169#endif /* not used */
170
171
172/**
173 * Updates the specified flags according to a 8-bit result.
174 *
175 * @param pVCpu The cross context virtual CPU structure of the calling thread.
176 * @param u8Result The result to set the flags according to.
177 * @param fToUpdate The flags to update.
178 * @param fUndefined The flags that are specified as undefined.
179 */
180static void iemHlpUpdateArithEFlagsU8(PVMCPU pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
181{
182 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
183 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
184 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
185 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
186}
187
188
189/**
190 * Updates the specified flags according to a 16-bit result.
191 *
192 * @param pVCpu The cross context virtual CPU structure of the calling thread.
193 * @param u16Result The result to set the flags according to.
194 * @param fToUpdate The flags to update.
195 * @param fUndefined The flags that are specified as undefined.
196 */
197static void iemHlpUpdateArithEFlagsU16(PVMCPU pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
198{
199 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
200 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
201 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
202 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
203}
204
205
206/**
207 * Helper used by iret.
208 *
209 * @param pVCpu The cross context virtual CPU structure of the calling thread.
210 * @param uCpl The new CPL.
211 * @param pSReg Pointer to the segment register.
212 */
213static void iemHlpAdjustSelectorForNewCpl(PVMCPU pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
214{
215#ifdef VBOX_WITH_RAW_MODE_NOT_R0
216 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
217 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSReg);
218#else
219 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
220#endif
221 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
222
223 if ( uCpl > pSReg->Attr.n.u2Dpl
224 && pSReg->Attr.n.u1DescType /* code or data, not system */
225 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
226 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
227 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
228}
229
230
231/**
232 * Indicates that we have modified the FPU state.
233 *
234 * @param pVCpu The cross context virtual CPU structure of the calling thread.
235 */
236DECLINLINE(void) iemHlpUsedFpu(PVMCPU pVCpu)
237{
238 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
239}
240
241/** @} */
242
243/** @name C Implementations
244 * @{
245 */
246
247/**
248 * Implements a 16-bit popa.
249 */
250IEM_CIMPL_DEF_0(iemCImpl_popa_16)
251{
252 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
253 RTGCPTR GCPtrLast = GCPtrStart + 15;
254 VBOXSTRICTRC rcStrict;
255
256 /*
257 * The docs are a bit hard to comprehend here, but it looks like we wrap
258 * around in real mode as long as none of the individual "popa" crosses the
259 * end of the stack segment. In protected mode we check the whole access
260 * in one go. For efficiency, only do the word-by-word thing if we're in
261 * danger of wrapping around.
262 */
263 /** @todo do popa boundary / wrap-around checks. */
264 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
265 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
266 {
267 /* word-by-word */
268 RTUINT64U TmpRsp;
269 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
270 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.di, &TmpRsp);
271 if (rcStrict == VINF_SUCCESS)
272 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.si, &TmpRsp);
273 if (rcStrict == VINF_SUCCESS)
274 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bp, &TmpRsp);
275 if (rcStrict == VINF_SUCCESS)
276 {
277 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
278 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bx, &TmpRsp);
279 }
280 if (rcStrict == VINF_SUCCESS)
281 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.dx, &TmpRsp);
282 if (rcStrict == VINF_SUCCESS)
283 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.cx, &TmpRsp);
284 if (rcStrict == VINF_SUCCESS)
285 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.ax, &TmpRsp);
286 if (rcStrict == VINF_SUCCESS)
287 {
288 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
290 }
291 }
292 else
293 {
294 uint16_t const *pa16Mem = NULL;
295 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
296 if (rcStrict == VINF_SUCCESS)
297 {
298 pVCpu->cpum.GstCtx.di = pa16Mem[7 - X86_GREG_xDI];
299 pVCpu->cpum.GstCtx.si = pa16Mem[7 - X86_GREG_xSI];
300 pVCpu->cpum.GstCtx.bp = pa16Mem[7 - X86_GREG_xBP];
301 /* skip sp */
302 pVCpu->cpum.GstCtx.bx = pa16Mem[7 - X86_GREG_xBX];
303 pVCpu->cpum.GstCtx.dx = pa16Mem[7 - X86_GREG_xDX];
304 pVCpu->cpum.GstCtx.cx = pa16Mem[7 - X86_GREG_xCX];
305 pVCpu->cpum.GstCtx.ax = pa16Mem[7 - X86_GREG_xAX];
306 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
307 if (rcStrict == VINF_SUCCESS)
308 {
309 iemRegAddToRsp(pVCpu, 16);
310 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
311 }
312 }
313 }
314 return rcStrict;
315}
316
317
318/**
319 * Implements a 32-bit popa.
320 */
321IEM_CIMPL_DEF_0(iemCImpl_popa_32)
322{
323 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
324 RTGCPTR GCPtrLast = GCPtrStart + 31;
325 VBOXSTRICTRC rcStrict;
326
327 /*
328 * The docs are a bit hard to comprehend here, but it looks like we wrap
329 * around in real mode as long as none of the individual "popa" crosses the
330 * end of the stack segment. In protected mode we check the whole access
331 * in one go. For efficiency, only do the word-by-word thing if we're in
332 * danger of wrapping around.
333 */
334 /** @todo do popa boundary / wrap-around checks. */
335 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
336 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
337 {
338 /* word-by-word */
339 RTUINT64U TmpRsp;
340 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
341 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edi, &TmpRsp);
342 if (rcStrict == VINF_SUCCESS)
343 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.esi, &TmpRsp);
344 if (rcStrict == VINF_SUCCESS)
345 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebp, &TmpRsp);
346 if (rcStrict == VINF_SUCCESS)
347 {
348 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
349 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebx, &TmpRsp);
350 }
351 if (rcStrict == VINF_SUCCESS)
352 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edx, &TmpRsp);
353 if (rcStrict == VINF_SUCCESS)
354 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ecx, &TmpRsp);
355 if (rcStrict == VINF_SUCCESS)
356 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.eax, &TmpRsp);
357 if (rcStrict == VINF_SUCCESS)
358 {
359#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
360 pVCpu->cpum.GstCtx.rdi &= UINT32_MAX;
361 pVCpu->cpum.GstCtx.rsi &= UINT32_MAX;
362 pVCpu->cpum.GstCtx.rbp &= UINT32_MAX;
363 pVCpu->cpum.GstCtx.rbx &= UINT32_MAX;
364 pVCpu->cpum.GstCtx.rdx &= UINT32_MAX;
365 pVCpu->cpum.GstCtx.rcx &= UINT32_MAX;
366 pVCpu->cpum.GstCtx.rax &= UINT32_MAX;
367#endif
368 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
370 }
371 }
372 else
373 {
374 uint32_t const *pa32Mem;
375 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
376 if (rcStrict == VINF_SUCCESS)
377 {
378 pVCpu->cpum.GstCtx.rdi = pa32Mem[7 - X86_GREG_xDI];
379 pVCpu->cpum.GstCtx.rsi = pa32Mem[7 - X86_GREG_xSI];
380 pVCpu->cpum.GstCtx.rbp = pa32Mem[7 - X86_GREG_xBP];
381 /* skip esp */
382 pVCpu->cpum.GstCtx.rbx = pa32Mem[7 - X86_GREG_xBX];
383 pVCpu->cpum.GstCtx.rdx = pa32Mem[7 - X86_GREG_xDX];
384 pVCpu->cpum.GstCtx.rcx = pa32Mem[7 - X86_GREG_xCX];
385 pVCpu->cpum.GstCtx.rax = pa32Mem[7 - X86_GREG_xAX];
386 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
387 if (rcStrict == VINF_SUCCESS)
388 {
389 iemRegAddToRsp(pVCpu, 32);
390 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
391 }
392 }
393 }
394 return rcStrict;
395}
396
397
398/**
399 * Implements a 16-bit pusha.
400 */
401IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
402{
403 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
404 RTGCPTR GCPtrBottom = GCPtrTop - 15;
405 VBOXSTRICTRC rcStrict;
406
407 /*
408 * The docs are a bit hard to comprehend here, but it looks like we wrap
409 * around in real mode as long as none of the individual "pushd" crosses the
410 * end of the stack segment. In protected mode we check the whole access
411 * in one go. For efficiency, only do the word-by-word thing if we're in
412 * danger of wrapping around.
413 */
414 /** @todo do pusha boundary / wrap-around checks. */
415 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
416 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
417 {
418 /* word-by-word */
419 RTUINT64U TmpRsp;
420 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
421 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.ax, &TmpRsp);
422 if (rcStrict == VINF_SUCCESS)
423 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.cx, &TmpRsp);
424 if (rcStrict == VINF_SUCCESS)
425 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.dx, &TmpRsp);
426 if (rcStrict == VINF_SUCCESS)
427 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bx, &TmpRsp);
428 if (rcStrict == VINF_SUCCESS)
429 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.sp, &TmpRsp);
430 if (rcStrict == VINF_SUCCESS)
431 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bp, &TmpRsp);
432 if (rcStrict == VINF_SUCCESS)
433 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.si, &TmpRsp);
434 if (rcStrict == VINF_SUCCESS)
435 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.di, &TmpRsp);
436 if (rcStrict == VINF_SUCCESS)
437 {
438 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
440 }
441 }
442 else
443 {
444 GCPtrBottom--;
445 uint16_t *pa16Mem = NULL;
446 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
447 if (rcStrict == VINF_SUCCESS)
448 {
449 pa16Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.di;
450 pa16Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.si;
451 pa16Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.bp;
452 pa16Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.sp;
453 pa16Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.bx;
454 pa16Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.dx;
455 pa16Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.cx;
456 pa16Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.ax;
457 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
458 if (rcStrict == VINF_SUCCESS)
459 {
460 iemRegSubFromRsp(pVCpu, 16);
461 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
462 }
463 }
464 }
465 return rcStrict;
466}
467
468
469/**
470 * Implements a 32-bit pusha.
471 */
472IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
473{
474 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
475 RTGCPTR GCPtrBottom = GCPtrTop - 31;
476 VBOXSTRICTRC rcStrict;
477
478 /*
479 * The docs are a bit hard to comprehend here, but it looks like we wrap
480 * around in real mode as long as none of the individual "pusha" crosses the
481 * end of the stack segment. In protected mode we check the whole access
482 * in one go. For efficiency, only do the word-by-word thing if we're in
483 * danger of wrapping around.
484 */
485 /** @todo do pusha boundary / wrap-around checks. */
486 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
487 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
488 {
489 /* word-by-word */
490 RTUINT64U TmpRsp;
491 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
492 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.eax, &TmpRsp);
493 if (rcStrict == VINF_SUCCESS)
494 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ecx, &TmpRsp);
495 if (rcStrict == VINF_SUCCESS)
496 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edx, &TmpRsp);
497 if (rcStrict == VINF_SUCCESS)
498 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebx, &TmpRsp);
499 if (rcStrict == VINF_SUCCESS)
500 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esp, &TmpRsp);
501 if (rcStrict == VINF_SUCCESS)
502 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebp, &TmpRsp);
503 if (rcStrict == VINF_SUCCESS)
504 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esi, &TmpRsp);
505 if (rcStrict == VINF_SUCCESS)
506 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edi, &TmpRsp);
507 if (rcStrict == VINF_SUCCESS)
508 {
509 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
510 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
511 }
512 }
513 else
514 {
515 GCPtrBottom--;
516 uint32_t *pa32Mem;
517 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
518 if (rcStrict == VINF_SUCCESS)
519 {
520 pa32Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.edi;
521 pa32Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.esi;
522 pa32Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.ebp;
523 pa32Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.esp;
524 pa32Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.ebx;
525 pa32Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.edx;
526 pa32Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.ecx;
527 pa32Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.eax;
528 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
529 if (rcStrict == VINF_SUCCESS)
530 {
531 iemRegSubFromRsp(pVCpu, 32);
532 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
533 }
534 }
535 }
536 return rcStrict;
537}
538
539
540/**
541 * Implements pushf.
542 *
543 *
544 * @param enmEffOpSize The effective operand size.
545 */
546IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
547{
548 VBOXSTRICTRC rcStrict;
549
550 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
551 {
552 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
553 IEM_SVM_UPDATE_NRIP(pVCpu);
554 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
555 }
556
557 /*
558 * If we're in V8086 mode some care is required (which is why we're in
559 * doing this in a C implementation).
560 */
561 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
562 if ( (fEfl & X86_EFL_VM)
563 && X86_EFL_GET_IOPL(fEfl) != 3 )
564 {
565 Assert(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE);
566 if ( enmEffOpSize != IEMMODE_16BIT
567 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
568 return iemRaiseGeneralProtectionFault0(pVCpu);
569 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
570 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
571 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
572 }
573 else
574 {
575
576 /*
577 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
578 */
579 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
580
581 switch (enmEffOpSize)
582 {
583 case IEMMODE_16BIT:
584 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
585 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
586 fEfl |= UINT16_C(0xf000);
587 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
588 break;
589 case IEMMODE_32BIT:
590 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
591 break;
592 case IEMMODE_64BIT:
593 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
594 break;
595 IEM_NOT_REACHED_DEFAULT_CASE_RET();
596 }
597 }
598 if (rcStrict != VINF_SUCCESS)
599 return rcStrict;
600
601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
602 return VINF_SUCCESS;
603}
604
605
606/**
607 * Implements popf.
608 *
609 * @param enmEffOpSize The effective operand size.
610 */
611IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
612{
613 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu);
614 VBOXSTRICTRC rcStrict;
615 uint32_t fEflNew;
616
617 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
618 {
619 Log2(("popf: Guest intercept -> #VMEXIT\n"));
620 IEM_SVM_UPDATE_NRIP(pVCpu);
621 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
622 }
623
624 /*
625 * V8086 is special as usual.
626 */
627 if (fEflOld & X86_EFL_VM)
628 {
629 /*
630 * Almost anything goes if IOPL is 3.
631 */
632 if (X86_EFL_GET_IOPL(fEflOld) == 3)
633 {
634 switch (enmEffOpSize)
635 {
636 case IEMMODE_16BIT:
637 {
638 uint16_t u16Value;
639 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
640 if (rcStrict != VINF_SUCCESS)
641 return rcStrict;
642 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
643 break;
644 }
645 case IEMMODE_32BIT:
646 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
647 if (rcStrict != VINF_SUCCESS)
648 return rcStrict;
649 break;
650 IEM_NOT_REACHED_DEFAULT_CASE_RET();
651 }
652
653 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
654 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
655 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
656 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
657 }
658 /*
659 * Interrupt flag virtualization with CR4.VME=1.
660 */
661 else if ( enmEffOpSize == IEMMODE_16BIT
662 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
663 {
664 uint16_t u16Value;
665 RTUINT64U TmpRsp;
666 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
667 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
668 if (rcStrict != VINF_SUCCESS)
669 return rcStrict;
670
671 /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
672 * or before? */
673 if ( ( (u16Value & X86_EFL_IF)
674 && (fEflOld & X86_EFL_VIP))
675 || (u16Value & X86_EFL_TF) )
676 return iemRaiseGeneralProtectionFault0(pVCpu);
677
678 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
679 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
680 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
681 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
682
683 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
684 }
685 else
686 return iemRaiseGeneralProtectionFault0(pVCpu);
687
688 }
689 /*
690 * Not in V8086 mode.
691 */
692 else
693 {
694 /* Pop the flags. */
695 switch (enmEffOpSize)
696 {
697 case IEMMODE_16BIT:
698 {
699 uint16_t u16Value;
700 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
701 if (rcStrict != VINF_SUCCESS)
702 return rcStrict;
703 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
704
705 /*
706 * Ancient CPU adjustments:
707 * - 8086, 80186, V20/30:
708 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
709 * practical reasons (masking below). We add them when pushing flags.
710 * - 80286:
711 * The NT and IOPL flags cannot be popped from real mode and are
712 * therefore always zero (since a 286 can never exit from PM and
713 * their initial value is zero). This changed on a 386 and can
714 * therefore be used to detect 286 or 386 CPU in real mode.
715 */
716 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
717 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
718 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
719 break;
720 }
721 case IEMMODE_32BIT:
722 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
723 if (rcStrict != VINF_SUCCESS)
724 return rcStrict;
725 break;
726 case IEMMODE_64BIT:
727 {
728 uint64_t u64Value;
729 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
730 if (rcStrict != VINF_SUCCESS)
731 return rcStrict;
732 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
733 break;
734 }
735 IEM_NOT_REACHED_DEFAULT_CASE_RET();
736 }
737
738 /* Merge them with the current flags. */
739 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
740 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
741 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
742 || pVCpu->iem.s.uCpl == 0)
743 {
744 fEflNew &= fPopfBits;
745 fEflNew |= ~fPopfBits & fEflOld;
746 }
747 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
748 {
749 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
750 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
751 }
752 else
753 {
754 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
755 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
756 }
757 }
758
759 /*
760 * Commit the flags.
761 */
762 Assert(fEflNew & RT_BIT_32(1));
763 IEMMISC_SET_EFL(pVCpu, fEflNew);
764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
765
766 return VINF_SUCCESS;
767}
768
769
770/**
771 * Implements an indirect call.
772 *
773 * @param uNewPC The new program counter (RIP) value (loaded from the
774 * operand).
775 * @param enmEffOpSize The effective operand size.
776 */
777IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
778{
779 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
780 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
781 return iemRaiseGeneralProtectionFault0(pVCpu);
782
783 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
784 if (rcStrict != VINF_SUCCESS)
785 return rcStrict;
786
787 pVCpu->cpum.GstCtx.rip = uNewPC;
788 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
789
790#ifndef IEM_WITH_CODE_TLB
791 /* Flush the prefetch buffer. */
792 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
793#endif
794 return VINF_SUCCESS;
795}
796
797
798/**
799 * Implements a 16-bit relative call.
800 *
801 * @param offDisp The displacment offset.
802 */
803IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
804{
805 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
806 uint16_t uNewPC = uOldPC + offDisp;
807 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
808 return iemRaiseGeneralProtectionFault0(pVCpu);
809
810 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
811 if (rcStrict != VINF_SUCCESS)
812 return rcStrict;
813
814 pVCpu->cpum.GstCtx.rip = uNewPC;
815 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
816
817#ifndef IEM_WITH_CODE_TLB
818 /* Flush the prefetch buffer. */
819 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
820#endif
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Implements a 32-bit indirect call.
827 *
828 * @param uNewPC The new program counter (RIP) value (loaded from the
829 * operand).
830 * @param enmEffOpSize The effective operand size.
831 */
832IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
833{
834 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
835 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
836 return iemRaiseGeneralProtectionFault0(pVCpu);
837
838 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
839 if (rcStrict != VINF_SUCCESS)
840 return rcStrict;
841
842#if defined(IN_RING3) && defined(VBOX_WITH_RAW_MODE) && defined(VBOX_WITH_CALL_RECORD)
843 /*
844 * CASM hook for recording interesting indirect calls.
845 */
846 if ( !pVCpu->cpum.GstCtx.eflags.Bits.u1IF
847 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
848 && !CSAMIsEnabled(pVCpu->CTX_SUFF(pVM))
849 && pVCpu->iem.s.uCpl == 0)
850 {
851 EMSTATE enmState = EMGetState(pVCpu);
852 if ( enmState == EMSTATE_IEM_THEN_REM
853 || enmState == EMSTATE_IEM
854 || enmState == EMSTATE_REM)
855 CSAMR3RecordCallAddress(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.eip);
856 }
857#endif
858
859 pVCpu->cpum.GstCtx.rip = uNewPC;
860 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
861
862#ifndef IEM_WITH_CODE_TLB
863 /* Flush the prefetch buffer. */
864 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
865#endif
866 return VINF_SUCCESS;
867}
868
869
870/**
871 * Implements a 32-bit relative call.
872 *
873 * @param offDisp The displacment offset.
874 */
875IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
876{
877 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
878 uint32_t uNewPC = uOldPC + offDisp;
879 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
880 return iemRaiseGeneralProtectionFault0(pVCpu);
881
882 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
883 if (rcStrict != VINF_SUCCESS)
884 return rcStrict;
885
886 pVCpu->cpum.GstCtx.rip = uNewPC;
887 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
888
889#ifndef IEM_WITH_CODE_TLB
890 /* Flush the prefetch buffer. */
891 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
892#endif
893 return VINF_SUCCESS;
894}
895
896
897/**
898 * Implements a 64-bit indirect call.
899 *
900 * @param uNewPC The new program counter (RIP) value (loaded from the
901 * operand).
902 * @param enmEffOpSize The effective operand size.
903 */
904IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
905{
906 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
907 if (!IEM_IS_CANONICAL(uNewPC))
908 return iemRaiseGeneralProtectionFault0(pVCpu);
909
910 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
911 if (rcStrict != VINF_SUCCESS)
912 return rcStrict;
913
914 pVCpu->cpum.GstCtx.rip = uNewPC;
915 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
916
917#ifndef IEM_WITH_CODE_TLB
918 /* Flush the prefetch buffer. */
919 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
920#endif
921 return VINF_SUCCESS;
922}
923
924
925/**
926 * Implements a 64-bit relative call.
927 *
928 * @param offDisp The displacment offset.
929 */
930IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
931{
932 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
933 uint64_t uNewPC = uOldPC + offDisp;
934 if (!IEM_IS_CANONICAL(uNewPC))
935 return iemRaiseNotCanonical(pVCpu);
936
937 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
938 if (rcStrict != VINF_SUCCESS)
939 return rcStrict;
940
941 pVCpu->cpum.GstCtx.rip = uNewPC;
942 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
943
944#ifndef IEM_WITH_CODE_TLB
945 /* Flush the prefetch buffer. */
946 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
947#endif
948
949 return VINF_SUCCESS;
950}
951
952
953/**
954 * Implements far jumps and calls thru task segments (TSS).
955 *
956 * @param uSel The selector.
957 * @param enmBranch The kind of branching we're performing.
958 * @param enmEffOpSize The effective operand size.
959 * @param pDesc The descriptor corresponding to @a uSel. The type is
960 * task gate.
961 */
962IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
963{
964#ifndef IEM_IMPLEMENTS_TASKSWITCH
965 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
966#else
967 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
968 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
969 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
970 RT_NOREF_PV(enmEffOpSize);
971 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
972
973 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
974 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
975 {
976 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
977 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
978 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
979 }
980
981 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
982 * far calls (see iemCImpl_callf). Most likely in both cases it should be
983 * checked here, need testcases. */
984 if (!pDesc->Legacy.Gen.u1Present)
985 {
986 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
987 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
988 }
989
990 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
991 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
992 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
993#endif
994}
995
996
997/**
998 * Implements far jumps and calls thru task gates.
999 *
1000 * @param uSel The selector.
1001 * @param enmBranch The kind of branching we're performing.
1002 * @param enmEffOpSize The effective operand size.
1003 * @param pDesc The descriptor corresponding to @a uSel. The type is
1004 * task gate.
1005 */
1006IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1007{
1008#ifndef IEM_IMPLEMENTS_TASKSWITCH
1009 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1010#else
1011 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1012 RT_NOREF_PV(enmEffOpSize);
1013 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1014
1015 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1016 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1017 {
1018 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1019 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1020 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1021 }
1022
1023 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1024 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1025 * checked here, need testcases. */
1026 if (!pDesc->Legacy.Gen.u1Present)
1027 {
1028 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1029 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1030 }
1031
1032 /*
1033 * Fetch the new TSS descriptor from the GDT.
1034 */
1035 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1036 if (uSelTss & X86_SEL_LDT)
1037 {
1038 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1039 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1040 }
1041
1042 IEMSELDESC TssDesc;
1043 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1044 if (rcStrict != VINF_SUCCESS)
1045 return rcStrict;
1046
1047 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1048 {
1049 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1050 TssDesc.Legacy.Gate.u4Type));
1051 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1052 }
1053
1054 if (!TssDesc.Legacy.Gate.u1Present)
1055 {
1056 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1057 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1058 }
1059
1060 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1061 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1062 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1063#endif
1064}
1065
1066
1067/**
1068 * Implements far jumps and calls thru call gates.
1069 *
1070 * @param uSel The selector.
1071 * @param enmBranch The kind of branching we're performing.
1072 * @param enmEffOpSize The effective operand size.
1073 * @param pDesc The descriptor corresponding to @a uSel. The type is
1074 * call gate.
1075 */
1076IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1077{
1078#define IEM_IMPLEMENTS_CALLGATE
1079#ifndef IEM_IMPLEMENTS_CALLGATE
1080 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1081#else
1082 RT_NOREF_PV(enmEffOpSize);
1083 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1084
1085 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1086 * inter-privilege calls and are much more complex.
1087 *
1088 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1089 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1090 * must be 16-bit or 32-bit.
1091 */
1092 /** @todo: effective operand size is probably irrelevant here, only the
1093 * call gate bitness matters??
1094 */
1095 VBOXSTRICTRC rcStrict;
1096 RTPTRUNION uPtrRet;
1097 uint64_t uNewRsp;
1098 uint64_t uNewRip;
1099 uint64_t u64Base;
1100 uint32_t cbLimit;
1101 RTSEL uNewCS;
1102 IEMSELDESC DescCS;
1103
1104 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1105 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1106 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1107 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1108
1109 /* Determine the new instruction pointer from the gate descriptor. */
1110 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1111 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1112 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1113
1114 /* Perform DPL checks on the gate descriptor. */
1115 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1116 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1117 {
1118 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1119 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1120 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1121 }
1122
1123 /** @todo does this catch NULL selectors, too? */
1124 if (!pDesc->Legacy.Gen.u1Present)
1125 {
1126 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1127 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1128 }
1129
1130 /*
1131 * Fetch the target CS descriptor from the GDT or LDT.
1132 */
1133 uNewCS = pDesc->Legacy.Gate.u16Sel;
1134 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1135 if (rcStrict != VINF_SUCCESS)
1136 return rcStrict;
1137
1138 /* Target CS must be a code selector. */
1139 if ( !DescCS.Legacy.Gen.u1DescType
1140 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1141 {
1142 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1143 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1144 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1145 }
1146
1147 /* Privilege checks on target CS. */
1148 if (enmBranch == IEMBRANCH_JUMP)
1149 {
1150 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1151 {
1152 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1153 {
1154 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1155 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1156 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1157 }
1158 }
1159 else
1160 {
1161 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1162 {
1163 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1164 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1165 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1166 }
1167 }
1168 }
1169 else
1170 {
1171 Assert(enmBranch == IEMBRANCH_CALL);
1172 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1173 {
1174 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1175 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1176 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1177 }
1178 }
1179
1180 /* Additional long mode checks. */
1181 if (IEM_IS_LONG_MODE(pVCpu))
1182 {
1183 if (!DescCS.Legacy.Gen.u1Long)
1184 {
1185 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1186 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1187 }
1188
1189 /* L vs D. */
1190 if ( DescCS.Legacy.Gen.u1Long
1191 && DescCS.Legacy.Gen.u1DefBig)
1192 {
1193 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1194 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1195 }
1196 }
1197
1198 if (!DescCS.Legacy.Gate.u1Present)
1199 {
1200 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1201 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1202 }
1203
1204 if (enmBranch == IEMBRANCH_JUMP)
1205 {
1206 /** @todo: This is very similar to regular far jumps; merge! */
1207 /* Jumps are fairly simple... */
1208
1209 /* Chop the high bits off if 16-bit gate (Intel says so). */
1210 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1211 uNewRip = (uint16_t)uNewRip;
1212
1213 /* Limit check for non-long segments. */
1214 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1215 if (DescCS.Legacy.Gen.u1Long)
1216 u64Base = 0;
1217 else
1218 {
1219 if (uNewRip > cbLimit)
1220 {
1221 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1222 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1223 }
1224 u64Base = X86DESC_BASE(&DescCS.Legacy);
1225 }
1226
1227 /* Canonical address check. */
1228 if (!IEM_IS_CANONICAL(uNewRip))
1229 {
1230 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1231 return iemRaiseNotCanonical(pVCpu);
1232 }
1233
1234 /*
1235 * Ok, everything checked out fine. Now set the accessed bit before
1236 * committing the result into CS, CSHID and RIP.
1237 */
1238 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1239 {
1240 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1241 if (rcStrict != VINF_SUCCESS)
1242 return rcStrict;
1243 /** @todo check what VT-x and AMD-V does. */
1244 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1245 }
1246
1247 /* commit */
1248 pVCpu->cpum.GstCtx.rip = uNewRip;
1249 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1250 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1251 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1252 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1253 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1254 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1255 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1256 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1257 }
1258 else
1259 {
1260 Assert(enmBranch == IEMBRANCH_CALL);
1261 /* Calls are much more complicated. */
1262
1263 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1264 {
1265 uint16_t offNewStack; /* Offset of new stack in TSS. */
1266 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1267 uint8_t uNewCSDpl;
1268 uint8_t cbWords;
1269 RTSEL uNewSS;
1270 RTSEL uOldSS;
1271 uint64_t uOldRsp;
1272 IEMSELDESC DescSS;
1273 RTPTRUNION uPtrTSS;
1274 RTGCPTR GCPtrTSS;
1275 RTPTRUNION uPtrParmWds;
1276 RTGCPTR GCPtrParmWds;
1277
1278 /* More privilege. This is the fun part. */
1279 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1280
1281 /*
1282 * Determine new SS:rSP from the TSS.
1283 */
1284 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
1285
1286 /* Figure out where the new stack pointer is stored in the TSS. */
1287 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1288 if (!IEM_IS_LONG_MODE(pVCpu))
1289 {
1290 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1291 {
1292 offNewStack = RT_UOFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1293 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1294 }
1295 else
1296 {
1297 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1298 offNewStack = RT_UOFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1299 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1300 }
1301 }
1302 else
1303 {
1304 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1305 offNewStack = RT_UOFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1306 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1307 }
1308
1309 /* Check against TSS limit. */
1310 if ((uint16_t)(offNewStack + cbNewStack - 1) > pVCpu->cpum.GstCtx.tr.u32Limit)
1311 {
1312 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pVCpu->cpum.GstCtx.tr.u32Limit));
1313 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pVCpu->cpum.GstCtx.tr.Sel);
1314 }
1315
1316 GCPtrTSS = pVCpu->cpum.GstCtx.tr.u64Base + offNewStack;
1317 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R);
1318 if (rcStrict != VINF_SUCCESS)
1319 {
1320 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1321 return rcStrict;
1322 }
1323
1324 if (!IEM_IS_LONG_MODE(pVCpu))
1325 {
1326 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1327 {
1328 uNewRsp = uPtrTSS.pu32[0];
1329 uNewSS = uPtrTSS.pu16[2];
1330 }
1331 else
1332 {
1333 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1334 uNewRsp = uPtrTSS.pu16[0];
1335 uNewSS = uPtrTSS.pu16[1];
1336 }
1337 }
1338 else
1339 {
1340 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1341 /* SS will be a NULL selector, but that's valid. */
1342 uNewRsp = uPtrTSS.pu64[0];
1343 uNewSS = uNewCSDpl;
1344 }
1345
1346 /* Done with the TSS now. */
1347 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1348 if (rcStrict != VINF_SUCCESS)
1349 {
1350 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1351 return rcStrict;
1352 }
1353
1354 /* Only used outside of long mode. */
1355 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1356
1357 /* If EFER.LMA is 0, there's extra work to do. */
1358 if (!IEM_IS_LONG_MODE(pVCpu))
1359 {
1360 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1361 {
1362 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1363 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1364 }
1365
1366 /* Grab the new SS descriptor. */
1367 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1368 if (rcStrict != VINF_SUCCESS)
1369 return rcStrict;
1370
1371 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1372 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1373 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1374 {
1375 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1376 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1377 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1378 }
1379
1380 /* Ensure new SS is a writable data segment. */
1381 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1382 {
1383 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1384 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1385 }
1386
1387 if (!DescSS.Legacy.Gen.u1Present)
1388 {
1389 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1390 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1391 }
1392 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1393 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1394 else
1395 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1396 }
1397 else
1398 {
1399 /* Just grab the new (NULL) SS descriptor. */
1400 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1401 * like we do... */
1402 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1403 if (rcStrict != VINF_SUCCESS)
1404 return rcStrict;
1405
1406 cbNewStack = sizeof(uint64_t) * 4;
1407 }
1408
1409 /** @todo: According to Intel, new stack is checked for enough space first,
1410 * then switched. According to AMD, the stack is switched first and
1411 * then pushes might fault!
1412 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1413 * incoming stack #PF happens before actual stack switch. AMD is
1414 * either lying or implicitly assumes that new state is committed
1415 * only if and when an instruction doesn't fault.
1416 */
1417
1418 /** @todo: According to AMD, CS is loaded first, then SS.
1419 * According to Intel, it's the other way around!?
1420 */
1421
1422 /** @todo: Intel and AMD disagree on when exactly the CPL changes! */
1423
1424 /* Set the accessed bit before committing new SS. */
1425 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1426 {
1427 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1428 if (rcStrict != VINF_SUCCESS)
1429 return rcStrict;
1430 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1431 }
1432
1433 /* Remember the old SS:rSP and their linear address. */
1434 uOldSS = pVCpu->cpum.GstCtx.ss.Sel;
1435 uOldRsp = pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig ? pVCpu->cpum.GstCtx.rsp : pVCpu->cpum.GstCtx.sp;
1436
1437 GCPtrParmWds = pVCpu->cpum.GstCtx.ss.u64Base + uOldRsp;
1438
1439 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1440 or #PF, the former is not implemented in this workaround. */
1441 /** @todo Proper fix callgate target stack exceptions. */
1442 /** @todo testcase: Cover callgates with partially or fully inaccessible
1443 * target stacks. */
1444 void *pvNewFrame;
1445 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1446 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW);
1447 if (rcStrict != VINF_SUCCESS)
1448 {
1449 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1450 return rcStrict;
1451 }
1452 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1453 if (rcStrict != VINF_SUCCESS)
1454 {
1455 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1456 return rcStrict;
1457 }
1458
1459 /* Commit new SS:rSP. */
1460 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
1461 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
1462 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1463 pVCpu->cpum.GstCtx.ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1464 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1465 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
1466 pVCpu->cpum.GstCtx.rsp = uNewRsp;
1467 pVCpu->iem.s.uCpl = uNewCSDpl;
1468 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
1469 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1470
1471 /* At this point the stack access must not fail because new state was already committed. */
1472 /** @todo this can still fail due to SS.LIMIT not check. */
1473 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1474 &uPtrRet.pv, &uNewRsp);
1475 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1476 VERR_INTERNAL_ERROR_5);
1477
1478 if (!IEM_IS_LONG_MODE(pVCpu))
1479 {
1480 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1481 {
1482 /* Push the old CS:rIP. */
1483 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1484 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1485
1486 if (cbWords)
1487 {
1488 /* Map the relevant chunk of the old stack. */
1489 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1490 if (rcStrict != VINF_SUCCESS)
1491 {
1492 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1493 return rcStrict;
1494 }
1495
1496 /* Copy the parameter (d)words. */
1497 for (int i = 0; i < cbWords; ++i)
1498 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1499
1500 /* Unmap the old stack. */
1501 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1502 if (rcStrict != VINF_SUCCESS)
1503 {
1504 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1505 return rcStrict;
1506 }
1507 }
1508
1509 /* Push the old SS:rSP. */
1510 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1511 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1512 }
1513 else
1514 {
1515 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1516
1517 /* Push the old CS:rIP. */
1518 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1519 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1520
1521 if (cbWords)
1522 {
1523 /* Map the relevant chunk of the old stack. */
1524 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1525 if (rcStrict != VINF_SUCCESS)
1526 {
1527 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1528 return rcStrict;
1529 }
1530
1531 /* Copy the parameter words. */
1532 for (int i = 0; i < cbWords; ++i)
1533 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1534
1535 /* Unmap the old stack. */
1536 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1537 if (rcStrict != VINF_SUCCESS)
1538 {
1539 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1540 return rcStrict;
1541 }
1542 }
1543
1544 /* Push the old SS:rSP. */
1545 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1546 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1547 }
1548 }
1549 else
1550 {
1551 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1552
1553 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1554 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1555 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1556 uPtrRet.pu64[2] = uOldRsp;
1557 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1558 }
1559
1560 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1561 if (rcStrict != VINF_SUCCESS)
1562 {
1563 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1564 return rcStrict;
1565 }
1566
1567 /* Chop the high bits off if 16-bit gate (Intel says so). */
1568 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1569 uNewRip = (uint16_t)uNewRip;
1570
1571 /* Limit / canonical check. */
1572 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1573 if (!IEM_IS_LONG_MODE(pVCpu))
1574 {
1575 if (uNewRip > cbLimit)
1576 {
1577 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1578 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1579 }
1580 u64Base = X86DESC_BASE(&DescCS.Legacy);
1581 }
1582 else
1583 {
1584 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1585 if (!IEM_IS_CANONICAL(uNewRip))
1586 {
1587 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1588 return iemRaiseNotCanonical(pVCpu);
1589 }
1590 u64Base = 0;
1591 }
1592
1593 /*
1594 * Now set the accessed bit before
1595 * writing the return address to the stack and committing the result into
1596 * CS, CSHID and RIP.
1597 */
1598 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1599 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1600 {
1601 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1602 if (rcStrict != VINF_SUCCESS)
1603 return rcStrict;
1604 /** @todo check what VT-x and AMD-V does. */
1605 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1606 }
1607
1608 /* Commit new CS:rIP. */
1609 pVCpu->cpum.GstCtx.rip = uNewRip;
1610 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1611 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1612 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1613 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1614 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1615 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1616 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1617 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1618 }
1619 else
1620 {
1621 /* Same privilege. */
1622 /** @todo: This is very similar to regular far calls; merge! */
1623
1624 /* Check stack first - may #SS(0). */
1625 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1626 * 16-bit code cause a two or four byte CS to be pushed? */
1627 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1628 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1629 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1630 &uPtrRet.pv, &uNewRsp);
1631 if (rcStrict != VINF_SUCCESS)
1632 return rcStrict;
1633
1634 /* Chop the high bits off if 16-bit gate (Intel says so). */
1635 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1636 uNewRip = (uint16_t)uNewRip;
1637
1638 /* Limit / canonical check. */
1639 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1640 if (!IEM_IS_LONG_MODE(pVCpu))
1641 {
1642 if (uNewRip > cbLimit)
1643 {
1644 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1645 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1646 }
1647 u64Base = X86DESC_BASE(&DescCS.Legacy);
1648 }
1649 else
1650 {
1651 if (!IEM_IS_CANONICAL(uNewRip))
1652 {
1653 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1654 return iemRaiseNotCanonical(pVCpu);
1655 }
1656 u64Base = 0;
1657 }
1658
1659 /*
1660 * Now set the accessed bit before
1661 * writing the return address to the stack and committing the result into
1662 * CS, CSHID and RIP.
1663 */
1664 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1665 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1666 {
1667 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1668 if (rcStrict != VINF_SUCCESS)
1669 return rcStrict;
1670 /** @todo check what VT-x and AMD-V does. */
1671 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1672 }
1673
1674 /* stack */
1675 if (!IEM_IS_LONG_MODE(pVCpu))
1676 {
1677 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1678 {
1679 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1680 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1681 }
1682 else
1683 {
1684 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1685 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1686 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1687 }
1688 }
1689 else
1690 {
1691 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1692 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1693 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1694 }
1695
1696 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1697 if (rcStrict != VINF_SUCCESS)
1698 return rcStrict;
1699
1700 /* commit */
1701 pVCpu->cpum.GstCtx.rip = uNewRip;
1702 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1703 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1704 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1705 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1706 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1707 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1708 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1709 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1710 }
1711 }
1712 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1713
1714 /* Flush the prefetch buffer. */
1715# ifdef IEM_WITH_CODE_TLB
1716 pVCpu->iem.s.pbInstrBuf = NULL;
1717# else
1718 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1719# endif
1720 return VINF_SUCCESS;
1721#endif
1722}
1723
1724
1725/**
1726 * Implements far jumps and calls thru system selectors.
1727 *
1728 * @param uSel The selector.
1729 * @param enmBranch The kind of branching we're performing.
1730 * @param enmEffOpSize The effective operand size.
1731 * @param pDesc The descriptor corresponding to @a uSel.
1732 */
1733IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1734{
1735 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1736 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1737 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1738
1739 if (IEM_IS_LONG_MODE(pVCpu))
1740 switch (pDesc->Legacy.Gen.u4Type)
1741 {
1742 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1743 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1744
1745 default:
1746 case AMD64_SEL_TYPE_SYS_LDT:
1747 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1748 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1749 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1750 case AMD64_SEL_TYPE_SYS_INT_GATE:
1751 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1752 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1753 }
1754
1755 switch (pDesc->Legacy.Gen.u4Type)
1756 {
1757 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1758 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1759 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1760
1761 case X86_SEL_TYPE_SYS_TASK_GATE:
1762 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1763
1764 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1765 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1766 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1767
1768 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1769 Log(("branch %04x -> busy 286 TSS\n", uSel));
1770 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1771
1772 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1773 Log(("branch %04x -> busy 386 TSS\n", uSel));
1774 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1775
1776 default:
1777 case X86_SEL_TYPE_SYS_LDT:
1778 case X86_SEL_TYPE_SYS_286_INT_GATE:
1779 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1780 case X86_SEL_TYPE_SYS_386_INT_GATE:
1781 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1782 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1783 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1784 }
1785}
1786
1787
1788/**
1789 * Implements far jumps.
1790 *
1791 * @param uSel The selector.
1792 * @param offSeg The segment offset.
1793 * @param enmEffOpSize The effective operand size.
1794 */
1795IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1796{
1797 NOREF(cbInstr);
1798 Assert(offSeg <= UINT32_MAX);
1799
1800 /*
1801 * Real mode and V8086 mode are easy. The only snag seems to be that
1802 * CS.limit doesn't change and the limit check is done against the current
1803 * limit.
1804 */
1805 /** @todo Robert Collins claims (The Segment Descriptor Cache, DDJ August
1806 * 1998) that up to and including the Intel 486, far control
1807 * transfers in real mode set default CS attributes (0x93) and also
1808 * set a 64K segment limit. Starting with the Pentium, the
1809 * attributes and limit are left alone but the access rights are
1810 * ignored. We only implement the Pentium+ behavior.
1811 * */
1812 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1813 {
1814 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1815 if (offSeg > pVCpu->cpum.GstCtx.cs.u32Limit)
1816 {
1817 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1818 return iemRaiseGeneralProtectionFault0(pVCpu);
1819 }
1820
1821 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1822 pVCpu->cpum.GstCtx.rip = offSeg;
1823 else
1824 pVCpu->cpum.GstCtx.rip = offSeg & UINT16_MAX;
1825 pVCpu->cpum.GstCtx.cs.Sel = uSel;
1826 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
1827 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1828 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
1829 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1830 return VINF_SUCCESS;
1831 }
1832
1833 /*
1834 * Protected mode. Need to parse the specified descriptor...
1835 */
1836 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1837 {
1838 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1839 return iemRaiseGeneralProtectionFault0(pVCpu);
1840 }
1841
1842 /* Fetch the descriptor. */
1843 IEMSELDESC Desc;
1844 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1845 if (rcStrict != VINF_SUCCESS)
1846 return rcStrict;
1847
1848 /* Is it there? */
1849 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1850 {
1851 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1852 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1853 }
1854
1855 /*
1856 * Deal with it according to its type. We do the standard code selectors
1857 * here and dispatch the system selectors to worker functions.
1858 */
1859 if (!Desc.Legacy.Gen.u1DescType)
1860 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1861
1862 /* Only code segments. */
1863 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1864 {
1865 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1866 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1867 }
1868
1869 /* L vs D. */
1870 if ( Desc.Legacy.Gen.u1Long
1871 && Desc.Legacy.Gen.u1DefBig
1872 && IEM_IS_LONG_MODE(pVCpu))
1873 {
1874 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1875 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1876 }
1877
1878 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1879 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1880 {
1881 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1882 {
1883 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1884 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1885 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1886 }
1887 }
1888 else
1889 {
1890 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1891 {
1892 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1893 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1894 }
1895 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1896 {
1897 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1898 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1899 }
1900 }
1901
1902 /* Chop the high bits if 16-bit (Intel says so). */
1903 if (enmEffOpSize == IEMMODE_16BIT)
1904 offSeg &= UINT16_MAX;
1905
1906 /* Limit check. (Should alternatively check for non-canonical addresses
1907 here, but that is ruled out by offSeg being 32-bit, right?) */
1908 uint64_t u64Base;
1909 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1910 if (Desc.Legacy.Gen.u1Long)
1911 u64Base = 0;
1912 else
1913 {
1914 if (offSeg > cbLimit)
1915 {
1916 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1917 /** @todo: Intel says this is #GP(0)! */
1918 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1919 }
1920 u64Base = X86DESC_BASE(&Desc.Legacy);
1921 }
1922
1923 /*
1924 * Ok, everything checked out fine. Now set the accessed bit before
1925 * committing the result into CS, CSHID and RIP.
1926 */
1927 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1928 {
1929 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1930 if (rcStrict != VINF_SUCCESS)
1931 return rcStrict;
1932 /** @todo check what VT-x and AMD-V does. */
1933 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1934 }
1935
1936 /* commit */
1937 pVCpu->cpum.GstCtx.rip = offSeg;
1938 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1939 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1940 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1941 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1942 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1943 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1944 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1945 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1946 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1947 /** @todo check if the hidden bits are loaded correctly for 64-bit
1948 * mode. */
1949
1950 /* Flush the prefetch buffer. */
1951#ifdef IEM_WITH_CODE_TLB
1952 pVCpu->iem.s.pbInstrBuf = NULL;
1953#else
1954 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1955#endif
1956
1957 return VINF_SUCCESS;
1958}
1959
1960
1961/**
1962 * Implements far calls.
1963 *
1964 * This very similar to iemCImpl_FarJmp.
1965 *
1966 * @param uSel The selector.
1967 * @param offSeg The segment offset.
1968 * @param enmEffOpSize The operand size (in case we need it).
1969 */
1970IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1971{
1972 VBOXSTRICTRC rcStrict;
1973 uint64_t uNewRsp;
1974 RTPTRUNION uPtrRet;
1975
1976 /*
1977 * Real mode and V8086 mode are easy. The only snag seems to be that
1978 * CS.limit doesn't change and the limit check is done against the current
1979 * limit.
1980 */
1981 /** @todo See comment for similar code in iemCImpl_FarJmp */
1982 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1983 {
1984 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1985
1986 /* Check stack first - may #SS(0). */
1987 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
1988 &uPtrRet.pv, &uNewRsp);
1989 if (rcStrict != VINF_SUCCESS)
1990 return rcStrict;
1991
1992 /* Check the target address range. */
1993 if (offSeg > UINT32_MAX)
1994 return iemRaiseGeneralProtectionFault0(pVCpu);
1995
1996 /* Everything is fine, push the return address. */
1997 if (enmEffOpSize == IEMMODE_16BIT)
1998 {
1999 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2000 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2001 }
2002 else
2003 {
2004 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2005 uPtrRet.pu16[2] = pVCpu->cpum.GstCtx.cs.Sel;
2006 }
2007 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2008 if (rcStrict != VINF_SUCCESS)
2009 return rcStrict;
2010
2011 /* Branch. */
2012 pVCpu->cpum.GstCtx.rip = offSeg;
2013 pVCpu->cpum.GstCtx.cs.Sel = uSel;
2014 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
2015 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2016 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
2017 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2018 return VINF_SUCCESS;
2019 }
2020
2021 /*
2022 * Protected mode. Need to parse the specified descriptor...
2023 */
2024 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2025 {
2026 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2027 return iemRaiseGeneralProtectionFault0(pVCpu);
2028 }
2029
2030 /* Fetch the descriptor. */
2031 IEMSELDESC Desc;
2032 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2033 if (rcStrict != VINF_SUCCESS)
2034 return rcStrict;
2035
2036 /*
2037 * Deal with it according to its type. We do the standard code selectors
2038 * here and dispatch the system selectors to worker functions.
2039 */
2040 if (!Desc.Legacy.Gen.u1DescType)
2041 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2042
2043 /* Only code segments. */
2044 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2045 {
2046 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2047 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2048 }
2049
2050 /* L vs D. */
2051 if ( Desc.Legacy.Gen.u1Long
2052 && Desc.Legacy.Gen.u1DefBig
2053 && IEM_IS_LONG_MODE(pVCpu))
2054 {
2055 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2056 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2057 }
2058
2059 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2060 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2061 {
2062 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2063 {
2064 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2065 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2066 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2067 }
2068 }
2069 else
2070 {
2071 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2072 {
2073 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2074 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2075 }
2076 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2077 {
2078 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2079 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2080 }
2081 }
2082
2083 /* Is it there? */
2084 if (!Desc.Legacy.Gen.u1Present)
2085 {
2086 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2087 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2088 }
2089
2090 /* Check stack first - may #SS(0). */
2091 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2092 * 16-bit code cause a two or four byte CS to be pushed? */
2093 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2094 enmEffOpSize == IEMMODE_64BIT ? 8+8
2095 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2096 &uPtrRet.pv, &uNewRsp);
2097 if (rcStrict != VINF_SUCCESS)
2098 return rcStrict;
2099
2100 /* Chop the high bits if 16-bit (Intel says so). */
2101 if (enmEffOpSize == IEMMODE_16BIT)
2102 offSeg &= UINT16_MAX;
2103
2104 /* Limit / canonical check. */
2105 uint64_t u64Base;
2106 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2107 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2108 {
2109 if (!IEM_IS_CANONICAL(offSeg))
2110 {
2111 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2112 return iemRaiseNotCanonical(pVCpu);
2113 }
2114 u64Base = 0;
2115 }
2116 else
2117 {
2118 if (offSeg > cbLimit)
2119 {
2120 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2121 /** @todo: Intel says this is #GP(0)! */
2122 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2123 }
2124 u64Base = X86DESC_BASE(&Desc.Legacy);
2125 }
2126
2127 /*
2128 * Now set the accessed bit before
2129 * writing the return address to the stack and committing the result into
2130 * CS, CSHID and RIP.
2131 */
2132 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2133 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2134 {
2135 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2136 if (rcStrict != VINF_SUCCESS)
2137 return rcStrict;
2138 /** @todo check what VT-x and AMD-V does. */
2139 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2140 }
2141
2142 /* stack */
2143 if (enmEffOpSize == IEMMODE_16BIT)
2144 {
2145 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2146 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2147 }
2148 else if (enmEffOpSize == IEMMODE_32BIT)
2149 {
2150 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2151 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2152 }
2153 else
2154 {
2155 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
2156 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2157 }
2158 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2159 if (rcStrict != VINF_SUCCESS)
2160 return rcStrict;
2161
2162 /* commit */
2163 pVCpu->cpum.GstCtx.rip = offSeg;
2164 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2165 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
2166 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
2167 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2168 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2169 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
2170 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2171 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2172 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2173 /** @todo check if the hidden bits are loaded correctly for 64-bit
2174 * mode. */
2175
2176 /* Flush the prefetch buffer. */
2177#ifdef IEM_WITH_CODE_TLB
2178 pVCpu->iem.s.pbInstrBuf = NULL;
2179#else
2180 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2181#endif
2182 return VINF_SUCCESS;
2183}
2184
2185
2186/**
2187 * Implements retf.
2188 *
2189 * @param enmEffOpSize The effective operand size.
2190 * @param cbPop The amount of arguments to pop from the stack
2191 * (bytes).
2192 */
2193IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2194{
2195 VBOXSTRICTRC rcStrict;
2196 RTCPTRUNION uPtrFrame;
2197 uint64_t uNewRsp;
2198 uint64_t uNewRip;
2199 uint16_t uNewCs;
2200 NOREF(cbInstr);
2201
2202 /*
2203 * Read the stack values first.
2204 */
2205 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2206 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2207 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2208 if (rcStrict != VINF_SUCCESS)
2209 return rcStrict;
2210 if (enmEffOpSize == IEMMODE_16BIT)
2211 {
2212 uNewRip = uPtrFrame.pu16[0];
2213 uNewCs = uPtrFrame.pu16[1];
2214 }
2215 else if (enmEffOpSize == IEMMODE_32BIT)
2216 {
2217 uNewRip = uPtrFrame.pu32[0];
2218 uNewCs = uPtrFrame.pu16[2];
2219 }
2220 else
2221 {
2222 uNewRip = uPtrFrame.pu64[0];
2223 uNewCs = uPtrFrame.pu16[4];
2224 }
2225 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2226 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2227 { /* extremely likely */ }
2228 else
2229 return rcStrict;
2230
2231 /*
2232 * Real mode and V8086 mode are easy.
2233 */
2234 /** @todo See comment for similar code in iemCImpl_FarJmp */
2235 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2236 {
2237 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2238 /** @todo check how this is supposed to work if sp=0xfffe. */
2239
2240 /* Check the limit of the new EIP. */
2241 /** @todo Intel pseudo code only does the limit check for 16-bit
2242 * operands, AMD does not make any distinction. What is right? */
2243 if (uNewRip > pVCpu->cpum.GstCtx.cs.u32Limit)
2244 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2245
2246 /* commit the operation. */
2247 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2248 pVCpu->cpum.GstCtx.rip = uNewRip;
2249 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2250 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2251 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2252 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2253 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2254 if (cbPop)
2255 iemRegAddToRsp(pVCpu, cbPop);
2256 return VINF_SUCCESS;
2257 }
2258
2259 /*
2260 * Protected mode is complicated, of course.
2261 */
2262 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2263 {
2264 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2265 return iemRaiseGeneralProtectionFault0(pVCpu);
2266 }
2267
2268 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
2269
2270 /* Fetch the descriptor. */
2271 IEMSELDESC DescCs;
2272 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2273 if (rcStrict != VINF_SUCCESS)
2274 return rcStrict;
2275
2276 /* Can only return to a code selector. */
2277 if ( !DescCs.Legacy.Gen.u1DescType
2278 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2279 {
2280 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2281 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2282 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2283 }
2284
2285 /* L vs D. */
2286 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2287 && DescCs.Legacy.Gen.u1DefBig
2288 && IEM_IS_LONG_MODE(pVCpu))
2289 {
2290 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2291 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2292 }
2293
2294 /* DPL/RPL/CPL checks. */
2295 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2296 {
2297 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2298 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2299 }
2300
2301 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2302 {
2303 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2304 {
2305 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2306 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2307 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2308 }
2309 }
2310 else
2311 {
2312 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2313 {
2314 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2315 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2316 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2317 }
2318 }
2319
2320 /* Is it there? */
2321 if (!DescCs.Legacy.Gen.u1Present)
2322 {
2323 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2324 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2325 }
2326
2327 /*
2328 * Return to outer privilege? (We'll typically have entered via a call gate.)
2329 */
2330 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2331 {
2332 /* Read the outer stack pointer stored *after* the parameters. */
2333 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop + cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2334 if (rcStrict != VINF_SUCCESS)
2335 return rcStrict;
2336
2337 uPtrFrame.pu8 += cbPop; /* Skip the parameters. */
2338
2339 uint16_t uNewOuterSs;
2340 uint64_t uNewOuterRsp;
2341 if (enmEffOpSize == IEMMODE_16BIT)
2342 {
2343 uNewOuterRsp = uPtrFrame.pu16[0];
2344 uNewOuterSs = uPtrFrame.pu16[1];
2345 }
2346 else if (enmEffOpSize == IEMMODE_32BIT)
2347 {
2348 uNewOuterRsp = uPtrFrame.pu32[0];
2349 uNewOuterSs = uPtrFrame.pu16[2];
2350 }
2351 else
2352 {
2353 uNewOuterRsp = uPtrFrame.pu64[0];
2354 uNewOuterSs = uPtrFrame.pu16[4];
2355 }
2356 uPtrFrame.pu8 -= cbPop; /* Put uPtrFrame back the way it was. */
2357 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2358 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2359 { /* extremely likely */ }
2360 else
2361 return rcStrict;
2362
2363 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2364 and read the selector. */
2365 IEMSELDESC DescSs;
2366 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2367 {
2368 if ( !DescCs.Legacy.Gen.u1Long
2369 || (uNewOuterSs & X86_SEL_RPL) == 3)
2370 {
2371 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2372 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2373 return iemRaiseGeneralProtectionFault0(pVCpu);
2374 }
2375 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2376 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2377 }
2378 else
2379 {
2380 /* Fetch the descriptor for the new stack segment. */
2381 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2382 if (rcStrict != VINF_SUCCESS)
2383 return rcStrict;
2384 }
2385
2386 /* Check that RPL of stack and code selectors match. */
2387 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2388 {
2389 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2390 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2391 }
2392
2393 /* Must be a writable data segment. */
2394 if ( !DescSs.Legacy.Gen.u1DescType
2395 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2396 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2397 {
2398 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2399 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2400 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2401 }
2402
2403 /* L vs D. (Not mentioned by intel.) */
2404 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2405 && DescSs.Legacy.Gen.u1DefBig
2406 && IEM_IS_LONG_MODE(pVCpu))
2407 {
2408 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2409 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2410 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2411 }
2412
2413 /* DPL/RPL/CPL checks. */
2414 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2415 {
2416 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2417 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2418 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2419 }
2420
2421 /* Is it there? */
2422 if (!DescSs.Legacy.Gen.u1Present)
2423 {
2424 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2425 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2426 }
2427
2428 /* Calc SS limit.*/
2429 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2430
2431 /* Is RIP canonical or within CS.limit? */
2432 uint64_t u64Base;
2433 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2434
2435 /** @todo Testcase: Is this correct? */
2436 if ( DescCs.Legacy.Gen.u1Long
2437 && IEM_IS_LONG_MODE(pVCpu) )
2438 {
2439 if (!IEM_IS_CANONICAL(uNewRip))
2440 {
2441 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2442 return iemRaiseNotCanonical(pVCpu);
2443 }
2444 u64Base = 0;
2445 }
2446 else
2447 {
2448 if (uNewRip > cbLimitCs)
2449 {
2450 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2451 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2452 /** @todo: Intel says this is #GP(0)! */
2453 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2454 }
2455 u64Base = X86DESC_BASE(&DescCs.Legacy);
2456 }
2457
2458 /*
2459 * Now set the accessed bit before
2460 * writing the return address to the stack and committing the result into
2461 * CS, CSHID and RIP.
2462 */
2463 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2464 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2465 {
2466 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2467 if (rcStrict != VINF_SUCCESS)
2468 return rcStrict;
2469 /** @todo check what VT-x and AMD-V does. */
2470 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2471 }
2472 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2473 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2474 {
2475 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2476 if (rcStrict != VINF_SUCCESS)
2477 return rcStrict;
2478 /** @todo check what VT-x and AMD-V does. */
2479 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2480 }
2481
2482 /* commit */
2483 if (enmEffOpSize == IEMMODE_16BIT)
2484 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2485 else
2486 pVCpu->cpum.GstCtx.rip = uNewRip;
2487 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2488 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2489 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2490 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2491 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2492 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2493 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2494 pVCpu->cpum.GstCtx.ss.Sel = uNewOuterSs;
2495 pVCpu->cpum.GstCtx.ss.ValidSel = uNewOuterSs;
2496 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
2497 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2498 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
2499 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2500 pVCpu->cpum.GstCtx.ss.u64Base = 0;
2501 else
2502 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2503 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2504 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewOuterRsp;
2505 else
2506 pVCpu->cpum.GstCtx.rsp = uNewOuterRsp;
2507
2508 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2509 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
2510 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
2511 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
2512 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
2513
2514 /** @todo check if the hidden bits are loaded correctly for 64-bit
2515 * mode. */
2516
2517 if (cbPop)
2518 iemRegAddToRsp(pVCpu, cbPop);
2519 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2520
2521 /* Done! */
2522 }
2523 /*
2524 * Return to the same privilege level
2525 */
2526 else
2527 {
2528 /* Limit / canonical check. */
2529 uint64_t u64Base;
2530 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2531
2532 /** @todo Testcase: Is this correct? */
2533 if ( DescCs.Legacy.Gen.u1Long
2534 && IEM_IS_LONG_MODE(pVCpu) )
2535 {
2536 if (!IEM_IS_CANONICAL(uNewRip))
2537 {
2538 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2539 return iemRaiseNotCanonical(pVCpu);
2540 }
2541 u64Base = 0;
2542 }
2543 else
2544 {
2545 if (uNewRip > cbLimitCs)
2546 {
2547 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2548 /** @todo: Intel says this is #GP(0)! */
2549 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2550 }
2551 u64Base = X86DESC_BASE(&DescCs.Legacy);
2552 }
2553
2554 /*
2555 * Now set the accessed bit before
2556 * writing the return address to the stack and committing the result into
2557 * CS, CSHID and RIP.
2558 */
2559 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2560 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2561 {
2562 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2563 if (rcStrict != VINF_SUCCESS)
2564 return rcStrict;
2565 /** @todo check what VT-x and AMD-V does. */
2566 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2567 }
2568
2569 /* commit */
2570 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2571 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
2572 else
2573 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2574 if (enmEffOpSize == IEMMODE_16BIT)
2575 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2576 else
2577 pVCpu->cpum.GstCtx.rip = uNewRip;
2578 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2579 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2580 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2581 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2582 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2583 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2584 /** @todo check if the hidden bits are loaded correctly for 64-bit
2585 * mode. */
2586 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2587 if (cbPop)
2588 iemRegAddToRsp(pVCpu, cbPop);
2589 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2590 }
2591
2592 /* Flush the prefetch buffer. */
2593#ifdef IEM_WITH_CODE_TLB
2594 pVCpu->iem.s.pbInstrBuf = NULL;
2595#else
2596 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2597#endif
2598 return VINF_SUCCESS;
2599}
2600
2601
2602/**
2603 * Implements retn.
2604 *
2605 * We're doing this in C because of the \#GP that might be raised if the popped
2606 * program counter is out of bounds.
2607 *
2608 * @param enmEffOpSize The effective operand size.
2609 * @param cbPop The amount of arguments to pop from the stack
2610 * (bytes).
2611 */
2612IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2613{
2614 NOREF(cbInstr);
2615
2616 /* Fetch the RSP from the stack. */
2617 VBOXSTRICTRC rcStrict;
2618 RTUINT64U NewRip;
2619 RTUINT64U NewRsp;
2620 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2621
2622 switch (enmEffOpSize)
2623 {
2624 case IEMMODE_16BIT:
2625 NewRip.u = 0;
2626 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2627 break;
2628 case IEMMODE_32BIT:
2629 NewRip.u = 0;
2630 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2631 break;
2632 case IEMMODE_64BIT:
2633 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2634 break;
2635 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2636 }
2637 if (rcStrict != VINF_SUCCESS)
2638 return rcStrict;
2639
2640 /* Check the new RSP before loading it. */
2641 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2642 * of it. The canonical test is performed here and for call. */
2643 if (enmEffOpSize != IEMMODE_64BIT)
2644 {
2645 if (NewRip.DWords.dw0 > pVCpu->cpum.GstCtx.cs.u32Limit)
2646 {
2647 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pVCpu->cpum.GstCtx.cs.u32Limit));
2648 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2649 }
2650 }
2651 else
2652 {
2653 if (!IEM_IS_CANONICAL(NewRip.u))
2654 {
2655 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2656 return iemRaiseNotCanonical(pVCpu);
2657 }
2658 }
2659
2660 /* Apply cbPop */
2661 if (cbPop)
2662 iemRegAddToRspEx(pVCpu, &NewRsp, cbPop);
2663
2664 /* Commit it. */
2665 pVCpu->cpum.GstCtx.rip = NewRip.u;
2666 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2667 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2668
2669 /* Flush the prefetch buffer. */
2670#ifndef IEM_WITH_CODE_TLB
2671 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2672#endif
2673
2674 return VINF_SUCCESS;
2675}
2676
2677
2678/**
2679 * Implements enter.
2680 *
2681 * We're doing this in C because the instruction is insane, even for the
2682 * u8NestingLevel=0 case dealing with the stack is tedious.
2683 *
2684 * @param enmEffOpSize The effective operand size.
2685 */
2686IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2687{
2688 /* Push RBP, saving the old value in TmpRbp. */
2689 RTUINT64U NewRsp; NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2690 RTUINT64U TmpRbp; TmpRbp.u = pVCpu->cpum.GstCtx.rbp;
2691 RTUINT64U NewRbp;
2692 VBOXSTRICTRC rcStrict;
2693 if (enmEffOpSize == IEMMODE_64BIT)
2694 {
2695 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2696 NewRbp = NewRsp;
2697 }
2698 else if (enmEffOpSize == IEMMODE_32BIT)
2699 {
2700 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2701 NewRbp = NewRsp;
2702 }
2703 else
2704 {
2705 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2706 NewRbp = TmpRbp;
2707 NewRbp.Words.w0 = NewRsp.Words.w0;
2708 }
2709 if (rcStrict != VINF_SUCCESS)
2710 return rcStrict;
2711
2712 /* Copy the parameters (aka nesting levels by Intel). */
2713 cParameters &= 0x1f;
2714 if (cParameters > 0)
2715 {
2716 switch (enmEffOpSize)
2717 {
2718 case IEMMODE_16BIT:
2719 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2720 TmpRbp.DWords.dw0 -= 2;
2721 else
2722 TmpRbp.Words.w0 -= 2;
2723 do
2724 {
2725 uint16_t u16Tmp;
2726 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2727 if (rcStrict != VINF_SUCCESS)
2728 break;
2729 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2730 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2731 break;
2732
2733 case IEMMODE_32BIT:
2734 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2735 TmpRbp.DWords.dw0 -= 4;
2736 else
2737 TmpRbp.Words.w0 -= 4;
2738 do
2739 {
2740 uint32_t u32Tmp;
2741 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2742 if (rcStrict != VINF_SUCCESS)
2743 break;
2744 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2745 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2746 break;
2747
2748 case IEMMODE_64BIT:
2749 TmpRbp.u -= 8;
2750 do
2751 {
2752 uint64_t u64Tmp;
2753 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2754 if (rcStrict != VINF_SUCCESS)
2755 break;
2756 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2757 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2758 break;
2759
2760 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2761 }
2762 if (rcStrict != VINF_SUCCESS)
2763 return VINF_SUCCESS;
2764
2765 /* Push the new RBP */
2766 if (enmEffOpSize == IEMMODE_64BIT)
2767 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2768 else if (enmEffOpSize == IEMMODE_32BIT)
2769 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2770 else
2771 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2772 if (rcStrict != VINF_SUCCESS)
2773 return rcStrict;
2774
2775 }
2776
2777 /* Recalc RSP. */
2778 iemRegSubFromRspEx(pVCpu, &NewRsp, cbFrame);
2779
2780 /** @todo Should probe write access at the new RSP according to AMD. */
2781
2782 /* Commit it. */
2783 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2784 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2785 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2786
2787 return VINF_SUCCESS;
2788}
2789
2790
2791
2792/**
2793 * Implements leave.
2794 *
2795 * We're doing this in C because messing with the stack registers is annoying
2796 * since they depends on SS attributes.
2797 *
2798 * @param enmEffOpSize The effective operand size.
2799 */
2800IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2801{
2802 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2803 RTUINT64U NewRsp;
2804 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2805 NewRsp.u = pVCpu->cpum.GstCtx.rbp;
2806 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2807 NewRsp.u = pVCpu->cpum.GstCtx.ebp;
2808 else
2809 {
2810 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2811 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2812 NewRsp.Words.w0 = pVCpu->cpum.GstCtx.bp;
2813 }
2814
2815 /* Pop RBP according to the operand size. */
2816 VBOXSTRICTRC rcStrict;
2817 RTUINT64U NewRbp;
2818 switch (enmEffOpSize)
2819 {
2820 case IEMMODE_16BIT:
2821 NewRbp.u = pVCpu->cpum.GstCtx.rbp;
2822 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2823 break;
2824 case IEMMODE_32BIT:
2825 NewRbp.u = 0;
2826 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2827 break;
2828 case IEMMODE_64BIT:
2829 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2830 break;
2831 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2832 }
2833 if (rcStrict != VINF_SUCCESS)
2834 return rcStrict;
2835
2836
2837 /* Commit it. */
2838 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2839 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2840 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2841
2842 return VINF_SUCCESS;
2843}
2844
2845
2846/**
2847 * Implements int3 and int XX.
2848 *
2849 * @param u8Int The interrupt vector number.
2850 * @param enmInt The int instruction type.
2851 */
2852IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2853{
2854 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2855 return iemRaiseXcptOrInt(pVCpu,
2856 cbInstr,
2857 u8Int,
2858 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2859 0,
2860 0);
2861}
2862
2863
2864/**
2865 * Implements iret for real mode and V8086 mode.
2866 *
2867 * @param enmEffOpSize The effective operand size.
2868 */
2869IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2870{
2871 X86EFLAGS Efl;
2872 Efl.u = IEMMISC_GET_EFL(pVCpu);
2873 NOREF(cbInstr);
2874
2875 /*
2876 * iret throws an exception if VME isn't enabled.
2877 */
2878 if ( Efl.Bits.u1VM
2879 && Efl.Bits.u2IOPL != 3
2880 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
2881 return iemRaiseGeneralProtectionFault0(pVCpu);
2882
2883 /*
2884 * Do the stack bits, but don't commit RSP before everything checks
2885 * out right.
2886 */
2887 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2888 VBOXSTRICTRC rcStrict;
2889 RTCPTRUNION uFrame;
2890 uint16_t uNewCs;
2891 uint32_t uNewEip;
2892 uint32_t uNewFlags;
2893 uint64_t uNewRsp;
2894 if (enmEffOpSize == IEMMODE_32BIT)
2895 {
2896 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
2897 if (rcStrict != VINF_SUCCESS)
2898 return rcStrict;
2899 uNewEip = uFrame.pu32[0];
2900 if (uNewEip > UINT16_MAX)
2901 return iemRaiseGeneralProtectionFault0(pVCpu);
2902
2903 uNewCs = (uint16_t)uFrame.pu32[1];
2904 uNewFlags = uFrame.pu32[2];
2905 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2906 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2907 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2908 | X86_EFL_ID;
2909 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2910 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2911 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2912 }
2913 else
2914 {
2915 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
2916 if (rcStrict != VINF_SUCCESS)
2917 return rcStrict;
2918 uNewEip = uFrame.pu16[0];
2919 uNewCs = uFrame.pu16[1];
2920 uNewFlags = uFrame.pu16[2];
2921 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2922 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2923 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2924 /** @todo The intel pseudo code does not indicate what happens to
2925 * reserved flags. We just ignore them. */
2926 /* Ancient CPU adjustments: See iemCImpl_popf. */
2927 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2928 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2929 }
2930 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2931 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2932 { /* extremely likely */ }
2933 else
2934 return rcStrict;
2935
2936 /** @todo Check how this is supposed to work if sp=0xfffe. */
2937 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2938 uNewCs, uNewEip, uNewFlags, uNewRsp));
2939
2940 /*
2941 * Check the limit of the new EIP.
2942 */
2943 /** @todo Only the AMD pseudo code check the limit here, what's
2944 * right? */
2945 if (uNewEip > pVCpu->cpum.GstCtx.cs.u32Limit)
2946 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2947
2948 /*
2949 * V8086 checks and flag adjustments
2950 */
2951 if (Efl.Bits.u1VM)
2952 {
2953 if (Efl.Bits.u2IOPL == 3)
2954 {
2955 /* Preserve IOPL and clear RF. */
2956 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
2957 uNewFlags |= Efl.u & (X86_EFL_IOPL);
2958 }
2959 else if ( enmEffOpSize == IEMMODE_16BIT
2960 && ( !(uNewFlags & X86_EFL_IF)
2961 || !Efl.Bits.u1VIP )
2962 && !(uNewFlags & X86_EFL_TF) )
2963 {
2964 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
2965 uNewFlags &= ~X86_EFL_VIF;
2966 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
2967 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
2968 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
2969 }
2970 else
2971 return iemRaiseGeneralProtectionFault0(pVCpu);
2972 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
2973 }
2974
2975 /*
2976 * Commit the operation.
2977 */
2978#ifdef DBGFTRACE_ENABLED
2979 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
2980 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
2981#endif
2982 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2983 pVCpu->cpum.GstCtx.rip = uNewEip;
2984 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2985 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2986 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2987 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2988 /** @todo do we load attribs and limit as well? */
2989 Assert(uNewFlags & X86_EFL_1);
2990 IEMMISC_SET_EFL(pVCpu, uNewFlags);
2991
2992 /* Flush the prefetch buffer. */
2993#ifdef IEM_WITH_CODE_TLB
2994 pVCpu->iem.s.pbInstrBuf = NULL;
2995#else
2996 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2997#endif
2998
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/**
3004 * Loads a segment register when entering V8086 mode.
3005 *
3006 * @param pSReg The segment register.
3007 * @param uSeg The segment to load.
3008 */
3009static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3010{
3011 pSReg->Sel = uSeg;
3012 pSReg->ValidSel = uSeg;
3013 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3014 pSReg->u64Base = (uint32_t)uSeg << 4;
3015 pSReg->u32Limit = 0xffff;
3016 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3017 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3018 * IRET'ing to V8086. */
3019}
3020
3021
3022/**
3023 * Implements iret for protected mode returning to V8086 mode.
3024 *
3025 * @param uNewEip The new EIP.
3026 * @param uNewCs The new CS.
3027 * @param uNewFlags The new EFLAGS.
3028 * @param uNewRsp The RSP after the initial IRET frame.
3029 *
3030 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3031 */
3032IEM_CIMPL_DEF_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp)
3033{
3034 RT_NOREF_PV(cbInstr);
3035 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
3036
3037 /*
3038 * Pop the V8086 specific frame bits off the stack.
3039 */
3040 VBOXSTRICTRC rcStrict;
3041 RTCPTRUNION uFrame;
3042 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 24, &uFrame.pv, &uNewRsp);
3043 if (rcStrict != VINF_SUCCESS)
3044 return rcStrict;
3045 uint32_t uNewEsp = uFrame.pu32[0];
3046 uint16_t uNewSs = uFrame.pu32[1];
3047 uint16_t uNewEs = uFrame.pu32[2];
3048 uint16_t uNewDs = uFrame.pu32[3];
3049 uint16_t uNewFs = uFrame.pu32[4];
3050 uint16_t uNewGs = uFrame.pu32[5];
3051 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3052 if (rcStrict != VINF_SUCCESS)
3053 return rcStrict;
3054
3055 /*
3056 * Commit the operation.
3057 */
3058 uNewFlags &= X86_EFL_LIVE_MASK;
3059 uNewFlags |= X86_EFL_RA1_MASK;
3060#ifdef DBGFTRACE_ENABLED
3061 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3062 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3063#endif
3064 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3065
3066 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3067 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.cs, uNewCs);
3068 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ss, uNewSs);
3069 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.es, uNewEs);
3070 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ds, uNewDs);
3071 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.fs, uNewFs);
3072 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.gs, uNewGs);
3073 pVCpu->cpum.GstCtx.rip = (uint16_t)uNewEip;
3074 pVCpu->cpum.GstCtx.rsp = uNewEsp; /** @todo check this out! */
3075 pVCpu->iem.s.uCpl = 3;
3076
3077 /* Flush the prefetch buffer. */
3078#ifdef IEM_WITH_CODE_TLB
3079 pVCpu->iem.s.pbInstrBuf = NULL;
3080#else
3081 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3082#endif
3083
3084 return VINF_SUCCESS;
3085}
3086
3087
3088/**
3089 * Implements iret for protected mode returning via a nested task.
3090 *
3091 * @param enmEffOpSize The effective operand size.
3092 */
3093IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3094{
3095 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3096#ifndef IEM_IMPLEMENTS_TASKSWITCH
3097 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3098#else
3099 RT_NOREF_PV(enmEffOpSize);
3100
3101 /*
3102 * Read the segment selector in the link-field of the current TSS.
3103 */
3104 RTSEL uSelRet;
3105 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base);
3106 if (rcStrict != VINF_SUCCESS)
3107 return rcStrict;
3108
3109 /*
3110 * Fetch the returning task's TSS descriptor from the GDT.
3111 */
3112 if (uSelRet & X86_SEL_LDT)
3113 {
3114 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3115 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3116 }
3117
3118 IEMSELDESC TssDesc;
3119 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3120 if (rcStrict != VINF_SUCCESS)
3121 return rcStrict;
3122
3123 if (TssDesc.Legacy.Gate.u1DescType)
3124 {
3125 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3126 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3127 }
3128
3129 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3130 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3131 {
3132 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3133 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3134 }
3135
3136 if (!TssDesc.Legacy.Gate.u1Present)
3137 {
3138 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3139 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3140 }
3141
3142 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
3143 return iemTaskSwitch(pVCpu, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3144 0 /* uCr2 */, uSelRet, &TssDesc);
3145#endif
3146}
3147
3148
3149/**
3150 * Implements iret for protected mode
3151 *
3152 * @param enmEffOpSize The effective operand size.
3153 */
3154IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3155{
3156 NOREF(cbInstr);
3157 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3158
3159 /*
3160 * Nested task return.
3161 */
3162 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3163 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3164
3165 /*
3166 * Normal return.
3167 *
3168 * Do the stack bits, but don't commit RSP before everything checks
3169 * out right.
3170 */
3171 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3172 VBOXSTRICTRC rcStrict;
3173 RTCPTRUNION uFrame;
3174 uint16_t uNewCs;
3175 uint32_t uNewEip;
3176 uint32_t uNewFlags;
3177 uint64_t uNewRsp;
3178 if (enmEffOpSize == IEMMODE_32BIT)
3179 {
3180 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
3181 if (rcStrict != VINF_SUCCESS)
3182 return rcStrict;
3183 uNewEip = uFrame.pu32[0];
3184 uNewCs = (uint16_t)uFrame.pu32[1];
3185 uNewFlags = uFrame.pu32[2];
3186 }
3187 else
3188 {
3189 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
3190 if (rcStrict != VINF_SUCCESS)
3191 return rcStrict;
3192 uNewEip = uFrame.pu16[0];
3193 uNewCs = uFrame.pu16[1];
3194 uNewFlags = uFrame.pu16[2];
3195 }
3196 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3197 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3198 { /* extremely likely */ }
3199 else
3200 return rcStrict;
3201 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3202
3203 /*
3204 * We're hopefully not returning to V8086 mode...
3205 */
3206 if ( (uNewFlags & X86_EFL_VM)
3207 && pVCpu->iem.s.uCpl == 0)
3208 {
3209 Assert(enmEffOpSize == IEMMODE_32BIT);
3210 return IEM_CIMPL_CALL_4(iemCImpl_iret_prot_v8086, uNewEip, uNewCs, uNewFlags, uNewRsp);
3211 }
3212
3213 /*
3214 * Protected mode.
3215 */
3216 /* Read the CS descriptor. */
3217 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3218 {
3219 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3220 return iemRaiseGeneralProtectionFault0(pVCpu);
3221 }
3222
3223 IEMSELDESC DescCS;
3224 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3225 if (rcStrict != VINF_SUCCESS)
3226 {
3227 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3228 return rcStrict;
3229 }
3230
3231 /* Must be a code descriptor. */
3232 if (!DescCS.Legacy.Gen.u1DescType)
3233 {
3234 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3235 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3236 }
3237 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3238 {
3239 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3240 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3241 }
3242
3243#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3244 /* Raw ring-0 and ring-1 compression adjustments for PATM performance tricks and other CS leaks. */
3245 PVM pVM = pVCpu->CTX_SUFF(pVM);
3246 if (EMIsRawRing0Enabled(pVM) && VM_IS_RAW_MODE_ENABLED(pVM))
3247 {
3248 if ((uNewCs & X86_SEL_RPL) == 1)
3249 {
3250 if ( pVCpu->iem.s.uCpl == 0
3251 && ( !EMIsRawRing1Enabled(pVM)
3252 || pVCpu->cpum.GstCtx.cs.Sel == (uNewCs & X86_SEL_MASK_OFF_RPL)) )
3253 {
3254 Log(("iret: Ring-0 compression fix: uNewCS=%#x -> %#x\n", uNewCs, uNewCs & X86_SEL_MASK_OFF_RPL));
3255 uNewCs &= X86_SEL_MASK_OFF_RPL;
3256 }
3257# ifdef LOG_ENABLED
3258 else if (pVCpu->iem.s.uCpl <= 1 && EMIsRawRing1Enabled(pVM))
3259 Log(("iret: uNewCs=%#x genuine return to ring-1.\n", uNewCs));
3260# endif
3261 }
3262 else if ( (uNewCs & X86_SEL_RPL) == 2
3263 && EMIsRawRing1Enabled(pVM)
3264 && pVCpu->iem.s.uCpl <= 1)
3265 {
3266 Log(("iret: Ring-1 compression fix: uNewCS=%#x -> %#x\n", uNewCs, (uNewCs & X86_SEL_MASK_OFF_RPL) | 1));
3267 uNewCs = (uNewCs & X86_SEL_MASK_OFF_RPL) | 2;
3268 }
3269 }
3270#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
3271
3272
3273 /* Privilege checks. */
3274 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3275 {
3276 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3277 {
3278 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3279 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3280 }
3281 }
3282 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3283 {
3284 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3285 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3286 }
3287 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3288 {
3289 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3290 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3291 }
3292
3293 /* Present? */
3294 if (!DescCS.Legacy.Gen.u1Present)
3295 {
3296 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3297 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3298 }
3299
3300 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3301
3302 /*
3303 * Return to outer level?
3304 */
3305 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3306 {
3307 uint16_t uNewSS;
3308 uint32_t uNewESP;
3309 if (enmEffOpSize == IEMMODE_32BIT)
3310 {
3311 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 8, &uFrame.pv, &uNewRsp);
3312 if (rcStrict != VINF_SUCCESS)
3313 return rcStrict;
3314/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3315 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3316 * bit of the popped SS selector it turns out. */
3317 uNewESP = uFrame.pu32[0];
3318 uNewSS = (uint16_t)uFrame.pu32[1];
3319 }
3320 else
3321 {
3322 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 4, &uFrame.pv, &uNewRsp);
3323 if (rcStrict != VINF_SUCCESS)
3324 return rcStrict;
3325 uNewESP = uFrame.pu16[0];
3326 uNewSS = uFrame.pu16[1];
3327 }
3328 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3329 if (rcStrict != VINF_SUCCESS)
3330 return rcStrict;
3331 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3332
3333 /* Read the SS descriptor. */
3334 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3335 {
3336 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3337 return iemRaiseGeneralProtectionFault0(pVCpu);
3338 }
3339
3340 IEMSELDESC DescSS;
3341 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3342 if (rcStrict != VINF_SUCCESS)
3343 {
3344 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3345 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3346 return rcStrict;
3347 }
3348
3349 /* Privilege checks. */
3350 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3351 {
3352 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3353 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3354 }
3355 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3356 {
3357 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3358 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3359 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3360 }
3361
3362 /* Must be a writeable data segment descriptor. */
3363 if (!DescSS.Legacy.Gen.u1DescType)
3364 {
3365 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3366 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3367 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3368 }
3369 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3370 {
3371 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3372 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3373 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3374 }
3375
3376 /* Present? */
3377 if (!DescSS.Legacy.Gen.u1Present)
3378 {
3379 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3380 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3381 }
3382
3383 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3384
3385 /* Check EIP. */
3386 if (uNewEip > cbLimitCS)
3387 {
3388 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3389 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3390 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3391 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3392 }
3393
3394 /*
3395 * Commit the changes, marking CS and SS accessed first since
3396 * that may fail.
3397 */
3398 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3399 {
3400 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3401 if (rcStrict != VINF_SUCCESS)
3402 return rcStrict;
3403 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3404 }
3405 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3406 {
3407 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3408 if (rcStrict != VINF_SUCCESS)
3409 return rcStrict;
3410 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3411 }
3412
3413 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3414 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3415 if (enmEffOpSize != IEMMODE_16BIT)
3416 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3417 if (pVCpu->iem.s.uCpl == 0)
3418 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3419 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3420 fEFlagsMask |= X86_EFL_IF;
3421 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3422 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3423 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3424 fEFlagsNew &= ~fEFlagsMask;
3425 fEFlagsNew |= uNewFlags & fEFlagsMask;
3426#ifdef DBGFTRACE_ENABLED
3427 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3428 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3429 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3430#endif
3431
3432 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3433 pVCpu->cpum.GstCtx.rip = uNewEip;
3434 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3435 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3436 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3437 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3438 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3439 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3440 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3441
3442 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
3443 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
3444 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3445 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3446 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3447 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3448 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3449 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewESP;
3450 else
3451 pVCpu->cpum.GstCtx.rsp = uNewESP;
3452
3453 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3454 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
3455 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
3456 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
3457 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
3458
3459 /* Done! */
3460
3461 }
3462 /*
3463 * Return to the same level.
3464 */
3465 else
3466 {
3467 /* Check EIP. */
3468 if (uNewEip > cbLimitCS)
3469 {
3470 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3471 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3472 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3473 }
3474
3475 /*
3476 * Commit the changes, marking CS first since it may fail.
3477 */
3478 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3479 {
3480 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3481 if (rcStrict != VINF_SUCCESS)
3482 return rcStrict;
3483 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3484 }
3485
3486 X86EFLAGS NewEfl;
3487 NewEfl.u = IEMMISC_GET_EFL(pVCpu);
3488 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3489 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3490 if (enmEffOpSize != IEMMODE_16BIT)
3491 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3492 if (pVCpu->iem.s.uCpl == 0)
3493 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3494 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3495 fEFlagsMask |= X86_EFL_IF;
3496 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3497 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3498 NewEfl.u &= ~fEFlagsMask;
3499 NewEfl.u |= fEFlagsMask & uNewFlags;
3500#ifdef DBGFTRACE_ENABLED
3501 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3502 pVCpu->iem.s.uCpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3503 uNewCs, uNewEip, uNewFlags, pVCpu->cpum.GstCtx.ss.Sel, uNewRsp);
3504#endif
3505
3506 IEMMISC_SET_EFL(pVCpu, NewEfl.u);
3507 pVCpu->cpum.GstCtx.rip = uNewEip;
3508 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3509 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3510 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3511 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3512 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3513 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3514 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3515 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3516 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3517 else
3518 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3519 /* Done! */
3520 }
3521
3522 /* Flush the prefetch buffer. */
3523#ifdef IEM_WITH_CODE_TLB
3524 pVCpu->iem.s.pbInstrBuf = NULL;
3525#else
3526 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3527#endif
3528
3529 return VINF_SUCCESS;
3530}
3531
3532
3533/**
3534 * Implements iret for long mode
3535 *
3536 * @param enmEffOpSize The effective operand size.
3537 */
3538IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3539{
3540 NOREF(cbInstr);
3541
3542 /*
3543 * Nested task return is not supported in long mode.
3544 */
3545 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3546 {
3547 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.eflags.u));
3548 return iemRaiseGeneralProtectionFault0(pVCpu);
3549 }
3550
3551 /*
3552 * Normal return.
3553 *
3554 * Do the stack bits, but don't commit RSP before everything checks
3555 * out right.
3556 */
3557 VBOXSTRICTRC rcStrict;
3558 RTCPTRUNION uFrame;
3559 uint64_t uNewRip;
3560 uint16_t uNewCs;
3561 uint16_t uNewSs;
3562 uint32_t uNewFlags;
3563 uint64_t uNewRsp;
3564 if (enmEffOpSize == IEMMODE_64BIT)
3565 {
3566 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, &uFrame.pv, &uNewRsp);
3567 if (rcStrict != VINF_SUCCESS)
3568 return rcStrict;
3569 uNewRip = uFrame.pu64[0];
3570 uNewCs = (uint16_t)uFrame.pu64[1];
3571 uNewFlags = (uint32_t)uFrame.pu64[2];
3572 uNewRsp = uFrame.pu64[3];
3573 uNewSs = (uint16_t)uFrame.pu64[4];
3574 }
3575 else if (enmEffOpSize == IEMMODE_32BIT)
3576 {
3577 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, &uFrame.pv, &uNewRsp);
3578 if (rcStrict != VINF_SUCCESS)
3579 return rcStrict;
3580 uNewRip = uFrame.pu32[0];
3581 uNewCs = (uint16_t)uFrame.pu32[1];
3582 uNewFlags = uFrame.pu32[2];
3583 uNewRsp = uFrame.pu32[3];
3584 uNewSs = (uint16_t)uFrame.pu32[4];
3585 }
3586 else
3587 {
3588 Assert(enmEffOpSize == IEMMODE_16BIT);
3589 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, &uFrame.pv, &uNewRsp);
3590 if (rcStrict != VINF_SUCCESS)
3591 return rcStrict;
3592 uNewRip = uFrame.pu16[0];
3593 uNewCs = uFrame.pu16[1];
3594 uNewFlags = uFrame.pu16[2];
3595 uNewRsp = uFrame.pu16[3];
3596 uNewSs = uFrame.pu16[4];
3597 }
3598 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3599 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3600 { /* extremely like */ }
3601 else
3602 return rcStrict;
3603 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3604
3605 /*
3606 * Check stuff.
3607 */
3608 /* Read the CS descriptor. */
3609 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3610 {
3611 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3612 return iemRaiseGeneralProtectionFault0(pVCpu);
3613 }
3614
3615 IEMSELDESC DescCS;
3616 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3617 if (rcStrict != VINF_SUCCESS)
3618 {
3619 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3620 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3621 return rcStrict;
3622 }
3623
3624 /* Must be a code descriptor. */
3625 if ( !DescCS.Legacy.Gen.u1DescType
3626 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3627 {
3628 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3629 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3630 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3631 }
3632
3633 /* Privilege checks. */
3634 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3635 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3636 {
3637 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3638 {
3639 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3640 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3641 }
3642 }
3643 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3644 {
3645 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3646 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3647 }
3648 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3649 {
3650 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3651 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3652 }
3653
3654 /* Present? */
3655 if (!DescCS.Legacy.Gen.u1Present)
3656 {
3657 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3658 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3659 }
3660
3661 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3662
3663 /* Read the SS descriptor. */
3664 IEMSELDESC DescSS;
3665 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3666 {
3667 if ( !DescCS.Legacy.Gen.u1Long
3668 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3669 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3670 {
3671 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3672 return iemRaiseGeneralProtectionFault0(pVCpu);
3673 }
3674 DescSS.Legacy.u = 0;
3675 }
3676 else
3677 {
3678 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3679 if (rcStrict != VINF_SUCCESS)
3680 {
3681 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3682 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3683 return rcStrict;
3684 }
3685 }
3686
3687 /* Privilege checks. */
3688 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3689 {
3690 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3691 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3692 }
3693
3694 uint32_t cbLimitSs;
3695 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3696 cbLimitSs = UINT32_MAX;
3697 else
3698 {
3699 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3700 {
3701 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3702 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3703 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3704 }
3705
3706 /* Must be a writeable data segment descriptor. */
3707 if (!DescSS.Legacy.Gen.u1DescType)
3708 {
3709 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3710 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3711 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3712 }
3713 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3714 {
3715 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3716 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3717 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3718 }
3719
3720 /* Present? */
3721 if (!DescSS.Legacy.Gen.u1Present)
3722 {
3723 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3724 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3725 }
3726 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3727 }
3728
3729 /* Check EIP. */
3730 if (DescCS.Legacy.Gen.u1Long)
3731 {
3732 if (!IEM_IS_CANONICAL(uNewRip))
3733 {
3734 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3735 uNewCs, uNewRip, uNewSs, uNewRsp));
3736 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3737 }
3738 }
3739 else
3740 {
3741 if (uNewRip > cbLimitCS)
3742 {
3743 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3744 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3745 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3746 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3747 }
3748 }
3749
3750 /*
3751 * Commit the changes, marking CS and SS accessed first since
3752 * that may fail.
3753 */
3754 /** @todo where exactly are these actually marked accessed by a real CPU? */
3755 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3756 {
3757 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3758 if (rcStrict != VINF_SUCCESS)
3759 return rcStrict;
3760 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3761 }
3762 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3763 {
3764 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3765 if (rcStrict != VINF_SUCCESS)
3766 return rcStrict;
3767 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3768 }
3769
3770 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3771 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3772 if (enmEffOpSize != IEMMODE_16BIT)
3773 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3774 if (pVCpu->iem.s.uCpl == 0)
3775 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3776 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3777 fEFlagsMask |= X86_EFL_IF;
3778 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3779 fEFlagsNew &= ~fEFlagsMask;
3780 fEFlagsNew |= uNewFlags & fEFlagsMask;
3781#ifdef DBGFTRACE_ENABLED
3782 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3783 pVCpu->iem.s.uCpl, uNewCpl, pVCpu->cpum.GstCtx.rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3784#endif
3785
3786 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3787 pVCpu->cpum.GstCtx.rip = uNewRip;
3788 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3789 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3790 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3791 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3792 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3793 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3794 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3795 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
3796 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3797 else
3798 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3799 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3800 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3801 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3802 {
3803 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3804 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3805 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3806 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3807 Log2(("iretq new SS: NULL\n"));
3808 }
3809 else
3810 {
3811 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3812 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3813 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3814 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3815 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
3816 }
3817
3818 if (pVCpu->iem.s.uCpl != uNewCpl)
3819 {
3820 pVCpu->iem.s.uCpl = uNewCpl;
3821 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.ds);
3822 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.es);
3823 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.fs);
3824 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.gs);
3825 }
3826
3827 /* Flush the prefetch buffer. */
3828#ifdef IEM_WITH_CODE_TLB
3829 pVCpu->iem.s.pbInstrBuf = NULL;
3830#else
3831 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3832#endif
3833
3834 return VINF_SUCCESS;
3835}
3836
3837
3838/**
3839 * Implements iret.
3840 *
3841 * @param enmEffOpSize The effective operand size.
3842 */
3843IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3844{
3845 /*
3846 * First, clear NMI blocking, if any, before causing any exceptions.
3847 * See Intel spec. 6.7.1 "Handling Multiple NMIs".
3848 */
3849 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3850
3851 /*
3852 * The SVM nested-guest intercept for iret takes priority over all exceptions,
3853 * see AMD spec. "15.9 Instruction Intercepts".
3854 */
3855 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3856 {
3857 Log(("iret: Guest intercept -> #VMEXIT\n"));
3858 IEM_SVM_UPDATE_NRIP(pVCpu);
3859 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3860 }
3861
3862 /*
3863 * Call a mode specific worker.
3864 */
3865 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3866 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3867 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
3868 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3869 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3870 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3871}
3872
3873
3874/**
3875 * Implements SYSCALL (AMD and Intel64).
3876 *
3877 * @param enmEffOpSize The effective operand size.
3878 */
3879IEM_CIMPL_DEF_0(iemCImpl_syscall)
3880{
3881 /*
3882 * Check preconditions.
3883 *
3884 * Note that CPUs described in the documentation may load a few odd values
3885 * into CS and SS than we allow here. This has yet to be checked on real
3886 * hardware.
3887 */
3888 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
3889 {
3890 Log(("syscall: Not enabled in EFER -> #UD\n"));
3891 return iemRaiseUndefinedOpcode(pVCpu);
3892 }
3893 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
3894 {
3895 Log(("syscall: Protected mode is required -> #GP(0)\n"));
3896 return iemRaiseGeneralProtectionFault0(pVCpu);
3897 }
3898 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
3899 {
3900 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3901 return iemRaiseUndefinedOpcode(pVCpu);
3902 }
3903
3904 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
3905
3906 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
3907 /** @todo what about LDT selectors? Shouldn't matter, really. */
3908 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
3909 uint16_t uNewSs = uNewCs + 8;
3910 if (uNewCs == 0 || uNewSs == 0)
3911 {
3912 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
3913 return iemRaiseGeneralProtectionFault0(pVCpu);
3914 }
3915
3916 /* Long mode and legacy mode differs. */
3917 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
3918 {
3919 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.msrLSTAR : pVCpu->cpum.GstCtx. msrCSTAR;
3920
3921 /* This test isn't in the docs, but I'm not trusting the guys writing
3922 the MSRs to have validated the values as canonical like they should. */
3923 if (!IEM_IS_CANONICAL(uNewRip))
3924 {
3925 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3926 return iemRaiseUndefinedOpcode(pVCpu);
3927 }
3928
3929 /*
3930 * Commit it.
3931 */
3932 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
3933 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.rip + cbInstr;
3934 pVCpu->cpum.GstCtx.rip = uNewRip;
3935
3936 pVCpu->cpum.GstCtx.rflags.u &= ~X86_EFL_RF;
3937 pVCpu->cpum.GstCtx.r11 = pVCpu->cpum.GstCtx.rflags.u;
3938 pVCpu->cpum.GstCtx.rflags.u &= ~pVCpu->cpum.GstCtx.msrSFMASK;
3939 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
3940
3941 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3942 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3943 }
3944 else
3945 {
3946 /*
3947 * Commit it.
3948 */
3949 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
3950 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
3951 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.eip + cbInstr;
3952 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
3953 pVCpu->cpum.GstCtx.rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
3954
3955 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3956 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3957 }
3958 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3959 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3960 pVCpu->cpum.GstCtx.cs.u64Base = 0;
3961 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
3962 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3963
3964 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3965 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3966 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3967 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3968 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3969
3970 /* Flush the prefetch buffer. */
3971#ifdef IEM_WITH_CODE_TLB
3972 pVCpu->iem.s.pbInstrBuf = NULL;
3973#else
3974 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3975#endif
3976
3977 return VINF_SUCCESS;
3978}
3979
3980
3981/**
3982 * Implements SYSRET (AMD and Intel64).
3983 */
3984IEM_CIMPL_DEF_0(iemCImpl_sysret)
3985
3986{
3987 RT_NOREF_PV(cbInstr);
3988
3989 /*
3990 * Check preconditions.
3991 *
3992 * Note that CPUs described in the documentation may load a few odd values
3993 * into CS and SS than we allow here. This has yet to be checked on real
3994 * hardware.
3995 */
3996 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
3997 {
3998 Log(("sysret: Not enabled in EFER -> #UD\n"));
3999 return iemRaiseUndefinedOpcode(pVCpu);
4000 }
4001 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4002 {
4003 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4004 return iemRaiseUndefinedOpcode(pVCpu);
4005 }
4006 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4007 {
4008 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4009 return iemRaiseGeneralProtectionFault0(pVCpu);
4010 }
4011 if (pVCpu->iem.s.uCpl != 0)
4012 {
4013 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4014 return iemRaiseGeneralProtectionFault0(pVCpu);
4015 }
4016
4017 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4018
4019 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4020 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4021 uint16_t uNewSs = uNewCs + 8;
4022 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4023 uNewCs += 16;
4024 if (uNewCs == 0 || uNewSs == 0)
4025 {
4026 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4027 return iemRaiseGeneralProtectionFault0(pVCpu);
4028 }
4029
4030 /*
4031 * Commit it.
4032 */
4033 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4034 {
4035 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4036 {
4037 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
4038 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
4039 /* Note! We disregard intel manual regarding the RCX cananonical
4040 check, ask intel+xen why AMD doesn't do it. */
4041 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4042 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4043 | (3 << X86DESCATTR_DPL_SHIFT);
4044 }
4045 else
4046 {
4047 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
4048 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
4049 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.ecx;
4050 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4051 | (3 << X86DESCATTR_DPL_SHIFT);
4052 }
4053 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4054 * what it really ignores. RF and VM are hinted at being zero, by AMD. */
4055 pVCpu->cpum.GstCtx.rflags.u = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4056 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4057 }
4058 else
4059 {
4060 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
4061 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4062 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_IF;
4063 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4064 | (3 << X86DESCATTR_DPL_SHIFT);
4065 }
4066 pVCpu->cpum.GstCtx.cs.Sel = uNewCs | 3;
4067 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs | 3;
4068 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4069 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4070 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4071
4072 pVCpu->cpum.GstCtx.ss.Sel = uNewSs | 3;
4073 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs | 3;
4074 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4075 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4076 pVCpu->cpum.GstCtx.ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4077 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4078 * on sysret. */
4079
4080 /* Flush the prefetch buffer. */
4081#ifdef IEM_WITH_CODE_TLB
4082 pVCpu->iem.s.pbInstrBuf = NULL;
4083#else
4084 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4085#endif
4086
4087 return VINF_SUCCESS;
4088}
4089
4090
4091/**
4092 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4093 *
4094 * @param iSegReg The segment register number (valid).
4095 * @param uSel The new selector value.
4096 */
4097IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4098{
4099 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
4100 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4101 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4102
4103 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4104
4105 /*
4106 * Real mode and V8086 mode are easy.
4107 */
4108 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4109 {
4110 *pSel = uSel;
4111 pHid->u64Base = (uint32_t)uSel << 4;
4112 pHid->ValidSel = uSel;
4113 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4114#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4115 /** @todo Does the CPU actually load limits and attributes in the
4116 * real/V8086 mode segment load case? It doesn't for CS in far
4117 * jumps... Affects unreal mode. */
4118 pHid->u32Limit = 0xffff;
4119 pHid->Attr.u = 0;
4120 pHid->Attr.n.u1Present = 1;
4121 pHid->Attr.n.u1DescType = 1;
4122 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4123 ? X86_SEL_TYPE_RW
4124 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4125#endif
4126 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4128 return VINF_SUCCESS;
4129 }
4130
4131 /*
4132 * Protected mode.
4133 *
4134 * Check if it's a null segment selector value first, that's OK for DS, ES,
4135 * FS and GS. If not null, then we have to load and parse the descriptor.
4136 */
4137 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4138 {
4139 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4140 if (iSegReg == X86_SREG_SS)
4141 {
4142 /* In 64-bit kernel mode, the stack can be 0 because of the way
4143 interrupts are dispatched. AMD seems to have a slighly more
4144 relaxed relationship to SS.RPL than intel does. */
4145 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4146 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4147 || pVCpu->iem.s.uCpl > 2
4148 || ( uSel != pVCpu->iem.s.uCpl
4149 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4150 {
4151 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4152 return iemRaiseGeneralProtectionFault0(pVCpu);
4153 }
4154 }
4155
4156 *pSel = uSel; /* Not RPL, remember :-) */
4157 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4158 if (iSegReg == X86_SREG_SS)
4159 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4160
4161 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4162 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4163
4164 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4165 return VINF_SUCCESS;
4166 }
4167
4168 /* Fetch the descriptor. */
4169 IEMSELDESC Desc;
4170 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4171 if (rcStrict != VINF_SUCCESS)
4172 return rcStrict;
4173
4174 /* Check GPs first. */
4175 if (!Desc.Legacy.Gen.u1DescType)
4176 {
4177 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4178 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4179 }
4180 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4181 {
4182 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4183 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4184 {
4185 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4186 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4187 }
4188 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4189 {
4190 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4191 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4192 }
4193 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4194 {
4195 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4196 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4197 }
4198 }
4199 else
4200 {
4201 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4202 {
4203 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4204 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4205 }
4206 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4207 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4208 {
4209#if 0 /* this is what intel says. */
4210 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4211 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4212 {
4213 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4214 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4215 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4216 }
4217#else /* this is what makes more sense. */
4218 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4219 {
4220 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4221 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4222 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4223 }
4224 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4225 {
4226 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4227 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4228 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4229 }
4230#endif
4231 }
4232 }
4233
4234 /* Is it there? */
4235 if (!Desc.Legacy.Gen.u1Present)
4236 {
4237 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4238 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4239 }
4240
4241 /* The base and limit. */
4242 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4243 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4244
4245 /*
4246 * Ok, everything checked out fine. Now set the accessed bit before
4247 * committing the result into the registers.
4248 */
4249 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4250 {
4251 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4252 if (rcStrict != VINF_SUCCESS)
4253 return rcStrict;
4254 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4255 }
4256
4257 /* commit */
4258 *pSel = uSel;
4259 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4260 pHid->u32Limit = cbLimit;
4261 pHid->u64Base = u64Base;
4262 pHid->ValidSel = uSel;
4263 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4264
4265 /** @todo check if the hidden bits are loaded correctly for 64-bit
4266 * mode. */
4267 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4268
4269 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4270 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4271 return VINF_SUCCESS;
4272}
4273
4274
4275/**
4276 * Implements 'mov SReg, r/m'.
4277 *
4278 * @param iSegReg The segment register number (valid).
4279 * @param uSel The new selector value.
4280 */
4281IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4282{
4283 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4284 if (rcStrict == VINF_SUCCESS)
4285 {
4286 if (iSegReg == X86_SREG_SS)
4287 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4288 }
4289 return rcStrict;
4290}
4291
4292
4293/**
4294 * Implements 'pop SReg'.
4295 *
4296 * @param iSegReg The segment register number (valid).
4297 * @param enmEffOpSize The efficient operand size (valid).
4298 */
4299IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4300{
4301 VBOXSTRICTRC rcStrict;
4302
4303 /*
4304 * Read the selector off the stack and join paths with mov ss, reg.
4305 */
4306 RTUINT64U TmpRsp;
4307 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
4308 switch (enmEffOpSize)
4309 {
4310 case IEMMODE_16BIT:
4311 {
4312 uint16_t uSel;
4313 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4314 if (rcStrict == VINF_SUCCESS)
4315 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4316 break;
4317 }
4318
4319 case IEMMODE_32BIT:
4320 {
4321 uint32_t u32Value;
4322 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4323 if (rcStrict == VINF_SUCCESS)
4324 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4325 break;
4326 }
4327
4328 case IEMMODE_64BIT:
4329 {
4330 uint64_t u64Value;
4331 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4332 if (rcStrict == VINF_SUCCESS)
4333 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4334 break;
4335 }
4336 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4337 }
4338
4339 /*
4340 * Commit the stack on success.
4341 */
4342 if (rcStrict == VINF_SUCCESS)
4343 {
4344 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
4345 if (iSegReg == X86_SREG_SS)
4346 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4347 }
4348 return rcStrict;
4349}
4350
4351
4352/**
4353 * Implements lgs, lfs, les, lds & lss.
4354 */
4355IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg,
4356 uint16_t, uSel,
4357 uint64_t, offSeg,
4358 uint8_t, iSegReg,
4359 uint8_t, iGReg,
4360 IEMMODE, enmEffOpSize)
4361{
4362 /*
4363 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4364 */
4365 /** @todo verify and test that mov, pop and lXs works the segment
4366 * register loading in the exact same way. */
4367 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4368 if (rcStrict == VINF_SUCCESS)
4369 {
4370 switch (enmEffOpSize)
4371 {
4372 case IEMMODE_16BIT:
4373 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4374 break;
4375 case IEMMODE_32BIT:
4376 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4377 break;
4378 case IEMMODE_64BIT:
4379 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4380 break;
4381 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4382 }
4383 }
4384
4385 return rcStrict;
4386}
4387
4388
4389/**
4390 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4391 *
4392 * @retval VINF_SUCCESS on success.
4393 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4394 * @retval iemMemFetchSysU64 return value.
4395 *
4396 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4397 * @param uSel The selector value.
4398 * @param fAllowSysDesc Whether system descriptors are OK or not.
4399 * @param pDesc Where to return the descriptor on success.
4400 */
4401static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPU pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4402{
4403 pDesc->Long.au64[0] = 0;
4404 pDesc->Long.au64[1] = 0;
4405
4406 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4407 return VINF_IEM_SELECTOR_NOT_OK;
4408
4409 /* Within the table limits? */
4410 RTGCPTR GCPtrBase;
4411 if (uSel & X86_SEL_LDT)
4412 {
4413 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4414 if ( !pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Present
4415 || (uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.ldtr.u32Limit )
4416 return VINF_IEM_SELECTOR_NOT_OK;
4417 GCPtrBase = pVCpu->cpum.GstCtx.ldtr.u64Base;
4418 }
4419 else
4420 {
4421 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4422 if ((uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.gdtr.cbGdt)
4423 return VINF_IEM_SELECTOR_NOT_OK;
4424 GCPtrBase = pVCpu->cpum.GstCtx.gdtr.pGdt;
4425 }
4426
4427 /* Fetch the descriptor. */
4428 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4429 if (rcStrict != VINF_SUCCESS)
4430 return rcStrict;
4431 if (!pDesc->Legacy.Gen.u1DescType)
4432 {
4433 if (!fAllowSysDesc)
4434 return VINF_IEM_SELECTOR_NOT_OK;
4435 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4436 {
4437 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4438 if (rcStrict != VINF_SUCCESS)
4439 return rcStrict;
4440 }
4441
4442 }
4443
4444 return VINF_SUCCESS;
4445}
4446
4447
4448/**
4449 * Implements verr (fWrite = false) and verw (fWrite = true).
4450 */
4451IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4452{
4453 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4454
4455 /** @todo figure whether the accessed bit is set or not. */
4456
4457 bool fAccessible = true;
4458 IEMSELDESC Desc;
4459 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4460 if (rcStrict == VINF_SUCCESS)
4461 {
4462 /* Check the descriptor, order doesn't matter much here. */
4463 if ( !Desc.Legacy.Gen.u1DescType
4464 || !Desc.Legacy.Gen.u1Present)
4465 fAccessible = false;
4466 else
4467 {
4468 if ( fWrite
4469 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4470 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4471 fAccessible = false;
4472
4473 /** @todo testcase for the conforming behavior. */
4474 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4475 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4476 {
4477 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4478 fAccessible = false;
4479 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4480 fAccessible = false;
4481 }
4482 }
4483
4484 }
4485 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4486 fAccessible = false;
4487 else
4488 return rcStrict;
4489
4490 /* commit */
4491 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible;
4492
4493 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4494 return VINF_SUCCESS;
4495}
4496
4497
4498/**
4499 * Implements LAR and LSL with 64-bit operand size.
4500 *
4501 * @returns VINF_SUCCESS.
4502 * @param pu16Dst Pointer to the destination register.
4503 * @param uSel The selector to load details for.
4504 * @param fIsLar true = LAR, false = LSL.
4505 */
4506IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4507{
4508 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4509
4510 /** @todo figure whether the accessed bit is set or not. */
4511
4512 bool fDescOk = true;
4513 IEMSELDESC Desc;
4514 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, true /*fAllowSysDesc*/, &Desc);
4515 if (rcStrict == VINF_SUCCESS)
4516 {
4517 /*
4518 * Check the descriptor type.
4519 */
4520 if (!Desc.Legacy.Gen.u1DescType)
4521 {
4522 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4523 {
4524 if (Desc.Long.Gen.u5Zeros)
4525 fDescOk = false;
4526 else
4527 switch (Desc.Long.Gen.u4Type)
4528 {
4529 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4530 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4531 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4532 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4533 break;
4534 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4535 fDescOk = fIsLar;
4536 break;
4537 default:
4538 fDescOk = false;
4539 break;
4540 }
4541 }
4542 else
4543 {
4544 switch (Desc.Long.Gen.u4Type)
4545 {
4546 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4547 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4548 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4549 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4550 case X86_SEL_TYPE_SYS_LDT:
4551 break;
4552 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4553 case X86_SEL_TYPE_SYS_TASK_GATE:
4554 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4555 fDescOk = fIsLar;
4556 break;
4557 default:
4558 fDescOk = false;
4559 break;
4560 }
4561 }
4562 }
4563 if (fDescOk)
4564 {
4565 /*
4566 * Check the RPL/DPL/CPL interaction..
4567 */
4568 /** @todo testcase for the conforming behavior. */
4569 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4570 || !Desc.Legacy.Gen.u1DescType)
4571 {
4572 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4573 fDescOk = false;
4574 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4575 fDescOk = false;
4576 }
4577 }
4578
4579 if (fDescOk)
4580 {
4581 /*
4582 * All fine, start committing the result.
4583 */
4584 if (fIsLar)
4585 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4586 else
4587 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
4588 }
4589
4590 }
4591 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4592 fDescOk = false;
4593 else
4594 return rcStrict;
4595
4596 /* commit flags value and advance rip. */
4597 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk;
4598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4599
4600 return VINF_SUCCESS;
4601}
4602
4603
4604/**
4605 * Implements LAR and LSL with 16-bit operand size.
4606 *
4607 * @returns VINF_SUCCESS.
4608 * @param pu16Dst Pointer to the destination register.
4609 * @param u16Sel The selector to load details for.
4610 * @param fIsLar true = LAR, false = LSL.
4611 */
4612IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
4613{
4614 uint64_t u64TmpDst = *pu16Dst;
4615 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
4616 *pu16Dst = u64TmpDst;
4617 return VINF_SUCCESS;
4618}
4619
4620
4621/**
4622 * Implements lgdt.
4623 *
4624 * @param iEffSeg The segment of the new gdtr contents
4625 * @param GCPtrEffSrc The address of the new gdtr contents.
4626 * @param enmEffOpSize The effective operand size.
4627 */
4628IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4629{
4630 if (pVCpu->iem.s.uCpl != 0)
4631 return iemRaiseGeneralProtectionFault0(pVCpu);
4632 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
4633
4634 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
4635 {
4636 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
4637 IEM_SVM_UPDATE_NRIP(pVCpu);
4638 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4639 }
4640
4641 /*
4642 * Fetch the limit and base address.
4643 */
4644 uint16_t cbLimit;
4645 RTGCPTR GCPtrBase;
4646 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4647 if (rcStrict == VINF_SUCCESS)
4648 {
4649 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4650 || X86_IS_CANONICAL(GCPtrBase))
4651 {
4652 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4653 if (rcStrict == VINF_SUCCESS)
4654 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4655 }
4656 else
4657 {
4658 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4659 return iemRaiseGeneralProtectionFault0(pVCpu);
4660 }
4661 }
4662 return rcStrict;
4663}
4664
4665
4666/**
4667 * Implements sgdt.
4668 *
4669 * @param iEffSeg The segment where to store the gdtr content.
4670 * @param GCPtrEffDst The address where to store the gdtr content.
4671 */
4672IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4673{
4674 /*
4675 * Join paths with sidt.
4676 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4677 * you really must know.
4678 */
4679 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_READS))
4680 {
4681 Log(("sgdt: Guest intercept -> #VMEXIT\n"));
4682 IEM_SVM_UPDATE_NRIP(pVCpu);
4683 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4684 }
4685
4686 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4687 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst);
4688 if (rcStrict == VINF_SUCCESS)
4689 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4690 return rcStrict;
4691}
4692
4693
4694/**
4695 * Implements lidt.
4696 *
4697 * @param iEffSeg The segment of the new idtr contents
4698 * @param GCPtrEffSrc The address of the new idtr contents.
4699 * @param enmEffOpSize The effective operand size.
4700 */
4701IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4702{
4703 if (pVCpu->iem.s.uCpl != 0)
4704 return iemRaiseGeneralProtectionFault0(pVCpu);
4705 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
4706
4707 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
4708 {
4709 Log(("lidt: Guest intercept -> #VMEXIT\n"));
4710 IEM_SVM_UPDATE_NRIP(pVCpu);
4711 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4712 }
4713
4714 /*
4715 * Fetch the limit and base address.
4716 */
4717 uint16_t cbLimit;
4718 RTGCPTR GCPtrBase;
4719 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4720 if (rcStrict == VINF_SUCCESS)
4721 {
4722 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4723 || X86_IS_CANONICAL(GCPtrBase))
4724 {
4725 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4726 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4727 }
4728 else
4729 {
4730 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4731 return iemRaiseGeneralProtectionFault0(pVCpu);
4732 }
4733 }
4734 return rcStrict;
4735}
4736
4737
4738/**
4739 * Implements sidt.
4740 *
4741 * @param iEffSeg The segment where to store the idtr content.
4742 * @param GCPtrEffDst The address where to store the idtr content.
4743 */
4744IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4745{
4746 /*
4747 * Join paths with sgdt.
4748 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4749 * you really must know.
4750 */
4751 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_READS))
4752 {
4753 Log(("sidt: Guest intercept -> #VMEXIT\n"));
4754 IEM_SVM_UPDATE_NRIP(pVCpu);
4755 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4756 }
4757
4758 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_IDTR);
4759 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst);
4760 if (rcStrict == VINF_SUCCESS)
4761 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4762 return rcStrict;
4763}
4764
4765
4766/**
4767 * Implements lldt.
4768 *
4769 * @param uNewLdt The new LDT selector value.
4770 */
4771IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
4772{
4773 /*
4774 * Check preconditions.
4775 */
4776 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4777 {
4778 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
4779 return iemRaiseUndefinedOpcode(pVCpu);
4780 }
4781 if (pVCpu->iem.s.uCpl != 0)
4782 {
4783 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
4784 return iemRaiseGeneralProtectionFault0(pVCpu);
4785 }
4786 if (uNewLdt & X86_SEL_LDT)
4787 {
4788 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
4789 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
4790 }
4791
4792 /*
4793 * Now, loading a NULL selector is easy.
4794 */
4795 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
4796 {
4797 /* Nested-guest SVM intercept. */
4798 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4799 {
4800 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4801 IEM_SVM_UPDATE_NRIP(pVCpu);
4802 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4803 }
4804
4805 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
4806 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_LDTR;
4807 CPUMSetGuestLDTR(pVCpu, uNewLdt);
4808 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt;
4809 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4810 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
4811 {
4812 /* AMD-V seems to leave the base and limit alone. */
4813 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4814 }
4815 else
4816 {
4817 /* VT-x (Intel 3960x) seems to be doing the following. */
4818 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
4819 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
4820 pVCpu->cpum.GstCtx.ldtr.u32Limit = UINT32_MAX;
4821 }
4822
4823 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4824 return VINF_SUCCESS;
4825 }
4826
4827 /*
4828 * Read the descriptor.
4829 */
4830 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR);
4831 IEMSELDESC Desc;
4832 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
4833 if (rcStrict != VINF_SUCCESS)
4834 return rcStrict;
4835
4836 /* Check GPs first. */
4837 if (Desc.Legacy.Gen.u1DescType)
4838 {
4839 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4840 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4841 }
4842 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
4843 {
4844 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4845 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4846 }
4847 uint64_t u64Base;
4848 if (!IEM_IS_LONG_MODE(pVCpu))
4849 u64Base = X86DESC_BASE(&Desc.Legacy);
4850 else
4851 {
4852 if (Desc.Long.Gen.u5Zeros)
4853 {
4854 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
4855 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4856 }
4857
4858 u64Base = X86DESC64_BASE(&Desc.Long);
4859 if (!IEM_IS_CANONICAL(u64Base))
4860 {
4861 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
4862 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4863 }
4864 }
4865
4866 /* NP */
4867 if (!Desc.Legacy.Gen.u1Present)
4868 {
4869 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
4870 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
4871 }
4872
4873 /* Nested-guest SVM intercept. */
4874 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4875 {
4876 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4877 IEM_SVM_UPDATE_NRIP(pVCpu);
4878 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4879 }
4880
4881 /*
4882 * It checks out alright, update the registers.
4883 */
4884/** @todo check if the actual value is loaded or if the RPL is dropped */
4885 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4886 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4887 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4888 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4889 pVCpu->cpum.GstCtx.ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
4890 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
4891
4892 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4893 return VINF_SUCCESS;
4894}
4895
4896
4897/**
4898 * Implements sldt GReg
4899 *
4900 * @param iGReg The general register to store the CRx value in.
4901 * @param enmEffOpSize The operand size.
4902 */
4903IEM_CIMPL_DEF_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
4904{
4905 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
4906
4907 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4908 switch (enmEffOpSize)
4909 {
4910 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4911 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4912 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4913 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4914 }
4915 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4916 return VINF_SUCCESS;
4917}
4918
4919
4920/**
4921 * Implements sldt mem.
4922 *
4923 * @param iGReg The general register to store the CRx value in.
4924 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
4925 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
4926 */
4927IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4928{
4929 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
4930
4931 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4932 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel);
4933 if (rcStrict == VINF_SUCCESS)
4934 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4935 return rcStrict;
4936}
4937
4938
4939/**
4940 * Implements ltr.
4941 *
4942 * @param uNewTr The new TSS selector value.
4943 */
4944IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
4945{
4946 /*
4947 * Check preconditions.
4948 */
4949 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4950 {
4951 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
4952 return iemRaiseUndefinedOpcode(pVCpu);
4953 }
4954 if (pVCpu->iem.s.uCpl != 0)
4955 {
4956 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
4957 return iemRaiseGeneralProtectionFault0(pVCpu);
4958 }
4959 if (uNewTr & X86_SEL_LDT)
4960 {
4961 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
4962 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
4963 }
4964 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
4965 {
4966 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
4967 return iemRaiseGeneralProtectionFault0(pVCpu);
4968 }
4969 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
4970 {
4971 Log(("ltr: Guest intercept -> #VMEXIT\n"));
4972 IEM_SVM_UPDATE_NRIP(pVCpu);
4973 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4974 }
4975
4976 /*
4977 * Read the descriptor.
4978 */
4979 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_TR);
4980 IEMSELDESC Desc;
4981 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
4982 if (rcStrict != VINF_SUCCESS)
4983 return rcStrict;
4984
4985 /* Check GPs first. */
4986 if (Desc.Legacy.Gen.u1DescType)
4987 {
4988 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4989 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4990 }
4991 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
4992 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
4993 || IEM_IS_LONG_MODE(pVCpu)) )
4994 {
4995 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4996 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4997 }
4998 uint64_t u64Base;
4999 if (!IEM_IS_LONG_MODE(pVCpu))
5000 u64Base = X86DESC_BASE(&Desc.Legacy);
5001 else
5002 {
5003 if (Desc.Long.Gen.u5Zeros)
5004 {
5005 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
5006 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5007 }
5008
5009 u64Base = X86DESC64_BASE(&Desc.Long);
5010 if (!IEM_IS_CANONICAL(u64Base))
5011 {
5012 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5013 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5014 }
5015 }
5016
5017 /* NP */
5018 if (!Desc.Legacy.Gen.u1Present)
5019 {
5020 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5021 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5022 }
5023
5024 /*
5025 * Set it busy.
5026 * Note! Intel says this should lock down the whole descriptor, but we'll
5027 * restrict our selves to 32-bit for now due to lack of inline
5028 * assembly and such.
5029 */
5030 void *pvDesc;
5031 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pVCpu->cpum.GstCtx.gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL), IEM_ACCESS_DATA_RW);
5032 if (rcStrict != VINF_SUCCESS)
5033 return rcStrict;
5034 switch ((uintptr_t)pvDesc & 3)
5035 {
5036 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5037 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5038 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5039 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5040 }
5041 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5042 if (rcStrict != VINF_SUCCESS)
5043 return rcStrict;
5044 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5045
5046 /*
5047 * It checks out alright, update the registers.
5048 */
5049/** @todo check if the actual value is loaded or if the RPL is dropped */
5050 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5051 pVCpu->cpum.GstCtx.tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5052 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5053 pVCpu->cpum.GstCtx.tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5054 pVCpu->cpum.GstCtx.tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5055 pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
5056
5057 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5058 return VINF_SUCCESS;
5059}
5060
5061
5062/**
5063 * Implements str GReg
5064 *
5065 * @param iGReg The general register to store the CRx value in.
5066 * @param enmEffOpSize The operand size.
5067 */
5068IEM_CIMPL_DEF_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5069{
5070 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5071
5072 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5073 switch (enmEffOpSize)
5074 {
5075 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5076 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5077 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5078 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5079 }
5080 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5081 return VINF_SUCCESS;
5082}
5083
5084
5085/**
5086 * Implements str mem.
5087 *
5088 * @param iGReg The general register to store the CRx value in.
5089 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5090 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5091 */
5092IEM_CIMPL_DEF_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5093{
5094 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5095
5096 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5097 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel);
5098 if (rcStrict == VINF_SUCCESS)
5099 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5100 return rcStrict;
5101}
5102
5103
5104/**
5105 * Implements mov GReg,CRx.
5106 *
5107 * @param iGReg The general register to store the CRx value in.
5108 * @param iCrReg The CRx register to read (valid).
5109 */
5110IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5111{
5112 if (pVCpu->iem.s.uCpl != 0)
5113 return iemRaiseGeneralProtectionFault0(pVCpu);
5114 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5115
5116 if (IEM_SVM_IS_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5117 {
5118 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5119 IEM_SVM_UPDATE_NRIP(pVCpu);
5120 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5121 }
5122
5123 /* read it */
5124 uint64_t crX;
5125 switch (iCrReg)
5126 {
5127 case 0:
5128 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5129 crX = pVCpu->cpum.GstCtx.cr0;
5130 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5131 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5132 break;
5133 case 2:
5134 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR2);
5135 crX = pVCpu->cpum.GstCtx.cr2;
5136 break;
5137 case 3:
5138 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5139 crX = pVCpu->cpum.GstCtx.cr3;
5140 break;
5141 case 4:
5142 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5143 crX = pVCpu->cpum.GstCtx.cr4;
5144 break;
5145 case 8:
5146 {
5147 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5148#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5149 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5150 {
5151 PCSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5152 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5153 {
5154 crX = pVmcbCtrl->IntCtrl.n.u8VTPR & 0xf;
5155 break;
5156 }
5157 }
5158#endif
5159 uint8_t uTpr;
5160 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5161 if (RT_SUCCESS(rc))
5162 crX = uTpr >> 4;
5163 else
5164 crX = 0;
5165 break;
5166 }
5167 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5168 }
5169
5170 /* store it */
5171 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5172 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5173 else
5174 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5175
5176 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5177 return VINF_SUCCESS;
5178}
5179
5180
5181/**
5182 * Implements smsw GReg
5183 *
5184 * @param iGReg The general register to store the CRx value in.
5185 * @param enmEffOpSize The operand size.
5186 */
5187IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5188{
5189 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5190
5191 switch (enmEffOpSize)
5192 {
5193 case IEMMODE_16BIT:
5194 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5195 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0;
5196 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5197 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xffe0;
5198 else
5199 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xfff0;
5200 break;
5201
5202 case IEMMODE_32BIT:
5203 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)pVCpu->cpum.GstCtx.cr0;
5204 break;
5205
5206 case IEMMODE_64BIT:
5207 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.cr0;
5208 break;
5209
5210 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5211 }
5212
5213 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5214 return VINF_SUCCESS;
5215}
5216
5217
5218/**
5219 * Implements smsw mem.
5220 *
5221 * @param iGReg The general register to store the CR0 value in.
5222 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5223 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5224 */
5225IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5226{
5227 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5228
5229 uint16_t u16Value;
5230 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5231 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0;
5232 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5233 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xffe0;
5234 else
5235 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xfff0;
5236
5237 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value);
5238 if (rcStrict == VINF_SUCCESS)
5239 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5240 return rcStrict;
5241}
5242
5243
5244/**
5245 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5246 *
5247 * @param iCrReg The CRx register to write (valid).
5248 * @param uNewCrX The new value.
5249 * @param enmAccessCrx The instruction that caused the CrX load.
5250 * @param iGReg The general register in case of a 'mov CRx,GReg'
5251 * instruction.
5252 */
5253IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5254{
5255 VBOXSTRICTRC rcStrict;
5256 int rc;
5257#ifndef VBOX_WITH_NESTED_HWVIRT_SVM
5258 RT_NOREF2(iGReg, enmAccessCrX);
5259#endif
5260
5261 /*
5262 * Try store it.
5263 * Unfortunately, CPUM only does a tiny bit of the work.
5264 */
5265 switch (iCrReg)
5266 {
5267 case 0:
5268 {
5269 /*
5270 * Perform checks.
5271 */
5272 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5273
5274 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr0;
5275 uint32_t const fValid = X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
5276 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
5277 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG;
5278
5279 /* ET is hardcoded on 486 and later. */
5280 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5281 uNewCrX |= X86_CR0_ET;
5282 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5283 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5284 {
5285 uNewCrX &= fValid;
5286 uNewCrX |= X86_CR0_ET;
5287 }
5288 else
5289 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5290
5291 /* Check for reserved bits. */
5292 if (uNewCrX & ~(uint64_t)fValid)
5293 {
5294 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5295 return iemRaiseGeneralProtectionFault0(pVCpu);
5296 }
5297
5298 /* Check for invalid combinations. */
5299 if ( (uNewCrX & X86_CR0_PG)
5300 && !(uNewCrX & X86_CR0_PE) )
5301 {
5302 Log(("Trying to set CR0.PG without CR0.PE\n"));
5303 return iemRaiseGeneralProtectionFault0(pVCpu);
5304 }
5305
5306 if ( !(uNewCrX & X86_CR0_CD)
5307 && (uNewCrX & X86_CR0_NW) )
5308 {
5309 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5310 return iemRaiseGeneralProtectionFault0(pVCpu);
5311 }
5312
5313 if ( !(uNewCrX & X86_CR0_PG)
5314 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE))
5315 {
5316 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5317 return iemRaiseGeneralProtectionFault0(pVCpu);
5318 }
5319
5320 /* Long mode consistency checks. */
5321 if ( (uNewCrX & X86_CR0_PG)
5322 && !(uOldCrX & X86_CR0_PG)
5323 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5324 {
5325 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE))
5326 {
5327 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5328 return iemRaiseGeneralProtectionFault0(pVCpu);
5329 }
5330 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long)
5331 {
5332 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5333 return iemRaiseGeneralProtectionFault0(pVCpu);
5334 }
5335 }
5336
5337 /* Check for bits that must remain set or cleared in VMX operation,
5338 see Intel spec. 23.8 "Restrictions on VMX operation". */
5339 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5340 {
5341 uint32_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
5342 if ((uNewCrX & uCr0Fixed0) != uCr0Fixed0)
5343 {
5344 Log(("Trying to clear reserved CR0 bits in VMX operation: NewCr0=%#llx MB1=%#llx\n", uNewCrX, uCr0Fixed0));
5345 return iemRaiseGeneralProtectionFault0(pVCpu);
5346 }
5347
5348 uint32_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
5349 if (uNewCrX & ~uCr0Fixed1)
5350 {
5351 Log(("Trying to set reserved CR0 bits in VMX operation: NewCr0=%#llx MB0=%#llx\n", uNewCrX, uCr0Fixed1));
5352 return iemRaiseGeneralProtectionFault0(pVCpu);
5353 }
5354 }
5355
5356 /** @todo check reserved PDPTR bits as AMD states. */
5357
5358 /*
5359 * SVM nested-guest CR0 write intercepts.
5360 */
5361 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5362 {
5363 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5364 IEM_SVM_UPDATE_NRIP(pVCpu);
5365 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5366 }
5367 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5368 {
5369 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5370 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5371 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5372 {
5373 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5374 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg));
5375 IEM_SVM_UPDATE_NRIP(pVCpu);
5376 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg);
5377 }
5378 }
5379
5380 /*
5381 * Change CR0.
5382 */
5383 CPUMSetGuestCR0(pVCpu, uNewCrX);
5384 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCrX);
5385
5386 /*
5387 * Change EFER.LMA if entering or leaving long mode.
5388 */
5389 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5390 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5391 {
5392 uint64_t NewEFER = pVCpu->cpum.GstCtx.msrEFER;
5393 if (uNewCrX & X86_CR0_PG)
5394 NewEFER |= MSR_K6_EFER_LMA;
5395 else
5396 NewEFER &= ~MSR_K6_EFER_LMA;
5397
5398 CPUMSetGuestEFER(pVCpu, NewEFER);
5399 Assert(pVCpu->cpum.GstCtx.msrEFER == NewEFER);
5400 }
5401
5402 /*
5403 * Inform PGM.
5404 */
5405 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
5406 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
5407 {
5408 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5409 AssertRCReturn(rc, rc);
5410 /* ignore informational status codes */
5411 }
5412 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
5413
5414#ifdef IN_RC
5415 /* Return to ring-3 for rescheduling if WP or AM changes. */
5416 if ( rcStrict == VINF_SUCCESS
5417 && ( (uNewCrX & (X86_CR0_WP | X86_CR0_AM))
5418 != (uOldCrX & (X86_CR0_WP | X86_CR0_AM))) )
5419 rcStrict = VINF_EM_RESCHEDULE;
5420#endif
5421 break;
5422 }
5423
5424 /*
5425 * CR2 can be changed without any restrictions.
5426 */
5427 case 2:
5428 {
5429 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5430 {
5431 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5432 IEM_SVM_UPDATE_NRIP(pVCpu);
5433 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5434 }
5435 pVCpu->cpum.GstCtx.cr2 = uNewCrX;
5436 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_CR2;
5437 rcStrict = VINF_SUCCESS;
5438 break;
5439 }
5440
5441 /*
5442 * CR3 is relatively simple, although AMD and Intel have different
5443 * accounts of how setting reserved bits are handled. We take intel's
5444 * word for the lower bits and AMD's for the high bits (63:52). The
5445 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5446 * on this.
5447 */
5448 /** @todo Testcase: Setting reserved bits in CR3, especially before
5449 * enabling paging. */
5450 case 3:
5451 {
5452 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5453
5454 /* clear bit 63 from the source operand and indicate no invalidations are required. */
5455 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
5456 && (uNewCrX & RT_BIT_64(63)))
5457 {
5458 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
5459 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
5460 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
5461 * Paging-Structure Caches". */
5462 uNewCrX &= ~RT_BIT_64(63);
5463 }
5464
5465 /* check / mask the value. */
5466 if (uNewCrX & UINT64_C(0xfff0000000000000))
5467 {
5468 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
5469 return iemRaiseGeneralProtectionFault0(pVCpu);
5470 }
5471
5472 uint64_t fValid;
5473 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
5474 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME))
5475 fValid = UINT64_C(0x000fffffffffffff);
5476 else
5477 fValid = UINT64_C(0xffffffff);
5478 if (uNewCrX & ~fValid)
5479 {
5480 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
5481 uNewCrX, uNewCrX & ~fValid));
5482 uNewCrX &= fValid;
5483 }
5484
5485 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
5486 {
5487 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5488 IEM_SVM_UPDATE_NRIP(pVCpu);
5489 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
5490 }
5491
5492 /** @todo If we're in PAE mode we should check the PDPTRs for
5493 * invalid bits. */
5494
5495 /* Make the change. */
5496 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
5497 AssertRCSuccessReturn(rc, rc);
5498
5499 /* Inform PGM. */
5500 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
5501 {
5502 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PGE));
5503 AssertRCReturn(rc, rc);
5504 /* ignore informational status codes */
5505 }
5506 rcStrict = VINF_SUCCESS;
5507 break;
5508 }
5509
5510 /*
5511 * CR4 is a bit more tedious as there are bits which cannot be cleared
5512 * under some circumstances and such.
5513 */
5514 case 4:
5515 {
5516 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5517 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr4;
5518
5519 /** @todo Shouldn't this look at the guest CPUID bits to determine
5520 * valid bits? e.g. if guest CPUID doesn't allow X86_CR4_OSXMMEEXCPT, we
5521 * should #GP(0). */
5522 /* reserved bits */
5523 uint32_t fValid = X86_CR4_VME | X86_CR4_PVI
5524 | X86_CR4_TSD | X86_CR4_DE
5525 | X86_CR4_PSE | X86_CR4_PAE
5526 | X86_CR4_MCE | X86_CR4_PGE
5527 | X86_CR4_PCE | X86_CR4_OSFXSR
5528 | X86_CR4_OSXMMEEXCPT;
5529 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmx)
5530 fValid |= X86_CR4_VMXE;
5531 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
5532 fValid |= X86_CR4_OSXSAVE;
5533 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPcid)
5534 fValid |= X86_CR4_PCIDE;
5535 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase)
5536 fValid |= X86_CR4_FSGSBASE;
5537 if (uNewCrX & ~(uint64_t)fValid)
5538 {
5539 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5540 return iemRaiseGeneralProtectionFault0(pVCpu);
5541 }
5542
5543 bool const fPcide = ((uNewCrX ^ uOldCrX) & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
5544 bool const fLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
5545
5546 /* PCIDE check. */
5547 if ( fPcide
5548 && ( !fLongMode
5549 || (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))))
5550 {
5551 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))));
5552 return iemRaiseGeneralProtectionFault0(pVCpu);
5553 }
5554
5555 /* PAE check. */
5556 if ( fLongMode
5557 && (uOldCrX & X86_CR4_PAE)
5558 && !(uNewCrX & X86_CR4_PAE))
5559 {
5560 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
5561 return iemRaiseGeneralProtectionFault0(pVCpu);
5562 }
5563
5564 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
5565 {
5566 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5567 IEM_SVM_UPDATE_NRIP(pVCpu);
5568 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
5569 }
5570
5571 /* Check for bits that must remain set or cleared in VMX operation,
5572 see Intel spec. 23.8 "Restrictions on VMX operation". */
5573 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5574 {
5575 uint32_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
5576 if ((uNewCrX & uCr4Fixed0) != uCr4Fixed0)
5577 {
5578 Log(("Trying to clear reserved CR4 bits in VMX operation: NewCr4=%#llx MB1=%#llx\n", uNewCrX, uCr4Fixed0));
5579 return iemRaiseGeneralProtectionFault0(pVCpu);
5580 }
5581
5582 uint32_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
5583 if (uNewCrX & ~uCr4Fixed1)
5584 {
5585 Log(("Trying to set reserved CR4 bits in VMX operation: NewCr4=%#llx MB0=%#llx\n", uNewCrX, uCr4Fixed1));
5586 return iemRaiseGeneralProtectionFault0(pVCpu);
5587 }
5588 }
5589
5590 /*
5591 * Change it.
5592 */
5593 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
5594 AssertRCSuccessReturn(rc, rc);
5595 Assert(pVCpu->cpum.GstCtx.cr4 == uNewCrX);
5596
5597 /*
5598 * Notify SELM and PGM.
5599 */
5600 /* SELM - VME may change things wrt to the TSS shadowing. */
5601 if ((uNewCrX ^ uOldCrX) & X86_CR4_VME)
5602 {
5603 Log(("iemCImpl_load_CrX: VME %d -> %d => Setting VMCPU_FF_SELM_SYNC_TSS\n",
5604 RT_BOOL(uOldCrX & X86_CR4_VME), RT_BOOL(uNewCrX & X86_CR4_VME) ));
5605#ifdef VBOX_WITH_RAW_MODE
5606 if (VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
5607 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
5608#endif
5609 }
5610
5611 /* PGM - flushing and mode. */
5612 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
5613 {
5614 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5615 AssertRCReturn(rc, rc);
5616 /* ignore informational status codes */
5617 }
5618 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
5619 break;
5620 }
5621
5622 /*
5623 * CR8 maps to the APIC TPR.
5624 */
5625 case 8:
5626 {
5627 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5628 if (uNewCrX & ~(uint64_t)0xf)
5629 {
5630 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
5631 return iemRaiseGeneralProtectionFault0(pVCpu);
5632 }
5633
5634#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5635 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5636 {
5637 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
5638 {
5639 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5640 IEM_SVM_UPDATE_NRIP(pVCpu);
5641 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
5642 }
5643
5644 PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5645 pVmcbCtrl->IntCtrl.n.u8VTPR = uNewCrX;
5646 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5647 {
5648 rcStrict = VINF_SUCCESS;
5649 break;
5650 }
5651 }
5652#endif
5653 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
5654 APICSetTpr(pVCpu, u8Tpr);
5655 rcStrict = VINF_SUCCESS;
5656 break;
5657 }
5658
5659 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5660 }
5661
5662 /*
5663 * Advance the RIP on success.
5664 */
5665 if (RT_SUCCESS(rcStrict))
5666 {
5667 if (rcStrict != VINF_SUCCESS)
5668 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
5669 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5670 }
5671
5672 return rcStrict;
5673}
5674
5675
5676/**
5677 * Implements mov CRx,GReg.
5678 *
5679 * @param iCrReg The CRx register to write (valid).
5680 * @param iGReg The general register to load the DRx value from.
5681 */
5682IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
5683{
5684 if (pVCpu->iem.s.uCpl != 0)
5685 return iemRaiseGeneralProtectionFault0(pVCpu);
5686 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5687
5688 /*
5689 * Read the new value from the source register and call common worker.
5690 */
5691 uint64_t uNewCrX;
5692 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5693 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
5694 else
5695 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
5696 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
5697}
5698
5699
5700/**
5701 * Implements 'LMSW r/m16'
5702 *
5703 * @param u16NewMsw The new value.
5704 */
5705IEM_CIMPL_DEF_1(iemCImpl_lmsw, uint16_t, u16NewMsw)
5706{
5707 if (pVCpu->iem.s.uCpl != 0)
5708 return iemRaiseGeneralProtectionFault0(pVCpu);
5709 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5710
5711 /*
5712 * Compose the new CR0 value and call common worker.
5713 */
5714 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5715 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5716 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5717 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
5718}
5719
5720
5721/**
5722 * Implements 'CLTS'.
5723 */
5724IEM_CIMPL_DEF_0(iemCImpl_clts)
5725{
5726 if (pVCpu->iem.s.uCpl != 0)
5727 return iemRaiseGeneralProtectionFault0(pVCpu);
5728
5729 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5730 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0;
5731 uNewCr0 &= ~X86_CR0_TS;
5732 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
5733}
5734
5735
5736/**
5737 * Implements mov GReg,DRx.
5738 *
5739 * @param iGReg The general register to store the DRx value in.
5740 * @param iDrReg The DRx register to read (0-7).
5741 */
5742IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
5743{
5744 /*
5745 * Check preconditions.
5746 */
5747
5748 /* Raise GPs. */
5749 if (pVCpu->iem.s.uCpl != 0)
5750 return iemRaiseGeneralProtectionFault0(pVCpu);
5751 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5752 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
5753
5754 if ( (iDrReg == 4 || iDrReg == 5)
5755 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
5756 {
5757 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
5758 return iemRaiseGeneralProtectionFault0(pVCpu);
5759 }
5760
5761 /* Raise #DB if general access detect is enabled. */
5762 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
5763 {
5764 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
5765 return iemRaiseDebugException(pVCpu);
5766 }
5767
5768 /*
5769 * Read the debug register and store it in the specified general register.
5770 */
5771 uint64_t drX;
5772 switch (iDrReg)
5773 {
5774 case 0:
5775 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5776 drX = pVCpu->cpum.GstCtx.dr[0];
5777 break;
5778 case 1:
5779 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5780 drX = pVCpu->cpum.GstCtx.dr[1];
5781 break;
5782 case 2:
5783 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5784 drX = pVCpu->cpum.GstCtx.dr[2];
5785 break;
5786 case 3:
5787 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5788 drX = pVCpu->cpum.GstCtx.dr[3];
5789 break;
5790 case 6:
5791 case 4:
5792 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
5793 drX = pVCpu->cpum.GstCtx.dr[6];
5794 drX |= X86_DR6_RA1_MASK;
5795 drX &= ~X86_DR6_RAZ_MASK;
5796 break;
5797 case 7:
5798 case 5:
5799 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
5800 drX = pVCpu->cpum.GstCtx.dr[7];
5801 drX |=X86_DR7_RA1_MASK;
5802 drX &= ~X86_DR7_RAZ_MASK;
5803 break;
5804 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5805 }
5806
5807 /** @todo SVM nested-guest intercept for DR8-DR15? */
5808 /*
5809 * Check for any SVM nested-guest intercepts for the DRx read.
5810 */
5811 if (IEM_SVM_IS_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
5812 {
5813 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
5814 IEM_SVM_UPDATE_NRIP(pVCpu);
5815 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
5816 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
5817 }
5818
5819 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5820 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
5821 else
5822 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
5823
5824 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5825 return VINF_SUCCESS;
5826}
5827
5828
5829/**
5830 * Implements mov DRx,GReg.
5831 *
5832 * @param iDrReg The DRx register to write (valid).
5833 * @param iGReg The general register to load the DRx value from.
5834 */
5835IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
5836{
5837 /*
5838 * Check preconditions.
5839 */
5840 if (pVCpu->iem.s.uCpl != 0)
5841 return iemRaiseGeneralProtectionFault0(pVCpu);
5842 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5843 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
5844
5845 if (iDrReg == 4 || iDrReg == 5)
5846 {
5847 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
5848 {
5849 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
5850 return iemRaiseGeneralProtectionFault0(pVCpu);
5851 }
5852 iDrReg += 2;
5853 }
5854
5855 /* Raise #DB if general access detect is enabled. */
5856 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
5857 * \#GP? */
5858 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
5859 {
5860 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
5861 return iemRaiseDebugException(pVCpu);
5862 }
5863
5864 /*
5865 * Read the new value from the source register.
5866 */
5867 uint64_t uNewDrX;
5868 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5869 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
5870 else
5871 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
5872
5873 /*
5874 * Adjust it.
5875 */
5876 switch (iDrReg)
5877 {
5878 case 0:
5879 case 1:
5880 case 2:
5881 case 3:
5882 /* nothing to adjust */
5883 break;
5884
5885 case 6:
5886 if (uNewDrX & X86_DR6_MBZ_MASK)
5887 {
5888 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5889 return iemRaiseGeneralProtectionFault0(pVCpu);
5890 }
5891 uNewDrX |= X86_DR6_RA1_MASK;
5892 uNewDrX &= ~X86_DR6_RAZ_MASK;
5893 break;
5894
5895 case 7:
5896 if (uNewDrX & X86_DR7_MBZ_MASK)
5897 {
5898 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5899 return iemRaiseGeneralProtectionFault0(pVCpu);
5900 }
5901 uNewDrX |= X86_DR7_RA1_MASK;
5902 uNewDrX &= ~X86_DR7_RAZ_MASK;
5903 break;
5904
5905 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5906 }
5907
5908 /** @todo SVM nested-guest intercept for DR8-DR15? */
5909 /*
5910 * Check for any SVM nested-guest intercepts for the DRx write.
5911 */
5912 if (IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
5913 {
5914 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
5915 IEM_SVM_UPDATE_NRIP(pVCpu);
5916 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
5917 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
5918 }
5919
5920 /*
5921 * Do the actual setting.
5922 */
5923 if (iDrReg < 4)
5924 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5925 else if (iDrReg == 6)
5926 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
5927
5928 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
5929 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
5930
5931 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5932 return VINF_SUCCESS;
5933}
5934
5935
5936/**
5937 * Implements 'INVLPG m'.
5938 *
5939 * @param GCPtrPage The effective address of the page to invalidate.
5940 * @remarks Updates the RIP.
5941 */
5942IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
5943{
5944 /* ring-0 only. */
5945 if (pVCpu->iem.s.uCpl != 0)
5946 return iemRaiseGeneralProtectionFault0(pVCpu);
5947 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5948 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
5949
5950#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5951 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
5952 {
5953 Log(("invlpg: Guest intercept (%RGp) -> VM-exit\n", GCPtrPage));
5954 return iemVmxVmexitInstrInvlpg(pVCpu, GCPtrPage, cbInstr);
5955 }
5956#endif
5957
5958 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
5959 {
5960 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
5961 IEM_SVM_UPDATE_NRIP(pVCpu);
5962 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG,
5963 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
5964 }
5965
5966 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
5967 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5968
5969 if (rc == VINF_SUCCESS)
5970 return VINF_SUCCESS;
5971 if (rc == VINF_PGM_SYNC_CR3)
5972 return iemSetPassUpStatus(pVCpu, rc);
5973
5974 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
5975 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
5976 return rc;
5977}
5978
5979
5980/**
5981 * Implements INVPCID.
5982 *
5983 * @param iEffSeg The segment of the invpcid descriptor.
5984 * @param GCPtrInvpcidDesc The address of invpcid descriptor.
5985 * @param uInvpcidType The invalidation type.
5986 * @remarks Updates the RIP.
5987 */
5988IEM_CIMPL_DEF_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint8_t, uInvpcidType)
5989{
5990 /*
5991 * Check preconditions.
5992 */
5993 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
5994 return iemRaiseUndefinedOpcode(pVCpu);
5995
5996 /* When in VMX non-root mode and INVPCID is not enabled, it results in #UD. */
5997 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5998 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_INVPCID))
5999 {
6000 Log(("invpcid: Not enabled for nested-guest execution -> #UD\n"));
6001 return iemRaiseUndefinedOpcode(pVCpu);
6002 }
6003
6004 if (pVCpu->iem.s.uCpl != 0)
6005 {
6006 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
6007 return iemRaiseGeneralProtectionFault0(pVCpu);
6008 }
6009
6010 if (IEM_IS_V86_MODE(pVCpu))
6011 {
6012 Log(("invpcid: v8086 mode -> #GP(0)\n"));
6013 return iemRaiseGeneralProtectionFault0(pVCpu);
6014 }
6015
6016 /*
6017 * Check nested-guest intercept.
6018 *
6019 * INVPCID causes a VM-exit if "enable INVPCID" and "INVLPG exiting" are
6020 * both set. We have already checked the former earlier in this function.
6021 *
6022 * CPL checks take priority over VM-exit.
6023 * See Intel spec. "25.1.1 Relative Priority of Faults and VM Exits".
6024 */
6025 /** @todo r=ramshankar: NSTVMX: I'm not entirely certain if V86 mode check has
6026 * higher or lower priority than a VM-exit, we assume higher for the time
6027 * being. */
6028 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6029 {
6030 Log(("invpcid: Guest intercept -> #VM-exit\n"));
6031 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_INVPCID, VMXINSTRID_NONE, cbInstr);
6032 }
6033
6034 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
6035 {
6036 Log(("invpcid: invalid/unrecognized invpcid type %#x -> #GP(0)\n", uInvpcidType));
6037 return iemRaiseGeneralProtectionFault0(pVCpu);
6038 }
6039 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6040
6041 /*
6042 * Fetch the invpcid descriptor from guest memory.
6043 */
6044 RTUINT128U uDesc;
6045 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvpcidDesc);
6046 if (rcStrict == VINF_SUCCESS)
6047 {
6048 /*
6049 * Validate the descriptor.
6050 */
6051 if (uDesc.s.Lo > 0xfff)
6052 {
6053 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
6054 return iemRaiseGeneralProtectionFault0(pVCpu);
6055 }
6056
6057 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
6058 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
6059 uint32_t const uCr4 = pVCpu->cpum.GstCtx.cr4;
6060 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
6061 switch (uInvpcidType)
6062 {
6063 case X86_INVPCID_TYPE_INDV_ADDR:
6064 {
6065 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
6066 {
6067 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
6068 return iemRaiseGeneralProtectionFault0(pVCpu);
6069 }
6070 if ( !(uCr4 & X86_CR4_PCIDE)
6071 && uPcid != 0)
6072 {
6073 Log(("invpcid: invalid pcid %#x\n", uPcid));
6074 return iemRaiseGeneralProtectionFault0(pVCpu);
6075 }
6076
6077 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
6078 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6079 break;
6080 }
6081
6082 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
6083 {
6084 if ( !(uCr4 & X86_CR4_PCIDE)
6085 && uPcid != 0)
6086 {
6087 Log(("invpcid: invalid pcid %#x\n", uPcid));
6088 return iemRaiseGeneralProtectionFault0(pVCpu);
6089 }
6090 /* Invalidate all mappings associated with PCID except global translations. */
6091 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6092 break;
6093 }
6094
6095 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
6096 {
6097 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
6098 break;
6099 }
6100
6101 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
6102 {
6103 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6104 break;
6105 }
6106 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6107 }
6108 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6109 }
6110 return rcStrict;
6111}
6112
6113
6114/**
6115 * Implements INVD.
6116 */
6117IEM_CIMPL_DEF_0(iemCImpl_invd)
6118{
6119 if (pVCpu->iem.s.uCpl != 0)
6120 {
6121 Log(("invd: CPL != 0 -> #GP(0)\n"));
6122 return iemRaiseGeneralProtectionFault0(pVCpu);
6123 }
6124
6125 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
6126
6127 /* We currently take no action here. */
6128 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6129 return VINF_SUCCESS;
6130}
6131
6132
6133/**
6134 * Implements WBINVD.
6135 */
6136IEM_CIMPL_DEF_0(iemCImpl_wbinvd)
6137{
6138 if (pVCpu->iem.s.uCpl != 0)
6139 {
6140 Log(("wbinvd: CPL != 0 -> #GP(0)\n"));
6141 return iemRaiseGeneralProtectionFault0(pVCpu);
6142 }
6143
6144 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
6145
6146 /* We currently take no action here. */
6147 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6148 return VINF_SUCCESS;
6149}
6150
6151
6152/** Opcode 0x0f 0xaa. */
6153IEM_CIMPL_DEF_0(iemCImpl_rsm)
6154{
6155 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6156 NOREF(cbInstr);
6157 return iemRaiseUndefinedOpcode(pVCpu);
6158}
6159
6160
6161/**
6162 * Implements RDTSC.
6163 */
6164IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
6165{
6166 /*
6167 * Check preconditions.
6168 */
6169 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
6170 return iemRaiseUndefinedOpcode(pVCpu);
6171
6172 if (pVCpu->iem.s.uCpl != 0)
6173 {
6174 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6175 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6176 {
6177 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6178 return iemRaiseGeneralProtectionFault0(pVCpu);
6179 }
6180 }
6181
6182 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6183 {
6184 Log(("rdtsc: Guest intercept -> VM-exit\n"));
6185 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSC, cbInstr);
6186 }
6187
6188 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
6189 {
6190 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
6191 IEM_SVM_UPDATE_NRIP(pVCpu);
6192 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6193 }
6194
6195 /*
6196 * Do the job.
6197 */
6198 uint64_t uTicks = TMCpuTickGet(pVCpu);
6199#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6200 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6201#endif
6202 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6203 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6204 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
6205 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6206 return VINF_SUCCESS;
6207}
6208
6209
6210/**
6211 * Implements RDTSC.
6212 */
6213IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
6214{
6215 /*
6216 * Check preconditions.
6217 */
6218 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
6219 return iemRaiseUndefinedOpcode(pVCpu);
6220
6221 if (pVCpu->iem.s.uCpl != 0)
6222 {
6223 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6224 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6225 {
6226 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6227 return iemRaiseGeneralProtectionFault0(pVCpu);
6228 }
6229 }
6230
6231 if (IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_RDTSCP))
6232 {
6233 Log(("rdtscp: Guest intercept -> VM-exit\n"));
6234 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSCP, cbInstr);
6235 }
6236 else if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
6237 {
6238 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
6239 IEM_SVM_UPDATE_NRIP(pVCpu);
6240 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6241 }
6242
6243 /*
6244 * Do the job.
6245 * Query the MSR first in case of trips to ring-3.
6246 */
6247 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
6248 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pVCpu->cpum.GstCtx.rcx);
6249 if (rcStrict == VINF_SUCCESS)
6250 {
6251 /* Low dword of the TSC_AUX msr only. */
6252 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
6253
6254 uint64_t uTicks = TMCpuTickGet(pVCpu);
6255#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6256 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6257#endif
6258 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6259 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6260 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
6261 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6262 }
6263 return rcStrict;
6264}
6265
6266
6267/**
6268 * Implements RDPMC.
6269 */
6270IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
6271{
6272 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6273
6274 if ( pVCpu->iem.s.uCpl != 0
6275 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCE))
6276 return iemRaiseGeneralProtectionFault0(pVCpu);
6277
6278 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDPMC_EXIT))
6279 {
6280 Log(("rdpmc: Guest intercept -> VM-exit\n"));
6281 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDPMC, cbInstr);
6282 }
6283
6284 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
6285 {
6286 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
6287 IEM_SVM_UPDATE_NRIP(pVCpu);
6288 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6289 }
6290
6291 /** @todo Emulate performance counters, for now just return 0. */
6292 pVCpu->cpum.GstCtx.rax = 0;
6293 pVCpu->cpum.GstCtx.rdx = 0;
6294 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
6295 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
6296 * ecx but see @bugref{3472}! */
6297
6298 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6299 return VINF_SUCCESS;
6300}
6301
6302
6303/**
6304 * Implements RDMSR.
6305 */
6306IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
6307{
6308 /*
6309 * Check preconditions.
6310 */
6311 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6312 return iemRaiseUndefinedOpcode(pVCpu);
6313 if (pVCpu->iem.s.uCpl != 0)
6314 return iemRaiseGeneralProtectionFault0(pVCpu);
6315
6316 /*
6317 * Check nested-guest intercepts.
6318 */
6319#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6320 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6321 && iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_RDMSR, pVCpu->cpum.GstCtx.ecx))
6322 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDMSR, cbInstr);
6323#endif
6324
6325#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6326 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6327 {
6328 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */);
6329 if (rcStrict == VINF_SVM_VMEXIT)
6330 return VINF_SUCCESS;
6331 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6332 {
6333 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
6334 return rcStrict;
6335 }
6336 }
6337#endif
6338
6339 /*
6340 * Do the job.
6341 */
6342 RTUINT64U uValue;
6343 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
6344 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
6345
6346 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, &uValue.u);
6347 if (rcStrict == VINF_SUCCESS)
6348 {
6349 pVCpu->cpum.GstCtx.rax = uValue.s.Lo;
6350 pVCpu->cpum.GstCtx.rdx = uValue.s.Hi;
6351 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
6352
6353 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6354 return VINF_SUCCESS;
6355 }
6356
6357#ifndef IN_RING3
6358 /* Deferred to ring-3. */
6359 if (rcStrict == VINF_CPUM_R3_MSR_READ)
6360 {
6361 Log(("IEM: rdmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
6362 return rcStrict;
6363 }
6364#endif
6365
6366 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6367 if (pVCpu->iem.s.cLogRelRdMsr < 32)
6368 {
6369 pVCpu->iem.s.cLogRelRdMsr++;
6370 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
6371 }
6372 else
6373 Log(( "IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
6374 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6375 return iemRaiseGeneralProtectionFault0(pVCpu);
6376}
6377
6378
6379/**
6380 * Implements WRMSR.
6381 */
6382IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
6383{
6384 /*
6385 * Check preconditions.
6386 */
6387 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6388 return iemRaiseUndefinedOpcode(pVCpu);
6389 if (pVCpu->iem.s.uCpl != 0)
6390 return iemRaiseGeneralProtectionFault0(pVCpu);
6391
6392 /*
6393 * Check nested-guest intercepts.
6394 */
6395#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6396 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6397 && iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_WRMSR, pVCpu->cpum.GstCtx.ecx))
6398 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WRMSR, cbInstr);
6399#endif
6400
6401#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6402 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6403 {
6404 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, true /* fWrite */);
6405 if (rcStrict == VINF_SVM_VMEXIT)
6406 return VINF_SUCCESS;
6407 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6408 {
6409 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
6410 return rcStrict;
6411 }
6412 }
6413#endif
6414
6415 /*
6416 * Do the job.
6417 */
6418 RTUINT64U uValue;
6419 uValue.s.Lo = pVCpu->cpum.GstCtx.eax;
6420 uValue.s.Hi = pVCpu->cpum.GstCtx.edx;
6421
6422 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
6423 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
6424
6425 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, uValue.u);
6426 if (rcStrict == VINF_SUCCESS)
6427 {
6428 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6429 return VINF_SUCCESS;
6430 }
6431
6432#ifndef IN_RING3
6433 /* Deferred to ring-3. */
6434 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
6435 {
6436 Log(("IEM: wrmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
6437 return rcStrict;
6438 }
6439#endif
6440
6441 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6442 if (pVCpu->iem.s.cLogRelWrMsr < 32)
6443 {
6444 pVCpu->iem.s.cLogRelWrMsr++;
6445 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx, uValue.s.Hi, uValue.s.Lo));
6446 }
6447 else
6448 Log(( "IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx, uValue.s.Hi, uValue.s.Lo));
6449 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6450 return iemRaiseGeneralProtectionFault0(pVCpu);
6451}
6452
6453
6454/**
6455 * Implements 'IN eAX, port'.
6456 *
6457 * @param u16Port The source port.
6458 * @param cbReg The register size.
6459 */
6460IEM_CIMPL_DEF_2(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg)
6461{
6462 /*
6463 * CPL check
6464 */
6465 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
6466 if (rcStrict != VINF_SUCCESS)
6467 return rcStrict;
6468
6469 /*
6470 * Check SVM nested-guest IO intercept.
6471 */
6472#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6473 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6474 {
6475 uint8_t cAddrSizeBits;
6476 switch (pVCpu->iem.s.enmEffAddrMode)
6477 {
6478 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6479 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6480 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6481 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6482 }
6483 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6484 false /* fRep */, false /* fStrIo */, cbInstr);
6485 if (rcStrict == VINF_SVM_VMEXIT)
6486 return VINF_SUCCESS;
6487 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6488 {
6489 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6490 VBOXSTRICTRC_VAL(rcStrict)));
6491 return rcStrict;
6492 }
6493 }
6494#endif
6495
6496 /*
6497 * Perform the I/O.
6498 */
6499 uint32_t u32Value = 0;
6500 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
6501 if (IOM_SUCCESS(rcStrict))
6502 {
6503 switch (cbReg)
6504 {
6505 case 1: pVCpu->cpum.GstCtx.al = (uint8_t)u32Value; break;
6506 case 2: pVCpu->cpum.GstCtx.ax = (uint16_t)u32Value; break;
6507 case 4: pVCpu->cpum.GstCtx.rax = u32Value; break;
6508 default: AssertFailedReturn(VERR_IEM_IPE_3);
6509 }
6510 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6511 pVCpu->iem.s.cPotentialExits++;
6512 if (rcStrict != VINF_SUCCESS)
6513 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6514 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6515
6516 /*
6517 * Check for I/O breakpoints.
6518 */
6519 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
6520 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6521 && X86_DR7_ANY_RW_IO(uDr7)
6522 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
6523 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6524 {
6525 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
6526 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
6527 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6528 rcStrict = iemRaiseDebugException(pVCpu);
6529 }
6530 }
6531
6532 return rcStrict;
6533}
6534
6535
6536/**
6537 * Implements 'IN eAX, DX'.
6538 *
6539 * @param cbReg The register size.
6540 */
6541IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
6542{
6543 return IEM_CIMPL_CALL_2(iemCImpl_in, pVCpu->cpum.GstCtx.dx, cbReg);
6544}
6545
6546
6547/**
6548 * Implements 'OUT port, eAX'.
6549 *
6550 * @param u16Port The destination port.
6551 * @param cbReg The register size.
6552 */
6553IEM_CIMPL_DEF_2(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg)
6554{
6555 /*
6556 * CPL check
6557 */
6558 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
6559 if (rcStrict != VINF_SUCCESS)
6560 return rcStrict;
6561
6562 /*
6563 * Check SVM nested-guest IO intercept.
6564 */
6565#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6566 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6567 {
6568 uint8_t cAddrSizeBits;
6569 switch (pVCpu->iem.s.enmEffAddrMode)
6570 {
6571 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6572 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6573 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6574 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6575 }
6576 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6577 false /* fRep */, false /* fStrIo */, cbInstr);
6578 if (rcStrict == VINF_SVM_VMEXIT)
6579 return VINF_SUCCESS;
6580 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6581 {
6582 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6583 VBOXSTRICTRC_VAL(rcStrict)));
6584 return rcStrict;
6585 }
6586 }
6587#endif
6588
6589 /*
6590 * Perform the I/O.
6591 */
6592 uint32_t u32Value;
6593 switch (cbReg)
6594 {
6595 case 1: u32Value = pVCpu->cpum.GstCtx.al; break;
6596 case 2: u32Value = pVCpu->cpum.GstCtx.ax; break;
6597 case 4: u32Value = pVCpu->cpum.GstCtx.eax; break;
6598 default: AssertFailedReturn(VERR_IEM_IPE_4);
6599 }
6600 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
6601 if (IOM_SUCCESS(rcStrict))
6602 {
6603 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6604 pVCpu->iem.s.cPotentialExits++;
6605 if (rcStrict != VINF_SUCCESS)
6606 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6607 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6608
6609 /*
6610 * Check for I/O breakpoints.
6611 */
6612 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
6613 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6614 && X86_DR7_ANY_RW_IO(uDr7)
6615 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
6616 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6617 {
6618 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
6619 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
6620 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6621 rcStrict = iemRaiseDebugException(pVCpu);
6622 }
6623 }
6624 return rcStrict;
6625}
6626
6627
6628/**
6629 * Implements 'OUT DX, eAX'.
6630 *
6631 * @param cbReg The register size.
6632 */
6633IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
6634{
6635 return IEM_CIMPL_CALL_2(iemCImpl_out, pVCpu->cpum.GstCtx.dx, cbReg);
6636}
6637
6638
6639/**
6640 * Implements 'CLI'.
6641 */
6642IEM_CIMPL_DEF_0(iemCImpl_cli)
6643{
6644 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
6645 uint32_t const fEflOld = fEfl;
6646
6647 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
6648 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
6649 {
6650 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6651 if (!(fEfl & X86_EFL_VM))
6652 {
6653 if (pVCpu->iem.s.uCpl <= uIopl)
6654 fEfl &= ~X86_EFL_IF;
6655 else if ( pVCpu->iem.s.uCpl == 3
6656 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI) )
6657 fEfl &= ~X86_EFL_VIF;
6658 else
6659 return iemRaiseGeneralProtectionFault0(pVCpu);
6660 }
6661 /* V8086 */
6662 else if (uIopl == 3)
6663 fEfl &= ~X86_EFL_IF;
6664 else if ( uIopl < 3
6665 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
6666 fEfl &= ~X86_EFL_VIF;
6667 else
6668 return iemRaiseGeneralProtectionFault0(pVCpu);
6669 }
6670 /* real mode */
6671 else
6672 fEfl &= ~X86_EFL_IF;
6673
6674 /* Commit. */
6675 IEMMISC_SET_EFL(pVCpu, fEfl);
6676 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6677 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
6678 return VINF_SUCCESS;
6679}
6680
6681
6682/**
6683 * Implements 'STI'.
6684 */
6685IEM_CIMPL_DEF_0(iemCImpl_sti)
6686{
6687 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
6688 uint32_t const fEflOld = fEfl;
6689
6690 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
6691 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
6692 {
6693 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6694 if (!(fEfl & X86_EFL_VM))
6695 {
6696 if (pVCpu->iem.s.uCpl <= uIopl)
6697 fEfl |= X86_EFL_IF;
6698 else if ( pVCpu->iem.s.uCpl == 3
6699 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI)
6700 && !(fEfl & X86_EFL_VIP) )
6701 fEfl |= X86_EFL_VIF;
6702 else
6703 return iemRaiseGeneralProtectionFault0(pVCpu);
6704 }
6705 /* V8086 */
6706 else if (uIopl == 3)
6707 fEfl |= X86_EFL_IF;
6708 else if ( uIopl < 3
6709 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME)
6710 && !(fEfl & X86_EFL_VIP) )
6711 fEfl |= X86_EFL_VIF;
6712 else
6713 return iemRaiseGeneralProtectionFault0(pVCpu);
6714 }
6715 /* real mode */
6716 else
6717 fEfl |= X86_EFL_IF;
6718
6719 /* Commit. */
6720 IEMMISC_SET_EFL(pVCpu, fEfl);
6721 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6722 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF))
6723 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
6724 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
6725 return VINF_SUCCESS;
6726}
6727
6728
6729/**
6730 * Implements 'HLT'.
6731 */
6732IEM_CIMPL_DEF_0(iemCImpl_hlt)
6733{
6734 if (pVCpu->iem.s.uCpl != 0)
6735 return iemRaiseGeneralProtectionFault0(pVCpu);
6736
6737 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_HLT_EXIT))
6738 {
6739 Log2(("hlt: Guest intercept -> VM-exit\n"));
6740 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_HLT, cbInstr);
6741 }
6742
6743 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
6744 {
6745 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
6746 IEM_SVM_UPDATE_NRIP(pVCpu);
6747 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6748 }
6749
6750 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6751 return VINF_EM_HALT;
6752}
6753
6754
6755/**
6756 * Implements 'MONITOR'.
6757 */
6758IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
6759{
6760 /*
6761 * Permission checks.
6762 */
6763 if (pVCpu->iem.s.uCpl != 0)
6764 {
6765 Log2(("monitor: CPL != 0\n"));
6766 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
6767 }
6768 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
6769 {
6770 Log2(("monitor: Not in CPUID\n"));
6771 return iemRaiseUndefinedOpcode(pVCpu);
6772 }
6773
6774 /*
6775 * Check VMX guest-intercept.
6776 * This should be considered a fault-like VM-exit.
6777 * See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
6778 */
6779 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MONITOR_EXIT))
6780 {
6781 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
6782 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_MONITOR, cbInstr);
6783 }
6784
6785 /*
6786 * Gather the operands and validate them.
6787 */
6788 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
6789 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
6790 uint32_t uEdx = pVCpu->cpum.GstCtx.edx;
6791/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
6792 * \#GP first. */
6793 if (uEcx != 0)
6794 {
6795 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
6796 return iemRaiseGeneralProtectionFault0(pVCpu);
6797 }
6798
6799 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
6800 if (rcStrict != VINF_SUCCESS)
6801 return rcStrict;
6802
6803 RTGCPHYS GCPhysMem;
6804 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
6805 if (rcStrict != VINF_SUCCESS)
6806 return rcStrict;
6807
6808 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
6809 {
6810 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
6811 IEM_SVM_UPDATE_NRIP(pVCpu);
6812 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6813 }
6814
6815 /*
6816 * Call EM to prepare the monitor/wait.
6817 */
6818 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem);
6819 Assert(rcStrict == VINF_SUCCESS);
6820
6821 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6822 return rcStrict;
6823}
6824
6825
6826/**
6827 * Implements 'MWAIT'.
6828 */
6829IEM_CIMPL_DEF_0(iemCImpl_mwait)
6830{
6831 /*
6832 * Permission checks.
6833 */
6834 if (pVCpu->iem.s.uCpl != 0)
6835 {
6836 Log2(("mwait: CPL != 0\n"));
6837 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
6838 * EFLAGS.VM then.) */
6839 return iemRaiseUndefinedOpcode(pVCpu);
6840 }
6841 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
6842 {
6843 Log2(("mwait: Not in CPUID\n"));
6844 return iemRaiseUndefinedOpcode(pVCpu);
6845 }
6846
6847 /*
6848 * Gather the operands and validate them.
6849 */
6850 uint32_t uEax = pVCpu->cpum.GstCtx.eax;
6851 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
6852 if (uEcx != 0)
6853 {
6854 /* Only supported extension is break on IRQ when IF=0. */
6855 if (uEcx > 1)
6856 {
6857 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
6858 return iemRaiseGeneralProtectionFault0(pVCpu);
6859 }
6860 uint32_t fMWaitFeatures = 0;
6861 uint32_t uIgnore = 0;
6862 CPUMGetGuestCpuId(pVCpu, 5, 0, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
6863 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
6864 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
6865 {
6866 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
6867 return iemRaiseGeneralProtectionFault0(pVCpu);
6868 }
6869 }
6870
6871 /*
6872 * Check SVM nested-guest mwait intercepts.
6873 */
6874 if ( IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
6875 && EMMonitorIsArmed(pVCpu))
6876 {
6877 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
6878 IEM_SVM_UPDATE_NRIP(pVCpu);
6879 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6880 }
6881 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
6882 {
6883 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
6884 IEM_SVM_UPDATE_NRIP(pVCpu);
6885 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6886 }
6887
6888 /*
6889 * Call EM to prepare the monitor/wait.
6890 */
6891 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
6892
6893 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6894 return rcStrict;
6895}
6896
6897
6898/**
6899 * Implements 'SWAPGS'.
6900 */
6901IEM_CIMPL_DEF_0(iemCImpl_swapgs)
6902{
6903 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
6904
6905 /*
6906 * Permission checks.
6907 */
6908 if (pVCpu->iem.s.uCpl != 0)
6909 {
6910 Log2(("swapgs: CPL != 0\n"));
6911 return iemRaiseUndefinedOpcode(pVCpu);
6912 }
6913
6914 /*
6915 * Do the job.
6916 */
6917 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_GS);
6918 uint64_t uOtherGsBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
6919 pVCpu->cpum.GstCtx.msrKERNELGSBASE = pVCpu->cpum.GstCtx.gs.u64Base;
6920 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase;
6921
6922 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6923 return VINF_SUCCESS;
6924}
6925
6926
6927/**
6928 * Implements 'CPUID'.
6929 */
6930IEM_CIMPL_DEF_0(iemCImpl_cpuid)
6931{
6932 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6933 {
6934 Log2(("cpuid: Guest intercept -> VM-exit\n"));
6935 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_CPUID, cbInstr);
6936 }
6937
6938 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
6939 {
6940 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
6941 IEM_SVM_UPDATE_NRIP(pVCpu);
6942 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6943 }
6944
6945 CPUMGetGuestCpuId(pVCpu, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx,
6946 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx, &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
6947 pVCpu->cpum.GstCtx.rax &= UINT32_C(0xffffffff);
6948 pVCpu->cpum.GstCtx.rbx &= UINT32_C(0xffffffff);
6949 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
6950 pVCpu->cpum.GstCtx.rdx &= UINT32_C(0xffffffff);
6951 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
6952
6953 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6954 pVCpu->iem.s.cPotentialExits++;
6955 return VINF_SUCCESS;
6956}
6957
6958
6959/**
6960 * Implements 'AAD'.
6961 *
6962 * @param bImm The immediate operand.
6963 */
6964IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
6965{
6966 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
6967 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
6968 pVCpu->cpum.GstCtx.ax = al;
6969 iemHlpUpdateArithEFlagsU8(pVCpu, al,
6970 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
6971 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
6972
6973 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6974 return VINF_SUCCESS;
6975}
6976
6977
6978/**
6979 * Implements 'AAM'.
6980 *
6981 * @param bImm The immediate operand. Cannot be 0.
6982 */
6983IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
6984{
6985 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
6986
6987 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
6988 uint8_t const al = (uint8_t)ax % bImm;
6989 uint8_t const ah = (uint8_t)ax / bImm;
6990 pVCpu->cpum.GstCtx.ax = (ah << 8) + al;
6991 iemHlpUpdateArithEFlagsU8(pVCpu, al,
6992 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
6993 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
6994
6995 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6996 return VINF_SUCCESS;
6997}
6998
6999
7000/**
7001 * Implements 'DAA'.
7002 */
7003IEM_CIMPL_DEF_0(iemCImpl_daa)
7004{
7005 uint8_t const al = pVCpu->cpum.GstCtx.al;
7006 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7007
7008 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7009 || (al & 0xf) >= 10)
7010 {
7011 pVCpu->cpum.GstCtx.al = al + 6;
7012 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7013 }
7014 else
7015 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7016
7017 if (al >= 0x9a || fCarry)
7018 {
7019 pVCpu->cpum.GstCtx.al += 0x60;
7020 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7021 }
7022 else
7023 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7024
7025 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7026 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7027 return VINF_SUCCESS;
7028}
7029
7030
7031/**
7032 * Implements 'DAS'.
7033 */
7034IEM_CIMPL_DEF_0(iemCImpl_das)
7035{
7036 uint8_t const uInputAL = pVCpu->cpum.GstCtx.al;
7037 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7038
7039 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7040 || (uInputAL & 0xf) >= 10)
7041 {
7042 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7043 if (uInputAL < 6)
7044 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7045 pVCpu->cpum.GstCtx.al = uInputAL - 6;
7046 }
7047 else
7048 {
7049 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7050 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7051 }
7052
7053 if (uInputAL >= 0x9a || fCarry)
7054 {
7055 pVCpu->cpum.GstCtx.al -= 0x60;
7056 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7057 }
7058
7059 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7060 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7061 return VINF_SUCCESS;
7062}
7063
7064
7065/**
7066 * Implements 'AAA'.
7067 */
7068IEM_CIMPL_DEF_0(iemCImpl_aaa)
7069{
7070 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
7071 {
7072 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7073 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7074 {
7075 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
7076 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7077 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7078 }
7079 else
7080 {
7081 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7082 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7083 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7084 }
7085 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7086 }
7087 else
7088 {
7089 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7090 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7091 {
7092 pVCpu->cpum.GstCtx.ax += UINT16_C(0x106);
7093 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7094 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7095 }
7096 else
7097 {
7098 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7099 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7100 }
7101 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7102 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7103 }
7104
7105 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7106 return VINF_SUCCESS;
7107}
7108
7109
7110/**
7111 * Implements 'AAS'.
7112 */
7113IEM_CIMPL_DEF_0(iemCImpl_aas)
7114{
7115 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
7116 {
7117 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7118 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7119 {
7120 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
7121 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7122 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7123 }
7124 else
7125 {
7126 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7127 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7128 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7129 }
7130 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7131 }
7132 else
7133 {
7134 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7135 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7136 {
7137 pVCpu->cpum.GstCtx.ax -= UINT16_C(0x106);
7138 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7139 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7140 }
7141 else
7142 {
7143 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7144 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7145 }
7146 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7147 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7148 }
7149
7150 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7151 return VINF_SUCCESS;
7152}
7153
7154
7155/**
7156 * Implements the 16-bit version of 'BOUND'.
7157 *
7158 * @note We have separate 16-bit and 32-bit variants of this function due to
7159 * the decoder using unsigned parameters, whereas we want signed one to
7160 * do the job. This is significant for a recompiler.
7161 */
7162IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
7163{
7164 /*
7165 * Check if the index is inside the bounds, otherwise raise #BR.
7166 */
7167 if ( idxArray >= idxLowerBound
7168 && idxArray <= idxUpperBound)
7169 {
7170 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7171 return VINF_SUCCESS;
7172 }
7173
7174 return iemRaiseBoundRangeExceeded(pVCpu);
7175}
7176
7177
7178/**
7179 * Implements the 32-bit version of 'BOUND'.
7180 */
7181IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
7182{
7183 /*
7184 * Check if the index is inside the bounds, otherwise raise #BR.
7185 */
7186 if ( idxArray >= idxLowerBound
7187 && idxArray <= idxUpperBound)
7188 {
7189 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7190 return VINF_SUCCESS;
7191 }
7192
7193 return iemRaiseBoundRangeExceeded(pVCpu);
7194}
7195
7196
7197
7198/*
7199 * Instantiate the various string operation combinations.
7200 */
7201#define OP_SIZE 8
7202#define ADDR_SIZE 16
7203#include "IEMAllCImplStrInstr.cpp.h"
7204#define OP_SIZE 8
7205#define ADDR_SIZE 32
7206#include "IEMAllCImplStrInstr.cpp.h"
7207#define OP_SIZE 8
7208#define ADDR_SIZE 64
7209#include "IEMAllCImplStrInstr.cpp.h"
7210
7211#define OP_SIZE 16
7212#define ADDR_SIZE 16
7213#include "IEMAllCImplStrInstr.cpp.h"
7214#define OP_SIZE 16
7215#define ADDR_SIZE 32
7216#include "IEMAllCImplStrInstr.cpp.h"
7217#define OP_SIZE 16
7218#define ADDR_SIZE 64
7219#include "IEMAllCImplStrInstr.cpp.h"
7220
7221#define OP_SIZE 32
7222#define ADDR_SIZE 16
7223#include "IEMAllCImplStrInstr.cpp.h"
7224#define OP_SIZE 32
7225#define ADDR_SIZE 32
7226#include "IEMAllCImplStrInstr.cpp.h"
7227#define OP_SIZE 32
7228#define ADDR_SIZE 64
7229#include "IEMAllCImplStrInstr.cpp.h"
7230
7231#define OP_SIZE 64
7232#define ADDR_SIZE 32
7233#include "IEMAllCImplStrInstr.cpp.h"
7234#define OP_SIZE 64
7235#define ADDR_SIZE 64
7236#include "IEMAllCImplStrInstr.cpp.h"
7237
7238
7239/**
7240 * Implements 'XGETBV'.
7241 */
7242IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
7243{
7244 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
7245 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
7246 {
7247 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7248 switch (uEcx)
7249 {
7250 case 0:
7251 break;
7252
7253 case 1: /** @todo Implement XCR1 support. */
7254 default:
7255 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
7256 return iemRaiseGeneralProtectionFault0(pVCpu);
7257
7258 }
7259 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
7260 pVCpu->cpum.GstCtx.rax = RT_LO_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
7261 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
7262
7263 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7264 return VINF_SUCCESS;
7265 }
7266 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
7267 return iemRaiseUndefinedOpcode(pVCpu);
7268}
7269
7270
7271/**
7272 * Implements 'XSETBV'.
7273 */
7274IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
7275{
7276 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
7277 {
7278 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
7279 {
7280 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
7281 IEM_SVM_UPDATE_NRIP(pVCpu);
7282 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7283 }
7284
7285 if (pVCpu->iem.s.uCpl == 0)
7286 {
7287 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
7288
7289 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7290 uint64_t uNewValue = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx);
7291 switch (uEcx)
7292 {
7293 case 0:
7294 {
7295 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
7296 if (rc == VINF_SUCCESS)
7297 break;
7298 Assert(rc == VERR_CPUM_RAISE_GP_0);
7299 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7300 return iemRaiseGeneralProtectionFault0(pVCpu);
7301 }
7302
7303 case 1: /** @todo Implement XCR1 support. */
7304 default:
7305 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7306 return iemRaiseGeneralProtectionFault0(pVCpu);
7307
7308 }
7309
7310 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7311 return VINF_SUCCESS;
7312 }
7313
7314 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
7315 return iemRaiseGeneralProtectionFault0(pVCpu);
7316 }
7317 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
7318 return iemRaiseUndefinedOpcode(pVCpu);
7319}
7320
7321#ifdef IN_RING3
7322
7323/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
7324struct IEMCIMPLCX16ARGS
7325{
7326 PRTUINT128U pu128Dst;
7327 PRTUINT128U pu128RaxRdx;
7328 PRTUINT128U pu128RbxRcx;
7329 uint32_t *pEFlags;
7330# ifdef VBOX_STRICT
7331 uint32_t cCalls;
7332# endif
7333};
7334
7335/**
7336 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
7337 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
7338 */
7339static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPU pVCpu, void *pvUser)
7340{
7341 RT_NOREF(pVM, pVCpu);
7342 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
7343# ifdef VBOX_STRICT
7344 Assert(pArgs->cCalls == 0);
7345 pArgs->cCalls++;
7346# endif
7347
7348 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
7349 return VINF_SUCCESS;
7350}
7351
7352#endif /* IN_RING3 */
7353
7354/**
7355 * Implements 'CMPXCHG16B' fallback using rendezvous.
7356 */
7357IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
7358 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
7359{
7360#ifdef IN_RING3
7361 struct IEMCIMPLCX16ARGS Args;
7362 Args.pu128Dst = pu128Dst;
7363 Args.pu128RaxRdx = pu128RaxRdx;
7364 Args.pu128RbxRcx = pu128RbxRcx;
7365 Args.pEFlags = pEFlags;
7366# ifdef VBOX_STRICT
7367 Args.cCalls = 0;
7368# endif
7369 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
7370 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
7371 Assert(Args.cCalls == 1);
7372 if (rcStrict == VINF_SUCCESS)
7373 {
7374 /* Duplicated tail code. */
7375 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
7376 if (rcStrict == VINF_SUCCESS)
7377 {
7378 pVCpu->cpum.GstCtx.eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
7379 if (!(*pEFlags & X86_EFL_ZF))
7380 {
7381 pVCpu->cpum.GstCtx.rax = pu128RaxRdx->s.Lo;
7382 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi;
7383 }
7384 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7385 }
7386 }
7387 return rcStrict;
7388#else
7389 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7390 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
7391#endif
7392}
7393
7394
7395/**
7396 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
7397 *
7398 * This is implemented in C because it triggers a load like behviour without
7399 * actually reading anything. Since that's not so common, it's implemented
7400 * here.
7401 *
7402 * @param iEffSeg The effective segment.
7403 * @param GCPtrEff The address of the image.
7404 */
7405IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7406{
7407 /*
7408 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
7409 */
7410 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
7411 if (rcStrict == VINF_SUCCESS)
7412 {
7413 RTGCPHYS GCPhysMem;
7414 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7415 if (rcStrict == VINF_SUCCESS)
7416 {
7417 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7418 return VINF_SUCCESS;
7419 }
7420 }
7421
7422 return rcStrict;
7423}
7424
7425
7426/**
7427 * Implements 'FINIT' and 'FNINIT'.
7428 *
7429 * @param fCheckXcpts Whether to check for umasked pending exceptions or
7430 * not.
7431 */
7432IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
7433{
7434 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
7435 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
7436 return iemRaiseDeviceNotAvailable(pVCpu);
7437
7438 iemFpuActualizeStateForChange(pVCpu);
7439 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87);
7440
7441 NOREF(fCheckXcpts); /** @todo trigger pending exceptions:
7442 if (fCheckXcpts && TODO )
7443 return iemRaiseMathFault(pVCpu);
7444 */
7445
7446 PX86XSAVEAREA pXState = pVCpu->cpum.GstCtx.CTX_SUFF(pXState);
7447 pXState->x87.FCW = 0x37f;
7448 pXState->x87.FSW = 0;
7449 pXState->x87.FTW = 0x00; /* 0 - empty. */
7450 pXState->x87.FPUDP = 0;
7451 pXState->x87.DS = 0; //??
7452 pXState->x87.Rsrvd2= 0;
7453 pXState->x87.FPUIP = 0;
7454 pXState->x87.CS = 0; //??
7455 pXState->x87.Rsrvd1= 0;
7456 pXState->x87.FOP = 0;
7457
7458 iemHlpUsedFpu(pVCpu);
7459 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7460 return VINF_SUCCESS;
7461}
7462
7463
7464/**
7465 * Implements 'FXSAVE'.
7466 *
7467 * @param iEffSeg The effective segment.
7468 * @param GCPtrEff The address of the image.
7469 * @param enmEffOpSize The operand size (only REX.W really matters).
7470 */
7471IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7472{
7473 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
7474
7475 /*
7476 * Raise exceptions.
7477 */
7478 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
7479 return iemRaiseUndefinedOpcode(pVCpu);
7480 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
7481 return iemRaiseDeviceNotAvailable(pVCpu);
7482 if (GCPtrEff & 15)
7483 {
7484 /** @todo CPU/VM detection possible! \#AC might not be signal for
7485 * all/any misalignment sizes, intel says its an implementation detail. */
7486 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7487 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7488 && pVCpu->iem.s.uCpl == 3)
7489 return iemRaiseAlignmentCheckException(pVCpu);
7490 return iemRaiseGeneralProtectionFault0(pVCpu);
7491 }
7492
7493 /*
7494 * Access the memory.
7495 */
7496 void *pvMem512;
7497 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7498 if (rcStrict != VINF_SUCCESS)
7499 return rcStrict;
7500 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7501 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7502
7503 /*
7504 * Store the registers.
7505 */
7506 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7507 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
7508
7509 /* common for all formats */
7510 pDst->FCW = pSrc->FCW;
7511 pDst->FSW = pSrc->FSW;
7512 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7513 pDst->FOP = pSrc->FOP;
7514 pDst->MXCSR = pSrc->MXCSR;
7515 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7516 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7517 {
7518 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
7519 * them for now... */
7520 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7521 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7522 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7523 pDst->aRegs[i].au32[3] = 0;
7524 }
7525
7526 /* FPU IP, CS, DP and DS. */
7527 pDst->FPUIP = pSrc->FPUIP;
7528 pDst->CS = pSrc->CS;
7529 pDst->FPUDP = pSrc->FPUDP;
7530 pDst->DS = pSrc->DS;
7531 if (enmEffOpSize == IEMMODE_64BIT)
7532 {
7533 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7534 pDst->Rsrvd1 = pSrc->Rsrvd1;
7535 pDst->Rsrvd2 = pSrc->Rsrvd2;
7536 pDst->au32RsrvdForSoftware[0] = 0;
7537 }
7538 else
7539 {
7540 pDst->Rsrvd1 = 0;
7541 pDst->Rsrvd2 = 0;
7542 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
7543 }
7544
7545 /* XMM registers. */
7546 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
7547 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7548 || pVCpu->iem.s.uCpl != 0)
7549 {
7550 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7551 for (uint32_t i = 0; i < cXmmRegs; i++)
7552 pDst->aXMM[i] = pSrc->aXMM[i];
7553 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7554 * right? */
7555 }
7556
7557 /*
7558 * Commit the memory.
7559 */
7560 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7561 if (rcStrict != VINF_SUCCESS)
7562 return rcStrict;
7563
7564 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7565 return VINF_SUCCESS;
7566}
7567
7568
7569/**
7570 * Implements 'FXRSTOR'.
7571 *
7572 * @param GCPtrEff The address of the image.
7573 * @param enmEffOpSize The operand size (only REX.W really matters).
7574 */
7575IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7576{
7577 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
7578
7579 /*
7580 * Raise exceptions.
7581 */
7582 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
7583 return iemRaiseUndefinedOpcode(pVCpu);
7584 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
7585 return iemRaiseDeviceNotAvailable(pVCpu);
7586 if (GCPtrEff & 15)
7587 {
7588 /** @todo CPU/VM detection possible! \#AC might not be signal for
7589 * all/any misalignment sizes, intel says its an implementation detail. */
7590 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7591 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7592 && pVCpu->iem.s.uCpl == 3)
7593 return iemRaiseAlignmentCheckException(pVCpu);
7594 return iemRaiseGeneralProtectionFault0(pVCpu);
7595 }
7596
7597 /*
7598 * Access the memory.
7599 */
7600 void *pvMem512;
7601 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
7602 if (rcStrict != VINF_SUCCESS)
7603 return rcStrict;
7604 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
7605 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7606
7607 /*
7608 * Check the state for stuff which will #GP(0).
7609 */
7610 uint32_t const fMXCSR = pSrc->MXCSR;
7611 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7612 if (fMXCSR & ~fMXCSR_MASK)
7613 {
7614 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
7615 return iemRaiseGeneralProtectionFault0(pVCpu);
7616 }
7617
7618 /*
7619 * Load the registers.
7620 */
7621 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7622 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
7623
7624 /* common for all formats */
7625 pDst->FCW = pSrc->FCW;
7626 pDst->FSW = pSrc->FSW;
7627 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7628 pDst->FOP = pSrc->FOP;
7629 pDst->MXCSR = fMXCSR;
7630 /* (MXCSR_MASK is read-only) */
7631 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
7632 {
7633 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7634 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7635 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7636 pDst->aRegs[i].au32[3] = 0;
7637 }
7638
7639 /* FPU IP, CS, DP and DS. */
7640 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7641 {
7642 pDst->FPUIP = pSrc->FPUIP;
7643 pDst->CS = pSrc->CS;
7644 pDst->Rsrvd1 = pSrc->Rsrvd1;
7645 pDst->FPUDP = pSrc->FPUDP;
7646 pDst->DS = pSrc->DS;
7647 pDst->Rsrvd2 = pSrc->Rsrvd2;
7648 }
7649 else
7650 {
7651 pDst->FPUIP = pSrc->FPUIP;
7652 pDst->CS = pSrc->CS;
7653 pDst->Rsrvd1 = 0;
7654 pDst->FPUDP = pSrc->FPUDP;
7655 pDst->DS = pSrc->DS;
7656 pDst->Rsrvd2 = 0;
7657 }
7658
7659 /* XMM registers. */
7660 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
7661 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7662 || pVCpu->iem.s.uCpl != 0)
7663 {
7664 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7665 for (uint32_t i = 0; i < cXmmRegs; i++)
7666 pDst->aXMM[i] = pSrc->aXMM[i];
7667 }
7668
7669 /*
7670 * Commit the memory.
7671 */
7672 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
7673 if (rcStrict != VINF_SUCCESS)
7674 return rcStrict;
7675
7676 iemHlpUsedFpu(pVCpu);
7677 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7678 return VINF_SUCCESS;
7679}
7680
7681
7682/**
7683 * Implements 'XSAVE'.
7684 *
7685 * @param iEffSeg The effective segment.
7686 * @param GCPtrEff The address of the image.
7687 * @param enmEffOpSize The operand size (only REX.W really matters).
7688 */
7689IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7690{
7691 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
7692
7693 /*
7694 * Raise exceptions.
7695 */
7696 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
7697 return iemRaiseUndefinedOpcode(pVCpu);
7698 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
7699 return iemRaiseDeviceNotAvailable(pVCpu);
7700 if (GCPtrEff & 63)
7701 {
7702 /** @todo CPU/VM detection possible! \#AC might not be signal for
7703 * all/any misalignment sizes, intel says its an implementation detail. */
7704 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7705 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7706 && pVCpu->iem.s.uCpl == 3)
7707 return iemRaiseAlignmentCheckException(pVCpu);
7708 return iemRaiseGeneralProtectionFault0(pVCpu);
7709 }
7710
7711 /*
7712 * Calc the requested mask
7713 */
7714 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
7715 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7716 uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
7717
7718/** @todo figure out the exact protocol for the memory access. Currently we
7719 * just need this crap to work halfways to make it possible to test
7720 * AVX instructions. */
7721/** @todo figure out the XINUSE and XMODIFIED */
7722
7723 /*
7724 * Access the x87 memory state.
7725 */
7726 /* The x87+SSE state. */
7727 void *pvMem512;
7728 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7729 if (rcStrict != VINF_SUCCESS)
7730 return rcStrict;
7731 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7732 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7733
7734 /* The header. */
7735 PX86XSAVEHDR pHdr;
7736 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW);
7737 if (rcStrict != VINF_SUCCESS)
7738 return rcStrict;
7739
7740 /*
7741 * Store the X87 state.
7742 */
7743 if (fReqComponents & XSAVE_C_X87)
7744 {
7745 /* common for all formats */
7746 pDst->FCW = pSrc->FCW;
7747 pDst->FSW = pSrc->FSW;
7748 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7749 pDst->FOP = pSrc->FOP;
7750 pDst->FPUIP = pSrc->FPUIP;
7751 pDst->CS = pSrc->CS;
7752 pDst->FPUDP = pSrc->FPUDP;
7753 pDst->DS = pSrc->DS;
7754 if (enmEffOpSize == IEMMODE_64BIT)
7755 {
7756 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7757 pDst->Rsrvd1 = pSrc->Rsrvd1;
7758 pDst->Rsrvd2 = pSrc->Rsrvd2;
7759 pDst->au32RsrvdForSoftware[0] = 0;
7760 }
7761 else
7762 {
7763 pDst->Rsrvd1 = 0;
7764 pDst->Rsrvd2 = 0;
7765 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
7766 }
7767 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7768 {
7769 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
7770 * them for now... */
7771 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7772 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7773 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7774 pDst->aRegs[i].au32[3] = 0;
7775 }
7776
7777 }
7778
7779 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
7780 {
7781 pDst->MXCSR = pSrc->MXCSR;
7782 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7783 }
7784
7785 if (fReqComponents & XSAVE_C_SSE)
7786 {
7787 /* XMM registers. */
7788 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7789 for (uint32_t i = 0; i < cXmmRegs; i++)
7790 pDst->aXMM[i] = pSrc->aXMM[i];
7791 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7792 * right? */
7793 }
7794
7795 /* Commit the x87 state bits. (probably wrong) */
7796 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7797 if (rcStrict != VINF_SUCCESS)
7798 return rcStrict;
7799
7800 /*
7801 * Store AVX state.
7802 */
7803 if (fReqComponents & XSAVE_C_YMM)
7804 {
7805 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
7806 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
7807 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
7808 PX86XSAVEYMMHI pCompDst;
7809 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
7810 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7811 if (rcStrict != VINF_SUCCESS)
7812 return rcStrict;
7813
7814 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7815 for (uint32_t i = 0; i < cXmmRegs; i++)
7816 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
7817
7818 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7819 if (rcStrict != VINF_SUCCESS)
7820 return rcStrict;
7821 }
7822
7823 /*
7824 * Update the header.
7825 */
7826 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
7827 | (fReqComponents & fXInUse);
7828
7829 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
7830 if (rcStrict != VINF_SUCCESS)
7831 return rcStrict;
7832
7833 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7834 return VINF_SUCCESS;
7835}
7836
7837
7838/**
7839 * Implements 'XRSTOR'.
7840 *
7841 * @param iEffSeg The effective segment.
7842 * @param GCPtrEff The address of the image.
7843 * @param enmEffOpSize The operand size (only REX.W really matters).
7844 */
7845IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7846{
7847 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
7848
7849 /*
7850 * Raise exceptions.
7851 */
7852 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
7853 return iemRaiseUndefinedOpcode(pVCpu);
7854 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
7855 return iemRaiseDeviceNotAvailable(pVCpu);
7856 if (GCPtrEff & 63)
7857 {
7858 /** @todo CPU/VM detection possible! \#AC might not be signal for
7859 * all/any misalignment sizes, intel says its an implementation detail. */
7860 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7861 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7862 && pVCpu->iem.s.uCpl == 3)
7863 return iemRaiseAlignmentCheckException(pVCpu);
7864 return iemRaiseGeneralProtectionFault0(pVCpu);
7865 }
7866
7867/** @todo figure out the exact protocol for the memory access. Currently we
7868 * just need this crap to work halfways to make it possible to test
7869 * AVX instructions. */
7870/** @todo figure out the XINUSE and XMODIFIED */
7871
7872 /*
7873 * Access the x87 memory state.
7874 */
7875 /* The x87+SSE state. */
7876 void *pvMem512;
7877 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
7878 if (rcStrict != VINF_SUCCESS)
7879 return rcStrict;
7880 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
7881 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7882
7883 /*
7884 * Calc the requested mask
7885 */
7886 PX86XSAVEHDR pHdrDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->Hdr;
7887 PCX86XSAVEHDR pHdrSrc;
7888 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_R);
7889 if (rcStrict != VINF_SUCCESS)
7890 return rcStrict;
7891
7892 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
7893 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7894 //uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
7895 uint64_t const fRstorMask = pHdrSrc->bmXState;
7896 uint64_t const fCompMask = pHdrSrc->bmXComp;
7897
7898 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7899
7900 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7901
7902 /* We won't need this any longer. */
7903 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
7904 if (rcStrict != VINF_SUCCESS)
7905 return rcStrict;
7906
7907 /*
7908 * Store the X87 state.
7909 */
7910 if (fReqComponents & XSAVE_C_X87)
7911 {
7912 if (fRstorMask & XSAVE_C_X87)
7913 {
7914 pDst->FCW = pSrc->FCW;
7915 pDst->FSW = pSrc->FSW;
7916 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7917 pDst->FOP = pSrc->FOP;
7918 pDst->FPUIP = pSrc->FPUIP;
7919 pDst->CS = pSrc->CS;
7920 pDst->FPUDP = pSrc->FPUDP;
7921 pDst->DS = pSrc->DS;
7922 if (enmEffOpSize == IEMMODE_64BIT)
7923 {
7924 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7925 pDst->Rsrvd1 = pSrc->Rsrvd1;
7926 pDst->Rsrvd2 = pSrc->Rsrvd2;
7927 }
7928 else
7929 {
7930 pDst->Rsrvd1 = 0;
7931 pDst->Rsrvd2 = 0;
7932 }
7933 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7934 {
7935 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7936 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7937 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7938 pDst->aRegs[i].au32[3] = 0;
7939 }
7940 }
7941 else
7942 {
7943 pDst->FCW = 0x37f;
7944 pDst->FSW = 0;
7945 pDst->FTW = 0x00; /* 0 - empty. */
7946 pDst->FPUDP = 0;
7947 pDst->DS = 0; //??
7948 pDst->Rsrvd2= 0;
7949 pDst->FPUIP = 0;
7950 pDst->CS = 0; //??
7951 pDst->Rsrvd1= 0;
7952 pDst->FOP = 0;
7953 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
7954 {
7955 pDst->aRegs[i].au32[0] = 0;
7956 pDst->aRegs[i].au32[1] = 0;
7957 pDst->aRegs[i].au32[2] = 0;
7958 pDst->aRegs[i].au32[3] = 0;
7959 }
7960 }
7961 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
7962 }
7963
7964 /* MXCSR */
7965 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
7966 {
7967 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
7968 pDst->MXCSR = pSrc->MXCSR;
7969 else
7970 pDst->MXCSR = 0x1f80;
7971 }
7972
7973 /* XMM registers. */
7974 if (fReqComponents & XSAVE_C_SSE)
7975 {
7976 if (fRstorMask & XSAVE_C_SSE)
7977 {
7978 for (uint32_t i = 0; i < cXmmRegs; i++)
7979 pDst->aXMM[i] = pSrc->aXMM[i];
7980 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7981 * right? */
7982 }
7983 else
7984 {
7985 for (uint32_t i = 0; i < cXmmRegs; i++)
7986 {
7987 pDst->aXMM[i].au64[0] = 0;
7988 pDst->aXMM[i].au64[1] = 0;
7989 }
7990 }
7991 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
7992 }
7993
7994 /* Unmap the x87 state bits (so we've don't run out of mapping). */
7995 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
7996 if (rcStrict != VINF_SUCCESS)
7997 return rcStrict;
7998
7999 /*
8000 * Restore AVX state.
8001 */
8002 if (fReqComponents & XSAVE_C_YMM)
8003 {
8004 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8005 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
8006
8007 if (fRstorMask & XSAVE_C_YMM)
8008 {
8009 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8010 PCX86XSAVEYMMHI pCompSrc;
8011 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
8012 iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT], IEM_ACCESS_DATA_R);
8013 if (rcStrict != VINF_SUCCESS)
8014 return rcStrict;
8015
8016 for (uint32_t i = 0; i < cXmmRegs; i++)
8017 {
8018 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
8019 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
8020 }
8021
8022 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
8023 if (rcStrict != VINF_SUCCESS)
8024 return rcStrict;
8025 }
8026 else
8027 {
8028 for (uint32_t i = 0; i < cXmmRegs; i++)
8029 {
8030 pCompDst->aYmmHi[i].au64[0] = 0;
8031 pCompDst->aYmmHi[i].au64[1] = 0;
8032 }
8033 }
8034 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
8035 }
8036
8037 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8038 return VINF_SUCCESS;
8039}
8040
8041
8042
8043
8044/**
8045 * Implements 'STMXCSR'.
8046 *
8047 * @param GCPtrEff The address of the image.
8048 */
8049IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8050{
8051 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8052
8053 /*
8054 * Raise exceptions.
8055 */
8056 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8057 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
8058 {
8059 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8060 {
8061 /*
8062 * Do the job.
8063 */
8064 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR);
8065 if (rcStrict == VINF_SUCCESS)
8066 {
8067 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8068 return VINF_SUCCESS;
8069 }
8070 return rcStrict;
8071 }
8072 return iemRaiseDeviceNotAvailable(pVCpu);
8073 }
8074 return iemRaiseUndefinedOpcode(pVCpu);
8075}
8076
8077
8078/**
8079 * Implements 'VSTMXCSR'.
8080 *
8081 * @param GCPtrEff The address of the image.
8082 */
8083IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8084{
8085 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_XCRx);
8086
8087 /*
8088 * Raise exceptions.
8089 */
8090 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
8091 ? (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
8092 : !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
8093 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8094 {
8095 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8096 {
8097 /*
8098 * Do the job.
8099 */
8100 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR);
8101 if (rcStrict == VINF_SUCCESS)
8102 {
8103 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8104 return VINF_SUCCESS;
8105 }
8106 return rcStrict;
8107 }
8108 return iemRaiseDeviceNotAvailable(pVCpu);
8109 }
8110 return iemRaiseUndefinedOpcode(pVCpu);
8111}
8112
8113
8114/**
8115 * Implements 'LDMXCSR'.
8116 *
8117 * @param GCPtrEff The address of the image.
8118 */
8119IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8120{
8121 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8122
8123 /*
8124 * Raise exceptions.
8125 */
8126 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
8127 * happen after or before \#UD and \#EM? */
8128 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8129 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
8130 {
8131 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8132 {
8133 /*
8134 * Do the job.
8135 */
8136 uint32_t fNewMxCsr;
8137 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
8138 if (rcStrict == VINF_SUCCESS)
8139 {
8140 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8141 if (!(fNewMxCsr & ~fMxCsrMask))
8142 {
8143 pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR = fNewMxCsr;
8144 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8145 return VINF_SUCCESS;
8146 }
8147 Log(("lddmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
8148 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
8149 return iemRaiseGeneralProtectionFault0(pVCpu);
8150 }
8151 return rcStrict;
8152 }
8153 return iemRaiseDeviceNotAvailable(pVCpu);
8154 }
8155 return iemRaiseUndefinedOpcode(pVCpu);
8156}
8157
8158
8159/**
8160 * Commmon routine for fnstenv and fnsave.
8161 *
8162 * @param pVCpu The cross context virtual CPU structure of the calling thread.
8163 * @param enmEffOpSize The effective operand size.
8164 * @param uPtr Where to store the state.
8165 */
8166static void iemCImplCommonFpuStoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr)
8167{
8168 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8169 PCX86FXSTATE pSrcX87 = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8170 if (enmEffOpSize == IEMMODE_16BIT)
8171 {
8172 uPtr.pu16[0] = pSrcX87->FCW;
8173 uPtr.pu16[1] = pSrcX87->FSW;
8174 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
8175 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8176 {
8177 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
8178 * protected mode or long mode and we save it in real mode? And vice
8179 * versa? And with 32-bit operand size? I think CPU is storing the
8180 * effective address ((CS << 4) + IP) in the offset register and not
8181 * doing any address calculations here. */
8182 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
8183 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
8184 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
8185 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
8186 }
8187 else
8188 {
8189 uPtr.pu16[3] = pSrcX87->FPUIP;
8190 uPtr.pu16[4] = pSrcX87->CS;
8191 uPtr.pu16[5] = pSrcX87->FPUDP;
8192 uPtr.pu16[6] = pSrcX87->DS;
8193 }
8194 }
8195 else
8196 {
8197 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
8198 uPtr.pu16[0*2] = pSrcX87->FCW;
8199 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
8200 uPtr.pu16[1*2] = pSrcX87->FSW;
8201 uPtr.pu16[1*2+1] = 0xffff;
8202 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
8203 uPtr.pu16[2*2+1] = 0xffff;
8204 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8205 {
8206 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
8207 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
8208 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
8209 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
8210 }
8211 else
8212 {
8213 uPtr.pu32[3] = pSrcX87->FPUIP;
8214 uPtr.pu16[4*2] = pSrcX87->CS;
8215 uPtr.pu16[4*2+1] = pSrcX87->FOP;
8216 uPtr.pu32[5] = pSrcX87->FPUDP;
8217 uPtr.pu16[6*2] = pSrcX87->DS;
8218 uPtr.pu16[6*2+1] = 0xffff;
8219 }
8220 }
8221}
8222
8223
8224/**
8225 * Commmon routine for fldenv and frstor
8226 *
8227 * @param pVCpu The cross context virtual CPU structure of the calling thread.
8228 * @param enmEffOpSize The effective operand size.
8229 * @param uPtr Where to store the state.
8230 */
8231static void iemCImplCommonFpuRestoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr)
8232{
8233 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8234 PX86FXSTATE pDstX87 = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8235 if (enmEffOpSize == IEMMODE_16BIT)
8236 {
8237 pDstX87->FCW = uPtr.pu16[0];
8238 pDstX87->FSW = uPtr.pu16[1];
8239 pDstX87->FTW = uPtr.pu16[2];
8240 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8241 {
8242 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
8243 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
8244 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
8245 pDstX87->CS = 0;
8246 pDstX87->Rsrvd1= 0;
8247 pDstX87->DS = 0;
8248 pDstX87->Rsrvd2= 0;
8249 }
8250 else
8251 {
8252 pDstX87->FPUIP = uPtr.pu16[3];
8253 pDstX87->CS = uPtr.pu16[4];
8254 pDstX87->Rsrvd1= 0;
8255 pDstX87->FPUDP = uPtr.pu16[5];
8256 pDstX87->DS = uPtr.pu16[6];
8257 pDstX87->Rsrvd2= 0;
8258 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
8259 }
8260 }
8261 else
8262 {
8263 pDstX87->FCW = uPtr.pu16[0*2];
8264 pDstX87->FSW = uPtr.pu16[1*2];
8265 pDstX87->FTW = uPtr.pu16[2*2];
8266 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8267 {
8268 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
8269 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
8270 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
8271 pDstX87->CS = 0;
8272 pDstX87->Rsrvd1= 0;
8273 pDstX87->DS = 0;
8274 pDstX87->Rsrvd2= 0;
8275 }
8276 else
8277 {
8278 pDstX87->FPUIP = uPtr.pu32[3];
8279 pDstX87->CS = uPtr.pu16[4*2];
8280 pDstX87->Rsrvd1= 0;
8281 pDstX87->FOP = uPtr.pu16[4*2+1];
8282 pDstX87->FPUDP = uPtr.pu32[5];
8283 pDstX87->DS = uPtr.pu16[6*2];
8284 pDstX87->Rsrvd2= 0;
8285 }
8286 }
8287
8288 /* Make adjustments. */
8289 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
8290 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
8291 iemFpuRecalcExceptionStatus(pDstX87);
8292 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
8293 * exceptions are pending after loading the saved state? */
8294}
8295
8296
8297/**
8298 * Implements 'FNSTENV'.
8299 *
8300 * @param enmEffOpSize The operand size (only REX.W really matters).
8301 * @param iEffSeg The effective segment register for @a GCPtrEff.
8302 * @param GCPtrEffDst The address of the image.
8303 */
8304IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8305{
8306 RTPTRUNION uPtr;
8307 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8308 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8309 if (rcStrict != VINF_SUCCESS)
8310 return rcStrict;
8311
8312 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
8313
8314 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8315 if (rcStrict != VINF_SUCCESS)
8316 return rcStrict;
8317
8318 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8319 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8320 return VINF_SUCCESS;
8321}
8322
8323
8324/**
8325 * Implements 'FNSAVE'.
8326 *
8327 * @param GCPtrEffDst The address of the image.
8328 * @param enmEffOpSize The operand size.
8329 */
8330IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8331{
8332 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8333
8334 RTPTRUNION uPtr;
8335 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8336 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8337 if (rcStrict != VINF_SUCCESS)
8338 return rcStrict;
8339
8340 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8341 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
8342 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8343 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8344 {
8345 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
8346 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
8347 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
8348 }
8349
8350 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8351 if (rcStrict != VINF_SUCCESS)
8352 return rcStrict;
8353
8354 /*
8355 * Re-initialize the FPU context.
8356 */
8357 pFpuCtx->FCW = 0x37f;
8358 pFpuCtx->FSW = 0;
8359 pFpuCtx->FTW = 0x00; /* 0 - empty */
8360 pFpuCtx->FPUDP = 0;
8361 pFpuCtx->DS = 0;
8362 pFpuCtx->Rsrvd2= 0;
8363 pFpuCtx->FPUIP = 0;
8364 pFpuCtx->CS = 0;
8365 pFpuCtx->Rsrvd1= 0;
8366 pFpuCtx->FOP = 0;
8367
8368 iemHlpUsedFpu(pVCpu);
8369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8370 return VINF_SUCCESS;
8371}
8372
8373
8374
8375/**
8376 * Implements 'FLDENV'.
8377 *
8378 * @param enmEffOpSize The operand size (only REX.W really matters).
8379 * @param iEffSeg The effective segment register for @a GCPtrEff.
8380 * @param GCPtrEffSrc The address of the image.
8381 */
8382IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8383{
8384 RTCPTRUNION uPtr;
8385 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8386 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8387 if (rcStrict != VINF_SUCCESS)
8388 return rcStrict;
8389
8390 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
8391
8392 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8393 if (rcStrict != VINF_SUCCESS)
8394 return rcStrict;
8395
8396 iemHlpUsedFpu(pVCpu);
8397 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8398 return VINF_SUCCESS;
8399}
8400
8401
8402/**
8403 * Implements 'FRSTOR'.
8404 *
8405 * @param GCPtrEffSrc The address of the image.
8406 * @param enmEffOpSize The operand size.
8407 */
8408IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8409{
8410 RTCPTRUNION uPtr;
8411 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8412 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8413 if (rcStrict != VINF_SUCCESS)
8414 return rcStrict;
8415
8416 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8417 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
8418 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8419 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8420 {
8421 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
8422 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
8423 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
8424 pFpuCtx->aRegs[i].au32[3] = 0;
8425 }
8426
8427 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8428 if (rcStrict != VINF_SUCCESS)
8429 return rcStrict;
8430
8431 iemHlpUsedFpu(pVCpu);
8432 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8433 return VINF_SUCCESS;
8434}
8435
8436
8437/**
8438 * Implements 'FLDCW'.
8439 *
8440 * @param u16Fcw The new FCW.
8441 */
8442IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
8443{
8444 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8445
8446 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
8447 /** @todo Testcase: Try see what happens when trying to set undefined bits
8448 * (other than 6 and 7). Currently ignoring them. */
8449 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
8450 * according to FSW. (This is was is currently implemented.) */
8451 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8452 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
8453 iemFpuRecalcExceptionStatus(pFpuCtx);
8454
8455 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8456 iemHlpUsedFpu(pVCpu);
8457 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8458 return VINF_SUCCESS;
8459}
8460
8461
8462
8463/**
8464 * Implements the underflow case of fxch.
8465 *
8466 * @param iStReg The other stack register.
8467 */
8468IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
8469{
8470 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8471
8472 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8473 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
8474 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8475 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
8476
8477 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
8478 * registers are read as QNaN and then exchanged. This could be
8479 * wrong... */
8480 if (pFpuCtx->FCW & X86_FCW_IM)
8481 {
8482 if (RT_BIT(iReg1) & pFpuCtx->FTW)
8483 {
8484 if (RT_BIT(iReg2) & pFpuCtx->FTW)
8485 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8486 else
8487 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
8488 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
8489 }
8490 else
8491 {
8492 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
8493 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8494 }
8495 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
8496 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
8497 }
8498 else
8499 {
8500 /* raise underflow exception, don't change anything. */
8501 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
8502 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8503 }
8504
8505 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
8506 iemHlpUsedFpu(pVCpu);
8507 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8508 return VINF_SUCCESS;
8509}
8510
8511
8512/**
8513 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
8514 *
8515 * @param cToAdd 1 or 7.
8516 */
8517IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
8518{
8519 Assert(iStReg < 8);
8520 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8521
8522 /*
8523 * Raise exceptions.
8524 */
8525 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
8526 return iemRaiseDeviceNotAvailable(pVCpu);
8527
8528 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8529 uint16_t u16Fsw = pFpuCtx->FSW;
8530 if (u16Fsw & X86_FSW_ES)
8531 return iemRaiseMathFault(pVCpu);
8532
8533 /*
8534 * Check if any of the register accesses causes #SF + #IA.
8535 */
8536 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
8537 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8538 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
8539 {
8540 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
8541 NOREF(u32Eflags);
8542
8543 pFpuCtx->FSW &= ~X86_FSW_C1;
8544 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
8545 if ( !(u16Fsw & X86_FSW_IE)
8546 || (pFpuCtx->FCW & X86_FCW_IM) )
8547 {
8548 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8549 pVCpu->cpum.GstCtx.eflags.u |= pVCpu->cpum.GstCtx.eflags.u & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8550 }
8551 }
8552 else if (pFpuCtx->FCW & X86_FCW_IM)
8553 {
8554 /* Masked underflow. */
8555 pFpuCtx->FSW &= ~X86_FSW_C1;
8556 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
8557 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8558 pVCpu->cpum.GstCtx.eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
8559 }
8560 else
8561 {
8562 /* Raise underflow - don't touch EFLAGS or TOP. */
8563 pFpuCtx->FSW &= ~X86_FSW_C1;
8564 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8565 fPop = false;
8566 }
8567
8568 /*
8569 * Pop if necessary.
8570 */
8571 if (fPop)
8572 {
8573 pFpuCtx->FTW &= ~RT_BIT(iReg1);
8574 pFpuCtx->FSW &= X86_FSW_TOP_MASK;
8575 pFpuCtx->FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
8576 }
8577
8578 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
8579 iemHlpUsedFpu(pVCpu);
8580 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8581 return VINF_SUCCESS;
8582}
8583
8584/** @} */
8585
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