VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h@ 37918

Last change on this file since 37918 was 37918, checked in by vboxsync, 13 years ago

IEM: Implemented AAD (used by the bios build by watcomc) and fixed a LES decoding bug.
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File size: 96.0 KB
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1/* $Id: IEMAllCImpl.cpp.h 37918 2011-07-13 13:38:33Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @name Misc Helpers
20 * @{
21 */
22
23/**
24 * Checks if we are allowed to access the given I/O port, raising the
25 * appropriate exceptions if we aren't (or if the I/O bitmap is not
26 * accessible).
27 *
28 * @returns Strict VBox status code.
29 *
30 * @param pIemCpu The IEM per CPU data.
31 * @param pCtx The register context.
32 * @param u16Port The port number.
33 * @param cbOperand The operand size.
34 */
35DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PIEMCPU pIemCpu, PCCPUMCTX pCtx, uint16_t u16Port, uint8_t cbOperand)
36{
37 if ( (pCtx->cr0 & X86_CR0_PE)
38 && ( pIemCpu->uCpl > pCtx->eflags.Bits.u2IOPL
39 || pCtx->eflags.Bits.u1VM) )
40 {
41 /** @todo I/O port permission bitmap check */
42 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
43 }
44 return VINF_SUCCESS;
45}
46
47
48#if 0
49/**
50 * Calculates the parity bit.
51 *
52 * @returns true if the bit is set, false if not.
53 * @param u8Result The least significant byte of the result.
54 */
55static bool iemHlpCalcParityFlag(uint8_t u8Result)
56{
57 /*
58 * Parity is set if the number of bits in the least significant byte of
59 * the result is even.
60 */
61 uint8_t cBits;
62 cBits = u8Result & 1; /* 0 */
63 u8Result >>= 1;
64 cBits += u8Result & 1;
65 u8Result >>= 1;
66 cBits += u8Result & 1;
67 u8Result >>= 1;
68 cBits += u8Result & 1;
69 u8Result >>= 1;
70 cBits += u8Result & 1; /* 4 */
71 u8Result >>= 1;
72 cBits += u8Result & 1;
73 u8Result >>= 1;
74 cBits += u8Result & 1;
75 u8Result >>= 1;
76 cBits += u8Result & 1;
77 return !(cBits & 1);
78}
79#endif /* not used */
80
81
82/**
83 * Updates the specified flags according to a 8-bit result.
84 *
85 * @param pIemCpu The.
86 * @param u8Result The result to set the flags according to.
87 * @param fToUpdate The flags to update.
88 * @param fUndefined The flags that are specified as undefined.
89 */
90static void iemHlpUpdateArithEFlagsU8(PIEMCPU pIemCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
91{
92 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
93
94 uint32_t fEFlags = pCtx->eflags.u;
95 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
96 pCtx->eflags.u &= ~(fToUpdate | fUndefined);
97 pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
98}
99
100
101/** @} */
102
103/** @name C Implementations
104 * @{
105 */
106
107/**
108 * Implements a 16-bit popa.
109 */
110IEM_CIMPL_DEF_0(iemCImpl_popa_16)
111{
112 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
113 RTGCPTR GCPtrStart = iemRegGetEffRsp(pCtx);
114 RTGCPTR GCPtrLast = GCPtrStart + 15;
115 VBOXSTRICTRC rcStrict;
116
117 /*
118 * The docs are a bit hard to comprehend here, but it looks like we wrap
119 * around in real mode as long as none of the individual "popa" crosses the
120 * end of the stack segment. In protected mode we check the whole access
121 * in one go. For efficiency, only do the word-by-word thing if we're in
122 * danger of wrapping around.
123 */
124 /** @todo do popa boundary / wrap-around checks. */
125 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pIemCpu)
126 && (pCtx->csHid.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
127 {
128 /* word-by-word */
129 RTUINT64U TmpRsp;
130 TmpRsp.u = pCtx->rsp;
131 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->di, &TmpRsp);
132 if (rcStrict == VINF_SUCCESS)
133 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->si, &TmpRsp);
134 if (rcStrict == VINF_SUCCESS)
135 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->bp, &TmpRsp);
136 if (rcStrict == VINF_SUCCESS)
137 {
138 iemRegAddToRspEx(&TmpRsp, 2, pCtx); /* sp */
139 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->bx, &TmpRsp);
140 }
141 if (rcStrict == VINF_SUCCESS)
142 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->dx, &TmpRsp);
143 if (rcStrict == VINF_SUCCESS)
144 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->cx, &TmpRsp);
145 if (rcStrict == VINF_SUCCESS)
146 rcStrict = iemMemStackPopU16Ex(pIemCpu, &pCtx->ax, &TmpRsp);
147 if (rcStrict == VINF_SUCCESS)
148 {
149 pCtx->rsp = TmpRsp.u;
150 iemRegAddToRip(pIemCpu, cbInstr);
151 }
152 }
153 else
154 {
155 uint16_t const *pa16Mem = NULL;
156 rcStrict = iemMemMap(pIemCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
157 if (rcStrict == VINF_SUCCESS)
158 {
159 pCtx->di = pa16Mem[7 - X86_GREG_xDI];
160 pCtx->si = pa16Mem[7 - X86_GREG_xSI];
161 pCtx->bp = pa16Mem[7 - X86_GREG_xBP];
162 /* skip sp */
163 pCtx->bx = pa16Mem[7 - X86_GREG_xBX];
164 pCtx->dx = pa16Mem[7 - X86_GREG_xDX];
165 pCtx->cx = pa16Mem[7 - X86_GREG_xCX];
166 pCtx->ax = pa16Mem[7 - X86_GREG_xAX];
167 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
168 if (rcStrict == VINF_SUCCESS)
169 {
170 iemRegAddToRsp(pCtx, 16);
171 iemRegAddToRip(pIemCpu, cbInstr);
172 }
173 }
174 }
175 return rcStrict;
176}
177
178
179/**
180 * Implements a 32-bit popa.
181 */
182IEM_CIMPL_DEF_0(iemCImpl_popa_32)
183{
184 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
185 RTGCPTR GCPtrStart = iemRegGetEffRsp(pCtx);
186 RTGCPTR GCPtrLast = GCPtrStart + 31;
187 VBOXSTRICTRC rcStrict;
188
189 /*
190 * The docs are a bit hard to comprehend here, but it looks like we wrap
191 * around in real mode as long as none of the individual "popa" crosses the
192 * end of the stack segment. In protected mode we check the whole access
193 * in one go. For efficiency, only do the word-by-word thing if we're in
194 * danger of wrapping around.
195 */
196 /** @todo do popa boundary / wrap-around checks. */
197 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pIemCpu)
198 && (pCtx->csHid.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
199 {
200 /* word-by-word */
201 RTUINT64U TmpRsp;
202 TmpRsp.u = pCtx->rsp;
203 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->edi, &TmpRsp);
204 if (rcStrict == VINF_SUCCESS)
205 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->esi, &TmpRsp);
206 if (rcStrict == VINF_SUCCESS)
207 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ebp, &TmpRsp);
208 if (rcStrict == VINF_SUCCESS)
209 {
210 iemRegAddToRspEx(&TmpRsp, 2, pCtx); /* sp */
211 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ebx, &TmpRsp);
212 }
213 if (rcStrict == VINF_SUCCESS)
214 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->edx, &TmpRsp);
215 if (rcStrict == VINF_SUCCESS)
216 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->ecx, &TmpRsp);
217 if (rcStrict == VINF_SUCCESS)
218 rcStrict = iemMemStackPopU32Ex(pIemCpu, &pCtx->eax, &TmpRsp);
219 if (rcStrict == VINF_SUCCESS)
220 {
221#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
222 pCtx->rdi &= UINT32_MAX;
223 pCtx->rsi &= UINT32_MAX;
224 pCtx->rbp &= UINT32_MAX;
225 pCtx->rbx &= UINT32_MAX;
226 pCtx->rdx &= UINT32_MAX;
227 pCtx->rcx &= UINT32_MAX;
228 pCtx->rax &= UINT32_MAX;
229#endif
230 pCtx->rsp = TmpRsp.u;
231 iemRegAddToRip(pIemCpu, cbInstr);
232 }
233 }
234 else
235 {
236 uint32_t const *pa32Mem;
237 rcStrict = iemMemMap(pIemCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
238 if (rcStrict == VINF_SUCCESS)
239 {
240 pCtx->rdi = pa32Mem[7 - X86_GREG_xDI];
241 pCtx->rsi = pa32Mem[7 - X86_GREG_xSI];
242 pCtx->rbp = pa32Mem[7 - X86_GREG_xBP];
243 /* skip esp */
244 pCtx->rbx = pa32Mem[7 - X86_GREG_xBX];
245 pCtx->rdx = pa32Mem[7 - X86_GREG_xDX];
246 pCtx->rcx = pa32Mem[7 - X86_GREG_xCX];
247 pCtx->rax = pa32Mem[7 - X86_GREG_xAX];
248 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
249 if (rcStrict == VINF_SUCCESS)
250 {
251 iemRegAddToRsp(pCtx, 32);
252 iemRegAddToRip(pIemCpu, cbInstr);
253 }
254 }
255 }
256 return rcStrict;
257}
258
259
260/**
261 * Implements a 16-bit pusha.
262 */
263IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
264{
265 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
266 RTGCPTR GCPtrTop = iemRegGetEffRsp(pCtx);
267 RTGCPTR GCPtrBottom = GCPtrTop - 15;
268 VBOXSTRICTRC rcStrict;
269
270 /*
271 * The docs are a bit hard to comprehend here, but it looks like we wrap
272 * around in real mode as long as none of the individual "pushd" crosses the
273 * end of the stack segment. In protected mode we check the whole access
274 * in one go. For efficiency, only do the word-by-word thing if we're in
275 * danger of wrapping around.
276 */
277 /** @todo do pusha boundary / wrap-around checks. */
278 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
279 && IEM_IS_REAL_OR_V86_MODE(pIemCpu) ) )
280 {
281 /* word-by-word */
282 RTUINT64U TmpRsp;
283 TmpRsp.u = pCtx->rsp;
284 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->ax, &TmpRsp);
285 if (rcStrict == VINF_SUCCESS)
286 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->cx, &TmpRsp);
287 if (rcStrict == VINF_SUCCESS)
288 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->dx, &TmpRsp);
289 if (rcStrict == VINF_SUCCESS)
290 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->bx, &TmpRsp);
291 if (rcStrict == VINF_SUCCESS)
292 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->sp, &TmpRsp);
293 if (rcStrict == VINF_SUCCESS)
294 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->bp, &TmpRsp);
295 if (rcStrict == VINF_SUCCESS)
296 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->si, &TmpRsp);
297 if (rcStrict == VINF_SUCCESS)
298 rcStrict = iemMemStackPushU16Ex(pIemCpu, pCtx->di, &TmpRsp);
299 if (rcStrict == VINF_SUCCESS)
300 {
301 pCtx->rsp = TmpRsp.u;
302 iemRegAddToRip(pIemCpu, cbInstr);
303 }
304 }
305 else
306 {
307 GCPtrBottom--;
308 uint16_t *pa16Mem = NULL;
309 rcStrict = iemMemMap(pIemCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
310 if (rcStrict == VINF_SUCCESS)
311 {
312 pa16Mem[7 - X86_GREG_xDI] = pCtx->di;
313 pa16Mem[7 - X86_GREG_xSI] = pCtx->si;
314 pa16Mem[7 - X86_GREG_xBP] = pCtx->bp;
315 pa16Mem[7 - X86_GREG_xSP] = pCtx->sp;
316 pa16Mem[7 - X86_GREG_xBX] = pCtx->bx;
317 pa16Mem[7 - X86_GREG_xDX] = pCtx->dx;
318 pa16Mem[7 - X86_GREG_xCX] = pCtx->cx;
319 pa16Mem[7 - X86_GREG_xAX] = pCtx->ax;
320 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
321 if (rcStrict == VINF_SUCCESS)
322 {
323 iemRegSubFromRsp(pCtx, 16);
324 iemRegAddToRip(pIemCpu, cbInstr);
325 }
326 }
327 }
328 return rcStrict;
329}
330
331
332/**
333 * Implements a 32-bit pusha.
334 */
335IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
336{
337 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
338 RTGCPTR GCPtrTop = iemRegGetEffRsp(pCtx);
339 RTGCPTR GCPtrBottom = GCPtrTop - 31;
340 VBOXSTRICTRC rcStrict;
341
342 /*
343 * The docs are a bit hard to comprehend here, but it looks like we wrap
344 * around in real mode as long as none of the individual "pusha" crosses the
345 * end of the stack segment. In protected mode we check the whole access
346 * in one go. For efficiency, only do the word-by-word thing if we're in
347 * danger of wrapping around.
348 */
349 /** @todo do pusha boundary / wrap-around checks. */
350 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
351 && IEM_IS_REAL_OR_V86_MODE(pIemCpu) ) )
352 {
353 /* word-by-word */
354 RTUINT64U TmpRsp;
355 TmpRsp.u = pCtx->rsp;
356 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->eax, &TmpRsp);
357 if (rcStrict == VINF_SUCCESS)
358 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ecx, &TmpRsp);
359 if (rcStrict == VINF_SUCCESS)
360 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->edx, &TmpRsp);
361 if (rcStrict == VINF_SUCCESS)
362 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ebx, &TmpRsp);
363 if (rcStrict == VINF_SUCCESS)
364 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->esp, &TmpRsp);
365 if (rcStrict == VINF_SUCCESS)
366 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->ebp, &TmpRsp);
367 if (rcStrict == VINF_SUCCESS)
368 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->esi, &TmpRsp);
369 if (rcStrict == VINF_SUCCESS)
370 rcStrict = iemMemStackPushU32Ex(pIemCpu, pCtx->edi, &TmpRsp);
371 if (rcStrict == VINF_SUCCESS)
372 {
373 pCtx->rsp = TmpRsp.u;
374 iemRegAddToRip(pIemCpu, cbInstr);
375 }
376 }
377 else
378 {
379 GCPtrBottom--;
380 uint32_t *pa32Mem;
381 rcStrict = iemMemMap(pIemCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
382 if (rcStrict == VINF_SUCCESS)
383 {
384 pa32Mem[7 - X86_GREG_xDI] = pCtx->edi;
385 pa32Mem[7 - X86_GREG_xSI] = pCtx->esi;
386 pa32Mem[7 - X86_GREG_xBP] = pCtx->ebp;
387 pa32Mem[7 - X86_GREG_xSP] = pCtx->esp;
388 pa32Mem[7 - X86_GREG_xBX] = pCtx->ebx;
389 pa32Mem[7 - X86_GREG_xDX] = pCtx->edx;
390 pa32Mem[7 - X86_GREG_xCX] = pCtx->ecx;
391 pa32Mem[7 - X86_GREG_xAX] = pCtx->eax;
392 rcStrict = iemMemCommitAndUnmap(pIemCpu, pa32Mem, IEM_ACCESS_STACK_W);
393 if (rcStrict == VINF_SUCCESS)
394 {
395 iemRegSubFromRsp(pCtx, 32);
396 iemRegAddToRip(pIemCpu, cbInstr);
397 }
398 }
399 }
400 return rcStrict;
401}
402
403
404/**
405 * Implements pushf.
406 *
407 *
408 * @param enmEffOpSize The effective operand size.
409 */
410IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
411{
412 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
413
414 /*
415 * If we're in V8086 mode some care is required (which is why we're in
416 * doing this in a C implementation).
417 */
418 uint32_t fEfl = pCtx->eflags.u;
419 if ( (fEfl & X86_EFL_VM)
420 && X86_EFL_GET_IOPL(fEfl) != 3 )
421 {
422 Assert(pCtx->cr0 & X86_CR0_PE);
423 if ( enmEffOpSize != IEMMODE_16BIT
424 || !(pCtx->cr4 & X86_CR4_VME))
425 return iemRaiseGeneralProtectionFault0(pIemCpu);
426 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
427 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
428 return iemMemStackPushU16(pIemCpu, (uint16_t)fEfl);
429 }
430
431 /*
432 * Ok, clear RF and VM and push the flags.
433 */
434 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
435
436 VBOXSTRICTRC rcStrict;
437 switch (enmEffOpSize)
438 {
439 case IEMMODE_16BIT:
440 rcStrict = iemMemStackPushU16(pIemCpu, (uint16_t)fEfl);
441 break;
442 case IEMMODE_32BIT:
443 rcStrict = iemMemStackPushU32(pIemCpu, fEfl);
444 break;
445 case IEMMODE_64BIT:
446 rcStrict = iemMemStackPushU64(pIemCpu, fEfl);
447 break;
448 IEM_NOT_REACHED_DEFAULT_CASE_RET();
449 }
450 if (rcStrict != VINF_SUCCESS)
451 return rcStrict;
452
453 iemRegAddToRip(pIemCpu, cbInstr);
454 return VINF_SUCCESS;
455}
456
457
458/**
459 * Implements popf.
460 *
461 * @param enmEffOpSize The effective operand size.
462 */
463IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
464{
465 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
466 uint32_t const fEflOld = pCtx->eflags.u;
467 VBOXSTRICTRC rcStrict;
468 uint32_t fEflNew;
469
470 /*
471 * V8086 is special as usual.
472 */
473 if (fEflOld & X86_EFL_VM)
474 {
475 /*
476 * Almost anything goes if IOPL is 3.
477 */
478 if (X86_EFL_GET_IOPL(fEflOld) == 3)
479 {
480 switch (enmEffOpSize)
481 {
482 case IEMMODE_16BIT:
483 {
484 uint16_t u16Value;
485 rcStrict = iemMemStackPopU16(pIemCpu, &u16Value);
486 if (rcStrict != VINF_SUCCESS)
487 return rcStrict;
488 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
489 break;
490 }
491 case IEMMODE_32BIT:
492 rcStrict = iemMemStackPopU32(pIemCpu, &fEflNew);
493 if (rcStrict != VINF_SUCCESS)
494 return rcStrict;
495 break;
496 IEM_NOT_REACHED_DEFAULT_CASE_RET();
497 }
498
499 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
500 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
501 }
502 /*
503 * Interrupt flag virtualization with CR4.VME=1.
504 */
505 else if ( enmEffOpSize == IEMMODE_16BIT
506 && (pCtx->cr4 & X86_CR4_VME) )
507 {
508 uint16_t u16Value;
509 RTUINT64U TmpRsp;
510 TmpRsp.u = pCtx->rsp;
511 rcStrict = iemMemStackPopU16Ex(pIemCpu, &u16Value, &TmpRsp);
512 if (rcStrict != VINF_SUCCESS)
513 return rcStrict;
514
515 /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
516 * or before? */
517 if ( ( (u16Value & X86_EFL_IF)
518 && (fEflOld & X86_EFL_VIP))
519 || (u16Value & X86_EFL_TF) )
520 return iemRaiseGeneralProtectionFault0(pIemCpu);
521
522 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
523 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
524 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
525 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
526
527 pCtx->rsp = TmpRsp.u;
528 }
529 else
530 return iemRaiseGeneralProtectionFault0(pIemCpu);
531
532 }
533 /*
534 * Not in V8086 mode.
535 */
536 else
537 {
538 /* Pop the flags. */
539 switch (enmEffOpSize)
540 {
541 case IEMMODE_16BIT:
542 {
543 uint16_t u16Value;
544 rcStrict = iemMemStackPopU16(pIemCpu, &u16Value);
545 if (rcStrict != VINF_SUCCESS)
546 return rcStrict;
547 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
548 break;
549 }
550 case IEMMODE_32BIT:
551 case IEMMODE_64BIT:
552 rcStrict = iemMemStackPopU32(pIemCpu, &fEflNew);
553 if (rcStrict != VINF_SUCCESS)
554 return rcStrict;
555 break;
556 IEM_NOT_REACHED_DEFAULT_CASE_RET();
557 }
558
559 /* Merge them with the current flags. */
560 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
561 || pIemCpu->uCpl == 0)
562 {
563 fEflNew &= X86_EFL_POPF_BITS;
564 fEflNew |= ~X86_EFL_POPF_BITS & fEflOld;
565 }
566 else if (pIemCpu->uCpl <= X86_EFL_GET_IOPL(fEflOld))
567 {
568 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
569 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
570 }
571 else
572 {
573 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
574 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
575 }
576 }
577
578 /*
579 * Commit the flags.
580 */
581 Assert(fEflNew & RT_BIT_32(1));
582 pCtx->eflags.u = fEflNew;
583 iemRegAddToRip(pIemCpu, cbInstr);
584
585 return VINF_SUCCESS;
586}
587
588
589/**
590 * Implements an indirect call.
591 *
592 * @param uNewPC The new program counter (RIP) value (loaded from the
593 * operand).
594 * @param enmEffOpSize The effective operand size.
595 */
596IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
597{
598 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
599 uint16_t uOldPC = pCtx->ip + cbInstr;
600 if (uNewPC > pCtx->csHid.u32Limit)
601 return iemRaiseGeneralProtectionFault0(pIemCpu);
602
603 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pIemCpu, uOldPC);
604 if (rcStrict != VINF_SUCCESS)
605 return rcStrict;
606
607 pCtx->rip = uNewPC;
608 return VINF_SUCCESS;
609
610}
611
612
613/**
614 * Implements a 16-bit relative call.
615 *
616 * @param offDisp The displacment offset.
617 */
618IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
619{
620 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
621 uint16_t uOldPC = pCtx->ip + cbInstr;
622 uint16_t uNewPC = uOldPC + offDisp;
623 if (uNewPC > pCtx->csHid.u32Limit)
624 return iemRaiseGeneralProtectionFault0(pIemCpu);
625
626 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pIemCpu, uOldPC);
627 if (rcStrict != VINF_SUCCESS)
628 return rcStrict;
629
630 pCtx->rip = uNewPC;
631 return VINF_SUCCESS;
632}
633
634
635/**
636 * Implements a 32-bit indirect call.
637 *
638 * @param uNewPC The new program counter (RIP) value (loaded from the
639 * operand).
640 * @param enmEffOpSize The effective operand size.
641 */
642IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
643{
644 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
645 uint32_t uOldPC = pCtx->eip + cbInstr;
646 if (uNewPC > pCtx->csHid.u32Limit)
647 return iemRaiseGeneralProtectionFault0(pIemCpu);
648
649 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pIemCpu, uOldPC);
650 if (rcStrict != VINF_SUCCESS)
651 return rcStrict;
652
653 pCtx->rip = uNewPC;
654 return VINF_SUCCESS;
655
656}
657
658
659/**
660 * Implements a 32-bit relative call.
661 *
662 * @param offDisp The displacment offset.
663 */
664IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
665{
666 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
667 uint32_t uOldPC = pCtx->eip + cbInstr;
668 uint32_t uNewPC = uOldPC + offDisp;
669 if (uNewPC > pCtx->csHid.u32Limit)
670 return iemRaiseGeneralProtectionFault0(pIemCpu);
671
672 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pIemCpu, uOldPC);
673 if (rcStrict != VINF_SUCCESS)
674 return rcStrict;
675
676 pCtx->rip = uNewPC;
677 return VINF_SUCCESS;
678}
679
680
681/**
682 * Implements a 64-bit indirect call.
683 *
684 * @param uNewPC The new program counter (RIP) value (loaded from the
685 * operand).
686 * @param enmEffOpSize The effective operand size.
687 */
688IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
689{
690 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
691 uint64_t uOldPC = pCtx->rip + cbInstr;
692 if (!IEM_IS_CANONICAL(uNewPC))
693 return iemRaiseGeneralProtectionFault0(pIemCpu);
694
695 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pIemCpu, uOldPC);
696 if (rcStrict != VINF_SUCCESS)
697 return rcStrict;
698
699 pCtx->rip = uNewPC;
700 return VINF_SUCCESS;
701
702}
703
704
705/**
706 * Implements a 64-bit relative call.
707 *
708 * @param offDisp The displacment offset.
709 */
710IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
711{
712 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
713 uint64_t uOldPC = pCtx->rip + cbInstr;
714 uint64_t uNewPC = uOldPC + offDisp;
715 if (!IEM_IS_CANONICAL(uNewPC))
716 return iemRaiseNotCanonical(pIemCpu);
717
718 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pIemCpu, uOldPC);
719 if (rcStrict != VINF_SUCCESS)
720 return rcStrict;
721
722 pCtx->rip = uNewPC;
723 return VINF_SUCCESS;
724}
725
726
727/**
728 * Implements far jumps.
729 *
730 * @param uSel The selector.
731 * @param offSeg The segment offset.
732 * @param enmEffOpSize The effective operand size.
733 */
734IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint32_t, offSeg, IEMMODE, enmEffOpSize)
735{
736 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
737
738 /*
739 * Real mode and V8086 mode are easy. The only snag seems to be that
740 * CS.limit doesn't change and the limit check is done against the current
741 * limit.
742 */
743 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
744 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
745 {
746 if (offSeg > pCtx->csHid.u32Limit)
747 return iemRaiseGeneralProtectionFault0(pIemCpu);
748
749 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
750 pCtx->rip = offSeg;
751 else
752 pCtx->rip = offSeg & UINT16_MAX;
753 pCtx->cs = uSel;
754 pCtx->csHid.u64Base = (uint32_t)uSel << 4;
755 /** @todo REM reset the accessed bit (see on jmp far16 after disabling
756 * PE. Check with VT-x and AMD-V. */
757#ifdef IEM_VERIFICATION_MODE
758 pCtx->csHid.Attr.u &= ~X86_SEL_TYPE_ACCESSED;
759#endif
760 return VINF_SUCCESS;
761 }
762
763 /*
764 * Protected mode. Need to parse the specified descriptor...
765 */
766 if (!(uSel & (X86_SEL_MASK | X86_SEL_LDT)))
767 {
768 Log(("jmpf %04x:%08x -> invalid selector, #GP(0)\n", uSel, offSeg));
769 return iemRaiseGeneralProtectionFault0(pIemCpu);
770 }
771
772 /* Fetch the descriptor. */
773 IEMSELDESC Desc;
774 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel);
775 if (rcStrict != VINF_SUCCESS)
776 return rcStrict;
777
778 /* Is it there? */
779 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
780 {
781 Log(("jmpf %04x:%08x -> segment not present\n", uSel, offSeg));
782 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
783 }
784
785 /*
786 * Deal with it according to its type.
787 */
788 if (Desc.Legacy.Gen.u1DescType)
789 {
790 /* Only code segments. */
791 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
792 {
793 Log(("jmpf %04x:%08x -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
794 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
795 }
796
797 /* L vs D. */
798 if ( Desc.Legacy.Gen.u1Long
799 && Desc.Legacy.Gen.u1DefBig
800 && IEM_IS_LONG_MODE(pIemCpu))
801 {
802 Log(("jmpf %04x:%08x -> both L and D are set.\n", uSel, offSeg));
803 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
804 }
805
806 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
807 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
808 {
809 if (Desc.Legacy.Gen.u2Dpl > pIemCpu->uCpl)
810 {
811 Log(("jmpf %04x:%08x -> DPL violation (conforming); DPL=%d CPL=%u\n",
812 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
813 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
814 }
815 }
816 else
817 {
818 if (Desc.Legacy.Gen.u2Dpl != pIemCpu->uCpl)
819 {
820 Log(("jmpf %04x:%08x -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
821 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
822 }
823 if ((uSel & X86_SEL_RPL) > pIemCpu->uCpl)
824 {
825 Log(("jmpf %04x:%08x -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pIemCpu->uCpl));
826 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
827 }
828 }
829
830 /* Limit check. (Should alternatively check for non-canonical addresses
831 here, but that is ruled out by offSeg being 32-bit, right?) */
832 uint64_t u64Base;
833 uint32_t cbLimit = X86DESC_LIMIT(Desc.Legacy);
834 if (Desc.Legacy.Gen.u1Granularity)
835 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
836 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
837 u64Base = 0;
838 else
839 {
840 if (offSeg > cbLimit)
841 {
842 Log(("jmpf %04x:%08x -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
843 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
844 }
845 u64Base = X86DESC_BASE(Desc.Legacy);
846 }
847
848 /*
849 * Ok, everything checked out fine. Now set the accessed bit before
850 * committing the result into CS, CSHID and RIP.
851 */
852 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
853 {
854 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
855 if (rcStrict != VINF_SUCCESS)
856 return rcStrict;
857#ifdef IEM_VERIFICATION_MODE /** @todo check what VT-x and AMD-V does. */
858 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
859#endif
860 }
861
862 /* commit */
863 pCtx->rip = offSeg;
864 pCtx->cs = uSel & (X86_SEL_MASK | X86_SEL_LDT);
865 pCtx->cs |= pIemCpu->uCpl; /** @todo is this right for conforming segs? or in general? */
866 pCtx->csHid.Attr.u = (Desc.Legacy.u >> (16+16+8)) & UINT32_C(0xf0ff);
867 pCtx->csHid.u32Limit = cbLimit;
868 pCtx->csHid.u64Base = u64Base;
869 /** @todo check if the hidden bits are loaded correctly for 64-bit
870 * mode. */
871 return VINF_SUCCESS;
872 }
873
874 /*
875 * System selector.
876 */
877 if (IEM_IS_LONG_MODE(pIemCpu))
878 switch (Desc.Legacy.Gen.u4Type)
879 {
880 case AMD64_SEL_TYPE_SYS_LDT:
881 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
882 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
883 case AMD64_SEL_TYPE_SYS_CALL_GATE:
884 case AMD64_SEL_TYPE_SYS_INT_GATE:
885 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
886 /* Call various functions to do the work. */
887 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
888 default:
889 Log(("jmpf %04x:%08x -> wrong sys selector (64-bit): %d\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
890 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
891
892 }
893 switch (Desc.Legacy.Gen.u4Type)
894 {
895 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
896 case X86_SEL_TYPE_SYS_LDT:
897 case X86_SEL_TYPE_SYS_286_CALL_GATE:
898 case X86_SEL_TYPE_SYS_TASK_GATE:
899 case X86_SEL_TYPE_SYS_286_INT_GATE:
900 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
901 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
902 case X86_SEL_TYPE_SYS_386_CALL_GATE:
903 case X86_SEL_TYPE_SYS_386_INT_GATE:
904 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
905 /* Call various functions to do the work. */
906 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
907
908 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
909 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
910 /* Call various functions to do the work. */
911 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
912
913 default:
914 Log(("jmpf %04x:%08x -> wrong sys selector (32-bit): %d\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
915 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
916 }
917}
918
919
920/**
921 * Implements far calls.
922 *
923 * @param uSel The selector.
924 * @param offSeg The segment offset.
925 * @param enmOpSize The operand size (in case we need it).
926 */
927IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmOpSize)
928{
929 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
930 VBOXSTRICTRC rcStrict;
931 uint64_t uNewRsp;
932 void *pvRet;
933
934 /*
935 * Real mode and V8086 mode are easy. The only snag seems to be that
936 * CS.limit doesn't change and the limit check is done against the current
937 * limit.
938 */
939 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
940 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
941 {
942 Assert(enmOpSize == IEMMODE_16BIT || enmOpSize == IEMMODE_32BIT);
943
944 /* Check stack first - may #SS(0). */
945 rcStrict = iemMemStackPushBeginSpecial(pIemCpu, enmOpSize == IEMMODE_32BIT ? 6 : 4,
946 &pvRet, &uNewRsp);
947 if (rcStrict != VINF_SUCCESS)
948 return rcStrict;
949
950 /* Check the target address range. */
951 if (offSeg > UINT32_MAX)
952 return iemRaiseGeneralProtectionFault0(pIemCpu);
953
954 /* Everything is fine, push the return address. */
955 if (enmOpSize == IEMMODE_16BIT)
956 {
957 ((uint16_t *)pvRet)[0] = pCtx->ip + cbInstr;
958 ((uint16_t *)pvRet)[1] = pCtx->cs;
959 }
960 else
961 {
962 ((uint32_t *)pvRet)[0] = pCtx->eip + cbInstr;
963 ((uint16_t *)pvRet)[3] = pCtx->cs;
964 }
965 rcStrict = iemMemStackPushCommitSpecial(pIemCpu, pvRet, uNewRsp);
966 if (rcStrict != VINF_SUCCESS)
967 return rcStrict;
968
969 /* Branch. */
970 pCtx->rip = offSeg;
971 pCtx->cs = uSel;
972 pCtx->csHid.u64Base = (uint32_t)uSel << 4;
973 /** @todo Does REM reset the accessed bit here to? (See on jmp far16
974 * after disabling PE.) Check with VT-x and AMD-V. */
975#ifdef IEM_VERIFICATION_MODE
976 pCtx->csHid.Attr.u &= ~X86_SEL_TYPE_ACCESSED;
977#endif
978 return VINF_SUCCESS;
979 }
980
981 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
982}
983
984
985/**
986 * Implements retf.
987 *
988 * @param enmEffOpSize The effective operand size.
989 * @param cbPop The amount of arguments to pop from the stack
990 * (bytes).
991 */
992IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
993{
994 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
995 VBOXSTRICTRC rcStrict;
996 uint64_t uNewRsp;
997
998 /*
999 * Real mode and V8086 mode are easy.
1000 */
1001 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
1002 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1003 {
1004 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
1005 uint16_t const *pu16Frame;
1006 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, enmEffOpSize == IEMMODE_32BIT ? 8 : 4,
1007 (void const **)&pu16Frame, &uNewRsp);
1008 if (rcStrict != VINF_SUCCESS)
1009 return rcStrict;
1010 uint32_t uNewEip;
1011 uint16_t uNewCS;
1012 if (enmEffOpSize == IEMMODE_32BIT)
1013 {
1014 uNewCS = pu16Frame[2];
1015 uNewEip = RT_MAKE_U32(pu16Frame[0], pu16Frame[1]);
1016 }
1017 else
1018 {
1019 uNewCS = pu16Frame[1];
1020 uNewEip = pu16Frame[0];
1021 }
1022 /** @todo check how this is supposed to work if sp=0xfffe. */
1023
1024 /* Check the limit of the new EIP. */
1025 /** @todo Intel pseudo code only does the limit check for 16-bit
1026 * operands, AMD does not make any distinction. What is right? */
1027 if (uNewEip > pCtx->csHid.u32Limit)
1028 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
1029
1030 /* commit the operation. */
1031 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, pu16Frame, uNewRsp);
1032 if (rcStrict != VINF_SUCCESS)
1033 return rcStrict;
1034 pCtx->rip = uNewEip;
1035 pCtx->cs = uNewCS;
1036 pCtx->csHid.u64Base = (uint32_t)uNewCS << 4;
1037 /** @todo do we load attribs and limit as well? */
1038 if (cbPop)
1039 iemRegAddToRsp(pCtx, cbPop);
1040 return VINF_SUCCESS;
1041 }
1042
1043 AssertFailed();
1044 return VERR_NOT_IMPLEMENTED;
1045}
1046
1047
1048/**
1049 * Implements retn.
1050 *
1051 * We're doing this in C because of the \#GP that might be raised if the popped
1052 * program counter is out of bounds.
1053 *
1054 * @param enmEffOpSize The effective operand size.
1055 * @param cbPop The amount of arguments to pop from the stack
1056 * (bytes).
1057 */
1058IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
1059{
1060 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1061
1062 /* Fetch the RSP from the stack. */
1063 VBOXSTRICTRC rcStrict;
1064 RTUINT64U NewRip;
1065 RTUINT64U NewRsp;
1066 NewRsp.u = pCtx->rsp;
1067 switch (enmEffOpSize)
1068 {
1069 case IEMMODE_16BIT:
1070 NewRip.u = 0;
1071 rcStrict = iemMemStackPopU16Ex(pIemCpu, &NewRip.Words.w0, &NewRsp);
1072 break;
1073 case IEMMODE_32BIT:
1074 NewRip.u = 0;
1075 rcStrict = iemMemStackPopU32Ex(pIemCpu, &NewRip.DWords.dw0, &NewRsp);
1076 break;
1077 case IEMMODE_64BIT:
1078 rcStrict = iemMemStackPopU64Ex(pIemCpu, &NewRip.u, &NewRsp);
1079 break;
1080 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1081 }
1082 if (rcStrict != VINF_SUCCESS)
1083 return rcStrict;
1084
1085 /* Check the new RSP before loading it. */
1086 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
1087 * of it. The canonical test is performed here and for call. */
1088 if (enmEffOpSize != IEMMODE_64BIT)
1089 {
1090 if (NewRip.DWords.dw0 > pCtx->csHid.u32Limit)
1091 {
1092 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pCtx->csHid.u32Limit));
1093 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
1094 }
1095 }
1096 else
1097 {
1098 if (!IEM_IS_CANONICAL(NewRip.u))
1099 {
1100 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
1101 return iemRaiseNotCanonical(pIemCpu);
1102 }
1103 }
1104
1105 /* Commit it. */
1106 pCtx->rip = NewRip.u;
1107 pCtx->rsp = NewRsp.u;
1108 if (cbPop)
1109 iemRegAddToRsp(pCtx, cbPop);
1110
1111 return VINF_SUCCESS;
1112}
1113
1114
1115/**
1116 * Implements leave.
1117 *
1118 * We're doing this in C because messing with the stack registers is annoying
1119 * since they depends on SS attributes.
1120 *
1121 * @param enmEffOpSize The effective operand size.
1122 */
1123IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
1124{
1125 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1126
1127 /* Calculate the intermediate RSP from RBP and the stack attributes. */
1128 RTUINT64U NewRsp;
1129 if (pCtx->ssHid.Attr.n.u1Long)
1130 {
1131 /** @todo Check that LEAVE actually preserve the high EBP bits. */
1132 NewRsp.u = pCtx->rsp;
1133 NewRsp.Words.w0 = pCtx->bp;
1134 }
1135 else if (pCtx->ssHid.Attr.n.u1DefBig)
1136 NewRsp.u = pCtx->ebp;
1137 else
1138 NewRsp.u = pCtx->rbp;
1139
1140 /* Pop RBP according to the operand size. */
1141 VBOXSTRICTRC rcStrict;
1142 RTUINT64U NewRbp;
1143 switch (enmEffOpSize)
1144 {
1145 case IEMMODE_16BIT:
1146 NewRbp.u = pCtx->rbp;
1147 rcStrict = iemMemStackPopU16Ex(pIemCpu, &NewRbp.Words.w0, &NewRsp);
1148 break;
1149 case IEMMODE_32BIT:
1150 NewRbp.u = 0;
1151 rcStrict = iemMemStackPopU32Ex(pIemCpu, &NewRbp.DWords.dw0, &NewRsp);
1152 break;
1153 case IEMMODE_64BIT:
1154 rcStrict = iemMemStackPopU64Ex(pIemCpu, &NewRbp.u, &NewRsp);
1155 break;
1156 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1157 }
1158 if (rcStrict != VINF_SUCCESS)
1159 return rcStrict;
1160
1161
1162 /* Commit it. */
1163 pCtx->rbp = NewRbp.u;
1164 pCtx->rsp = NewRsp.u;
1165 iemRegAddToRip(pIemCpu, cbInstr);
1166
1167 return VINF_SUCCESS;
1168}
1169
1170
1171/**
1172 * Implements int3 and int XX.
1173 *
1174 * @param u8Int The interrupt vector number.
1175 * @param fIsBpInstr Is it the breakpoint instruction.
1176 */
1177IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, bool, fIsBpInstr)
1178{
1179 Assert(pIemCpu->cXcptRecursions == 0);
1180 return iemRaiseXcptOrInt(pIemCpu,
1181 cbInstr,
1182 u8Int,
1183 (fIsBpInstr ? IEM_XCPT_FLAGS_BP_INSTR : 0) | IEM_XCPT_FLAGS_T_SOFT_INT,
1184 0,
1185 0);
1186}
1187
1188
1189/**
1190 * Implements iret for real mode and V8086 mode.
1191 *
1192 * @param enmEffOpSize The effective operand size.
1193 */
1194IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
1195{
1196 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1197
1198 /*
1199 * iret throws an exception if VME isn't enabled.
1200 */
1201 if ( pCtx->eflags.Bits.u1VM
1202 && !(pCtx->cr4 & X86_CR4_VME))
1203 return iemRaiseGeneralProtectionFault0(pIemCpu);
1204
1205 /*
1206 * Do the stack bits, but don't commit RSP before everything checks
1207 * out right.
1208 */
1209 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
1210 VBOXSTRICTRC rcStrict;
1211 RTCPTRUNION uFrame;
1212 uint16_t uNewCS;
1213 uint32_t uNewEip;
1214 uint32_t uNewFlags;
1215 uint64_t uNewRsp;
1216 if (enmEffOpSize == IEMMODE_32BIT)
1217 {
1218 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 12, &uFrame.pv, &uNewRsp);
1219 if (rcStrict != VINF_SUCCESS)
1220 return rcStrict;
1221 uNewEip = uFrame.pu32[0];
1222 uNewCS = (uint16_t)uFrame.pu32[1];
1223 uNewFlags = uFrame.pu32[2];
1224 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
1225 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
1226 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
1227 | X86_EFL_ID;
1228 uNewFlags |= pCtx->eflags.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
1229 }
1230 else
1231 {
1232 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 6, &uFrame.pv, &uNewRsp);
1233 if (rcStrict != VINF_SUCCESS)
1234 return rcStrict;
1235 uNewEip = uFrame.pu16[0];
1236 uNewCS = uFrame.pu16[1];
1237 uNewFlags = uFrame.pu16[2];
1238 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
1239 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
1240 uNewFlags |= pCtx->eflags.u & (UINT32_C(0xffff0000) | X86_EFL_1);
1241 /** @todo The intel pseudo code does not indicate what happens to
1242 * reserved flags. We just ignore them. */
1243 }
1244 /** @todo Check how this is supposed to work if sp=0xfffe. */
1245
1246 /*
1247 * Check the limit of the new EIP.
1248 */
1249 /** @todo Only the AMD pseudo code check the limit here, what's
1250 * right? */
1251 if (uNewEip > pCtx->csHid.u32Limit)
1252 return iemRaiseSelectorBounds(pIemCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
1253
1254 /*
1255 * V8086 checks and flag adjustments
1256 */
1257 if (pCtx->eflags.Bits.u1VM)
1258 {
1259 if (pCtx->eflags.Bits.u2IOPL == 3)
1260 {
1261 /* Preserve IOPL and clear RF. */
1262 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
1263 uNewFlags |= pCtx->eflags.u & (X86_EFL_IOPL);
1264 }
1265 else if ( enmEffOpSize == IEMMODE_16BIT
1266 && ( !(uNewFlags & X86_EFL_IF)
1267 || !pCtx->eflags.Bits.u1VIP )
1268 && !(uNewFlags & X86_EFL_TF) )
1269 {
1270 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
1271 uNewFlags &= ~X86_EFL_VIF;
1272 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
1273 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
1274 uNewFlags |= pCtx->eflags.u & (X86_EFL_IF | X86_EFL_IOPL);
1275 }
1276 else
1277 return iemRaiseGeneralProtectionFault0(pIemCpu);
1278 }
1279
1280 /*
1281 * Commit the operation.
1282 */
1283 rcStrict = iemMemStackPopCommitSpecial(pIemCpu, uFrame.pv, uNewRsp);
1284 if (rcStrict != VINF_SUCCESS)
1285 return rcStrict;
1286 pCtx->rip = uNewEip;
1287 pCtx->cs = uNewCS;
1288 pCtx->csHid.u64Base = (uint32_t)uNewCS << 4;
1289 /** @todo do we load attribs and limit as well? */
1290 Assert(uNewFlags & X86_EFL_1);
1291 pCtx->eflags.u = uNewFlags;
1292
1293 return VINF_SUCCESS;
1294}
1295
1296
1297/**
1298 * Implements iret for protected mode
1299 *
1300 * @param enmEffOpSize The effective operand size.
1301 */
1302IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
1303{
1304 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1305
1306 /*
1307 * Nested task return.
1308 */
1309 if (pCtx->eflags.Bits.u1NT)
1310 {
1311 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
1312 }
1313 /*
1314 * Normal return.
1315 */
1316 else
1317 {
1318 /*
1319 * Do the stack bits, but don't commit RSP before everything checks
1320 * out right.
1321 */
1322 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
1323 VBOXSTRICTRC rcStrict;
1324 RTCPTRUNION uFrame;
1325 uint16_t uNewCS;
1326 uint32_t uNewEip;
1327 uint32_t uNewFlags;
1328 uint64_t uNewRsp;
1329 if (enmEffOpSize == IEMMODE_32BIT)
1330 {
1331 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 12, &uFrame.pv, &uNewRsp);
1332 if (rcStrict != VINF_SUCCESS)
1333 return rcStrict;
1334 uNewEip = uFrame.pu32[0];
1335 uNewCS = (uint16_t)uFrame.pu32[1];
1336 uNewFlags = uFrame.pu32[2];
1337 }
1338 else
1339 {
1340 rcStrict = iemMemStackPopBeginSpecial(pIemCpu, 6, &uFrame.pv, &uNewRsp);
1341 if (rcStrict != VINF_SUCCESS)
1342 return rcStrict;
1343 uNewEip = uFrame.pu16[0];
1344 uNewCS = uFrame.pu16[1];
1345 uNewFlags = uFrame.pu16[2];
1346 }
1347 rcStrict = iemMemCommitAndUnmap(pIemCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
1348 if (rcStrict != VINF_SUCCESS)
1349 return rcStrict;
1350
1351 /*
1352 * What are we returning to?
1353 */
1354 if ( (uNewFlags & X86_EFL_VM)
1355 && pIemCpu->uCpl == 0)
1356 {
1357 /* V8086 mode! */
1358 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
1359 }
1360 else
1361 {
1362 /*
1363 * Protected mode.
1364 */
1365 /* Read the CS descriptor. */
1366 if (!(uNewCS & (X86_SEL_MASK | X86_SEL_LDT)))
1367 {
1368 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCS, uNewEip));
1369 return iemRaiseGeneralProtectionFault0(pIemCpu);
1370 }
1371
1372 IEMSELDESC DescCS;
1373 rcStrict = iemMemFetchSelDesc(pIemCpu, &DescCS, uNewCS);
1374 if (rcStrict != VINF_SUCCESS)
1375 return rcStrict;
1376
1377 /* Must be a code descriptor. */
1378 if (!DescCS.Legacy.Gen.u1DescType)
1379 {
1380 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCS, uNewEip, DescCS.Legacy.Gen.u4Type));
1381 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1382 }
1383 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1384 {
1385 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCS, uNewEip, DescCS.Legacy.Gen.u4Type));
1386 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1387 }
1388
1389 /* Privilege checks. */
1390 if ((uNewCS & X86_SEL_RPL) < pIemCpu->uCpl)
1391 {
1392 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCS, uNewEip, pIemCpu->uCpl));
1393 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1394 }
1395 if ( (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1396 && (uNewCS & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
1397 {
1398 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCS, uNewEip, DescCS.Legacy.Gen.u2Dpl));
1399 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewCS);
1400 }
1401
1402 /* Present? */
1403 if (!DescCS.Legacy.Gen.u1Present)
1404 {
1405 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCS, uNewEip));
1406 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewCS);
1407 }
1408
1409 uint32_t cbLimitCS = X86DESC_LIMIT(DescCS.Legacy);
1410 if (DescCS.Legacy.Gen.u1Granularity)
1411 cbLimitCS = (cbLimitCS << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1412
1413 /*
1414 * Different level?
1415 */
1416 if ((uNewCS & X86_SEL_RPL) != pIemCpu->uCpl)
1417 {
1418 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
1419 }
1420 /*
1421 * Same level.
1422 */
1423 else
1424 {
1425 /* Check EIP. */
1426 if (uNewEip > cbLimitCS)
1427 {
1428 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewEip, cbLimitCS));
1429 return iemRaiseSelectorBoundsBySelector(pIemCpu, uNewCS);
1430 }
1431
1432 /*
1433 * Commit the changes, marking CS first since it may fail.
1434 */
1435 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1436 {
1437 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uNewCS);
1438 if (rcStrict != VINF_SUCCESS)
1439 return rcStrict;
1440 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1441 }
1442
1443 pCtx->rip = uNewEip;
1444 pCtx->cs = uNewCS;
1445 pCtx->csHid.Attr.u = X86DESC_GET_HID_ATTR(DescCS.Legacy);
1446 pCtx->csHid.u32Limit = cbLimitCS;
1447 pCtx->csHid.u64Base = X86DESC_BASE(DescCS.Legacy);
1448 pCtx->rsp = uNewRsp;
1449
1450 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
1451 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
1452 if (enmEffOpSize != IEMMODE_16BIT)
1453 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
1454 if (pIemCpu->uCpl == 0)
1455 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
1456 else if (pIemCpu->uCpl <= pCtx->eflags.Bits.u2IOPL)
1457 fEFlagsMask |= X86_EFL_IF;
1458 pCtx->eflags.u &= ~fEFlagsMask;
1459 pCtx->eflags.u |= fEFlagsMask & uNewFlags;
1460 /* Done! */
1461 }
1462 }
1463 }
1464
1465 return VINF_SUCCESS;
1466}
1467
1468
1469/**
1470 * Implements iret for long mode
1471 *
1472 * @param enmEffOpSize The effective operand size.
1473 */
1474IEM_CIMPL_DEF_1(iemCImpl_iret_long, IEMMODE, enmEffOpSize)
1475{
1476 //PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1477 //VBOXSTRICTRC rcStrict;
1478 //uint64_t uNewRsp;
1479
1480 return VERR_NOT_IMPLEMENTED;
1481}
1482
1483
1484/**
1485 * Implements iret.
1486 *
1487 * @param enmEffOpSize The effective operand size.
1488 */
1489IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
1490{
1491 /*
1492 * Call a mode specific worker.
1493 */
1494 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
1495 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1496 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
1497 if (IEM_IS_LONG_MODE(pIemCpu))
1498 return IEM_CIMPL_CALL_1(iemCImpl_iret_long, enmEffOpSize);
1499
1500 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
1501}
1502
1503
1504/**
1505 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
1506 *
1507 * @param iSegReg The segment register number (valid).
1508 * @param uSel The new selector value.
1509 */
1510IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
1511{
1512 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1513 uint16_t *pSel = iemSRegRef(pIemCpu, iSegReg);
1514 PCPUMSELREGHID pHid = iemSRegGetHid(pIemCpu, iSegReg);
1515
1516 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
1517
1518 /*
1519 * Real mode and V8086 mode are easy.
1520 */
1521 if ( pIemCpu->enmCpuMode == IEMMODE_16BIT
1522 && IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1523 {
1524 *pSel = uSel;
1525 pHid->u64Base = (uint32_t)uSel << 4;
1526 /** @todo Does the CPU actually load limits and attributes in the
1527 * real/V8086 mode segment load case? It doesn't for CS in far
1528 * jumps... Affects unreal mode. */
1529 pHid->u32Limit = 0xffff;
1530 pHid->Attr.u = 0;
1531 pHid->Attr.n.u1Present = 1;
1532 pHid->Attr.n.u1DescType = 1;
1533 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
1534 ? X86_SEL_TYPE_RW
1535 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
1536
1537 iemRegAddToRip(pIemCpu, cbInstr);
1538 return VINF_SUCCESS;
1539 }
1540
1541 /*
1542 * Protected mode.
1543 *
1544 * Check if it's a null segment selector value first, that's OK for DS, ES,
1545 * FS and GS. If not null, then we have to load and parse the descriptor.
1546 */
1547 if (!(uSel & (X86_SEL_MASK | X86_SEL_LDT)))
1548 {
1549 if (iSegReg == X86_SREG_SS)
1550 {
1551 if ( pIemCpu->enmCpuMode != IEMMODE_64BIT
1552 || pIemCpu->uCpl != 0
1553 || uSel != 0) /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? */
1554 {
1555 Log(("load sreg -> invalid stack selector, #GP(0)\n", uSel));
1556 return iemRaiseGeneralProtectionFault0(pIemCpu);
1557 }
1558
1559 /* In 64-bit kernel mode, the stack can be 0 because of the way
1560 interrupts are dispatched when in kernel ctx. Just load the
1561 selector value into the register and leave the hidden bits
1562 as is. */
1563 *pSel = uSel;
1564 iemRegAddToRip(pIemCpu, cbInstr);
1565 return VINF_SUCCESS;
1566 }
1567
1568 *pSel = uSel; /* Not RPL, remember :-) */
1569 if ( pIemCpu->enmCpuMode == IEMMODE_64BIT
1570 && iSegReg != X86_SREG_FS
1571 && iSegReg != X86_SREG_GS)
1572 {
1573 /** @todo figure out what this actually does, it works. Needs
1574 * testcase! */
1575 pHid->Attr.u = 0;
1576 pHid->Attr.n.u1Present = 1;
1577 pHid->Attr.n.u1Long = 1;
1578 pHid->Attr.n.u4Type = X86_SEL_TYPE_RW;
1579 pHid->Attr.n.u2Dpl = 3;
1580 pHid->u32Limit = 0;
1581 pHid->u64Base = 0;
1582 }
1583 else
1584 {
1585 pHid->Attr.u = 0;
1586 pHid->u32Limit = 0;
1587 pHid->u64Base = 0;
1588 }
1589 iemRegAddToRip(pIemCpu, cbInstr);
1590 return VINF_SUCCESS;
1591 }
1592
1593 /* Fetch the descriptor. */
1594 IEMSELDESC Desc;
1595 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uSel);
1596 if (rcStrict != VINF_SUCCESS)
1597 return rcStrict;
1598
1599 /* Check GPs first. */
1600 if (!Desc.Legacy.Gen.u1DescType)
1601 {
1602 Log(("load sreg %d - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
1603 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1604 }
1605 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
1606 {
1607 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
1608 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
1609 {
1610 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
1611 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1612 }
1613 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
1614 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
1615 {
1616 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
1617 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1618 }
1619 if ((uSel & X86_SEL_RPL) != pIemCpu->uCpl)
1620 {
1621 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pIemCpu->uCpl));
1622 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1623 }
1624 if (Desc.Legacy.Gen.u2Dpl != pIemCpu->uCpl)
1625 {
1626 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pIemCpu->uCpl));
1627 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1628 }
1629 }
1630 else
1631 {
1632 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
1633 {
1634 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
1635 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1636 }
1637 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1638 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1639 {
1640#if 0 /* this is what intel says. */
1641 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
1642 && pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
1643 {
1644 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
1645 iSegReg, uSel, (uSel & X86_SEL_RPL), pIemCpu->uCpl, Desc.Legacy.Gen.u2Dpl));
1646 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1647 }
1648#else /* this is what makes more sense. */
1649 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
1650 {
1651 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
1652 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
1653 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1654 }
1655 if (pIemCpu->uCpl > Desc.Legacy.Gen.u2Dpl)
1656 {
1657 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
1658 iSegReg, uSel, pIemCpu->uCpl, Desc.Legacy.Gen.u2Dpl));
1659 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uSel);
1660 }
1661#endif
1662 }
1663 }
1664
1665 /* Is it there? */
1666 if (!Desc.Legacy.Gen.u1Present)
1667 {
1668 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
1669 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uSel);
1670 }
1671
1672 /* The the base and limit. */
1673 uint64_t u64Base;
1674 uint32_t cbLimit = X86DESC_LIMIT(Desc.Legacy);
1675 if (Desc.Legacy.Gen.u1Granularity)
1676 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1677
1678 if ( pIemCpu->enmCpuMode == IEMMODE_64BIT
1679 && iSegReg < X86_SREG_FS)
1680 u64Base = 0;
1681 else
1682 u64Base = X86DESC_BASE(Desc.Legacy);
1683
1684 /*
1685 * Ok, everything checked out fine. Now set the accessed bit before
1686 * committing the result into the registers.
1687 */
1688 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1689 {
1690 rcStrict = iemMemMarkSelDescAccessed(pIemCpu, uSel);
1691 if (rcStrict != VINF_SUCCESS)
1692 return rcStrict;
1693 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1694 }
1695
1696 /* commit */
1697 *pSel = uSel;
1698 pHid->Attr.u = (Desc.Legacy.u >> (16+16+8)) & UINT32_C(0xf0ff); /** @todo do we have a define for 0xf0ff? */
1699 pHid->u32Limit = cbLimit;
1700 pHid->u64Base = u64Base;
1701
1702 /** @todo check if the hidden bits are loaded correctly for 64-bit
1703 * mode. */
1704
1705 iemRegAddToRip(pIemCpu, cbInstr);
1706 return VINF_SUCCESS;
1707}
1708
1709
1710/**
1711 * Implements 'mov SReg, r/m'.
1712 *
1713 * @param iSegReg The segment register number (valid).
1714 * @param uSel The new selector value.
1715 */
1716IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
1717{
1718 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
1719 if (rcStrict == VINF_SUCCESS)
1720 {
1721 if (iSegReg == X86_SREG_SS)
1722 {
1723 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1724 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
1725 }
1726 }
1727 return rcStrict;
1728}
1729
1730
1731/**
1732 * Implements 'pop SReg'.
1733 *
1734 * @param iSegReg The segment register number (valid).
1735 * @param enmEffOpSize The efficient operand size (valid).
1736 */
1737IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
1738{
1739 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1740 VBOXSTRICTRC rcStrict;
1741
1742 /*
1743 * Read the selector off the stack and join paths with mov ss, reg.
1744 */
1745 RTUINT64U TmpRsp;
1746 TmpRsp.u = pCtx->rsp;
1747 switch (enmEffOpSize)
1748 {
1749 case IEMMODE_16BIT:
1750 {
1751 uint16_t uSel;
1752 rcStrict = iemMemStackPopU16Ex(pIemCpu, &uSel, &TmpRsp);
1753 if (rcStrict == VINF_SUCCESS)
1754 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
1755 break;
1756 }
1757
1758 case IEMMODE_32BIT:
1759 {
1760 uint32_t u32Value;
1761 rcStrict = iemMemStackPopU32Ex(pIemCpu, &u32Value, &TmpRsp);
1762 if (rcStrict == VINF_SUCCESS)
1763 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
1764 break;
1765 }
1766
1767 case IEMMODE_64BIT:
1768 {
1769 uint64_t u64Value;
1770 rcStrict = iemMemStackPopU64Ex(pIemCpu, &u64Value, &TmpRsp);
1771 if (rcStrict == VINF_SUCCESS)
1772 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
1773 break;
1774 }
1775 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1776 }
1777
1778 /*
1779 * Commit the stack on success.
1780 */
1781 if (rcStrict == VINF_SUCCESS)
1782 {
1783 pCtx->rsp = TmpRsp.u;
1784 if (iSegReg == X86_SREG_SS)
1785 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
1786 }
1787 return rcStrict;
1788}
1789
1790
1791/**
1792 * Implements lgs, lfs, les, lds & lss.
1793 */
1794IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg,
1795 uint16_t, uSel,
1796 uint64_t, offSeg,
1797 uint8_t, iSegReg,
1798 uint8_t, iGReg,
1799 IEMMODE, enmEffOpSize)
1800{
1801 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1802 VBOXSTRICTRC rcStrict;
1803
1804 /*
1805 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
1806 */
1807 /** @todo verify and test that mov, pop and lXs works the segment
1808 * register loading in the exact same way. */
1809 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
1810 if (rcStrict == VINF_SUCCESS)
1811 {
1812 switch (enmEffOpSize)
1813 {
1814 case IEMMODE_16BIT:
1815 *(uint16_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
1816 break;
1817 case IEMMODE_32BIT:
1818 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
1819 break;
1820 case IEMMODE_64BIT:
1821 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = offSeg;
1822 break;
1823 IEM_NOT_REACHED_DEFAULT_CASE_RET();
1824 }
1825 }
1826
1827 return rcStrict;
1828}
1829
1830
1831/**
1832 * Implements lgdt.
1833 *
1834 * @param iEffSeg The segment of the new ldtr contents
1835 * @param GCPtrEffSrc The address of the new ldtr contents.
1836 * @param enmEffOpSize The effective operand size.
1837 */
1838IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
1839{
1840 if (pIemCpu->uCpl != 0)
1841 return iemRaiseGeneralProtectionFault0(pIemCpu);
1842 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
1843
1844 /*
1845 * Fetch the limit and base address.
1846 */
1847 uint16_t cbLimit;
1848 RTGCPTR GCPtrBase;
1849 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pIemCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
1850 if (rcStrict == VINF_SUCCESS)
1851 {
1852 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
1853 rcStrict = CPUMSetGuestGDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit);
1854 else
1855 {
1856 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1857 pCtx->gdtr.cbGdt = cbLimit;
1858 pCtx->gdtr.pGdt = GCPtrBase;
1859 }
1860 if (rcStrict == VINF_SUCCESS)
1861 iemRegAddToRip(pIemCpu, cbInstr);
1862 }
1863 return rcStrict;
1864}
1865
1866
1867/**
1868 * Implements lidt.
1869 *
1870 * @param iEffSeg The segment of the new ldtr contents
1871 * @param GCPtrEffSrc The address of the new ldtr contents.
1872 * @param enmEffOpSize The effective operand size.
1873 */
1874IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
1875{
1876 if (pIemCpu->uCpl != 0)
1877 return iemRaiseGeneralProtectionFault0(pIemCpu);
1878 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
1879
1880 /*
1881 * Fetch the limit and base address.
1882 */
1883 uint16_t cbLimit;
1884 RTGCPTR GCPtrBase;
1885 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pIemCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
1886 if (rcStrict == VINF_SUCCESS)
1887 {
1888 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
1889 rcStrict = CPUMSetGuestIDTR(IEMCPU_TO_VMCPU(pIemCpu), GCPtrBase, cbLimit);
1890 else
1891 {
1892 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1893 pCtx->idtr.cbIdt = cbLimit;
1894 pCtx->idtr.pIdt = GCPtrBase;
1895 }
1896 if (rcStrict == VINF_SUCCESS)
1897 iemRegAddToRip(pIemCpu, cbInstr);
1898 }
1899 return rcStrict;
1900}
1901
1902
1903/**
1904 * Implements lldt.
1905 *
1906 * @param uNewLdt The new LDT selector value.
1907 */
1908IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
1909{
1910 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
1911
1912 /*
1913 * Check preconditions.
1914 */
1915 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
1916 {
1917 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
1918 return iemRaiseUndefinedOpcode(pIemCpu);
1919 }
1920 if (pIemCpu->uCpl != 0)
1921 {
1922 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pIemCpu->uCpl));
1923 return iemRaiseGeneralProtectionFault0(pIemCpu);
1924 }
1925 if (uNewLdt & X86_SEL_LDT)
1926 {
1927 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
1928 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewLdt);
1929 }
1930
1931 /*
1932 * Now, loading a NULL selector is easy.
1933 */
1934 if ((uNewLdt & X86_SEL_MASK) == 0)
1935 {
1936 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
1937 /** @todo check if the actual value is loaded or if it's always 0. */
1938 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
1939 CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), 0);
1940 else
1941 pCtx->ldtr = 0;
1942 pCtx->ldtrHid.Attr.u = 0;
1943 pCtx->ldtrHid.u64Base = 0;
1944 pCtx->ldtrHid.u32Limit = 0;
1945
1946 iemRegAddToRip(pIemCpu, cbInstr);
1947 return VINF_SUCCESS;
1948 }
1949
1950 /*
1951 * Read the descriptor.
1952 */
1953 IEMSELDESC Desc;
1954 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uNewLdt);
1955 if (rcStrict != VINF_SUCCESS)
1956 return rcStrict;
1957
1958 /* Check GPs first. */
1959 if (Desc.Legacy.Gen.u1DescType)
1960 {
1961 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
1962 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK);
1963 }
1964 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1965 {
1966 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
1967 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK);
1968 }
1969 uint64_t u64Base;
1970 if (!IEM_IS_LONG_MODE(pIemCpu))
1971 u64Base = X86DESC_BASE(Desc.Legacy);
1972 else
1973 {
1974 if (Desc.Long.Gen.u5Zeros)
1975 {
1976 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
1977 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK);
1978 }
1979
1980 u64Base = X86DESC64_BASE(Desc.Long);
1981 if (!IEM_IS_CANONICAL(u64Base))
1982 {
1983 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
1984 return iemRaiseGeneralProtectionFault(pIemCpu, uNewLdt & X86_SEL_MASK);
1985 }
1986 }
1987
1988 /* NP */
1989 if (!Desc.Legacy.Gen.u1Present)
1990 {
1991 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
1992 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewLdt);
1993 }
1994
1995 /*
1996 * It checks out alright, update the registers.
1997 */
1998/** @todo check if the actual value is loaded or if the RPL is dropped */
1999 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2000 CPUMSetGuestLDTR(IEMCPU_TO_VMCPU(pIemCpu), uNewLdt & X86_SEL_MASK);
2001 else
2002 pCtx->ldtr = uNewLdt & X86_SEL_MASK;
2003 pCtx->ldtrHid.Attr.u = X86DESC_GET_HID_ATTR(Desc.Legacy);
2004 pCtx->ldtrHid.u32Limit = X86DESC_LIMIT(Desc.Legacy);
2005 pCtx->ldtrHid.u64Base = u64Base;
2006
2007 iemRegAddToRip(pIemCpu, cbInstr);
2008 return VINF_SUCCESS;
2009}
2010
2011
2012/**
2013 * Implements lldt.
2014 *
2015 * @param uNewLdt The new LDT selector value.
2016 */
2017IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
2018{
2019 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2020
2021 /*
2022 * Check preconditions.
2023 */
2024 if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
2025 {
2026 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
2027 return iemRaiseUndefinedOpcode(pIemCpu);
2028 }
2029 if (pIemCpu->uCpl != 0)
2030 {
2031 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pIemCpu->uCpl));
2032 return iemRaiseGeneralProtectionFault0(pIemCpu);
2033 }
2034 if (uNewTr & X86_SEL_LDT)
2035 {
2036 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
2037 return iemRaiseGeneralProtectionFaultBySelector(pIemCpu, uNewTr);
2038 }
2039 if ((uNewTr & X86_SEL_MASK) == 0)
2040 {
2041 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
2042 return iemRaiseGeneralProtectionFault0(pIemCpu);
2043 }
2044
2045 /*
2046 * Read the descriptor.
2047 */
2048 IEMSELDESC Desc;
2049 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pIemCpu, &Desc, uNewTr);
2050 if (rcStrict != VINF_SUCCESS)
2051 return rcStrict;
2052
2053 /* Check GPs first. */
2054 if (Desc.Legacy.Gen.u1DescType)
2055 {
2056 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
2057 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK);
2058 }
2059 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
2060 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
2061 || IEM_IS_LONG_MODE(pIemCpu)) )
2062 {
2063 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
2064 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK);
2065 }
2066 uint64_t u64Base;
2067 if (!IEM_IS_LONG_MODE(pIemCpu))
2068 u64Base = X86DESC_BASE(Desc.Legacy);
2069 else
2070 {
2071 if (Desc.Long.Gen.u5Zeros)
2072 {
2073 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
2074 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK);
2075 }
2076
2077 u64Base = X86DESC64_BASE(Desc.Long);
2078 if (!IEM_IS_CANONICAL(u64Base))
2079 {
2080 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
2081 return iemRaiseGeneralProtectionFault(pIemCpu, uNewTr & X86_SEL_MASK);
2082 }
2083 }
2084
2085 /* NP */
2086 if (!Desc.Legacy.Gen.u1Present)
2087 {
2088 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
2089 return iemRaiseSelectorNotPresentBySelector(pIemCpu, uNewTr);
2090 }
2091
2092 /*
2093 * Set it busy.
2094 * Note! Intel says this should lock down the whole descriptor, but we'll
2095 * restrict our selves to 32-bit for now due to lack of inline
2096 * assembly and such.
2097 */
2098 void *pvDesc;
2099 rcStrict = iemMemMap(pIemCpu, &pvDesc, 8, UINT8_MAX, pCtx->gdtr.pGdt, IEM_ACCESS_DATA_RW);
2100 if (rcStrict != VINF_SUCCESS)
2101 return rcStrict;
2102 switch ((uintptr_t)pvDesc & 3)
2103 {
2104 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
2105 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
2106 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 16); break;
2107 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 8); break;
2108 }
2109 rcStrict = iemMemMap(pIemCpu, &pvDesc, 8, UINT8_MAX, pCtx->gdtr.pGdt, IEM_ACCESS_DATA_RW);
2110 if (rcStrict != VINF_SUCCESS)
2111 return rcStrict;
2112 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
2113
2114 /*
2115 * It checks out alright, update the registers.
2116 */
2117/** @todo check if the actual value is loaded or if the RPL is dropped */
2118 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2119 CPUMSetGuestTR(IEMCPU_TO_VMCPU(pIemCpu), uNewTr & X86_SEL_MASK);
2120 else
2121 pCtx->tr = uNewTr & X86_SEL_MASK;
2122 pCtx->trHid.Attr.u = X86DESC_GET_HID_ATTR(Desc.Legacy);
2123 pCtx->trHid.u32Limit = X86DESC_LIMIT(Desc.Legacy);
2124 pCtx->trHid.u64Base = u64Base;
2125
2126 iemRegAddToRip(pIemCpu, cbInstr);
2127 return VINF_SUCCESS;
2128}
2129
2130
2131/**
2132 * Implements mov GReg,CRx.
2133 *
2134 * @param iGReg The general register to store the CRx value in.
2135 * @param iCrReg The CRx register to read (valid).
2136 */
2137IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
2138{
2139 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2140 if (pIemCpu->uCpl != 0)
2141 return iemRaiseGeneralProtectionFault0(pIemCpu);
2142 Assert(!pCtx->eflags.Bits.u1VM);
2143
2144 /* read it */
2145 uint64_t crX;
2146 switch (iCrReg)
2147 {
2148 case 0: crX = pCtx->cr0; break;
2149 case 2: crX = pCtx->cr2; break;
2150 case 3: crX = pCtx->cr3; break;
2151 case 4: crX = pCtx->cr4; break;
2152 case 8:
2153 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2154 AssertFailedReturn(VERR_NOT_IMPLEMENTED); /** @todo implement CR8 reading and writing. */
2155 else
2156 crX = 0xff;
2157 break;
2158 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
2159 }
2160
2161 /* store it */
2162 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2163 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = crX;
2164 else
2165 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = (uint32_t)crX;
2166
2167 iemRegAddToRip(pIemCpu, cbInstr);
2168 return VINF_SUCCESS;
2169}
2170
2171
2172/**
2173 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
2174 *
2175 * @param iCrReg The CRx register to write (valid).
2176 * @param uNewCrX The new value.
2177 */
2178IEM_CIMPL_DEF_2(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX)
2179{
2180 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2181 PVMCPU pVCpu = IEMCPU_TO_VMCPU(pIemCpu);
2182 VBOXSTRICTRC rcStrict;
2183 int rc;
2184
2185 /*
2186 * Try store it.
2187 * Unfortunately, CPUM only does a tiny bit of the work.
2188 */
2189 switch (iCrReg)
2190 {
2191 case 0:
2192 {
2193 /*
2194 * Perform checks.
2195 */
2196 uint64_t const uOldCrX = pCtx->cr0;
2197 uNewCrX |= X86_CR0_ET; /* hardcoded */
2198
2199 /* Check for reserved bits. */
2200 uint32_t const fValid = X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
2201 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
2202 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG;
2203 if (uNewCrX & ~(uint64_t)fValid)
2204 {
2205 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
2206 return iemRaiseGeneralProtectionFault0(pIemCpu);
2207 }
2208
2209 /* Check for invalid combinations. */
2210 if ( (uNewCrX & X86_CR0_PG)
2211 && !(uNewCrX & X86_CR0_PE) )
2212 {
2213 Log(("Trying to set CR0.PG without CR0.PE\n"));
2214 return iemRaiseGeneralProtectionFault0(pIemCpu);
2215 }
2216
2217 if ( !(uNewCrX & X86_CR0_CD)
2218 && (uNewCrX & X86_CR0_NW) )
2219 {
2220 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
2221 return iemRaiseGeneralProtectionFault0(pIemCpu);
2222 }
2223
2224 /* Long mode consistency checks. */
2225 if ( (uNewCrX & X86_CR0_PG)
2226 && !(uOldCrX & X86_CR0_PG)
2227 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
2228 {
2229 if (!(pCtx->cr4 & X86_CR4_PAE))
2230 {
2231 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
2232 return iemRaiseGeneralProtectionFault0(pIemCpu);
2233 }
2234 if (pCtx->csHid.Attr.n.u1Long)
2235 {
2236 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
2237 return iemRaiseGeneralProtectionFault0(pIemCpu);
2238 }
2239 }
2240
2241 /** @todo check reserved PDPTR bits as AMD states. */
2242
2243 /*
2244 * Change CR0.
2245 */
2246 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2247 {
2248 rc = CPUMSetGuestCR0(pVCpu, uNewCrX);
2249 AssertRCSuccessReturn(rc, RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_3);
2250 }
2251 else
2252 pCtx->cr0 = uNewCrX;
2253 Assert(pCtx->cr0 == uNewCrX);
2254
2255 /*
2256 * Change EFER.LMA if entering or leaving long mode.
2257 */
2258 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
2259 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
2260 {
2261 uint64_t NewEFER = pCtx->msrEFER;
2262 if (uNewCrX & X86_CR0_PG)
2263 NewEFER |= MSR_K6_EFER_LME;
2264 else
2265 NewEFER &= ~MSR_K6_EFER_LME;
2266
2267 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2268 CPUMSetGuestEFER(pVCpu, NewEFER);
2269 else
2270 pCtx->msrEFER = NewEFER;
2271 Assert(pCtx->msrEFER == NewEFER);
2272 }
2273
2274 /*
2275 * Inform PGM.
2276 */
2277 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2278 {
2279 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
2280 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
2281 {
2282 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
2283 AssertRCReturn(rc, rc);
2284 /* ignore informational status codes */
2285 }
2286 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2287 /** @todo Status code management. */
2288 }
2289 else
2290 rcStrict = VINF_SUCCESS;
2291 break;
2292 }
2293
2294 /*
2295 * CR2 can be changed without any restrictions.
2296 */
2297 case 2:
2298 pCtx->cr2 = uNewCrX;
2299 rcStrict = VINF_SUCCESS;
2300 break;
2301
2302 /*
2303 * CR3 is relatively simple, although AMD and Intel have different
2304 * accounts of how setting reserved bits are handled. We take intel's
2305 * word for the lower bits and AMD's for the high bits (63:52).
2306 */
2307 /** @todo Testcase: Setting reserved bits in CR3, especially before
2308 * enabling paging. */
2309 case 3:
2310 {
2311 /* check / mask the value. */
2312 if (uNewCrX & UINT64_C(0xfff0000000000000))
2313 {
2314 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
2315 return iemRaiseGeneralProtectionFault0(pIemCpu);
2316 }
2317
2318 uint64_t fValid;
2319 if ( (pCtx->cr4 & X86_CR4_PAE)
2320 && (pCtx->msrEFER & MSR_K6_EFER_LME))
2321 fValid = UINT64_C(0x000ffffffffff014);
2322 else if (pCtx->cr4 & X86_CR4_PAE)
2323 fValid = UINT64_C(0xfffffff4);
2324 else
2325 fValid = UINT64_C(0xfffff014);
2326 if (uNewCrX & ~fValid)
2327 {
2328 Log(("Automatically clearing reserved bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
2329 uNewCrX, uNewCrX & ~fValid));
2330 uNewCrX &= fValid;
2331 }
2332
2333 /** @todo If we're in PAE mode we should check the PDPTRs for
2334 * invalid bits. */
2335
2336 /* Make the change. */
2337 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2338 {
2339 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
2340 AssertRCSuccessReturn(rc, rc);
2341 }
2342 else
2343 pCtx->cr3 = uNewCrX;
2344
2345 /* Inform PGM. */
2346 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2347 {
2348 if (pCtx->cr0 & X86_CR0_PG)
2349 {
2350 rc = PGMFlushTLB(pVCpu, pCtx->cr3, !(pCtx->cr3 & X86_CR4_PGE));
2351 AssertRCReturn(rc, rc);
2352 /* ignore informational status codes */
2353 /** @todo status code management */
2354 }
2355 }
2356 rcStrict = VINF_SUCCESS;
2357 break;
2358 }
2359
2360 /*
2361 * CR4 is a bit more tedious as there are bits which cannot be cleared
2362 * under some circumstances and such.
2363 */
2364 case 4:
2365 {
2366 uint64_t const uOldCrX = pCtx->cr0;
2367
2368 /* reserved bits */
2369 uint32_t fValid = X86_CR4_VME | X86_CR4_PVI
2370 | X86_CR4_TSD | X86_CR4_DE
2371 | X86_CR4_PSE | X86_CR4_PAE
2372 | X86_CR4_MCE | X86_CR4_PGE
2373 | X86_CR4_PCE | X86_CR4_OSFSXR
2374 | X86_CR4_OSXMMEEXCPT;
2375 //if (xxx)
2376 // fValid |= X86_CR4_VMXE;
2377 //if (xxx)
2378 // fValid |= X86_CR4_OSXSAVE;
2379 if (uNewCrX & ~(uint64_t)fValid)
2380 {
2381 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
2382 return iemRaiseGeneralProtectionFault0(pIemCpu);
2383 }
2384
2385 /* long mode checks. */
2386 if ( (uOldCrX & X86_CR4_PAE)
2387 && !(uNewCrX & X86_CR4_PAE)
2388 && (pCtx->msrEFER & MSR_K6_EFER_LMA) )
2389 {
2390 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
2391 return iemRaiseGeneralProtectionFault0(pIemCpu);
2392 }
2393
2394
2395 /*
2396 * Change it.
2397 */
2398 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2399 {
2400 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
2401 AssertRCSuccessReturn(rc, rc);
2402 }
2403 else
2404 pCtx->cr4 = uNewCrX;
2405 Assert(pCtx->cr4 == uNewCrX);
2406
2407 /*
2408 * Notify SELM and PGM.
2409 */
2410 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2411 {
2412 /* SELM - VME may change things wrt to the TSS shadowing. */
2413 if ((uNewCrX ^ uOldCrX) & X86_CR4_VME)
2414 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
2415
2416 /* PGM - flushing and mode. */
2417 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
2418 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
2419 {
2420 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
2421 AssertRCReturn(rc, rc);
2422 /* ignore informational status codes */
2423 }
2424 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2425 /** @todo Status code management. */
2426 }
2427 else
2428 rcStrict = VINF_SUCCESS;
2429 break;
2430 }
2431
2432 /*
2433 * CR8 maps to the APIC TPR.
2434 */
2435 case 8:
2436 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2437 AssertFailedReturn(VERR_NOT_IMPLEMENTED); /** @todo implement CR8 reading and writing. */
2438 else
2439 rcStrict = VINF_SUCCESS;
2440 break;
2441
2442 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
2443 }
2444
2445 /*
2446 * Advance the RIP on success.
2447 */
2448 /** @todo Status code management. */
2449 if (rcStrict == VINF_SUCCESS)
2450 iemRegAddToRip(pIemCpu, cbInstr);
2451 return rcStrict;
2452
2453}
2454
2455
2456/**
2457 * Implements mov CRx,GReg.
2458 *
2459 * @param iCrReg The CRx register to write (valid).
2460 * @param iGReg The general register to load the DRx value from.
2461 */
2462IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
2463{
2464 if (pIemCpu->uCpl != 0)
2465 return iemRaiseGeneralProtectionFault0(pIemCpu);
2466 Assert(!pIemCpu->CTX_SUFF(pCtx)->eflags.Bits.u1VM);
2467
2468 /*
2469 * Read the new value from the source register and call common worker.
2470 */
2471 uint64_t uNewCrX;
2472 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2473 uNewCrX = iemGRegFetchU64(pIemCpu, iGReg);
2474 else
2475 uNewCrX = iemGRegFetchU32(pIemCpu, iGReg);
2476 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, iCrReg, uNewCrX);
2477}
2478
2479
2480/**
2481 * Implements 'LMSW r/m16'
2482 *
2483 * @param u16NewMsw The new value.
2484 */
2485IEM_CIMPL_DEF_1(iemCImpl_lmsw, uint16_t, u16NewMsw)
2486{
2487 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2488
2489 if (pIemCpu->uCpl != 0)
2490 return iemRaiseGeneralProtectionFault0(pIemCpu);
2491 Assert(!pCtx->eflags.Bits.u1VM);
2492
2493 /*
2494 * Compose the new CR0 value and call common worker.
2495 */
2496 uint64_t uNewCr0 = pCtx->cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2497 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
2498 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0);
2499}
2500
2501
2502/**
2503 * Implements 'CLTS'.
2504 */
2505IEM_CIMPL_DEF_0(iemCImpl_clts)
2506{
2507 if (pIemCpu->uCpl != 0)
2508 return iemRaiseGeneralProtectionFault0(pIemCpu);
2509
2510 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2511 uint64_t uNewCr0 = pCtx->cr0;
2512 uNewCr0 &= ~X86_CR0_TS;
2513 return IEM_CIMPL_CALL_2(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0);
2514}
2515
2516
2517/**
2518 * Implements mov GReg,DRx.
2519 *
2520 * @param iGReg The general register to store the DRx value in.
2521 * @param iDrReg The DRx register to read (0-7).
2522 */
2523IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
2524{
2525 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2526
2527 /*
2528 * Check preconditions.
2529 */
2530
2531 /* Raise GPs. */
2532 if (pIemCpu->uCpl != 0)
2533 return iemRaiseGeneralProtectionFault0(pIemCpu);
2534 Assert(!pCtx->eflags.Bits.u1VM);
2535
2536 if ( (iDrReg == 4 || iDrReg == 5)
2537 && (pCtx->cr4 & X86_CR4_DE) )
2538 {
2539 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
2540 return iemRaiseGeneralProtectionFault0(pIemCpu);
2541 }
2542
2543 /* Raise #DB if general access detect is enabled. */
2544 if (pCtx->dr[7] & X86_DR7_GD)
2545 {
2546 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
2547 return iemRaiseDebugException(pIemCpu);
2548 }
2549
2550 /*
2551 * Read the debug register and store it in the specified general register.
2552 */
2553 uint64_t drX;
2554 switch (iDrReg)
2555 {
2556 case 0: drX = pCtx->dr[0]; break;
2557 case 1: drX = pCtx->dr[1]; break;
2558 case 2: drX = pCtx->dr[2]; break;
2559 case 3: drX = pCtx->dr[3]; break;
2560 case 6:
2561 case 4:
2562 drX = pCtx->dr[6];
2563 drX &= ~RT_BIT_32(12);
2564 drX |= UINT32_C(0xffff0ff0);
2565 break;
2566 case 7:
2567 case 5:
2568 drX = pCtx->dr[7];
2569 drX &= ~(RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(14) | RT_BIT_32(15));
2570 drX |= RT_BIT_32(10);
2571 break;
2572 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
2573 }
2574
2575 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2576 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = drX;
2577 else
2578 *(uint64_t *)iemGRegRef(pIemCpu, iGReg) = (uint32_t)drX;
2579
2580 iemRegAddToRip(pIemCpu, cbInstr);
2581 return VINF_SUCCESS;
2582}
2583
2584
2585/**
2586 * Implements mov DRx,GReg.
2587 *
2588 * @param iDrReg The DRx register to write (valid).
2589 * @param iGReg The general register to load the DRx value from.
2590 */
2591IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
2592{
2593 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2594
2595 /*
2596 * Check preconditions.
2597 */
2598 if (pIemCpu->uCpl != 0)
2599 return iemRaiseGeneralProtectionFault0(pIemCpu);
2600 Assert(!pCtx->eflags.Bits.u1VM);
2601
2602 if ( (iDrReg == 4 || iDrReg == 5)
2603 && (pCtx->cr4 & X86_CR4_DE) )
2604 {
2605 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
2606 return iemRaiseGeneralProtectionFault0(pIemCpu);
2607 }
2608
2609 /* Raise #DB if general access detect is enabled. */
2610 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
2611 * \#GP? */
2612 if (pCtx->dr[7] & X86_DR7_GD)
2613 {
2614 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
2615 return iemRaiseDebugException(pIemCpu);
2616 }
2617
2618 /*
2619 * Read the new value from the source register.
2620 */
2621 uint64_t uNewDrX;
2622 if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
2623 uNewDrX = iemGRegFetchU64(pIemCpu, iGReg);
2624 else
2625 uNewDrX = iemGRegFetchU32(pIemCpu, iGReg);
2626
2627 /*
2628 * Adjust it.
2629 */
2630 switch (iDrReg)
2631 {
2632 case 0:
2633 case 1:
2634 case 2:
2635 case 3:
2636 /* nothing to adjust */
2637 break;
2638
2639 case 6:
2640 case 4:
2641 if (uNewDrX & UINT64_C(0xffffffff00000000))
2642 {
2643 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
2644 return iemRaiseGeneralProtectionFault0(pIemCpu);
2645 }
2646 uNewDrX &= ~RT_BIT_32(12);
2647 uNewDrX |= UINT32_C(0xffff0ff0);
2648 break;
2649
2650 case 7:
2651 case 5:
2652 if (uNewDrX & UINT64_C(0xffffffff00000000))
2653 {
2654 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
2655 return iemRaiseGeneralProtectionFault0(pIemCpu);
2656 }
2657 uNewDrX &= ~(RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT_32(14) | RT_BIT_32(15));
2658 uNewDrX |= RT_BIT_32(10);
2659 break;
2660
2661 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2662 }
2663
2664 /*
2665 * Do the actual setting.
2666 */
2667 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2668 {
2669 int rc = CPUMSetGuestDRx(IEMCPU_TO_VMCPU(pIemCpu), iDrReg, uNewDrX);
2670 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_INTERNAL_ERROR : rc);
2671 }
2672 else
2673 pCtx->dr[iDrReg] = uNewDrX;
2674
2675 iemRegAddToRip(pIemCpu, cbInstr);
2676 return VINF_SUCCESS;
2677}
2678
2679
2680/**
2681 * Implements RDTSC.
2682 */
2683IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
2684{
2685 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2686
2687 /*
2688 * Check preconditions.
2689 */
2690 if (!IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(X86_CPUID_FEATURE_EDX_TSC))
2691 return iemRaiseUndefinedOpcode(pIemCpu);
2692
2693 if ( (pCtx->cr4 & X86_CR4_TSD)
2694 && pIemCpu->uCpl != 0)
2695 {
2696 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pIemCpu->uCpl));
2697 return iemRaiseGeneralProtectionFault0(pIemCpu);
2698 }
2699
2700 /*
2701 * Do the job.
2702 */
2703 uint64_t uTicks = TMCpuTickGet(IEMCPU_TO_VMCPU(pIemCpu));
2704 pCtx->rax = (uint32_t)uTicks;
2705 pCtx->rdx = uTicks >> 32;
2706#ifdef IEM_VERIFICATION_MODE
2707 pIemCpu->fIgnoreRaxRdx = true;
2708#endif
2709
2710 iemRegAddToRip(pIemCpu, cbInstr);
2711 return VINF_SUCCESS;
2712}
2713
2714
2715/**
2716 * Implements 'IN eAX, port'.
2717 *
2718 * @param u16Port The source port.
2719 * @param cbReg The register size.
2720 */
2721IEM_CIMPL_DEF_2(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg)
2722{
2723 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2724
2725 /*
2726 * CPL check
2727 */
2728 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pIemCpu, pCtx, u16Port, cbReg);
2729 if (rcStrict != VINF_SUCCESS)
2730 return rcStrict;
2731
2732 /*
2733 * Perform the I/O.
2734 */
2735 uint32_t u32Value;
2736 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2737 rcStrict = IOMIOPortRead(IEMCPU_TO_VM(pIemCpu), u16Port, &u32Value, cbReg);
2738 else
2739 rcStrict = iemVerifyFakeIOPortRead(pIemCpu, u16Port, &u32Value, cbReg);
2740 if (IOM_SUCCESS(rcStrict))
2741 {
2742 switch (cbReg)
2743 {
2744 case 1: pCtx->al = (uint8_t)u32Value; break;
2745 case 2: pCtx->ax = (uint16_t)u32Value; break;
2746 case 4: pCtx->rax = u32Value; break;
2747 default: AssertFailedReturn(VERR_INTERNAL_ERROR_3);
2748 }
2749 iemRegAddToRip(pIemCpu, cbInstr);
2750 pIemCpu->cPotentialExits++;
2751 }
2752 /** @todo massage rcStrict. */
2753 return rcStrict;
2754}
2755
2756
2757/**
2758 * Implements 'IN eAX, DX'.
2759 *
2760 * @param cbReg The register size.
2761 */
2762IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
2763{
2764 return IEM_CIMPL_CALL_2(iemCImpl_in, pIemCpu->CTX_SUFF(pCtx)->dx, cbReg);
2765}
2766
2767
2768/**
2769 * Implements 'OUT port, eAX'.
2770 *
2771 * @param u16Port The destination port.
2772 * @param cbReg The register size.
2773 */
2774IEM_CIMPL_DEF_2(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg)
2775{
2776 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2777
2778 /*
2779 * CPL check
2780 */
2781 if ( (pCtx->cr0 & X86_CR0_PE)
2782 && ( pIemCpu->uCpl > pCtx->eflags.Bits.u2IOPL
2783 || pCtx->eflags.Bits.u1VM) )
2784 {
2785 /** @todo I/O port permission bitmap check */
2786 AssertFailedReturn(VERR_NOT_IMPLEMENTED);
2787 }
2788
2789 /*
2790 * Perform the I/O.
2791 */
2792 uint32_t u32Value;
2793 switch (cbReg)
2794 {
2795 case 1: u32Value = pCtx->al; break;
2796 case 2: u32Value = pCtx->ax; break;
2797 case 4: u32Value = pCtx->eax; break;
2798 default: AssertFailedReturn(VERR_INTERNAL_ERROR_3);
2799 }
2800 VBOXSTRICTRC rc;
2801 if (!IEM_VERIFICATION_ENABLED(pIemCpu))
2802 rc = IOMIOPortWrite(IEMCPU_TO_VM(pIemCpu), u16Port, u32Value, cbReg);
2803 else
2804 rc = iemVerifyFakeIOPortWrite(pIemCpu, u16Port, u32Value, cbReg);
2805 if (IOM_SUCCESS(rc))
2806 {
2807 iemRegAddToRip(pIemCpu, cbInstr);
2808 pIemCpu->cPotentialExits++;
2809 /** @todo massage rc. */
2810 }
2811 return rc;
2812}
2813
2814
2815/**
2816 * Implements 'OUT DX, eAX'.
2817 *
2818 * @param cbReg The register size.
2819 */
2820IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
2821{
2822 return IEM_CIMPL_CALL_2(iemCImpl_out, pIemCpu->CTX_SUFF(pCtx)->dx, cbReg);
2823}
2824
2825
2826/**
2827 * Implements 'CLI'.
2828 */
2829IEM_CIMPL_DEF_0(iemCImpl_cli)
2830{
2831 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2832
2833 if (pCtx->cr0 & X86_CR0_PE)
2834 {
2835 uint8_t const uIopl = pCtx->eflags.Bits.u2IOPL;
2836 if (!pCtx->eflags.Bits.u1VM)
2837 {
2838 if (pIemCpu->uCpl <= uIopl)
2839 pCtx->eflags.Bits.u1IF = 0;
2840 else if ( pIemCpu->uCpl == 3
2841 && (pCtx->cr4 & X86_CR4_PVI) )
2842 pCtx->eflags.Bits.u1VIF = 0;
2843 else
2844 return iemRaiseGeneralProtectionFault0(pIemCpu);
2845 }
2846 /* V8086 */
2847 else if (uIopl == 3)
2848 pCtx->eflags.Bits.u1IF = 0;
2849 else if ( uIopl < 3
2850 && (pCtx->cr4 & X86_CR4_VME) )
2851 pCtx->eflags.Bits.u1VIF = 0;
2852 else
2853 return iemRaiseGeneralProtectionFault0(pIemCpu);
2854 }
2855 /* real mode */
2856 else
2857 pCtx->eflags.Bits.u1IF = 0;
2858 iemRegAddToRip(pIemCpu, cbInstr);
2859 return VINF_SUCCESS;
2860}
2861
2862
2863/**
2864 * Implements 'STI'.
2865 */
2866IEM_CIMPL_DEF_0(iemCImpl_sti)
2867{
2868 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2869
2870 if (pCtx->cr0 & X86_CR0_PE)
2871 {
2872 uint8_t const uIopl = pCtx->eflags.Bits.u2IOPL;
2873 if (!pCtx->eflags.Bits.u1VM)
2874 {
2875 if (pIemCpu->uCpl <= uIopl)
2876 pCtx->eflags.Bits.u1IF = 1;
2877 else if ( pIemCpu->uCpl == 3
2878 && (pCtx->cr4 & X86_CR4_PVI)
2879 && !pCtx->eflags.Bits.u1VIP )
2880 pCtx->eflags.Bits.u1VIF = 1;
2881 else
2882 return iemRaiseGeneralProtectionFault0(pIemCpu);
2883 }
2884 /* V8086 */
2885 else if (uIopl == 3)
2886 pCtx->eflags.Bits.u1IF = 1;
2887 else if ( uIopl < 3
2888 && (pCtx->cr4 & X86_CR4_VME)
2889 && !pCtx->eflags.Bits.u1VIP )
2890 pCtx->eflags.Bits.u1VIF = 1;
2891 else
2892 return iemRaiseGeneralProtectionFault0(pIemCpu);
2893 }
2894 /* real mode */
2895 else
2896 pCtx->eflags.Bits.u1IF = 1;
2897
2898 iemRegAddToRip(pIemCpu, cbInstr);
2899 EMSetInhibitInterruptsPC(IEMCPU_TO_VMCPU(pIemCpu), pCtx->rip);
2900 return VINF_SUCCESS;
2901}
2902
2903
2904/**
2905 * Implements 'HLT'.
2906 */
2907IEM_CIMPL_DEF_0(iemCImpl_hlt)
2908{
2909 if (pIemCpu->uCpl != 0)
2910 return iemRaiseGeneralProtectionFault0(pIemCpu);
2911 iemRegAddToRip(pIemCpu, cbInstr);
2912 return VINF_EM_HALT;
2913}
2914
2915
2916/**
2917 * Implements 'CPUID'.
2918 */
2919IEM_CIMPL_DEF_0(iemCImpl_cpuid)
2920{
2921 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2922
2923 CPUMGetGuestCpuId(IEMCPU_TO_VMCPU(pIemCpu), pCtx->eax, &pCtx->eax, &pCtx->ebx, &pCtx->ecx, &pCtx->edx);
2924 pCtx->rax &= UINT32_C(0xffffffff);
2925 pCtx->rbx &= UINT32_C(0xffffffff);
2926 pCtx->rcx &= UINT32_C(0xffffffff);
2927 pCtx->rdx &= UINT32_C(0xffffffff);
2928
2929 iemRegAddToRip(pIemCpu, cbInstr);
2930 return VINF_SUCCESS;
2931}
2932
2933
2934/**
2935 * Implements 'AAD'.
2936 *
2937 * @param enmEffOpSize The effective operand size.
2938 */
2939IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
2940{
2941 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
2942
2943 uint16_t const ax = pCtx->ax;
2944 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
2945 pCtx->ax = al;
2946 iemHlpUpdateArithEFlagsU8(pIemCpu, al,
2947 X86_EFL_SF | X86_EFL_SF | X86_EFL_PF,
2948 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
2949
2950 iemRegAddToRip(pIemCpu, cbInstr);
2951 return VINF_SUCCESS;
2952}
2953
2954
2955
2956
2957/*
2958 * Instantiate the various string operation combinations.
2959 */
2960#define OP_SIZE 8
2961#define ADDR_SIZE 16
2962#include "IEMAllCImplStrInstr.cpp.h"
2963#define OP_SIZE 8
2964#define ADDR_SIZE 32
2965#include "IEMAllCImplStrInstr.cpp.h"
2966#define OP_SIZE 8
2967#define ADDR_SIZE 64
2968#include "IEMAllCImplStrInstr.cpp.h"
2969
2970#define OP_SIZE 16
2971#define ADDR_SIZE 16
2972#include "IEMAllCImplStrInstr.cpp.h"
2973#define OP_SIZE 16
2974#define ADDR_SIZE 32
2975#include "IEMAllCImplStrInstr.cpp.h"
2976#define OP_SIZE 16
2977#define ADDR_SIZE 64
2978#include "IEMAllCImplStrInstr.cpp.h"
2979
2980#define OP_SIZE 32
2981#define ADDR_SIZE 16
2982#include "IEMAllCImplStrInstr.cpp.h"
2983#define OP_SIZE 32
2984#define ADDR_SIZE 32
2985#include "IEMAllCImplStrInstr.cpp.h"
2986#define OP_SIZE 32
2987#define ADDR_SIZE 64
2988#include "IEMAllCImplStrInstr.cpp.h"
2989
2990#define OP_SIZE 64
2991#define ADDR_SIZE 32
2992#include "IEMAllCImplStrInstr.cpp.h"
2993#define OP_SIZE 64
2994#define ADDR_SIZE 64
2995#include "IEMAllCImplStrInstr.cpp.h"
2996
2997
2998/**
2999 * Implements 'FINIT' and 'FNINIT'.
3000 *
3001 * @param fCheckXcpts Whether to check for umasked pending exceptions or
3002 * not.
3003 */
3004IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
3005{
3006 PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
3007
3008 if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
3009 return iemRaiseDeviceNotAvailable(pIemCpu);
3010 /** @todo trigger pending exceptions:
3011 if (fCheckXcpts && TODO )
3012 return iemRaiseMathFault(pIemCpu);
3013 */
3014
3015 if (iemFRegIsFxSaveFormat(pIemCpu))
3016 {
3017 pCtx->fpu.FCW = 0x37f;
3018 pCtx->fpu.FSW = 0;
3019 pCtx->fpu.FTW = 0x00; /* 0 - empty. */
3020 pCtx->fpu.FPUDP = 0;
3021 pCtx->fpu.DS = 0; //??
3022 pCtx->fpu.FPUIP = 0;
3023 pCtx->fpu.CS = 0; //??
3024 pCtx->fpu.FOP = 0;
3025 }
3026 else
3027 {
3028 PX86FPUSTATE pFpu = (PX86FPUSTATE)&pCtx->fpu;
3029 pFpu->FCW = 0x37f;
3030 pFpu->FSW = 0;
3031 pFpu->FTW = 0xffff; /* 11 - empty */
3032 pFpu->FPUOO = 0; //??
3033 pFpu->FPUOS = 0; //??
3034 pFpu->FPUIP = 0;
3035 pFpu->CS = 0; //??
3036 pFpu->FOP = 0;
3037 }
3038
3039 iemRegAddToRip(pIemCpu, cbInstr);
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/** @} */
3045
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