VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h@ 70612

Last change on this file since 70612 was 70612, checked in by vboxsync, 7 years ago

VMM: Expose PCID, INVPCID, FSGSBASE features to guests. Implemented the relevant instructions in IEM.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 282.9 KB
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1/* $Id: IEMAllCImpl.cpp.h 70612 2018-01-17 18:12:23Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifdef VBOX_WITH_NESTED_HWVIRT
19# include "IEMAllCImplSvmInstr.cpp.h"
20#endif
21
22/** @name Misc Helpers
23 * @{
24 */
25
26
27/**
28 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
29 *
30 * @returns Strict VBox status code.
31 *
32 * @param pVCpu The cross context virtual CPU structure of the calling thread.
33 * @param pCtx The register context.
34 * @param u16Port The port number.
35 * @param cbOperand The operand size.
36 */
37static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPU pVCpu, PCCPUMCTX pCtx, uint16_t u16Port, uint8_t cbOperand)
38{
39 /* The TSS bits we're interested in are the same on 386 and AMD64. */
40 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
41 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
42 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
43 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
44
45 /*
46 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
47 */
48 Assert(!pCtx->tr.Attr.n.u1DescType);
49 if (RT_UNLIKELY( pCtx->tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
50 && pCtx->tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
51 {
52 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
53 u16Port, cbOperand, pCtx->tr.Attr.n.u4Type, pCtx->tr.Attr.u));
54 return iemRaiseGeneralProtectionFault0(pVCpu);
55 }
56
57 /*
58 * Read the bitmap offset (may #PF).
59 */
60 uint16_t offBitmap;
61 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
62 pCtx->tr.u64Base + RT_OFFSETOF(X86TSS64, offIoBitmap));
63 if (rcStrict != VINF_SUCCESS)
64 {
65 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
66 return rcStrict;
67 }
68
69 /*
70 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
71 * describes the CPU actually reading two bytes regardless of whether the
72 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
73 */
74 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
75 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
76 * for instance sizeof(X86TSS32). */
77 if (offFirstBit + 1 > pCtx->tr.u32Limit) /* the limit is inclusive */
78 {
79 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
80 offFirstBit, pCtx->tr.u32Limit));
81 return iemRaiseGeneralProtectionFault0(pVCpu);
82 }
83
84 /*
85 * Read the necessary bits.
86 */
87 /** @todo Test the assertion in the intel manual that the CPU reads two
88 * bytes. The question is how this works wrt to #PF and #GP on the
89 * 2nd byte when it's not required. */
90 uint16_t bmBytes = UINT16_MAX;
91 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pCtx->tr.u64Base + offFirstBit);
92 if (rcStrict != VINF_SUCCESS)
93 {
94 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
95 return rcStrict;
96 }
97
98 /*
99 * Perform the check.
100 */
101 uint16_t fPortMask = (1 << cbOperand) - 1;
102 bmBytes >>= (u16Port & 7);
103 if (bmBytes & fPortMask)
104 {
105 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
106 u16Port, cbOperand, bmBytes, fPortMask));
107 return iemRaiseGeneralProtectionFault0(pVCpu);
108 }
109
110 return VINF_SUCCESS;
111}
112
113
114/**
115 * Checks if we are allowed to access the given I/O port, raising the
116 * appropriate exceptions if we aren't (or if the I/O bitmap is not
117 * accessible).
118 *
119 * @returns Strict VBox status code.
120 *
121 * @param pVCpu The cross context virtual CPU structure of the calling thread.
122 * @param pCtx The register context.
123 * @param u16Port The port number.
124 * @param cbOperand The operand size.
125 */
126DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPU pVCpu, PCCPUMCTX pCtx, uint16_t u16Port, uint8_t cbOperand)
127{
128 X86EFLAGS Efl;
129 Efl.u = IEMMISC_GET_EFL(pVCpu, pCtx);
130 if ( (pCtx->cr0 & X86_CR0_PE)
131 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
132 || Efl.Bits.u1VM) )
133 return iemHlpCheckPortIOPermissionBitmap(pVCpu, pCtx, u16Port, cbOperand);
134 return VINF_SUCCESS;
135}
136
137
138#if 0
139/**
140 * Calculates the parity bit.
141 *
142 * @returns true if the bit is set, false if not.
143 * @param u8Result The least significant byte of the result.
144 */
145static bool iemHlpCalcParityFlag(uint8_t u8Result)
146{
147 /*
148 * Parity is set if the number of bits in the least significant byte of
149 * the result is even.
150 */
151 uint8_t cBits;
152 cBits = u8Result & 1; /* 0 */
153 u8Result >>= 1;
154 cBits += u8Result & 1;
155 u8Result >>= 1;
156 cBits += u8Result & 1;
157 u8Result >>= 1;
158 cBits += u8Result & 1;
159 u8Result >>= 1;
160 cBits += u8Result & 1; /* 4 */
161 u8Result >>= 1;
162 cBits += u8Result & 1;
163 u8Result >>= 1;
164 cBits += u8Result & 1;
165 u8Result >>= 1;
166 cBits += u8Result & 1;
167 return !(cBits & 1);
168}
169#endif /* not used */
170
171
172/**
173 * Updates the specified flags according to a 8-bit result.
174 *
175 * @param pVCpu The cross context virtual CPU structure of the calling thread.
176 * @param u8Result The result to set the flags according to.
177 * @param fToUpdate The flags to update.
178 * @param fUndefined The flags that are specified as undefined.
179 */
180static void iemHlpUpdateArithEFlagsU8(PVMCPU pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
181{
182 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
183
184 uint32_t fEFlags = pCtx->eflags.u;
185 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
186 pCtx->eflags.u &= ~(fToUpdate | fUndefined);
187 pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
188#ifdef IEM_VERIFICATION_MODE_FULL
189 pVCpu->iem.s.fUndefinedEFlags |= fUndefined;
190#endif
191}
192
193
194/**
195 * Updates the specified flags according to a 16-bit result.
196 *
197 * @param pVCpu The cross context virtual CPU structure of the calling thread.
198 * @param u16Result The result to set the flags according to.
199 * @param fToUpdate The flags to update.
200 * @param fUndefined The flags that are specified as undefined.
201 */
202static void iemHlpUpdateArithEFlagsU16(PVMCPU pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
203{
204 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
205
206 uint32_t fEFlags = pCtx->eflags.u;
207 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
208 pCtx->eflags.u &= ~(fToUpdate | fUndefined);
209 pCtx->eflags.u |= (fToUpdate | fUndefined) & fEFlags;
210#ifdef IEM_VERIFICATION_MODE_FULL
211 pVCpu->iem.s.fUndefinedEFlags |= fUndefined;
212#endif
213}
214
215
216/**
217 * Helper used by iret.
218 *
219 * @param pVCpu The cross context virtual CPU structure of the calling thread.
220 * @param uCpl The new CPL.
221 * @param pSReg Pointer to the segment register.
222 */
223static void iemHlpAdjustSelectorForNewCpl(PVMCPU pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
224{
225#ifdef VBOX_WITH_RAW_MODE_NOT_R0
226 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
227 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSReg);
228#else
229 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
230#endif
231
232 if ( uCpl > pSReg->Attr.n.u2Dpl
233 && pSReg->Attr.n.u1DescType /* code or data, not system */
234 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
235 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
236 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
237}
238
239
240/**
241 * Indicates that we have modified the FPU state.
242 *
243 * @param pVCpu The cross context virtual CPU structure of the calling thread.
244 */
245DECLINLINE(void) iemHlpUsedFpu(PVMCPU pVCpu)
246{
247 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
248}
249
250/** @} */
251
252/** @name C Implementations
253 * @{
254 */
255
256/**
257 * Implements a 16-bit popa.
258 */
259IEM_CIMPL_DEF_0(iemCImpl_popa_16)
260{
261 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
262 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu, pCtx);
263 RTGCPTR GCPtrLast = GCPtrStart + 15;
264 VBOXSTRICTRC rcStrict;
265
266 /*
267 * The docs are a bit hard to comprehend here, but it looks like we wrap
268 * around in real mode as long as none of the individual "popa" crosses the
269 * end of the stack segment. In protected mode we check the whole access
270 * in one go. For efficiency, only do the word-by-word thing if we're in
271 * danger of wrapping around.
272 */
273 /** @todo do popa boundary / wrap-around checks. */
274 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
275 && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
276 {
277 /* word-by-word */
278 RTUINT64U TmpRsp;
279 TmpRsp.u = pCtx->rsp;
280 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->di, &TmpRsp);
281 if (rcStrict == VINF_SUCCESS)
282 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->si, &TmpRsp);
283 if (rcStrict == VINF_SUCCESS)
284 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->bp, &TmpRsp);
285 if (rcStrict == VINF_SUCCESS)
286 {
287 iemRegAddToRspEx(pVCpu, pCtx, &TmpRsp, 2); /* sp */
288 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->bx, &TmpRsp);
289 }
290 if (rcStrict == VINF_SUCCESS)
291 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->dx, &TmpRsp);
292 if (rcStrict == VINF_SUCCESS)
293 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->cx, &TmpRsp);
294 if (rcStrict == VINF_SUCCESS)
295 rcStrict = iemMemStackPopU16Ex(pVCpu, &pCtx->ax, &TmpRsp);
296 if (rcStrict == VINF_SUCCESS)
297 {
298 pCtx->rsp = TmpRsp.u;
299 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
300 }
301 }
302 else
303 {
304 uint16_t const *pa16Mem = NULL;
305 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
306 if (rcStrict == VINF_SUCCESS)
307 {
308 pCtx->di = pa16Mem[7 - X86_GREG_xDI];
309 pCtx->si = pa16Mem[7 - X86_GREG_xSI];
310 pCtx->bp = pa16Mem[7 - X86_GREG_xBP];
311 /* skip sp */
312 pCtx->bx = pa16Mem[7 - X86_GREG_xBX];
313 pCtx->dx = pa16Mem[7 - X86_GREG_xDX];
314 pCtx->cx = pa16Mem[7 - X86_GREG_xCX];
315 pCtx->ax = pa16Mem[7 - X86_GREG_xAX];
316 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
317 if (rcStrict == VINF_SUCCESS)
318 {
319 iemRegAddToRsp(pVCpu, pCtx, 16);
320 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
321 }
322 }
323 }
324 return rcStrict;
325}
326
327
328/**
329 * Implements a 32-bit popa.
330 */
331IEM_CIMPL_DEF_0(iemCImpl_popa_32)
332{
333 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
334 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu, pCtx);
335 RTGCPTR GCPtrLast = GCPtrStart + 31;
336 VBOXSTRICTRC rcStrict;
337
338 /*
339 * The docs are a bit hard to comprehend here, but it looks like we wrap
340 * around in real mode as long as none of the individual "popa" crosses the
341 * end of the stack segment. In protected mode we check the whole access
342 * in one go. For efficiency, only do the word-by-word thing if we're in
343 * danger of wrapping around.
344 */
345 /** @todo do popa boundary / wrap-around checks. */
346 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
347 && (pCtx->cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
348 {
349 /* word-by-word */
350 RTUINT64U TmpRsp;
351 TmpRsp.u = pCtx->rsp;
352 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->edi, &TmpRsp);
353 if (rcStrict == VINF_SUCCESS)
354 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->esi, &TmpRsp);
355 if (rcStrict == VINF_SUCCESS)
356 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->ebp, &TmpRsp);
357 if (rcStrict == VINF_SUCCESS)
358 {
359 iemRegAddToRspEx(pVCpu, pCtx, &TmpRsp, 2); /* sp */
360 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->ebx, &TmpRsp);
361 }
362 if (rcStrict == VINF_SUCCESS)
363 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->edx, &TmpRsp);
364 if (rcStrict == VINF_SUCCESS)
365 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->ecx, &TmpRsp);
366 if (rcStrict == VINF_SUCCESS)
367 rcStrict = iemMemStackPopU32Ex(pVCpu, &pCtx->eax, &TmpRsp);
368 if (rcStrict == VINF_SUCCESS)
369 {
370#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
371 pCtx->rdi &= UINT32_MAX;
372 pCtx->rsi &= UINT32_MAX;
373 pCtx->rbp &= UINT32_MAX;
374 pCtx->rbx &= UINT32_MAX;
375 pCtx->rdx &= UINT32_MAX;
376 pCtx->rcx &= UINT32_MAX;
377 pCtx->rax &= UINT32_MAX;
378#endif
379 pCtx->rsp = TmpRsp.u;
380 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
381 }
382 }
383 else
384 {
385 uint32_t const *pa32Mem;
386 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
387 if (rcStrict == VINF_SUCCESS)
388 {
389 pCtx->rdi = pa32Mem[7 - X86_GREG_xDI];
390 pCtx->rsi = pa32Mem[7 - X86_GREG_xSI];
391 pCtx->rbp = pa32Mem[7 - X86_GREG_xBP];
392 /* skip esp */
393 pCtx->rbx = pa32Mem[7 - X86_GREG_xBX];
394 pCtx->rdx = pa32Mem[7 - X86_GREG_xDX];
395 pCtx->rcx = pa32Mem[7 - X86_GREG_xCX];
396 pCtx->rax = pa32Mem[7 - X86_GREG_xAX];
397 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
398 if (rcStrict == VINF_SUCCESS)
399 {
400 iemRegAddToRsp(pVCpu, pCtx, 32);
401 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
402 }
403 }
404 }
405 return rcStrict;
406}
407
408
409/**
410 * Implements a 16-bit pusha.
411 */
412IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
413{
414 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
415 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu, pCtx);
416 RTGCPTR GCPtrBottom = GCPtrTop - 15;
417 VBOXSTRICTRC rcStrict;
418
419 /*
420 * The docs are a bit hard to comprehend here, but it looks like we wrap
421 * around in real mode as long as none of the individual "pushd" crosses the
422 * end of the stack segment. In protected mode we check the whole access
423 * in one go. For efficiency, only do the word-by-word thing if we're in
424 * danger of wrapping around.
425 */
426 /** @todo do pusha boundary / wrap-around checks. */
427 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
428 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
429 {
430 /* word-by-word */
431 RTUINT64U TmpRsp;
432 TmpRsp.u = pCtx->rsp;
433 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->ax, &TmpRsp);
434 if (rcStrict == VINF_SUCCESS)
435 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->cx, &TmpRsp);
436 if (rcStrict == VINF_SUCCESS)
437 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->dx, &TmpRsp);
438 if (rcStrict == VINF_SUCCESS)
439 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->bx, &TmpRsp);
440 if (rcStrict == VINF_SUCCESS)
441 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->sp, &TmpRsp);
442 if (rcStrict == VINF_SUCCESS)
443 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->bp, &TmpRsp);
444 if (rcStrict == VINF_SUCCESS)
445 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->si, &TmpRsp);
446 if (rcStrict == VINF_SUCCESS)
447 rcStrict = iemMemStackPushU16Ex(pVCpu, pCtx->di, &TmpRsp);
448 if (rcStrict == VINF_SUCCESS)
449 {
450 pCtx->rsp = TmpRsp.u;
451 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
452 }
453 }
454 else
455 {
456 GCPtrBottom--;
457 uint16_t *pa16Mem = NULL;
458 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
459 if (rcStrict == VINF_SUCCESS)
460 {
461 pa16Mem[7 - X86_GREG_xDI] = pCtx->di;
462 pa16Mem[7 - X86_GREG_xSI] = pCtx->si;
463 pa16Mem[7 - X86_GREG_xBP] = pCtx->bp;
464 pa16Mem[7 - X86_GREG_xSP] = pCtx->sp;
465 pa16Mem[7 - X86_GREG_xBX] = pCtx->bx;
466 pa16Mem[7 - X86_GREG_xDX] = pCtx->dx;
467 pa16Mem[7 - X86_GREG_xCX] = pCtx->cx;
468 pa16Mem[7 - X86_GREG_xAX] = pCtx->ax;
469 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
470 if (rcStrict == VINF_SUCCESS)
471 {
472 iemRegSubFromRsp(pVCpu, pCtx, 16);
473 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
474 }
475 }
476 }
477 return rcStrict;
478}
479
480
481/**
482 * Implements a 32-bit pusha.
483 */
484IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
485{
486 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
487 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu, pCtx);
488 RTGCPTR GCPtrBottom = GCPtrTop - 31;
489 VBOXSTRICTRC rcStrict;
490
491 /*
492 * The docs are a bit hard to comprehend here, but it looks like we wrap
493 * around in real mode as long as none of the individual "pusha" crosses the
494 * end of the stack segment. In protected mode we check the whole access
495 * in one go. For efficiency, only do the word-by-word thing if we're in
496 * danger of wrapping around.
497 */
498 /** @todo do pusha boundary / wrap-around checks. */
499 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
500 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
501 {
502 /* word-by-word */
503 RTUINT64U TmpRsp;
504 TmpRsp.u = pCtx->rsp;
505 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->eax, &TmpRsp);
506 if (rcStrict == VINF_SUCCESS)
507 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->ecx, &TmpRsp);
508 if (rcStrict == VINF_SUCCESS)
509 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->edx, &TmpRsp);
510 if (rcStrict == VINF_SUCCESS)
511 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->ebx, &TmpRsp);
512 if (rcStrict == VINF_SUCCESS)
513 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->esp, &TmpRsp);
514 if (rcStrict == VINF_SUCCESS)
515 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->ebp, &TmpRsp);
516 if (rcStrict == VINF_SUCCESS)
517 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->esi, &TmpRsp);
518 if (rcStrict == VINF_SUCCESS)
519 rcStrict = iemMemStackPushU32Ex(pVCpu, pCtx->edi, &TmpRsp);
520 if (rcStrict == VINF_SUCCESS)
521 {
522 pCtx->rsp = TmpRsp.u;
523 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
524 }
525 }
526 else
527 {
528 GCPtrBottom--;
529 uint32_t *pa32Mem;
530 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
531 if (rcStrict == VINF_SUCCESS)
532 {
533 pa32Mem[7 - X86_GREG_xDI] = pCtx->edi;
534 pa32Mem[7 - X86_GREG_xSI] = pCtx->esi;
535 pa32Mem[7 - X86_GREG_xBP] = pCtx->ebp;
536 pa32Mem[7 - X86_GREG_xSP] = pCtx->esp;
537 pa32Mem[7 - X86_GREG_xBX] = pCtx->ebx;
538 pa32Mem[7 - X86_GREG_xDX] = pCtx->edx;
539 pa32Mem[7 - X86_GREG_xCX] = pCtx->ecx;
540 pa32Mem[7 - X86_GREG_xAX] = pCtx->eax;
541 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
542 if (rcStrict == VINF_SUCCESS)
543 {
544 iemRegSubFromRsp(pVCpu, pCtx, 32);
545 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
546 }
547 }
548 }
549 return rcStrict;
550}
551
552
553/**
554 * Implements pushf.
555 *
556 *
557 * @param enmEffOpSize The effective operand size.
558 */
559IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
560{
561 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
562 VBOXSTRICTRC rcStrict;
563
564 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
565 {
566 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
567 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
568 }
569
570 /*
571 * If we're in V8086 mode some care is required (which is why we're in
572 * doing this in a C implementation).
573 */
574 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu, pCtx);
575 if ( (fEfl & X86_EFL_VM)
576 && X86_EFL_GET_IOPL(fEfl) != 3 )
577 {
578 Assert(pCtx->cr0 & X86_CR0_PE);
579 if ( enmEffOpSize != IEMMODE_16BIT
580 || !(pCtx->cr4 & X86_CR4_VME))
581 return iemRaiseGeneralProtectionFault0(pVCpu);
582 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
583 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
584 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
585 }
586 else
587 {
588
589 /*
590 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
591 */
592 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
593
594 switch (enmEffOpSize)
595 {
596 case IEMMODE_16BIT:
597 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
598 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
599 fEfl |= UINT16_C(0xf000);
600 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
601 break;
602 case IEMMODE_32BIT:
603 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
604 break;
605 case IEMMODE_64BIT:
606 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
607 break;
608 IEM_NOT_REACHED_DEFAULT_CASE_RET();
609 }
610 }
611 if (rcStrict != VINF_SUCCESS)
612 return rcStrict;
613
614 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Implements popf.
621 *
622 * @param enmEffOpSize The effective operand size.
623 */
624IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
625{
626 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
627 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu, pCtx);
628 VBOXSTRICTRC rcStrict;
629 uint32_t fEflNew;
630
631 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
632 {
633 Log2(("popf: Guest intercept -> #VMEXIT\n"));
634 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
635 }
636
637 /*
638 * V8086 is special as usual.
639 */
640 if (fEflOld & X86_EFL_VM)
641 {
642 /*
643 * Almost anything goes if IOPL is 3.
644 */
645 if (X86_EFL_GET_IOPL(fEflOld) == 3)
646 {
647 switch (enmEffOpSize)
648 {
649 case IEMMODE_16BIT:
650 {
651 uint16_t u16Value;
652 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
653 if (rcStrict != VINF_SUCCESS)
654 return rcStrict;
655 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
656 break;
657 }
658 case IEMMODE_32BIT:
659 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
660 if (rcStrict != VINF_SUCCESS)
661 return rcStrict;
662 break;
663 IEM_NOT_REACHED_DEFAULT_CASE_RET();
664 }
665
666 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
667 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
668 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
669 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
670 }
671 /*
672 * Interrupt flag virtualization with CR4.VME=1.
673 */
674 else if ( enmEffOpSize == IEMMODE_16BIT
675 && (pCtx->cr4 & X86_CR4_VME) )
676 {
677 uint16_t u16Value;
678 RTUINT64U TmpRsp;
679 TmpRsp.u = pCtx->rsp;
680 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
681 if (rcStrict != VINF_SUCCESS)
682 return rcStrict;
683
684 /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
685 * or before? */
686 if ( ( (u16Value & X86_EFL_IF)
687 && (fEflOld & X86_EFL_VIP))
688 || (u16Value & X86_EFL_TF) )
689 return iemRaiseGeneralProtectionFault0(pVCpu);
690
691 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
692 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
693 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
694 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
695
696 pCtx->rsp = TmpRsp.u;
697 }
698 else
699 return iemRaiseGeneralProtectionFault0(pVCpu);
700
701 }
702 /*
703 * Not in V8086 mode.
704 */
705 else
706 {
707 /* Pop the flags. */
708 switch (enmEffOpSize)
709 {
710 case IEMMODE_16BIT:
711 {
712 uint16_t u16Value;
713 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
714 if (rcStrict != VINF_SUCCESS)
715 return rcStrict;
716 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
717
718 /*
719 * Ancient CPU adjustments:
720 * - 8086, 80186, V20/30:
721 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
722 * practical reasons (masking below). We add them when pushing flags.
723 * - 80286:
724 * The NT and IOPL flags cannot be popped from real mode and are
725 * therefore always zero (since a 286 can never exit from PM and
726 * their initial value is zero). This changed on a 386 and can
727 * therefore be used to detect 286 or 386 CPU in real mode.
728 */
729 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
730 && !(pCtx->cr0 & X86_CR0_PE) )
731 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
732 break;
733 }
734 case IEMMODE_32BIT:
735 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
736 if (rcStrict != VINF_SUCCESS)
737 return rcStrict;
738 break;
739 case IEMMODE_64BIT:
740 {
741 uint64_t u64Value;
742 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
743 if (rcStrict != VINF_SUCCESS)
744 return rcStrict;
745 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
746 break;
747 }
748 IEM_NOT_REACHED_DEFAULT_CASE_RET();
749 }
750
751 /* Merge them with the current flags. */
752 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
753 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
754 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
755 || pVCpu->iem.s.uCpl == 0)
756 {
757 fEflNew &= fPopfBits;
758 fEflNew |= ~fPopfBits & fEflOld;
759 }
760 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
761 {
762 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
763 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
764 }
765 else
766 {
767 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
768 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
769 }
770 }
771
772 /*
773 * Commit the flags.
774 */
775 Assert(fEflNew & RT_BIT_32(1));
776 IEMMISC_SET_EFL(pVCpu, pCtx, fEflNew);
777 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
778
779 return VINF_SUCCESS;
780}
781
782
783/**
784 * Implements an indirect call.
785 *
786 * @param uNewPC The new program counter (RIP) value (loaded from the
787 * operand).
788 * @param enmEffOpSize The effective operand size.
789 */
790IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
791{
792 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
793 uint16_t uOldPC = pCtx->ip + cbInstr;
794 if (uNewPC > pCtx->cs.u32Limit)
795 return iemRaiseGeneralProtectionFault0(pVCpu);
796
797 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
798 if (rcStrict != VINF_SUCCESS)
799 return rcStrict;
800
801 pCtx->rip = uNewPC;
802 pCtx->eflags.Bits.u1RF = 0;
803
804#ifndef IEM_WITH_CODE_TLB
805 /* Flush the prefetch buffer. */
806 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
807#endif
808 return VINF_SUCCESS;
809}
810
811
812/**
813 * Implements a 16-bit relative call.
814 *
815 * @param offDisp The displacment offset.
816 */
817IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
818{
819 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
820 uint16_t uOldPC = pCtx->ip + cbInstr;
821 uint16_t uNewPC = uOldPC + offDisp;
822 if (uNewPC > pCtx->cs.u32Limit)
823 return iemRaiseGeneralProtectionFault0(pVCpu);
824
825 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
826 if (rcStrict != VINF_SUCCESS)
827 return rcStrict;
828
829 pCtx->rip = uNewPC;
830 pCtx->eflags.Bits.u1RF = 0;
831
832#ifndef IEM_WITH_CODE_TLB
833 /* Flush the prefetch buffer. */
834 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
835#endif
836 return VINF_SUCCESS;
837}
838
839
840/**
841 * Implements a 32-bit indirect call.
842 *
843 * @param uNewPC The new program counter (RIP) value (loaded from the
844 * operand).
845 * @param enmEffOpSize The effective operand size.
846 */
847IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
848{
849 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
850 uint32_t uOldPC = pCtx->eip + cbInstr;
851 if (uNewPC > pCtx->cs.u32Limit)
852 return iemRaiseGeneralProtectionFault0(pVCpu);
853
854 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
855 if (rcStrict != VINF_SUCCESS)
856 return rcStrict;
857
858#if defined(IN_RING3) && defined(VBOX_WITH_RAW_MODE) && defined(VBOX_WITH_CALL_RECORD)
859 /*
860 * CASM hook for recording interesting indirect calls.
861 */
862 if ( !pCtx->eflags.Bits.u1IF
863 && (pCtx->cr0 & X86_CR0_PG)
864 && !CSAMIsEnabled(pVCpu->CTX_SUFF(pVM))
865 && pVCpu->iem.s.uCpl == 0)
866 {
867 EMSTATE enmState = EMGetState(pVCpu);
868 if ( enmState == EMSTATE_IEM_THEN_REM
869 || enmState == EMSTATE_IEM
870 || enmState == EMSTATE_REM)
871 CSAMR3RecordCallAddress(pVCpu->CTX_SUFF(pVM), pCtx->eip);
872 }
873#endif
874
875 pCtx->rip = uNewPC;
876 pCtx->eflags.Bits.u1RF = 0;
877
878#ifndef IEM_WITH_CODE_TLB
879 /* Flush the prefetch buffer. */
880 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
881#endif
882 return VINF_SUCCESS;
883}
884
885
886/**
887 * Implements a 32-bit relative call.
888 *
889 * @param offDisp The displacment offset.
890 */
891IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
892{
893 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
894 uint32_t uOldPC = pCtx->eip + cbInstr;
895 uint32_t uNewPC = uOldPC + offDisp;
896 if (uNewPC > pCtx->cs.u32Limit)
897 return iemRaiseGeneralProtectionFault0(pVCpu);
898
899 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
900 if (rcStrict != VINF_SUCCESS)
901 return rcStrict;
902
903 pCtx->rip = uNewPC;
904 pCtx->eflags.Bits.u1RF = 0;
905
906#ifndef IEM_WITH_CODE_TLB
907 /* Flush the prefetch buffer. */
908 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
909#endif
910 return VINF_SUCCESS;
911}
912
913
914/**
915 * Implements a 64-bit indirect call.
916 *
917 * @param uNewPC The new program counter (RIP) value (loaded from the
918 * operand).
919 * @param enmEffOpSize The effective operand size.
920 */
921IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
922{
923 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
924 uint64_t uOldPC = pCtx->rip + cbInstr;
925 if (!IEM_IS_CANONICAL(uNewPC))
926 return iemRaiseGeneralProtectionFault0(pVCpu);
927
928 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
929 if (rcStrict != VINF_SUCCESS)
930 return rcStrict;
931
932 pCtx->rip = uNewPC;
933 pCtx->eflags.Bits.u1RF = 0;
934
935#ifndef IEM_WITH_CODE_TLB
936 /* Flush the prefetch buffer. */
937 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
938#endif
939 return VINF_SUCCESS;
940}
941
942
943/**
944 * Implements a 64-bit relative call.
945 *
946 * @param offDisp The displacment offset.
947 */
948IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
949{
950 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
951 uint64_t uOldPC = pCtx->rip + cbInstr;
952 uint64_t uNewPC = uOldPC + offDisp;
953 if (!IEM_IS_CANONICAL(uNewPC))
954 return iemRaiseNotCanonical(pVCpu);
955
956 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
957 if (rcStrict != VINF_SUCCESS)
958 return rcStrict;
959
960 pCtx->rip = uNewPC;
961 pCtx->eflags.Bits.u1RF = 0;
962
963#ifndef IEM_WITH_CODE_TLB
964 /* Flush the prefetch buffer. */
965 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
966#endif
967
968 return VINF_SUCCESS;
969}
970
971
972/**
973 * Implements far jumps and calls thru task segments (TSS).
974 *
975 * @param uSel The selector.
976 * @param enmBranch The kind of branching we're performing.
977 * @param enmEffOpSize The effective operand size.
978 * @param pDesc The descriptor corresponding to @a uSel. The type is
979 * task gate.
980 */
981IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
982{
983#ifndef IEM_IMPLEMENTS_TASKSWITCH
984 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
985#else
986 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
987 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
988 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
989 RT_NOREF_PV(enmEffOpSize);
990
991 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
992 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
993 {
994 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
995 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
996 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
997 }
998
999 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1000 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1001 * checked here, need testcases. */
1002 if (!pDesc->Legacy.Gen.u1Present)
1003 {
1004 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
1005 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1006 }
1007
1008 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1009 uint32_t uNextEip = pCtx->eip + cbInstr;
1010 return iemTaskSwitch(pVCpu, pCtx, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1011 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
1012#endif
1013}
1014
1015
1016/**
1017 * Implements far jumps and calls thru task gates.
1018 *
1019 * @param uSel The selector.
1020 * @param enmBranch The kind of branching we're performing.
1021 * @param enmEffOpSize The effective operand size.
1022 * @param pDesc The descriptor corresponding to @a uSel. The type is
1023 * task gate.
1024 */
1025IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1026{
1027#ifndef IEM_IMPLEMENTS_TASKSWITCH
1028 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1029#else
1030 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1031 RT_NOREF_PV(enmEffOpSize);
1032
1033 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1034 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1035 {
1036 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1037 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1038 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1039 }
1040
1041 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1042 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1043 * checked here, need testcases. */
1044 if (!pDesc->Legacy.Gen.u1Present)
1045 {
1046 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1047 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1048 }
1049
1050 /*
1051 * Fetch the new TSS descriptor from the GDT.
1052 */
1053 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1054 if (uSelTss & X86_SEL_LDT)
1055 {
1056 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1057 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1058 }
1059
1060 IEMSELDESC TssDesc;
1061 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1062 if (rcStrict != VINF_SUCCESS)
1063 return rcStrict;
1064
1065 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1066 {
1067 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1068 TssDesc.Legacy.Gate.u4Type));
1069 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1070 }
1071
1072 if (!TssDesc.Legacy.Gate.u1Present)
1073 {
1074 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1075 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1076 }
1077
1078 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1079 uint32_t uNextEip = pCtx->eip + cbInstr;
1080 return iemTaskSwitch(pVCpu, pCtx, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1081 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1082#endif
1083}
1084
1085
1086/**
1087 * Implements far jumps and calls thru call gates.
1088 *
1089 * @param uSel The selector.
1090 * @param enmBranch The kind of branching we're performing.
1091 * @param enmEffOpSize The effective operand size.
1092 * @param pDesc The descriptor corresponding to @a uSel. The type is
1093 * call gate.
1094 */
1095IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1096{
1097#define IEM_IMPLEMENTS_CALLGATE
1098#ifndef IEM_IMPLEMENTS_CALLGATE
1099 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1100#else
1101 RT_NOREF_PV(enmEffOpSize);
1102
1103 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1104 * inter-privilege calls and are much more complex.
1105 *
1106 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1107 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1108 * must be 16-bit or 32-bit.
1109 */
1110 /** @todo: effective operand size is probably irrelevant here, only the
1111 * call gate bitness matters??
1112 */
1113 VBOXSTRICTRC rcStrict;
1114 RTPTRUNION uPtrRet;
1115 uint64_t uNewRsp;
1116 uint64_t uNewRip;
1117 uint64_t u64Base;
1118 uint32_t cbLimit;
1119 RTSEL uNewCS;
1120 IEMSELDESC DescCS;
1121
1122 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1123 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1124 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1125 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1126
1127 /* Determine the new instruction pointer from the gate descriptor. */
1128 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1129 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1130 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1131
1132 /* Perform DPL checks on the gate descriptor. */
1133 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1134 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1135 {
1136 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1137 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1138 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1139 }
1140
1141 /** @todo does this catch NULL selectors, too? */
1142 if (!pDesc->Legacy.Gen.u1Present)
1143 {
1144 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1145 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1146 }
1147
1148 /*
1149 * Fetch the target CS descriptor from the GDT or LDT.
1150 */
1151 uNewCS = pDesc->Legacy.Gate.u16Sel;
1152 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1153 if (rcStrict != VINF_SUCCESS)
1154 return rcStrict;
1155
1156 /* Target CS must be a code selector. */
1157 if ( !DescCS.Legacy.Gen.u1DescType
1158 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1159 {
1160 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1161 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1162 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1163 }
1164
1165 /* Privilege checks on target CS. */
1166 if (enmBranch == IEMBRANCH_JUMP)
1167 {
1168 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1169 {
1170 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1171 {
1172 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1173 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1174 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1175 }
1176 }
1177 else
1178 {
1179 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1180 {
1181 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1182 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1183 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1184 }
1185 }
1186 }
1187 else
1188 {
1189 Assert(enmBranch == IEMBRANCH_CALL);
1190 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1191 {
1192 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1193 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1194 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1195 }
1196 }
1197
1198 /* Additional long mode checks. */
1199 if (IEM_IS_LONG_MODE(pVCpu))
1200 {
1201 if (!DescCS.Legacy.Gen.u1Long)
1202 {
1203 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1204 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1205 }
1206
1207 /* L vs D. */
1208 if ( DescCS.Legacy.Gen.u1Long
1209 && DescCS.Legacy.Gen.u1DefBig)
1210 {
1211 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1212 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1213 }
1214 }
1215
1216 if (!DescCS.Legacy.Gate.u1Present)
1217 {
1218 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1219 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1220 }
1221
1222 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1223
1224 if (enmBranch == IEMBRANCH_JUMP)
1225 {
1226 /** @todo: This is very similar to regular far jumps; merge! */
1227 /* Jumps are fairly simple... */
1228
1229 /* Chop the high bits off if 16-bit gate (Intel says so). */
1230 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1231 uNewRip = (uint16_t)uNewRip;
1232
1233 /* Limit check for non-long segments. */
1234 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1235 if (DescCS.Legacy.Gen.u1Long)
1236 u64Base = 0;
1237 else
1238 {
1239 if (uNewRip > cbLimit)
1240 {
1241 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1242 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1243 }
1244 u64Base = X86DESC_BASE(&DescCS.Legacy);
1245 }
1246
1247 /* Canonical address check. */
1248 if (!IEM_IS_CANONICAL(uNewRip))
1249 {
1250 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1251 return iemRaiseNotCanonical(pVCpu);
1252 }
1253
1254 /*
1255 * Ok, everything checked out fine. Now set the accessed bit before
1256 * committing the result into CS, CSHID and RIP.
1257 */
1258 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1259 {
1260 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1261 if (rcStrict != VINF_SUCCESS)
1262 return rcStrict;
1263 /** @todo check what VT-x and AMD-V does. */
1264 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1265 }
1266
1267 /* commit */
1268 pCtx->rip = uNewRip;
1269 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1270 pCtx->cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1271 pCtx->cs.ValidSel = pCtx->cs.Sel;
1272 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1273 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1274 pCtx->cs.u32Limit = cbLimit;
1275 pCtx->cs.u64Base = u64Base;
1276 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
1277 }
1278 else
1279 {
1280 Assert(enmBranch == IEMBRANCH_CALL);
1281 /* Calls are much more complicated. */
1282
1283 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1284 {
1285 uint16_t offNewStack; /* Offset of new stack in TSS. */
1286 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1287 uint8_t uNewCSDpl;
1288 uint8_t cbWords;
1289 RTSEL uNewSS;
1290 RTSEL uOldSS;
1291 uint64_t uOldRsp;
1292 IEMSELDESC DescSS;
1293 RTPTRUNION uPtrTSS;
1294 RTGCPTR GCPtrTSS;
1295 RTPTRUNION uPtrParmWds;
1296 RTGCPTR GCPtrParmWds;
1297
1298 /* More privilege. This is the fun part. */
1299 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1300
1301 /*
1302 * Determine new SS:rSP from the TSS.
1303 */
1304 Assert(!pCtx->tr.Attr.n.u1DescType);
1305
1306 /* Figure out where the new stack pointer is stored in the TSS. */
1307 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1308 if (!IEM_IS_LONG_MODE(pVCpu))
1309 {
1310 if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1311 {
1312 offNewStack = RT_OFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1313 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1314 }
1315 else
1316 {
1317 Assert(pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1318 offNewStack = RT_OFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1319 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1320 }
1321 }
1322 else
1323 {
1324 Assert(pCtx->tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1325 offNewStack = RT_OFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1326 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1327 }
1328
1329 /* Check against TSS limit. */
1330 if ((uint16_t)(offNewStack + cbNewStack - 1) > pCtx->tr.u32Limit)
1331 {
1332 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pCtx->tr.u32Limit));
1333 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pCtx->tr.Sel);
1334 }
1335
1336 GCPtrTSS = pCtx->tr.u64Base + offNewStack;
1337 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R);
1338 if (rcStrict != VINF_SUCCESS)
1339 {
1340 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1341 return rcStrict;
1342 }
1343
1344 if (!IEM_IS_LONG_MODE(pVCpu))
1345 {
1346 if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1347 {
1348 uNewRsp = uPtrTSS.pu32[0];
1349 uNewSS = uPtrTSS.pu16[2];
1350 }
1351 else
1352 {
1353 Assert(pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1354 uNewRsp = uPtrTSS.pu16[0];
1355 uNewSS = uPtrTSS.pu16[1];
1356 }
1357 }
1358 else
1359 {
1360 Assert(pCtx->tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1361 /* SS will be a NULL selector, but that's valid. */
1362 uNewRsp = uPtrTSS.pu64[0];
1363 uNewSS = uNewCSDpl;
1364 }
1365
1366 /* Done with the TSS now. */
1367 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1368 if (rcStrict != VINF_SUCCESS)
1369 {
1370 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1371 return rcStrict;
1372 }
1373
1374 /* Only used outside of long mode. */
1375 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1376
1377 /* If EFER.LMA is 0, there's extra work to do. */
1378 if (!IEM_IS_LONG_MODE(pVCpu))
1379 {
1380 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1381 {
1382 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1383 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1384 }
1385
1386 /* Grab the new SS descriptor. */
1387 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1388 if (rcStrict != VINF_SUCCESS)
1389 return rcStrict;
1390
1391 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1392 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1393 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1394 {
1395 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1396 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1397 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1398 }
1399
1400 /* Ensure new SS is a writable data segment. */
1401 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1402 {
1403 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1404 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1405 }
1406
1407 if (!DescSS.Legacy.Gen.u1Present)
1408 {
1409 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1410 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1411 }
1412 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1413 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1414 else
1415 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1416 }
1417 else
1418 {
1419 /* Just grab the new (NULL) SS descriptor. */
1420 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1421 * like we do... */
1422 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1423 if (rcStrict != VINF_SUCCESS)
1424 return rcStrict;
1425
1426 cbNewStack = sizeof(uint64_t) * 4;
1427 }
1428
1429 /** @todo: According to Intel, new stack is checked for enough space first,
1430 * then switched. According to AMD, the stack is switched first and
1431 * then pushes might fault!
1432 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1433 * incoming stack #PF happens before actual stack switch. AMD is
1434 * either lying or implicitly assumes that new state is committed
1435 * only if and when an instruction doesn't fault.
1436 */
1437
1438 /** @todo: According to AMD, CS is loaded first, then SS.
1439 * According to Intel, it's the other way around!?
1440 */
1441
1442 /** @todo: Intel and AMD disagree on when exactly the CPL changes! */
1443
1444 /* Set the accessed bit before committing new SS. */
1445 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1446 {
1447 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1448 if (rcStrict != VINF_SUCCESS)
1449 return rcStrict;
1450 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1451 }
1452
1453 /* Remember the old SS:rSP and their linear address. */
1454 uOldSS = pCtx->ss.Sel;
1455 uOldRsp = pCtx->ss.Attr.n.u1DefBig ? pCtx->rsp : pCtx->sp;
1456
1457 GCPtrParmWds = pCtx->ss.u64Base + uOldRsp;
1458
1459 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1460 or #PF, the former is not implemented in this workaround. */
1461 /** @todo Proper fix callgate target stack exceptions. */
1462 /** @todo testcase: Cover callgates with partially or fully inaccessible
1463 * target stacks. */
1464 void *pvNewFrame;
1465 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1466 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW);
1467 if (rcStrict != VINF_SUCCESS)
1468 {
1469 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1470 return rcStrict;
1471 }
1472 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1473 if (rcStrict != VINF_SUCCESS)
1474 {
1475 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1476 return rcStrict;
1477 }
1478
1479 /* Commit new SS:rSP. */
1480 pCtx->ss.Sel = uNewSS;
1481 pCtx->ss.ValidSel = uNewSS;
1482 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1483 pCtx->ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1484 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1485 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1486 pCtx->rsp = uNewRsp;
1487 pVCpu->iem.s.uCpl = uNewCSDpl;
1488 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
1489 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1490
1491 /* At this point the stack access must not fail because new state was already committed. */
1492 /** @todo this can still fail due to SS.LIMIT not check. */
1493 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1494 &uPtrRet.pv, &uNewRsp);
1495 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1496 VERR_INTERNAL_ERROR_5);
1497
1498 if (!IEM_IS_LONG_MODE(pVCpu))
1499 {
1500 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1501 {
1502 /* Push the old CS:rIP. */
1503 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
1504 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1505
1506 if (cbWords)
1507 {
1508 /* Map the relevant chunk of the old stack. */
1509 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1510 if (rcStrict != VINF_SUCCESS)
1511 {
1512 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1513 return rcStrict;
1514 }
1515
1516 /* Copy the parameter (d)words. */
1517 for (int i = 0; i < cbWords; ++i)
1518 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1519
1520 /* Unmap the old stack. */
1521 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1522 if (rcStrict != VINF_SUCCESS)
1523 {
1524 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1525 return rcStrict;
1526 }
1527 }
1528
1529 /* Push the old SS:rSP. */
1530 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1531 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1532 }
1533 else
1534 {
1535 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1536
1537 /* Push the old CS:rIP. */
1538 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
1539 uPtrRet.pu16[1] = pCtx->cs.Sel;
1540
1541 if (cbWords)
1542 {
1543 /* Map the relevant chunk of the old stack. */
1544 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1545 if (rcStrict != VINF_SUCCESS)
1546 {
1547 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1548 return rcStrict;
1549 }
1550
1551 /* Copy the parameter words. */
1552 for (int i = 0; i < cbWords; ++i)
1553 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1554
1555 /* Unmap the old stack. */
1556 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1557 if (rcStrict != VINF_SUCCESS)
1558 {
1559 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1560 return rcStrict;
1561 }
1562 }
1563
1564 /* Push the old SS:rSP. */
1565 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1566 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1567 }
1568 }
1569 else
1570 {
1571 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1572
1573 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1574 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
1575 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1576 uPtrRet.pu64[2] = uOldRsp;
1577 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1578 }
1579
1580 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1581 if (rcStrict != VINF_SUCCESS)
1582 {
1583 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1584 return rcStrict;
1585 }
1586
1587 /* Chop the high bits off if 16-bit gate (Intel says so). */
1588 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1589 uNewRip = (uint16_t)uNewRip;
1590
1591 /* Limit / canonical check. */
1592 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1593 if (!IEM_IS_LONG_MODE(pVCpu))
1594 {
1595 if (uNewRip > cbLimit)
1596 {
1597 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1598 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1599 }
1600 u64Base = X86DESC_BASE(&DescCS.Legacy);
1601 }
1602 else
1603 {
1604 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1605 if (!IEM_IS_CANONICAL(uNewRip))
1606 {
1607 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1608 return iemRaiseNotCanonical(pVCpu);
1609 }
1610 u64Base = 0;
1611 }
1612
1613 /*
1614 * Now set the accessed bit before
1615 * writing the return address to the stack and committing the result into
1616 * CS, CSHID and RIP.
1617 */
1618 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1619 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1620 {
1621 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1622 if (rcStrict != VINF_SUCCESS)
1623 return rcStrict;
1624 /** @todo check what VT-x and AMD-V does. */
1625 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1626 }
1627
1628 /* Commit new CS:rIP. */
1629 pCtx->rip = uNewRip;
1630 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1631 pCtx->cs.Sel |= pVCpu->iem.s.uCpl;
1632 pCtx->cs.ValidSel = pCtx->cs.Sel;
1633 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1634 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1635 pCtx->cs.u32Limit = cbLimit;
1636 pCtx->cs.u64Base = u64Base;
1637 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
1638 }
1639 else
1640 {
1641 /* Same privilege. */
1642 /** @todo: This is very similar to regular far calls; merge! */
1643
1644 /* Check stack first - may #SS(0). */
1645 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1646 * 16-bit code cause a two or four byte CS to be pushed? */
1647 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1648 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1649 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1650 &uPtrRet.pv, &uNewRsp);
1651 if (rcStrict != VINF_SUCCESS)
1652 return rcStrict;
1653
1654 /* Chop the high bits off if 16-bit gate (Intel says so). */
1655 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1656 uNewRip = (uint16_t)uNewRip;
1657
1658 /* Limit / canonical check. */
1659 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1660 if (!IEM_IS_LONG_MODE(pVCpu))
1661 {
1662 if (uNewRip > cbLimit)
1663 {
1664 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1665 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1666 }
1667 u64Base = X86DESC_BASE(&DescCS.Legacy);
1668 }
1669 else
1670 {
1671 if (!IEM_IS_CANONICAL(uNewRip))
1672 {
1673 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1674 return iemRaiseNotCanonical(pVCpu);
1675 }
1676 u64Base = 0;
1677 }
1678
1679 /*
1680 * Now set the accessed bit before
1681 * writing the return address to the stack and committing the result into
1682 * CS, CSHID and RIP.
1683 */
1684 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1685 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1686 {
1687 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1688 if (rcStrict != VINF_SUCCESS)
1689 return rcStrict;
1690 /** @todo check what VT-x and AMD-V does. */
1691 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1692 }
1693
1694 /* stack */
1695 if (!IEM_IS_LONG_MODE(pVCpu))
1696 {
1697 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1698 {
1699 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
1700 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1701 }
1702 else
1703 {
1704 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1705 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
1706 uPtrRet.pu16[1] = pCtx->cs.Sel;
1707 }
1708 }
1709 else
1710 {
1711 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1712 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
1713 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1714 }
1715
1716 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1717 if (rcStrict != VINF_SUCCESS)
1718 return rcStrict;
1719
1720 /* commit */
1721 pCtx->rip = uNewRip;
1722 pCtx->cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1723 pCtx->cs.Sel |= pVCpu->iem.s.uCpl;
1724 pCtx->cs.ValidSel = pCtx->cs.Sel;
1725 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1726 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1727 pCtx->cs.u32Limit = cbLimit;
1728 pCtx->cs.u64Base = u64Base;
1729 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
1730 }
1731 }
1732 pCtx->eflags.Bits.u1RF = 0;
1733
1734 /* Flush the prefetch buffer. */
1735# ifdef IEM_WITH_CODE_TLB
1736 pVCpu->iem.s.pbInstrBuf = NULL;
1737# else
1738 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1739# endif
1740 return VINF_SUCCESS;
1741#endif
1742}
1743
1744
1745/**
1746 * Implements far jumps and calls thru system selectors.
1747 *
1748 * @param uSel The selector.
1749 * @param enmBranch The kind of branching we're performing.
1750 * @param enmEffOpSize The effective operand size.
1751 * @param pDesc The descriptor corresponding to @a uSel.
1752 */
1753IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1754{
1755 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1756 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1757
1758 if (IEM_IS_LONG_MODE(pVCpu))
1759 switch (pDesc->Legacy.Gen.u4Type)
1760 {
1761 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1762 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1763
1764 default:
1765 case AMD64_SEL_TYPE_SYS_LDT:
1766 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1767 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1768 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1769 case AMD64_SEL_TYPE_SYS_INT_GATE:
1770 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1771 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1772 }
1773
1774 switch (pDesc->Legacy.Gen.u4Type)
1775 {
1776 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1777 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1778 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1779
1780 case X86_SEL_TYPE_SYS_TASK_GATE:
1781 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1782
1783 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1784 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1785 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1786
1787 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1788 Log(("branch %04x -> busy 286 TSS\n", uSel));
1789 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1790
1791 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1792 Log(("branch %04x -> busy 386 TSS\n", uSel));
1793 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1794
1795 default:
1796 case X86_SEL_TYPE_SYS_LDT:
1797 case X86_SEL_TYPE_SYS_286_INT_GATE:
1798 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1799 case X86_SEL_TYPE_SYS_386_INT_GATE:
1800 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1801 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1802 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1803 }
1804}
1805
1806
1807/**
1808 * Implements far jumps.
1809 *
1810 * @param uSel The selector.
1811 * @param offSeg The segment offset.
1812 * @param enmEffOpSize The effective operand size.
1813 */
1814IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1815{
1816 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1817 NOREF(cbInstr);
1818 Assert(offSeg <= UINT32_MAX);
1819
1820 /*
1821 * Real mode and V8086 mode are easy. The only snag seems to be that
1822 * CS.limit doesn't change and the limit check is done against the current
1823 * limit.
1824 */
1825 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_16BIT
1826 && IEM_IS_REAL_OR_V86_MODE(pVCpu))
1827 {
1828 if (offSeg > pCtx->cs.u32Limit)
1829 {
1830 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1831 return iemRaiseGeneralProtectionFault0(pVCpu);
1832 }
1833
1834 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1835 pCtx->rip = offSeg;
1836 else
1837 pCtx->rip = offSeg & UINT16_MAX;
1838 pCtx->cs.Sel = uSel;
1839 pCtx->cs.ValidSel = uSel;
1840 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1841 pCtx->cs.u64Base = (uint32_t)uSel << 4;
1842 pCtx->eflags.Bits.u1RF = 0;
1843 return VINF_SUCCESS;
1844 }
1845
1846 /*
1847 * Protected mode. Need to parse the specified descriptor...
1848 */
1849 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1850 {
1851 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1852 return iemRaiseGeneralProtectionFault0(pVCpu);
1853 }
1854
1855 /* Fetch the descriptor. */
1856 IEMSELDESC Desc;
1857 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1858 if (rcStrict != VINF_SUCCESS)
1859 return rcStrict;
1860
1861 /* Is it there? */
1862 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1863 {
1864 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1865 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1866 }
1867
1868 /*
1869 * Deal with it according to its type. We do the standard code selectors
1870 * here and dispatch the system selectors to worker functions.
1871 */
1872 if (!Desc.Legacy.Gen.u1DescType)
1873 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1874
1875 /* Only code segments. */
1876 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1877 {
1878 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1879 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1880 }
1881
1882 /* L vs D. */
1883 if ( Desc.Legacy.Gen.u1Long
1884 && Desc.Legacy.Gen.u1DefBig
1885 && IEM_IS_LONG_MODE(pVCpu))
1886 {
1887 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1888 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1889 }
1890
1891 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1892 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1893 {
1894 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1895 {
1896 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1897 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1898 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1899 }
1900 }
1901 else
1902 {
1903 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1904 {
1905 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1906 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1907 }
1908 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1909 {
1910 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1911 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1912 }
1913 }
1914
1915 /* Chop the high bits if 16-bit (Intel says so). */
1916 if (enmEffOpSize == IEMMODE_16BIT)
1917 offSeg &= UINT16_MAX;
1918
1919 /* Limit check. (Should alternatively check for non-canonical addresses
1920 here, but that is ruled out by offSeg being 32-bit, right?) */
1921 uint64_t u64Base;
1922 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1923 if (Desc.Legacy.Gen.u1Long)
1924 u64Base = 0;
1925 else
1926 {
1927 if (offSeg > cbLimit)
1928 {
1929 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1930 /** @todo: Intel says this is #GP(0)! */
1931 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1932 }
1933 u64Base = X86DESC_BASE(&Desc.Legacy);
1934 }
1935
1936 /*
1937 * Ok, everything checked out fine. Now set the accessed bit before
1938 * committing the result into CS, CSHID and RIP.
1939 */
1940 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1941 {
1942 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1943 if (rcStrict != VINF_SUCCESS)
1944 return rcStrict;
1945 /** @todo check what VT-x and AMD-V does. */
1946 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1947 }
1948
1949 /* commit */
1950 pCtx->rip = offSeg;
1951 pCtx->cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1952 pCtx->cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1953 pCtx->cs.ValidSel = pCtx->cs.Sel;
1954 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1955 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1956 pCtx->cs.u32Limit = cbLimit;
1957 pCtx->cs.u64Base = u64Base;
1958 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
1959 pCtx->eflags.Bits.u1RF = 0;
1960 /** @todo check if the hidden bits are loaded correctly for 64-bit
1961 * mode. */
1962
1963 /* Flush the prefetch buffer. */
1964#ifdef IEM_WITH_CODE_TLB
1965 pVCpu->iem.s.pbInstrBuf = NULL;
1966#else
1967 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1968#endif
1969
1970 return VINF_SUCCESS;
1971}
1972
1973
1974/**
1975 * Implements far calls.
1976 *
1977 * This very similar to iemCImpl_FarJmp.
1978 *
1979 * @param uSel The selector.
1980 * @param offSeg The segment offset.
1981 * @param enmEffOpSize The operand size (in case we need it).
1982 */
1983IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1984{
1985 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1986 VBOXSTRICTRC rcStrict;
1987 uint64_t uNewRsp;
1988 RTPTRUNION uPtrRet;
1989
1990 /*
1991 * Real mode and V8086 mode are easy. The only snag seems to be that
1992 * CS.limit doesn't change and the limit check is done against the current
1993 * limit.
1994 */
1995 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_16BIT
1996 && IEM_IS_REAL_OR_V86_MODE(pVCpu))
1997 {
1998 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1999
2000 /* Check stack first - may #SS(0). */
2001 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 6 : 4,
2002 &uPtrRet.pv, &uNewRsp);
2003 if (rcStrict != VINF_SUCCESS)
2004 return rcStrict;
2005
2006 /* Check the target address range. */
2007 if (offSeg > UINT32_MAX)
2008 return iemRaiseGeneralProtectionFault0(pVCpu);
2009
2010 /* Everything is fine, push the return address. */
2011 if (enmEffOpSize == IEMMODE_16BIT)
2012 {
2013 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
2014 uPtrRet.pu16[1] = pCtx->cs.Sel;
2015 }
2016 else
2017 {
2018 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
2019 uPtrRet.pu16[3] = pCtx->cs.Sel;
2020 }
2021 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2022 if (rcStrict != VINF_SUCCESS)
2023 return rcStrict;
2024
2025 /* Branch. */
2026 pCtx->rip = offSeg;
2027 pCtx->cs.Sel = uSel;
2028 pCtx->cs.ValidSel = uSel;
2029 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2030 pCtx->cs.u64Base = (uint32_t)uSel << 4;
2031 pCtx->eflags.Bits.u1RF = 0;
2032 return VINF_SUCCESS;
2033 }
2034
2035 /*
2036 * Protected mode. Need to parse the specified descriptor...
2037 */
2038 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2039 {
2040 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2041 return iemRaiseGeneralProtectionFault0(pVCpu);
2042 }
2043
2044 /* Fetch the descriptor. */
2045 IEMSELDESC Desc;
2046 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2047 if (rcStrict != VINF_SUCCESS)
2048 return rcStrict;
2049
2050 /*
2051 * Deal with it according to its type. We do the standard code selectors
2052 * here and dispatch the system selectors to worker functions.
2053 */
2054 if (!Desc.Legacy.Gen.u1DescType)
2055 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2056
2057 /* Only code segments. */
2058 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2059 {
2060 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2061 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2062 }
2063
2064 /* L vs D. */
2065 if ( Desc.Legacy.Gen.u1Long
2066 && Desc.Legacy.Gen.u1DefBig
2067 && IEM_IS_LONG_MODE(pVCpu))
2068 {
2069 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2070 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2071 }
2072
2073 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2074 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2075 {
2076 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2077 {
2078 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2079 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2080 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2081 }
2082 }
2083 else
2084 {
2085 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2086 {
2087 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2088 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2089 }
2090 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2091 {
2092 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2093 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2094 }
2095 }
2096
2097 /* Is it there? */
2098 if (!Desc.Legacy.Gen.u1Present)
2099 {
2100 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2101 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2102 }
2103
2104 /* Check stack first - may #SS(0). */
2105 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2106 * 16-bit code cause a two or four byte CS to be pushed? */
2107 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2108 enmEffOpSize == IEMMODE_64BIT ? 8+8
2109 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2110 &uPtrRet.pv, &uNewRsp);
2111 if (rcStrict != VINF_SUCCESS)
2112 return rcStrict;
2113
2114 /* Chop the high bits if 16-bit (Intel says so). */
2115 if (enmEffOpSize == IEMMODE_16BIT)
2116 offSeg &= UINT16_MAX;
2117
2118 /* Limit / canonical check. */
2119 uint64_t u64Base;
2120 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2121 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2122 {
2123 if (!IEM_IS_CANONICAL(offSeg))
2124 {
2125 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2126 return iemRaiseNotCanonical(pVCpu);
2127 }
2128 u64Base = 0;
2129 }
2130 else
2131 {
2132 if (offSeg > cbLimit)
2133 {
2134 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2135 /** @todo: Intel says this is #GP(0)! */
2136 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2137 }
2138 u64Base = X86DESC_BASE(&Desc.Legacy);
2139 }
2140
2141 /*
2142 * Now set the accessed bit before
2143 * writing the return address to the stack and committing the result into
2144 * CS, CSHID and RIP.
2145 */
2146 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2147 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2148 {
2149 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2150 if (rcStrict != VINF_SUCCESS)
2151 return rcStrict;
2152 /** @todo check what VT-x and AMD-V does. */
2153 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2154 }
2155
2156 /* stack */
2157 if (enmEffOpSize == IEMMODE_16BIT)
2158 {
2159 uPtrRet.pu16[0] = pCtx->ip + cbInstr;
2160 uPtrRet.pu16[1] = pCtx->cs.Sel;
2161 }
2162 else if (enmEffOpSize == IEMMODE_32BIT)
2163 {
2164 uPtrRet.pu32[0] = pCtx->eip + cbInstr;
2165 uPtrRet.pu32[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2166 }
2167 else
2168 {
2169 uPtrRet.pu64[0] = pCtx->rip + cbInstr;
2170 uPtrRet.pu64[1] = pCtx->cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2171 }
2172 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2173 if (rcStrict != VINF_SUCCESS)
2174 return rcStrict;
2175
2176 /* commit */
2177 pCtx->rip = offSeg;
2178 pCtx->cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2179 pCtx->cs.Sel |= pVCpu->iem.s.uCpl;
2180 pCtx->cs.ValidSel = pCtx->cs.Sel;
2181 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2182 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2183 pCtx->cs.u32Limit = cbLimit;
2184 pCtx->cs.u64Base = u64Base;
2185 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
2186 pCtx->eflags.Bits.u1RF = 0;
2187 /** @todo check if the hidden bits are loaded correctly for 64-bit
2188 * mode. */
2189
2190 /* Flush the prefetch buffer. */
2191#ifdef IEM_WITH_CODE_TLB
2192 pVCpu->iem.s.pbInstrBuf = NULL;
2193#else
2194 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2195#endif
2196 return VINF_SUCCESS;
2197}
2198
2199
2200/**
2201 * Implements retf.
2202 *
2203 * @param enmEffOpSize The effective operand size.
2204 * @param cbPop The amount of arguments to pop from the stack
2205 * (bytes).
2206 */
2207IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2208{
2209 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
2210 VBOXSTRICTRC rcStrict;
2211 RTCPTRUNION uPtrFrame;
2212 uint64_t uNewRsp;
2213 uint64_t uNewRip;
2214 uint16_t uNewCs;
2215 NOREF(cbInstr);
2216
2217 /*
2218 * Read the stack values first.
2219 */
2220 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2221 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2222 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2223 if (rcStrict != VINF_SUCCESS)
2224 return rcStrict;
2225 if (enmEffOpSize == IEMMODE_16BIT)
2226 {
2227 uNewRip = uPtrFrame.pu16[0];
2228 uNewCs = uPtrFrame.pu16[1];
2229 }
2230 else if (enmEffOpSize == IEMMODE_32BIT)
2231 {
2232 uNewRip = uPtrFrame.pu32[0];
2233 uNewCs = uPtrFrame.pu16[2];
2234 }
2235 else
2236 {
2237 uNewRip = uPtrFrame.pu64[0];
2238 uNewCs = uPtrFrame.pu16[4];
2239 }
2240 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2241 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2242 { /* extremely likely */ }
2243 else
2244 return rcStrict;
2245
2246 /*
2247 * Real mode and V8086 mode are easy.
2248 */
2249 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_16BIT
2250 && IEM_IS_REAL_OR_V86_MODE(pVCpu))
2251 {
2252 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2253 /** @todo check how this is supposed to work if sp=0xfffe. */
2254
2255 /* Check the limit of the new EIP. */
2256 /** @todo Intel pseudo code only does the limit check for 16-bit
2257 * operands, AMD does not make any distinction. What is right? */
2258 if (uNewRip > pCtx->cs.u32Limit)
2259 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2260
2261 /* commit the operation. */
2262 pCtx->rsp = uNewRsp;
2263 pCtx->rip = uNewRip;
2264 pCtx->cs.Sel = uNewCs;
2265 pCtx->cs.ValidSel = uNewCs;
2266 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2267 pCtx->cs.u64Base = (uint32_t)uNewCs << 4;
2268 pCtx->eflags.Bits.u1RF = 0;
2269 /** @todo do we load attribs and limit as well? */
2270 if (cbPop)
2271 iemRegAddToRsp(pVCpu, pCtx, cbPop);
2272 return VINF_SUCCESS;
2273 }
2274
2275 /*
2276 * Protected mode is complicated, of course.
2277 */
2278 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2279 {
2280 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2281 return iemRaiseGeneralProtectionFault0(pVCpu);
2282 }
2283
2284 /* Fetch the descriptor. */
2285 IEMSELDESC DescCs;
2286 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2287 if (rcStrict != VINF_SUCCESS)
2288 return rcStrict;
2289
2290 /* Can only return to a code selector. */
2291 if ( !DescCs.Legacy.Gen.u1DescType
2292 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2293 {
2294 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2295 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2296 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2297 }
2298
2299 /* L vs D. */
2300 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2301 && DescCs.Legacy.Gen.u1DefBig
2302 && IEM_IS_LONG_MODE(pVCpu))
2303 {
2304 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2305 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2306 }
2307
2308 /* DPL/RPL/CPL checks. */
2309 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2310 {
2311 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2312 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2313 }
2314
2315 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2316 {
2317 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2318 {
2319 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2320 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2321 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2322 }
2323 }
2324 else
2325 {
2326 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2327 {
2328 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2329 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2330 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2331 }
2332 }
2333
2334 /* Is it there? */
2335 if (!DescCs.Legacy.Gen.u1Present)
2336 {
2337 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2338 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2339 }
2340
2341 /*
2342 * Return to outer privilege? (We'll typically have entered via a call gate.)
2343 */
2344 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2345 {
2346 /* Read the outer stack pointer stored *after* the parameters. */
2347 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop + cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2348 if (rcStrict != VINF_SUCCESS)
2349 return rcStrict;
2350
2351 uPtrFrame.pu8 += cbPop; /* Skip the parameters. */
2352
2353 uint16_t uNewOuterSs;
2354 uint64_t uNewOuterRsp;
2355 if (enmEffOpSize == IEMMODE_16BIT)
2356 {
2357 uNewOuterRsp = uPtrFrame.pu16[0];
2358 uNewOuterSs = uPtrFrame.pu16[1];
2359 }
2360 else if (enmEffOpSize == IEMMODE_32BIT)
2361 {
2362 uNewOuterRsp = uPtrFrame.pu32[0];
2363 uNewOuterSs = uPtrFrame.pu16[2];
2364 }
2365 else
2366 {
2367 uNewOuterRsp = uPtrFrame.pu64[0];
2368 uNewOuterSs = uPtrFrame.pu16[4];
2369 }
2370 uPtrFrame.pu8 -= cbPop; /* Put uPtrFrame back the way it was. */
2371 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2372 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2373 { /* extremely likely */ }
2374 else
2375 return rcStrict;
2376
2377 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2378 and read the selector. */
2379 IEMSELDESC DescSs;
2380 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2381 {
2382 if ( !DescCs.Legacy.Gen.u1Long
2383 || (uNewOuterSs & X86_SEL_RPL) == 3)
2384 {
2385 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2386 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2387 return iemRaiseGeneralProtectionFault0(pVCpu);
2388 }
2389 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2390 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2391 }
2392 else
2393 {
2394 /* Fetch the descriptor for the new stack segment. */
2395 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2396 if (rcStrict != VINF_SUCCESS)
2397 return rcStrict;
2398 }
2399
2400 /* Check that RPL of stack and code selectors match. */
2401 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2402 {
2403 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2404 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2405 }
2406
2407 /* Must be a writable data segment. */
2408 if ( !DescSs.Legacy.Gen.u1DescType
2409 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2410 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2411 {
2412 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2413 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2414 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2415 }
2416
2417 /* L vs D. (Not mentioned by intel.) */
2418 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2419 && DescSs.Legacy.Gen.u1DefBig
2420 && IEM_IS_LONG_MODE(pVCpu))
2421 {
2422 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2423 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2424 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2425 }
2426
2427 /* DPL/RPL/CPL checks. */
2428 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2429 {
2430 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2431 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2432 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2433 }
2434
2435 /* Is it there? */
2436 if (!DescSs.Legacy.Gen.u1Present)
2437 {
2438 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2439 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2440 }
2441
2442 /* Calc SS limit.*/
2443 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2444
2445 /* Is RIP canonical or within CS.limit? */
2446 uint64_t u64Base;
2447 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2448
2449 /** @todo Testcase: Is this correct? */
2450 if ( DescCs.Legacy.Gen.u1Long
2451 && IEM_IS_LONG_MODE(pVCpu) )
2452 {
2453 if (!IEM_IS_CANONICAL(uNewRip))
2454 {
2455 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2456 return iemRaiseNotCanonical(pVCpu);
2457 }
2458 u64Base = 0;
2459 }
2460 else
2461 {
2462 if (uNewRip > cbLimitCs)
2463 {
2464 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2465 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2466 /** @todo: Intel says this is #GP(0)! */
2467 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2468 }
2469 u64Base = X86DESC_BASE(&DescCs.Legacy);
2470 }
2471
2472 /*
2473 * Now set the accessed bit before
2474 * writing the return address to the stack and committing the result into
2475 * CS, CSHID and RIP.
2476 */
2477 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2478 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2479 {
2480 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2481 if (rcStrict != VINF_SUCCESS)
2482 return rcStrict;
2483 /** @todo check what VT-x and AMD-V does. */
2484 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2485 }
2486 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2487 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2488 {
2489 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2490 if (rcStrict != VINF_SUCCESS)
2491 return rcStrict;
2492 /** @todo check what VT-x and AMD-V does. */
2493 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2494 }
2495
2496 /* commit */
2497 if (enmEffOpSize == IEMMODE_16BIT)
2498 pCtx->rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2499 else
2500 pCtx->rip = uNewRip;
2501 pCtx->cs.Sel = uNewCs;
2502 pCtx->cs.ValidSel = uNewCs;
2503 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2504 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2505 pCtx->cs.u32Limit = cbLimitCs;
2506 pCtx->cs.u64Base = u64Base;
2507 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
2508 pCtx->ss.Sel = uNewOuterSs;
2509 pCtx->ss.ValidSel = uNewOuterSs;
2510 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2511 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2512 pCtx->ss.u32Limit = cbLimitSs;
2513 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2514 pCtx->ss.u64Base = 0;
2515 else
2516 pCtx->ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2517 if (!pCtx->ss.Attr.n.u1DefBig)
2518 pCtx->sp = (uint16_t)uNewOuterRsp;
2519 else
2520 pCtx->rsp = uNewOuterRsp;
2521
2522 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2523 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->ds);
2524 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->es);
2525 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->fs);
2526 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->gs);
2527
2528 /** @todo check if the hidden bits are loaded correctly for 64-bit
2529 * mode. */
2530
2531 if (cbPop)
2532 iemRegAddToRsp(pVCpu, pCtx, cbPop);
2533 pCtx->eflags.Bits.u1RF = 0;
2534
2535 /* Done! */
2536 }
2537 /*
2538 * Return to the same privilege level
2539 */
2540 else
2541 {
2542 /* Limit / canonical check. */
2543 uint64_t u64Base;
2544 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2545
2546 /** @todo Testcase: Is this correct? */
2547 if ( DescCs.Legacy.Gen.u1Long
2548 && IEM_IS_LONG_MODE(pVCpu) )
2549 {
2550 if (!IEM_IS_CANONICAL(uNewRip))
2551 {
2552 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2553 return iemRaiseNotCanonical(pVCpu);
2554 }
2555 u64Base = 0;
2556 }
2557 else
2558 {
2559 if (uNewRip > cbLimitCs)
2560 {
2561 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2562 /** @todo: Intel says this is #GP(0)! */
2563 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2564 }
2565 u64Base = X86DESC_BASE(&DescCs.Legacy);
2566 }
2567
2568 /*
2569 * Now set the accessed bit before
2570 * writing the return address to the stack and committing the result into
2571 * CS, CSHID and RIP.
2572 */
2573 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2574 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2575 {
2576 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2577 if (rcStrict != VINF_SUCCESS)
2578 return rcStrict;
2579 /** @todo check what VT-x and AMD-V does. */
2580 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2581 }
2582
2583 /* commit */
2584 if (!pCtx->ss.Attr.n.u1DefBig)
2585 pCtx->sp = (uint16_t)uNewRsp;
2586 else
2587 pCtx->rsp = uNewRsp;
2588 if (enmEffOpSize == IEMMODE_16BIT)
2589 pCtx->rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2590 else
2591 pCtx->rip = uNewRip;
2592 pCtx->cs.Sel = uNewCs;
2593 pCtx->cs.ValidSel = uNewCs;
2594 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2595 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2596 pCtx->cs.u32Limit = cbLimitCs;
2597 pCtx->cs.u64Base = u64Base;
2598 /** @todo check if the hidden bits are loaded correctly for 64-bit
2599 * mode. */
2600 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
2601 if (cbPop)
2602 iemRegAddToRsp(pVCpu, pCtx, cbPop);
2603 pCtx->eflags.Bits.u1RF = 0;
2604 }
2605
2606 /* Flush the prefetch buffer. */
2607#ifdef IEM_WITH_CODE_TLB
2608 pVCpu->iem.s.pbInstrBuf = NULL;
2609#else
2610 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2611#endif
2612 return VINF_SUCCESS;
2613}
2614
2615
2616/**
2617 * Implements retn.
2618 *
2619 * We're doing this in C because of the \#GP that might be raised if the popped
2620 * program counter is out of bounds.
2621 *
2622 * @param enmEffOpSize The effective operand size.
2623 * @param cbPop The amount of arguments to pop from the stack
2624 * (bytes).
2625 */
2626IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2627{
2628 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
2629 NOREF(cbInstr);
2630
2631 /* Fetch the RSP from the stack. */
2632 VBOXSTRICTRC rcStrict;
2633 RTUINT64U NewRip;
2634 RTUINT64U NewRsp;
2635 NewRsp.u = pCtx->rsp;
2636
2637 switch (enmEffOpSize)
2638 {
2639 case IEMMODE_16BIT:
2640 NewRip.u = 0;
2641 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2642 break;
2643 case IEMMODE_32BIT:
2644 NewRip.u = 0;
2645 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2646 break;
2647 case IEMMODE_64BIT:
2648 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2649 break;
2650 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2651 }
2652 if (rcStrict != VINF_SUCCESS)
2653 return rcStrict;
2654
2655 /* Check the new RSP before loading it. */
2656 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2657 * of it. The canonical test is performed here and for call. */
2658 if (enmEffOpSize != IEMMODE_64BIT)
2659 {
2660 if (NewRip.DWords.dw0 > pCtx->cs.u32Limit)
2661 {
2662 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pCtx->cs.u32Limit));
2663 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2664 }
2665 }
2666 else
2667 {
2668 if (!IEM_IS_CANONICAL(NewRip.u))
2669 {
2670 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2671 return iemRaiseNotCanonical(pVCpu);
2672 }
2673 }
2674
2675 /* Apply cbPop */
2676 if (cbPop)
2677 iemRegAddToRspEx(pVCpu, pCtx, &NewRsp, cbPop);
2678
2679 /* Commit it. */
2680 pCtx->rip = NewRip.u;
2681 pCtx->rsp = NewRsp.u;
2682 pCtx->eflags.Bits.u1RF = 0;
2683
2684 /* Flush the prefetch buffer. */
2685#ifndef IEM_WITH_CODE_TLB
2686 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2687#endif
2688
2689 return VINF_SUCCESS;
2690}
2691
2692
2693/**
2694 * Implements enter.
2695 *
2696 * We're doing this in C because the instruction is insane, even for the
2697 * u8NestingLevel=0 case dealing with the stack is tedious.
2698 *
2699 * @param enmEffOpSize The effective operand size.
2700 */
2701IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2702{
2703 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
2704
2705 /* Push RBP, saving the old value in TmpRbp. */
2706 RTUINT64U NewRsp; NewRsp.u = pCtx->rsp;
2707 RTUINT64U TmpRbp; TmpRbp.u = pCtx->rbp;
2708 RTUINT64U NewRbp;
2709 VBOXSTRICTRC rcStrict;
2710 if (enmEffOpSize == IEMMODE_64BIT)
2711 {
2712 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2713 NewRbp = NewRsp;
2714 }
2715 else if (enmEffOpSize == IEMMODE_32BIT)
2716 {
2717 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2718 NewRbp = NewRsp;
2719 }
2720 else
2721 {
2722 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2723 NewRbp = TmpRbp;
2724 NewRbp.Words.w0 = NewRsp.Words.w0;
2725 }
2726 if (rcStrict != VINF_SUCCESS)
2727 return rcStrict;
2728
2729 /* Copy the parameters (aka nesting levels by Intel). */
2730 cParameters &= 0x1f;
2731 if (cParameters > 0)
2732 {
2733 switch (enmEffOpSize)
2734 {
2735 case IEMMODE_16BIT:
2736 if (pCtx->ss.Attr.n.u1DefBig)
2737 TmpRbp.DWords.dw0 -= 2;
2738 else
2739 TmpRbp.Words.w0 -= 2;
2740 do
2741 {
2742 uint16_t u16Tmp;
2743 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2744 if (rcStrict != VINF_SUCCESS)
2745 break;
2746 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2747 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2748 break;
2749
2750 case IEMMODE_32BIT:
2751 if (pCtx->ss.Attr.n.u1DefBig)
2752 TmpRbp.DWords.dw0 -= 4;
2753 else
2754 TmpRbp.Words.w0 -= 4;
2755 do
2756 {
2757 uint32_t u32Tmp;
2758 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2759 if (rcStrict != VINF_SUCCESS)
2760 break;
2761 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2762 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2763 break;
2764
2765 case IEMMODE_64BIT:
2766 TmpRbp.u -= 8;
2767 do
2768 {
2769 uint64_t u64Tmp;
2770 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2771 if (rcStrict != VINF_SUCCESS)
2772 break;
2773 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2774 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2775 break;
2776
2777 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2778 }
2779 if (rcStrict != VINF_SUCCESS)
2780 return VINF_SUCCESS;
2781
2782 /* Push the new RBP */
2783 if (enmEffOpSize == IEMMODE_64BIT)
2784 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2785 else if (enmEffOpSize == IEMMODE_32BIT)
2786 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2787 else
2788 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2789 if (rcStrict != VINF_SUCCESS)
2790 return rcStrict;
2791
2792 }
2793
2794 /* Recalc RSP. */
2795 iemRegSubFromRspEx(pVCpu, pCtx, &NewRsp, cbFrame);
2796
2797 /** @todo Should probe write access at the new RSP according to AMD. */
2798
2799 /* Commit it. */
2800 pCtx->rbp = NewRbp.u;
2801 pCtx->rsp = NewRsp.u;
2802 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2803
2804 return VINF_SUCCESS;
2805}
2806
2807
2808
2809/**
2810 * Implements leave.
2811 *
2812 * We're doing this in C because messing with the stack registers is annoying
2813 * since they depends on SS attributes.
2814 *
2815 * @param enmEffOpSize The effective operand size.
2816 */
2817IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2818{
2819 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
2820
2821 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2822 RTUINT64U NewRsp;
2823 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2824 NewRsp.u = pCtx->rbp;
2825 else if (pCtx->ss.Attr.n.u1DefBig)
2826 NewRsp.u = pCtx->ebp;
2827 else
2828 {
2829 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2830 NewRsp.u = pCtx->rsp;
2831 NewRsp.Words.w0 = pCtx->bp;
2832 }
2833
2834 /* Pop RBP according to the operand size. */
2835 VBOXSTRICTRC rcStrict;
2836 RTUINT64U NewRbp;
2837 switch (enmEffOpSize)
2838 {
2839 case IEMMODE_16BIT:
2840 NewRbp.u = pCtx->rbp;
2841 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2842 break;
2843 case IEMMODE_32BIT:
2844 NewRbp.u = 0;
2845 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2846 break;
2847 case IEMMODE_64BIT:
2848 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2849 break;
2850 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2851 }
2852 if (rcStrict != VINF_SUCCESS)
2853 return rcStrict;
2854
2855
2856 /* Commit it. */
2857 pCtx->rbp = NewRbp.u;
2858 pCtx->rsp = NewRsp.u;
2859 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2860
2861 return VINF_SUCCESS;
2862}
2863
2864
2865/**
2866 * Implements int3 and int XX.
2867 *
2868 * @param u8Int The interrupt vector number.
2869 * @param enmInt The int instruction type.
2870 */
2871IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2872{
2873 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2874 return iemRaiseXcptOrInt(pVCpu,
2875 cbInstr,
2876 u8Int,
2877 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2878 0,
2879 0);
2880}
2881
2882
2883/**
2884 * Implements iret for real mode and V8086 mode.
2885 *
2886 * @param enmEffOpSize The effective operand size.
2887 */
2888IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2889{
2890 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
2891 X86EFLAGS Efl;
2892 Efl.u = IEMMISC_GET_EFL(pVCpu, pCtx);
2893 NOREF(cbInstr);
2894
2895 /*
2896 * iret throws an exception if VME isn't enabled.
2897 */
2898 if ( Efl.Bits.u1VM
2899 && Efl.Bits.u2IOPL != 3
2900 && !(pCtx->cr4 & X86_CR4_VME))
2901 return iemRaiseGeneralProtectionFault0(pVCpu);
2902
2903 /*
2904 * Do the stack bits, but don't commit RSP before everything checks
2905 * out right.
2906 */
2907 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2908 VBOXSTRICTRC rcStrict;
2909 RTCPTRUNION uFrame;
2910 uint16_t uNewCs;
2911 uint32_t uNewEip;
2912 uint32_t uNewFlags;
2913 uint64_t uNewRsp;
2914 if (enmEffOpSize == IEMMODE_32BIT)
2915 {
2916 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
2917 if (rcStrict != VINF_SUCCESS)
2918 return rcStrict;
2919 uNewEip = uFrame.pu32[0];
2920 if (uNewEip > UINT16_MAX)
2921 return iemRaiseGeneralProtectionFault0(pVCpu);
2922
2923 uNewCs = (uint16_t)uFrame.pu32[1];
2924 uNewFlags = uFrame.pu32[2];
2925 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2926 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2927 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2928 | X86_EFL_ID;
2929 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2930 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2931 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2932 }
2933 else
2934 {
2935 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
2936 if (rcStrict != VINF_SUCCESS)
2937 return rcStrict;
2938 uNewEip = uFrame.pu16[0];
2939 uNewCs = uFrame.pu16[1];
2940 uNewFlags = uFrame.pu16[2];
2941 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2942 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2943 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2944 /** @todo The intel pseudo code does not indicate what happens to
2945 * reserved flags. We just ignore them. */
2946 /* Ancient CPU adjustments: See iemCImpl_popf. */
2947 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2948 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2949 }
2950 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2951 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2952 { /* extremely likely */ }
2953 else
2954 return rcStrict;
2955
2956 /** @todo Check how this is supposed to work if sp=0xfffe. */
2957 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2958 uNewCs, uNewEip, uNewFlags, uNewRsp));
2959
2960 /*
2961 * Check the limit of the new EIP.
2962 */
2963 /** @todo Only the AMD pseudo code check the limit here, what's
2964 * right? */
2965 if (uNewEip > pCtx->cs.u32Limit)
2966 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2967
2968 /*
2969 * V8086 checks and flag adjustments
2970 */
2971 if (Efl.Bits.u1VM)
2972 {
2973 if (Efl.Bits.u2IOPL == 3)
2974 {
2975 /* Preserve IOPL and clear RF. */
2976 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
2977 uNewFlags |= Efl.u & (X86_EFL_IOPL);
2978 }
2979 else if ( enmEffOpSize == IEMMODE_16BIT
2980 && ( !(uNewFlags & X86_EFL_IF)
2981 || !Efl.Bits.u1VIP )
2982 && !(uNewFlags & X86_EFL_TF) )
2983 {
2984 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
2985 uNewFlags &= ~X86_EFL_VIF;
2986 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
2987 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
2988 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
2989 }
2990 else
2991 return iemRaiseGeneralProtectionFault0(pVCpu);
2992 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
2993 }
2994
2995 /*
2996 * Commit the operation.
2997 */
2998#ifdef DBGFTRACE_ENABLED
2999 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
3000 pCtx->cs.Sel, pCtx->eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
3001#endif
3002 pCtx->rsp = uNewRsp;
3003 pCtx->rip = uNewEip;
3004 pCtx->cs.Sel = uNewCs;
3005 pCtx->cs.ValidSel = uNewCs;
3006 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3007 pCtx->cs.u64Base = (uint32_t)uNewCs << 4;
3008 /** @todo do we load attribs and limit as well? */
3009 Assert(uNewFlags & X86_EFL_1);
3010 IEMMISC_SET_EFL(pVCpu, pCtx, uNewFlags);
3011
3012 /* Flush the prefetch buffer. */
3013#ifdef IEM_WITH_CODE_TLB
3014 pVCpu->iem.s.pbInstrBuf = NULL;
3015#else
3016 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3017#endif
3018
3019 return VINF_SUCCESS;
3020}
3021
3022
3023/**
3024 * Loads a segment register when entering V8086 mode.
3025 *
3026 * @param pSReg The segment register.
3027 * @param uSeg The segment to load.
3028 */
3029static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3030{
3031 pSReg->Sel = uSeg;
3032 pSReg->ValidSel = uSeg;
3033 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3034 pSReg->u64Base = (uint32_t)uSeg << 4;
3035 pSReg->u32Limit = 0xffff;
3036 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3037 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3038 * IRET'ing to V8086. */
3039}
3040
3041
3042/**
3043 * Implements iret for protected mode returning to V8086 mode.
3044 *
3045 * @param pCtx Pointer to the CPU context.
3046 * @param uNewEip The new EIP.
3047 * @param uNewCs The new CS.
3048 * @param uNewFlags The new EFLAGS.
3049 * @param uNewRsp The RSP after the initial IRET frame.
3050 *
3051 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3052 */
3053IEM_CIMPL_DEF_5(iemCImpl_iret_prot_v8086, PCPUMCTX, pCtx, uint32_t, uNewEip, uint16_t, uNewCs,
3054 uint32_t, uNewFlags, uint64_t, uNewRsp)
3055{
3056 RT_NOREF_PV(cbInstr);
3057
3058 /*
3059 * Pop the V8086 specific frame bits off the stack.
3060 */
3061 VBOXSTRICTRC rcStrict;
3062 RTCPTRUNION uFrame;
3063 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 24, &uFrame.pv, &uNewRsp);
3064 if (rcStrict != VINF_SUCCESS)
3065 return rcStrict;
3066 uint32_t uNewEsp = uFrame.pu32[0];
3067 uint16_t uNewSs = uFrame.pu32[1];
3068 uint16_t uNewEs = uFrame.pu32[2];
3069 uint16_t uNewDs = uFrame.pu32[3];
3070 uint16_t uNewFs = uFrame.pu32[4];
3071 uint16_t uNewGs = uFrame.pu32[5];
3072 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3073 if (rcStrict != VINF_SUCCESS)
3074 return rcStrict;
3075
3076 /*
3077 * Commit the operation.
3078 */
3079 uNewFlags &= X86_EFL_LIVE_MASK;
3080 uNewFlags |= X86_EFL_RA1_MASK;
3081#ifdef DBGFTRACE_ENABLED
3082 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3083 pCtx->cs.Sel, pCtx->eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3084#endif
3085 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pCtx->cs.Sel, pCtx->eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3086
3087 IEMMISC_SET_EFL(pVCpu, pCtx, uNewFlags);
3088 iemCImplCommonV8086LoadSeg(&pCtx->cs, uNewCs);
3089 iemCImplCommonV8086LoadSeg(&pCtx->ss, uNewSs);
3090 iemCImplCommonV8086LoadSeg(&pCtx->es, uNewEs);
3091 iemCImplCommonV8086LoadSeg(&pCtx->ds, uNewDs);
3092 iemCImplCommonV8086LoadSeg(&pCtx->fs, uNewFs);
3093 iemCImplCommonV8086LoadSeg(&pCtx->gs, uNewGs);
3094 pCtx->rip = (uint16_t)uNewEip;
3095 pCtx->rsp = uNewEsp; /** @todo check this out! */
3096 pVCpu->iem.s.uCpl = 3;
3097
3098 /* Flush the prefetch buffer. */
3099#ifdef IEM_WITH_CODE_TLB
3100 pVCpu->iem.s.pbInstrBuf = NULL;
3101#else
3102 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3103#endif
3104
3105 return VINF_SUCCESS;
3106}
3107
3108
3109/**
3110 * Implements iret for protected mode returning via a nested task.
3111 *
3112 * @param enmEffOpSize The effective operand size.
3113 */
3114IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3115{
3116 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3117#ifndef IEM_IMPLEMENTS_TASKSWITCH
3118 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3119#else
3120 RT_NOREF_PV(enmEffOpSize);
3121
3122 /*
3123 * Read the segment selector in the link-field of the current TSS.
3124 */
3125 RTSEL uSelRet;
3126 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
3127 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pCtx->tr.u64Base);
3128 if (rcStrict != VINF_SUCCESS)
3129 return rcStrict;
3130
3131 /*
3132 * Fetch the returning task's TSS descriptor from the GDT.
3133 */
3134 if (uSelRet & X86_SEL_LDT)
3135 {
3136 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3137 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3138 }
3139
3140 IEMSELDESC TssDesc;
3141 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3142 if (rcStrict != VINF_SUCCESS)
3143 return rcStrict;
3144
3145 if (TssDesc.Legacy.Gate.u1DescType)
3146 {
3147 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3148 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3149 }
3150
3151 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3152 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3153 {
3154 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3155 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3156 }
3157
3158 if (!TssDesc.Legacy.Gate.u1Present)
3159 {
3160 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3161 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3162 }
3163
3164 uint32_t uNextEip = pCtx->eip + cbInstr;
3165 return iemTaskSwitch(pVCpu, pCtx, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3166 0 /* uCr2 */, uSelRet, &TssDesc);
3167#endif
3168}
3169
3170
3171/**
3172 * Implements iret for protected mode
3173 *
3174 * @param enmEffOpSize The effective operand size.
3175 */
3176IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3177{
3178 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
3179 NOREF(cbInstr);
3180 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3181
3182 /*
3183 * Nested task return.
3184 */
3185 if (pCtx->eflags.Bits.u1NT)
3186 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3187
3188 /*
3189 * Normal return.
3190 *
3191 * Do the stack bits, but don't commit RSP before everything checks
3192 * out right.
3193 */
3194 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3195 VBOXSTRICTRC rcStrict;
3196 RTCPTRUNION uFrame;
3197 uint16_t uNewCs;
3198 uint32_t uNewEip;
3199 uint32_t uNewFlags;
3200 uint64_t uNewRsp;
3201 if (enmEffOpSize == IEMMODE_32BIT)
3202 {
3203 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
3204 if (rcStrict != VINF_SUCCESS)
3205 return rcStrict;
3206 uNewEip = uFrame.pu32[0];
3207 uNewCs = (uint16_t)uFrame.pu32[1];
3208 uNewFlags = uFrame.pu32[2];
3209 }
3210 else
3211 {
3212 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
3213 if (rcStrict != VINF_SUCCESS)
3214 return rcStrict;
3215 uNewEip = uFrame.pu16[0];
3216 uNewCs = uFrame.pu16[1];
3217 uNewFlags = uFrame.pu16[2];
3218 }
3219 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3220 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3221 { /* extremely likely */ }
3222 else
3223 return rcStrict;
3224 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3225
3226 /*
3227 * We're hopefully not returning to V8086 mode...
3228 */
3229 if ( (uNewFlags & X86_EFL_VM)
3230 && pVCpu->iem.s.uCpl == 0)
3231 {
3232 Assert(enmEffOpSize == IEMMODE_32BIT);
3233 return IEM_CIMPL_CALL_5(iemCImpl_iret_prot_v8086, pCtx, uNewEip, uNewCs, uNewFlags, uNewRsp);
3234 }
3235
3236 /*
3237 * Protected mode.
3238 */
3239 /* Read the CS descriptor. */
3240 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3241 {
3242 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3243 return iemRaiseGeneralProtectionFault0(pVCpu);
3244 }
3245
3246 IEMSELDESC DescCS;
3247 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3248 if (rcStrict != VINF_SUCCESS)
3249 {
3250 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3251 return rcStrict;
3252 }
3253
3254 /* Must be a code descriptor. */
3255 if (!DescCS.Legacy.Gen.u1DescType)
3256 {
3257 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3258 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3259 }
3260 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3261 {
3262 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3263 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3264 }
3265
3266#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3267 /* Raw ring-0 and ring-1 compression adjustments for PATM performance tricks and other CS leaks. */
3268 PVM pVM = pVCpu->CTX_SUFF(pVM);
3269 if (EMIsRawRing0Enabled(pVM) && !HMIsEnabled(pVM))
3270 {
3271 if ((uNewCs & X86_SEL_RPL) == 1)
3272 {
3273 if ( pVCpu->iem.s.uCpl == 0
3274 && ( !EMIsRawRing1Enabled(pVM)
3275 || pCtx->cs.Sel == (uNewCs & X86_SEL_MASK_OFF_RPL)) )
3276 {
3277 Log(("iret: Ring-0 compression fix: uNewCS=%#x -> %#x\n", uNewCs, uNewCs & X86_SEL_MASK_OFF_RPL));
3278 uNewCs &= X86_SEL_MASK_OFF_RPL;
3279 }
3280# ifdef LOG_ENABLED
3281 else if (pVCpu->iem.s.uCpl <= 1 && EMIsRawRing1Enabled(pVM))
3282 Log(("iret: uNewCs=%#x genuine return to ring-1.\n", uNewCs));
3283# endif
3284 }
3285 else if ( (uNewCs & X86_SEL_RPL) == 2
3286 && EMIsRawRing1Enabled(pVM)
3287 && pVCpu->iem.s.uCpl <= 1)
3288 {
3289 Log(("iret: Ring-1 compression fix: uNewCS=%#x -> %#x\n", uNewCs, (uNewCs & X86_SEL_MASK_OFF_RPL) | 1));
3290 uNewCs = (uNewCs & X86_SEL_MASK_OFF_RPL) | 2;
3291 }
3292 }
3293#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
3294
3295
3296 /* Privilege checks. */
3297 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3298 {
3299 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3300 {
3301 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3302 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3303 }
3304 }
3305 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3306 {
3307 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3308 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3309 }
3310 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3311 {
3312 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3313 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3314 }
3315
3316 /* Present? */
3317 if (!DescCS.Legacy.Gen.u1Present)
3318 {
3319 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3320 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3321 }
3322
3323 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3324
3325 /*
3326 * Return to outer level?
3327 */
3328 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3329 {
3330 uint16_t uNewSS;
3331 uint32_t uNewESP;
3332 if (enmEffOpSize == IEMMODE_32BIT)
3333 {
3334 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 8, &uFrame.pv, &uNewRsp);
3335 if (rcStrict != VINF_SUCCESS)
3336 return rcStrict;
3337/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3338 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3339 * bit of the popped SS selector it turns out. */
3340 uNewESP = uFrame.pu32[0];
3341 uNewSS = (uint16_t)uFrame.pu32[1];
3342 }
3343 else
3344 {
3345 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 4, &uFrame.pv, &uNewRsp);
3346 if (rcStrict != VINF_SUCCESS)
3347 return rcStrict;
3348 uNewESP = uFrame.pu16[0];
3349 uNewSS = uFrame.pu16[1];
3350 }
3351 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3352 if (rcStrict != VINF_SUCCESS)
3353 return rcStrict;
3354 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3355
3356 /* Read the SS descriptor. */
3357 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3358 {
3359 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3360 return iemRaiseGeneralProtectionFault0(pVCpu);
3361 }
3362
3363 IEMSELDESC DescSS;
3364 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3365 if (rcStrict != VINF_SUCCESS)
3366 {
3367 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3368 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3369 return rcStrict;
3370 }
3371
3372 /* Privilege checks. */
3373 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3374 {
3375 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3376 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3377 }
3378 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3379 {
3380 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3381 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3382 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3383 }
3384
3385 /* Must be a writeable data segment descriptor. */
3386 if (!DescSS.Legacy.Gen.u1DescType)
3387 {
3388 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3389 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3390 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3391 }
3392 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3393 {
3394 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3395 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3396 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3397 }
3398
3399 /* Present? */
3400 if (!DescSS.Legacy.Gen.u1Present)
3401 {
3402 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3403 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3404 }
3405
3406 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3407
3408 /* Check EIP. */
3409 if (uNewEip > cbLimitCS)
3410 {
3411 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3412 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3413 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3414 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3415 }
3416
3417 /*
3418 * Commit the changes, marking CS and SS accessed first since
3419 * that may fail.
3420 */
3421 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3422 {
3423 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3424 if (rcStrict != VINF_SUCCESS)
3425 return rcStrict;
3426 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3427 }
3428 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3429 {
3430 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3431 if (rcStrict != VINF_SUCCESS)
3432 return rcStrict;
3433 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3434 }
3435
3436 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3437 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3438 if (enmEffOpSize != IEMMODE_16BIT)
3439 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3440 if (pVCpu->iem.s.uCpl == 0)
3441 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3442 else if (pVCpu->iem.s.uCpl <= pCtx->eflags.Bits.u2IOPL)
3443 fEFlagsMask |= X86_EFL_IF;
3444 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3445 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3446 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu, pCtx);
3447 fEFlagsNew &= ~fEFlagsMask;
3448 fEFlagsNew |= uNewFlags & fEFlagsMask;
3449#ifdef DBGFTRACE_ENABLED
3450 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3451 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pCtx->cs.Sel, pCtx->eip,
3452 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3453#endif
3454
3455 IEMMISC_SET_EFL(pVCpu, pCtx, fEFlagsNew);
3456 pCtx->rip = uNewEip;
3457 pCtx->cs.Sel = uNewCs;
3458 pCtx->cs.ValidSel = uNewCs;
3459 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3460 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3461 pCtx->cs.u32Limit = cbLimitCS;
3462 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3463 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
3464
3465 pCtx->ss.Sel = uNewSS;
3466 pCtx->ss.ValidSel = uNewSS;
3467 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3468 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3469 pCtx->ss.u32Limit = cbLimitSs;
3470 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3471 if (!pCtx->ss.Attr.n.u1DefBig)
3472 pCtx->sp = (uint16_t)uNewESP;
3473 else
3474 pCtx->rsp = uNewESP;
3475
3476 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3477 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->ds);
3478 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->es);
3479 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->fs);
3480 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pCtx->gs);
3481
3482 /* Done! */
3483
3484 }
3485 /*
3486 * Return to the same level.
3487 */
3488 else
3489 {
3490 /* Check EIP. */
3491 if (uNewEip > cbLimitCS)
3492 {
3493 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3494 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3495 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3496 }
3497
3498 /*
3499 * Commit the changes, marking CS first since it may fail.
3500 */
3501 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3502 {
3503 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3504 if (rcStrict != VINF_SUCCESS)
3505 return rcStrict;
3506 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3507 }
3508
3509 X86EFLAGS NewEfl;
3510 NewEfl.u = IEMMISC_GET_EFL(pVCpu, pCtx);
3511 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3512 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3513 if (enmEffOpSize != IEMMODE_16BIT)
3514 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3515 if (pVCpu->iem.s.uCpl == 0)
3516 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3517 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3518 fEFlagsMask |= X86_EFL_IF;
3519 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3520 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3521 NewEfl.u &= ~fEFlagsMask;
3522 NewEfl.u |= fEFlagsMask & uNewFlags;
3523#ifdef DBGFTRACE_ENABLED
3524 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3525 pVCpu->iem.s.uCpl, pCtx->cs.Sel, pCtx->eip,
3526 uNewCs, uNewEip, uNewFlags, pCtx->ss.Sel, uNewRsp);
3527#endif
3528
3529 IEMMISC_SET_EFL(pVCpu, pCtx, NewEfl.u);
3530 pCtx->rip = uNewEip;
3531 pCtx->cs.Sel = uNewCs;
3532 pCtx->cs.ValidSel = uNewCs;
3533 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3534 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3535 pCtx->cs.u32Limit = cbLimitCS;
3536 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3537 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
3538 if (!pCtx->ss.Attr.n.u1DefBig)
3539 pCtx->sp = (uint16_t)uNewRsp;
3540 else
3541 pCtx->rsp = uNewRsp;
3542 /* Done! */
3543 }
3544
3545 /* Flush the prefetch buffer. */
3546#ifdef IEM_WITH_CODE_TLB
3547 pVCpu->iem.s.pbInstrBuf = NULL;
3548#else
3549 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3550#endif
3551
3552 return VINF_SUCCESS;
3553}
3554
3555
3556/**
3557 * Implements iret for long mode
3558 *
3559 * @param enmEffOpSize The effective operand size.
3560 */
3561IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3562{
3563 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
3564 NOREF(cbInstr);
3565
3566 /*
3567 * Nested task return is not supported in long mode.
3568 */
3569 if (pCtx->eflags.Bits.u1NT)
3570 {
3571 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pCtx->eflags.u));
3572 return iemRaiseGeneralProtectionFault0(pVCpu);
3573 }
3574
3575 /*
3576 * Normal return.
3577 *
3578 * Do the stack bits, but don't commit RSP before everything checks
3579 * out right.
3580 */
3581 VBOXSTRICTRC rcStrict;
3582 RTCPTRUNION uFrame;
3583 uint64_t uNewRip;
3584 uint16_t uNewCs;
3585 uint16_t uNewSs;
3586 uint32_t uNewFlags;
3587 uint64_t uNewRsp;
3588 if (enmEffOpSize == IEMMODE_64BIT)
3589 {
3590 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, &uFrame.pv, &uNewRsp);
3591 if (rcStrict != VINF_SUCCESS)
3592 return rcStrict;
3593 uNewRip = uFrame.pu64[0];
3594 uNewCs = (uint16_t)uFrame.pu64[1];
3595 uNewFlags = (uint32_t)uFrame.pu64[2];
3596 uNewRsp = uFrame.pu64[3];
3597 uNewSs = (uint16_t)uFrame.pu64[4];
3598 }
3599 else if (enmEffOpSize == IEMMODE_32BIT)
3600 {
3601 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, &uFrame.pv, &uNewRsp);
3602 if (rcStrict != VINF_SUCCESS)
3603 return rcStrict;
3604 uNewRip = uFrame.pu32[0];
3605 uNewCs = (uint16_t)uFrame.pu32[1];
3606 uNewFlags = uFrame.pu32[2];
3607 uNewRsp = uFrame.pu32[3];
3608 uNewSs = (uint16_t)uFrame.pu32[4];
3609 }
3610 else
3611 {
3612 Assert(enmEffOpSize == IEMMODE_16BIT);
3613 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, &uFrame.pv, &uNewRsp);
3614 if (rcStrict != VINF_SUCCESS)
3615 return rcStrict;
3616 uNewRip = uFrame.pu16[0];
3617 uNewCs = uFrame.pu16[1];
3618 uNewFlags = uFrame.pu16[2];
3619 uNewRsp = uFrame.pu16[3];
3620 uNewSs = uFrame.pu16[4];
3621 }
3622 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3623 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3624 { /* extremely like */ }
3625 else
3626 return rcStrict;
3627 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3628
3629 /*
3630 * Check stuff.
3631 */
3632 /* Read the CS descriptor. */
3633 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3634 {
3635 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3636 return iemRaiseGeneralProtectionFault0(pVCpu);
3637 }
3638
3639 IEMSELDESC DescCS;
3640 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3641 if (rcStrict != VINF_SUCCESS)
3642 {
3643 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3644 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3645 return rcStrict;
3646 }
3647
3648 /* Must be a code descriptor. */
3649 if ( !DescCS.Legacy.Gen.u1DescType
3650 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3651 {
3652 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3653 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3654 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3655 }
3656
3657 /* Privilege checks. */
3658 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3659 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3660 {
3661 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3662 {
3663 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3664 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3665 }
3666 }
3667 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3668 {
3669 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3670 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3671 }
3672 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3673 {
3674 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3675 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3676 }
3677
3678 /* Present? */
3679 if (!DescCS.Legacy.Gen.u1Present)
3680 {
3681 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3682 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3683 }
3684
3685 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3686
3687 /* Read the SS descriptor. */
3688 IEMSELDESC DescSS;
3689 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3690 {
3691 if ( !DescCS.Legacy.Gen.u1Long
3692 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3693 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3694 {
3695 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3696 return iemRaiseGeneralProtectionFault0(pVCpu);
3697 }
3698 DescSS.Legacy.u = 0;
3699 }
3700 else
3701 {
3702 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3703 if (rcStrict != VINF_SUCCESS)
3704 {
3705 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3706 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3707 return rcStrict;
3708 }
3709 }
3710
3711 /* Privilege checks. */
3712 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3713 {
3714 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3715 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3716 }
3717
3718 uint32_t cbLimitSs;
3719 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3720 cbLimitSs = UINT32_MAX;
3721 else
3722 {
3723 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3724 {
3725 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3726 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3727 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3728 }
3729
3730 /* Must be a writeable data segment descriptor. */
3731 if (!DescSS.Legacy.Gen.u1DescType)
3732 {
3733 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3734 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3735 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3736 }
3737 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3738 {
3739 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3740 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3741 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3742 }
3743
3744 /* Present? */
3745 if (!DescSS.Legacy.Gen.u1Present)
3746 {
3747 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3748 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3749 }
3750 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3751 }
3752
3753 /* Check EIP. */
3754 if (DescCS.Legacy.Gen.u1Long)
3755 {
3756 if (!IEM_IS_CANONICAL(uNewRip))
3757 {
3758 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3759 uNewCs, uNewRip, uNewSs, uNewRsp));
3760 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3761 }
3762 }
3763 else
3764 {
3765 if (uNewRip > cbLimitCS)
3766 {
3767 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3768 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3769 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3770 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3771 }
3772 }
3773
3774 /*
3775 * Commit the changes, marking CS and SS accessed first since
3776 * that may fail.
3777 */
3778 /** @todo where exactly are these actually marked accessed by a real CPU? */
3779 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3780 {
3781 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3782 if (rcStrict != VINF_SUCCESS)
3783 return rcStrict;
3784 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3785 }
3786 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3787 {
3788 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3789 if (rcStrict != VINF_SUCCESS)
3790 return rcStrict;
3791 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3792 }
3793
3794 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3795 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3796 if (enmEffOpSize != IEMMODE_16BIT)
3797 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3798 if (pVCpu->iem.s.uCpl == 0)
3799 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3800 else if (pVCpu->iem.s.uCpl <= pCtx->eflags.Bits.u2IOPL)
3801 fEFlagsMask |= X86_EFL_IF;
3802 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu, pCtx);
3803 fEFlagsNew &= ~fEFlagsMask;
3804 fEFlagsNew |= uNewFlags & fEFlagsMask;
3805#ifdef DBGFTRACE_ENABLED
3806 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3807 pVCpu->iem.s.uCpl, uNewCpl, pCtx->rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3808#endif
3809
3810 IEMMISC_SET_EFL(pVCpu, pCtx, fEFlagsNew);
3811 pCtx->rip = uNewRip;
3812 pCtx->cs.Sel = uNewCs;
3813 pCtx->cs.ValidSel = uNewCs;
3814 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3815 pCtx->cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3816 pCtx->cs.u32Limit = cbLimitCS;
3817 pCtx->cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3818 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pCtx);
3819 if (pCtx->cs.Attr.n.u1Long || pCtx->cs.Attr.n.u1DefBig)
3820 pCtx->rsp = uNewRsp;
3821 else
3822 pCtx->sp = (uint16_t)uNewRsp;
3823 pCtx->ss.Sel = uNewSs;
3824 pCtx->ss.ValidSel = uNewSs;
3825 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3826 {
3827 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3828 pCtx->ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3829 pCtx->ss.u32Limit = UINT32_MAX;
3830 pCtx->ss.u64Base = 0;
3831 Log2(("iretq new SS: NULL\n"));
3832 }
3833 else
3834 {
3835 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3836 pCtx->ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3837 pCtx->ss.u32Limit = cbLimitSs;
3838 pCtx->ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3839 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u));
3840 }
3841
3842 if (pVCpu->iem.s.uCpl != uNewCpl)
3843 {
3844 pVCpu->iem.s.uCpl = uNewCpl;
3845 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pCtx->ds);
3846 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pCtx->es);
3847 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pCtx->fs);
3848 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pCtx->gs);
3849 }
3850
3851 /* Flush the prefetch buffer. */
3852#ifdef IEM_WITH_CODE_TLB
3853 pVCpu->iem.s.pbInstrBuf = NULL;
3854#else
3855 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3856#endif
3857
3858 return VINF_SUCCESS;
3859}
3860
3861
3862/**
3863 * Implements iret.
3864 *
3865 * @param enmEffOpSize The effective operand size.
3866 */
3867IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3868{
3869 /*
3870 * First, clear NMI blocking, if any, before causing any exceptions.
3871 */
3872 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3873
3874 /*
3875 * The SVM nested-guest intercept for iret takes priority over all exceptions,
3876 * see AMD spec. "15.9 Instruction Intercepts".
3877 */
3878 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3879 {
3880 Log(("iret: Guest intercept -> #VMEXIT\n"));
3881 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3882 }
3883
3884 /*
3885 * Call a mode specific worker.
3886 */
3887 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3888 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3889 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3890 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3891 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3892}
3893
3894
3895/**
3896 * Implements SYSCALL (AMD and Intel64).
3897 *
3898 * @param enmEffOpSize The effective operand size.
3899 */
3900IEM_CIMPL_DEF_0(iemCImpl_syscall)
3901{
3902 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
3903
3904 /*
3905 * Check preconditions.
3906 *
3907 * Note that CPUs described in the documentation may load a few odd values
3908 * into CS and SS than we allow here. This has yet to be checked on real
3909 * hardware.
3910 */
3911 if (!(pCtx->msrEFER & MSR_K6_EFER_SCE))
3912 {
3913 Log(("syscall: Not enabled in EFER -> #UD\n"));
3914 return iemRaiseUndefinedOpcode(pVCpu);
3915 }
3916 if (!(pCtx->cr0 & X86_CR0_PE))
3917 {
3918 Log(("syscall: Protected mode is required -> #GP(0)\n"));
3919 return iemRaiseGeneralProtectionFault0(pVCpu);
3920 }
3921 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(pCtx))
3922 {
3923 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3924 return iemRaiseUndefinedOpcode(pVCpu);
3925 }
3926
3927 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
3928 /** @todo what about LDT selectors? Shouldn't matter, really. */
3929 uint16_t uNewCs = (pCtx->msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
3930 uint16_t uNewSs = uNewCs + 8;
3931 if (uNewCs == 0 || uNewSs == 0)
3932 {
3933 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
3934 return iemRaiseGeneralProtectionFault0(pVCpu);
3935 }
3936
3937 /* Long mode and legacy mode differs. */
3938 if (CPUMIsGuestInLongModeEx(pCtx))
3939 {
3940 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->msrLSTAR : pCtx-> msrCSTAR;
3941
3942 /* This test isn't in the docs, but I'm not trusting the guys writing
3943 the MSRs to have validated the values as canonical like they should. */
3944 if (!IEM_IS_CANONICAL(uNewRip))
3945 {
3946 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3947 return iemRaiseUndefinedOpcode(pVCpu);
3948 }
3949
3950 /*
3951 * Commit it.
3952 */
3953 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, uNewRip));
3954 pCtx->rcx = pCtx->rip + cbInstr;
3955 pCtx->rip = uNewRip;
3956
3957 pCtx->rflags.u &= ~X86_EFL_RF;
3958 pCtx->r11 = pCtx->rflags.u;
3959 pCtx->rflags.u &= ~pCtx->msrSFMASK;
3960 pCtx->rflags.u |= X86_EFL_1;
3961
3962 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3963 pCtx->ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3964 }
3965 else
3966 {
3967 /*
3968 * Commit it.
3969 */
3970 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
3971 pCtx->cs, pCtx->eip, pCtx->eflags.u, uNewCs, (uint32_t)(pCtx->msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
3972 pCtx->rcx = pCtx->eip + cbInstr;
3973 pCtx->rip = pCtx->msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
3974 pCtx->rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
3975
3976 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3977 pCtx->ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3978 }
3979 pCtx->cs.Sel = uNewCs;
3980 pCtx->cs.ValidSel = uNewCs;
3981 pCtx->cs.u64Base = 0;
3982 pCtx->cs.u32Limit = UINT32_MAX;
3983 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
3984
3985 pCtx->ss.Sel = uNewSs;
3986 pCtx->ss.ValidSel = uNewSs;
3987 pCtx->ss.u64Base = 0;
3988 pCtx->ss.u32Limit = UINT32_MAX;
3989 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
3990
3991 /* Flush the prefetch buffer. */
3992#ifdef IEM_WITH_CODE_TLB
3993 pVCpu->iem.s.pbInstrBuf = NULL;
3994#else
3995 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3996#endif
3997
3998 return VINF_SUCCESS;
3999}
4000
4001
4002/**
4003 * Implements SYSRET (AMD and Intel64).
4004 */
4005IEM_CIMPL_DEF_0(iemCImpl_sysret)
4006
4007{
4008 RT_NOREF_PV(cbInstr);
4009 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4010
4011 /*
4012 * Check preconditions.
4013 *
4014 * Note that CPUs described in the documentation may load a few odd values
4015 * into CS and SS than we allow here. This has yet to be checked on real
4016 * hardware.
4017 */
4018 if (!(pCtx->msrEFER & MSR_K6_EFER_SCE))
4019 {
4020 Log(("sysret: Not enabled in EFER -> #UD\n"));
4021 return iemRaiseUndefinedOpcode(pVCpu);
4022 }
4023 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(pCtx))
4024 {
4025 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4026 return iemRaiseUndefinedOpcode(pVCpu);
4027 }
4028 if (!(pCtx->cr0 & X86_CR0_PE))
4029 {
4030 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4031 return iemRaiseGeneralProtectionFault0(pVCpu);
4032 }
4033 if (pVCpu->iem.s.uCpl != 0)
4034 {
4035 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4036 return iemRaiseGeneralProtectionFault0(pVCpu);
4037 }
4038
4039 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4040 uint16_t uNewCs = (pCtx->msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4041 uint16_t uNewSs = uNewCs + 8;
4042 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4043 uNewCs += 16;
4044 if (uNewCs == 0 || uNewSs == 0)
4045 {
4046 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4047 return iemRaiseGeneralProtectionFault0(pVCpu);
4048 }
4049
4050 /*
4051 * Commit it.
4052 */
4053 if (CPUMIsGuestInLongModeEx(pCtx))
4054 {
4055 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4056 {
4057 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
4058 pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, pCtx->rcx, pCtx->r11));
4059 /* Note! We disregard intel manual regarding the RCX cananonical
4060 check, ask intel+xen why AMD doesn't do it. */
4061 pCtx->rip = pCtx->rcx;
4062 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4063 | (3 << X86DESCATTR_DPL_SHIFT);
4064 }
4065 else
4066 {
4067 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
4068 pCtx->cs, pCtx->rip, pCtx->rflags.u, uNewCs, pCtx->ecx, pCtx->r11));
4069 pCtx->rip = pCtx->ecx;
4070 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4071 | (3 << X86DESCATTR_DPL_SHIFT);
4072 }
4073 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4074 * what it really ignores. RF and VM are hinted at being zero, by AMD. */
4075 pCtx->rflags.u = pCtx->r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4076 pCtx->rflags.u |= X86_EFL_1;
4077 }
4078 else
4079 {
4080 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pCtx->cs, pCtx->eip, pCtx->eflags.u, uNewCs, pCtx->ecx));
4081 pCtx->rip = pCtx->rcx;
4082 pCtx->rflags.u |= X86_EFL_IF;
4083 pCtx->cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4084 | (3 << X86DESCATTR_DPL_SHIFT);
4085 }
4086 pCtx->cs.Sel = uNewCs | 3;
4087 pCtx->cs.ValidSel = uNewCs | 3;
4088 pCtx->cs.u64Base = 0;
4089 pCtx->cs.u32Limit = UINT32_MAX;
4090 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
4091
4092 pCtx->ss.Sel = uNewSs | 3;
4093 pCtx->ss.ValidSel = uNewSs | 3;
4094 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
4095 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4096 pCtx->ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4097 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4098 * on sysret. */
4099
4100 /* Flush the prefetch buffer. */
4101#ifdef IEM_WITH_CODE_TLB
4102 pVCpu->iem.s.pbInstrBuf = NULL;
4103#else
4104 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4105#endif
4106
4107 return VINF_SUCCESS;
4108}
4109
4110
4111/**
4112 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4113 *
4114 * @param iSegReg The segment register number (valid).
4115 * @param uSel The new selector value.
4116 */
4117IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4118{
4119 /*PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);*/
4120 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4121 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4122
4123 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4124
4125 /*
4126 * Real mode and V8086 mode are easy.
4127 */
4128 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_16BIT
4129 && IEM_IS_REAL_OR_V86_MODE(pVCpu))
4130 {
4131 *pSel = uSel;
4132 pHid->u64Base = (uint32_t)uSel << 4;
4133 pHid->ValidSel = uSel;
4134 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4135#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4136 /** @todo Does the CPU actually load limits and attributes in the
4137 * real/V8086 mode segment load case? It doesn't for CS in far
4138 * jumps... Affects unreal mode. */
4139 pHid->u32Limit = 0xffff;
4140 pHid->Attr.u = 0;
4141 pHid->Attr.n.u1Present = 1;
4142 pHid->Attr.n.u1DescType = 1;
4143 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4144 ? X86_SEL_TYPE_RW
4145 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4146#endif
4147 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4149 return VINF_SUCCESS;
4150 }
4151
4152 /*
4153 * Protected mode.
4154 *
4155 * Check if it's a null segment selector value first, that's OK for DS, ES,
4156 * FS and GS. If not null, then we have to load and parse the descriptor.
4157 */
4158 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4159 {
4160 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4161 if (iSegReg == X86_SREG_SS)
4162 {
4163 /* In 64-bit kernel mode, the stack can be 0 because of the way
4164 interrupts are dispatched. AMD seems to have a slighly more
4165 relaxed relationship to SS.RPL than intel does. */
4166 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4167 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4168 || pVCpu->iem.s.uCpl > 2
4169 || ( uSel != pVCpu->iem.s.uCpl
4170 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4171 {
4172 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4173 return iemRaiseGeneralProtectionFault0(pVCpu);
4174 }
4175 }
4176
4177 *pSel = uSel; /* Not RPL, remember :-) */
4178 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4179 if (iSegReg == X86_SREG_SS)
4180 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4181
4182 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4183 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4184
4185 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4186 return VINF_SUCCESS;
4187 }
4188
4189 /* Fetch the descriptor. */
4190 IEMSELDESC Desc;
4191 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4192 if (rcStrict != VINF_SUCCESS)
4193 return rcStrict;
4194
4195 /* Check GPs first. */
4196 if (!Desc.Legacy.Gen.u1DescType)
4197 {
4198 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4199 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4200 }
4201 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4202 {
4203 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4204 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4205 {
4206 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4207 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4208 }
4209 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4210 {
4211 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4212 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4213 }
4214 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4215 {
4216 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4217 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4218 }
4219 }
4220 else
4221 {
4222 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4223 {
4224 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4225 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4226 }
4227 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4228 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4229 {
4230#if 0 /* this is what intel says. */
4231 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4232 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4233 {
4234 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4235 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4236 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4237 }
4238#else /* this is what makes more sense. */
4239 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4240 {
4241 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4242 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4243 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4244 }
4245 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4246 {
4247 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4248 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4249 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4250 }
4251#endif
4252 }
4253 }
4254
4255 /* Is it there? */
4256 if (!Desc.Legacy.Gen.u1Present)
4257 {
4258 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4259 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4260 }
4261
4262 /* The base and limit. */
4263 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4264 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4265
4266 /*
4267 * Ok, everything checked out fine. Now set the accessed bit before
4268 * committing the result into the registers.
4269 */
4270 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4271 {
4272 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4273 if (rcStrict != VINF_SUCCESS)
4274 return rcStrict;
4275 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4276 }
4277
4278 /* commit */
4279 *pSel = uSel;
4280 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4281 pHid->u32Limit = cbLimit;
4282 pHid->u64Base = u64Base;
4283 pHid->ValidSel = uSel;
4284 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4285
4286 /** @todo check if the hidden bits are loaded correctly for 64-bit
4287 * mode. */
4288 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4289
4290 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4291 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4292 return VINF_SUCCESS;
4293}
4294
4295
4296/**
4297 * Implements 'mov SReg, r/m'.
4298 *
4299 * @param iSegReg The segment register number (valid).
4300 * @param uSel The new selector value.
4301 */
4302IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4303{
4304 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4305 if (rcStrict == VINF_SUCCESS)
4306 {
4307 if (iSegReg == X86_SREG_SS)
4308 {
4309 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4310 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
4311 }
4312 }
4313 return rcStrict;
4314}
4315
4316
4317/**
4318 * Implements 'pop SReg'.
4319 *
4320 * @param iSegReg The segment register number (valid).
4321 * @param enmEffOpSize The efficient operand size (valid).
4322 */
4323IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4324{
4325 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4326 VBOXSTRICTRC rcStrict;
4327
4328 /*
4329 * Read the selector off the stack and join paths with mov ss, reg.
4330 */
4331 RTUINT64U TmpRsp;
4332 TmpRsp.u = pCtx->rsp;
4333 switch (enmEffOpSize)
4334 {
4335 case IEMMODE_16BIT:
4336 {
4337 uint16_t uSel;
4338 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4339 if (rcStrict == VINF_SUCCESS)
4340 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4341 break;
4342 }
4343
4344 case IEMMODE_32BIT:
4345 {
4346 uint32_t u32Value;
4347 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4348 if (rcStrict == VINF_SUCCESS)
4349 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4350 break;
4351 }
4352
4353 case IEMMODE_64BIT:
4354 {
4355 uint64_t u64Value;
4356 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4357 if (rcStrict == VINF_SUCCESS)
4358 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4359 break;
4360 }
4361 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4362 }
4363
4364 /*
4365 * Commit the stack on success.
4366 */
4367 if (rcStrict == VINF_SUCCESS)
4368 {
4369 pCtx->rsp = TmpRsp.u;
4370 if (iSegReg == X86_SREG_SS)
4371 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
4372 }
4373 return rcStrict;
4374}
4375
4376
4377/**
4378 * Implements lgs, lfs, les, lds & lss.
4379 */
4380IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg,
4381 uint16_t, uSel,
4382 uint64_t, offSeg,
4383 uint8_t, iSegReg,
4384 uint8_t, iGReg,
4385 IEMMODE, enmEffOpSize)
4386{
4387 /*PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);*/
4388 VBOXSTRICTRC rcStrict;
4389
4390 /*
4391 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4392 */
4393 /** @todo verify and test that mov, pop and lXs works the segment
4394 * register loading in the exact same way. */
4395 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4396 if (rcStrict == VINF_SUCCESS)
4397 {
4398 switch (enmEffOpSize)
4399 {
4400 case IEMMODE_16BIT:
4401 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4402 break;
4403 case IEMMODE_32BIT:
4404 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4405 break;
4406 case IEMMODE_64BIT:
4407 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4408 break;
4409 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4410 }
4411 }
4412
4413 return rcStrict;
4414}
4415
4416
4417/**
4418 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4419 *
4420 * @retval VINF_SUCCESS on success.
4421 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4422 * @retval iemMemFetchSysU64 return value.
4423 *
4424 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4425 * @param uSel The selector value.
4426 * @param fAllowSysDesc Whether system descriptors are OK or not.
4427 * @param pDesc Where to return the descriptor on success.
4428 */
4429static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPU pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4430{
4431 pDesc->Long.au64[0] = 0;
4432 pDesc->Long.au64[1] = 0;
4433
4434 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4435 return VINF_IEM_SELECTOR_NOT_OK;
4436
4437 /* Within the table limits? */
4438 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4439 RTGCPTR GCPtrBase;
4440 if (uSel & X86_SEL_LDT)
4441 {
4442 if ( !pCtx->ldtr.Attr.n.u1Present
4443 || (uSel | X86_SEL_RPL_LDT) > pCtx->ldtr.u32Limit )
4444 return VINF_IEM_SELECTOR_NOT_OK;
4445 GCPtrBase = pCtx->ldtr.u64Base;
4446 }
4447 else
4448 {
4449 if ((uSel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
4450 return VINF_IEM_SELECTOR_NOT_OK;
4451 GCPtrBase = pCtx->gdtr.pGdt;
4452 }
4453
4454 /* Fetch the descriptor. */
4455 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4456 if (rcStrict != VINF_SUCCESS)
4457 return rcStrict;
4458 if (!pDesc->Legacy.Gen.u1DescType)
4459 {
4460 if (!fAllowSysDesc)
4461 return VINF_IEM_SELECTOR_NOT_OK;
4462 if (CPUMIsGuestInLongModeEx(pCtx))
4463 {
4464 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4465 if (rcStrict != VINF_SUCCESS)
4466 return rcStrict;
4467 }
4468
4469 }
4470
4471 return VINF_SUCCESS;
4472}
4473
4474
4475/**
4476 * Implements verr (fWrite = false) and verw (fWrite = true).
4477 */
4478IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4479{
4480 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4481
4482 /** @todo figure whether the accessed bit is set or not. */
4483
4484 bool fAccessible = true;
4485 IEMSELDESC Desc;
4486 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4487 if (rcStrict == VINF_SUCCESS)
4488 {
4489 /* Check the descriptor, order doesn't matter much here. */
4490 if ( !Desc.Legacy.Gen.u1DescType
4491 || !Desc.Legacy.Gen.u1Present)
4492 fAccessible = false;
4493 else
4494 {
4495 if ( fWrite
4496 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4497 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4498 fAccessible = false;
4499
4500 /** @todo testcase for the conforming behavior. */
4501 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4502 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4503 {
4504 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4505 fAccessible = false;
4506 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4507 fAccessible = false;
4508 }
4509 }
4510
4511 }
4512 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4513 fAccessible = false;
4514 else
4515 return rcStrict;
4516
4517 /* commit */
4518 IEM_GET_CTX(pVCpu)->eflags.Bits.u1ZF = fAccessible;
4519
4520 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4521 return VINF_SUCCESS;
4522}
4523
4524
4525/**
4526 * Implements LAR and LSL with 64-bit operand size.
4527 *
4528 * @returns VINF_SUCCESS.
4529 * @param pu16Dst Pointer to the destination register.
4530 * @param uSel The selector to load details for.
4531 * @param fIsLar true = LAR, false = LSL.
4532 */
4533IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4534{
4535 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4536
4537 /** @todo figure whether the accessed bit is set or not. */
4538
4539 bool fDescOk = true;
4540 IEMSELDESC Desc;
4541 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4542 if (rcStrict == VINF_SUCCESS)
4543 {
4544 /*
4545 * Check the descriptor type.
4546 */
4547 if (!Desc.Legacy.Gen.u1DescType)
4548 {
4549 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4550 {
4551 if (Desc.Long.Gen.u5Zeros)
4552 fDescOk = false;
4553 else
4554 switch (Desc.Long.Gen.u4Type)
4555 {
4556 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4557 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4558 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4559 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4560 break;
4561 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4562 fDescOk = fIsLar;
4563 break;
4564 default:
4565 fDescOk = false;
4566 break;
4567 }
4568 }
4569 else
4570 {
4571 switch (Desc.Long.Gen.u4Type)
4572 {
4573 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4574 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4575 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4576 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4577 case X86_SEL_TYPE_SYS_LDT:
4578 break;
4579 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4580 case X86_SEL_TYPE_SYS_TASK_GATE:
4581 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4582 fDescOk = fIsLar;
4583 break;
4584 default:
4585 fDescOk = false;
4586 break;
4587 }
4588 }
4589 }
4590 if (fDescOk)
4591 {
4592 /*
4593 * Check the RPL/DPL/CPL interaction..
4594 */
4595 /** @todo testcase for the conforming behavior. */
4596 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4597 || !Desc.Legacy.Gen.u1DescType)
4598 {
4599 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4600 fDescOk = false;
4601 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4602 fDescOk = false;
4603 }
4604 }
4605
4606 if (fDescOk)
4607 {
4608 /*
4609 * All fine, start committing the result.
4610 */
4611 if (fIsLar)
4612 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4613 else
4614 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
4615 }
4616
4617 }
4618 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4619 fDescOk = false;
4620 else
4621 return rcStrict;
4622
4623 /* commit flags value and advance rip. */
4624 IEM_GET_CTX(pVCpu)->eflags.Bits.u1ZF = fDescOk;
4625 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4626
4627 return VINF_SUCCESS;
4628}
4629
4630
4631/**
4632 * Implements LAR and LSL with 16-bit operand size.
4633 *
4634 * @returns VINF_SUCCESS.
4635 * @param pu16Dst Pointer to the destination register.
4636 * @param u16Sel The selector to load details for.
4637 * @param fIsLar true = LAR, false = LSL.
4638 */
4639IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
4640{
4641 uint64_t u64TmpDst = *pu16Dst;
4642 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
4643 *pu16Dst = u64TmpDst;
4644 return VINF_SUCCESS;
4645}
4646
4647
4648/**
4649 * Implements lgdt.
4650 *
4651 * @param iEffSeg The segment of the new gdtr contents
4652 * @param GCPtrEffSrc The address of the new gdtr contents.
4653 * @param enmEffOpSize The effective operand size.
4654 */
4655IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4656{
4657 if (pVCpu->iem.s.uCpl != 0)
4658 return iemRaiseGeneralProtectionFault0(pVCpu);
4659 Assert(!IEM_GET_CTX(pVCpu)->eflags.Bits.u1VM);
4660
4661 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
4662 {
4663 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
4664 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4665 }
4666
4667 /*
4668 * Fetch the limit and base address.
4669 */
4670 uint16_t cbLimit;
4671 RTGCPTR GCPtrBase;
4672 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4673 if (rcStrict == VINF_SUCCESS)
4674 {
4675 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4676 || X86_IS_CANONICAL(GCPtrBase))
4677 {
4678 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
4679 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4680 else
4681 {
4682 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4683 pCtx->gdtr.cbGdt = cbLimit;
4684 pCtx->gdtr.pGdt = GCPtrBase;
4685 }
4686 if (rcStrict == VINF_SUCCESS)
4687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4688 }
4689 else
4690 {
4691 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4692 return iemRaiseGeneralProtectionFault0(pVCpu);
4693 }
4694 }
4695 return rcStrict;
4696}
4697
4698
4699/**
4700 * Implements sgdt.
4701 *
4702 * @param iEffSeg The segment where to store the gdtr content.
4703 * @param GCPtrEffDst The address where to store the gdtr content.
4704 */
4705IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4706{
4707 /*
4708 * Join paths with sidt.
4709 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4710 * you really must know.
4711 */
4712 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4713 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pCtx->gdtr.cbGdt, pCtx->gdtr.pGdt, iEffSeg, GCPtrEffDst);
4714 if (rcStrict == VINF_SUCCESS)
4715 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4716 return rcStrict;
4717}
4718
4719
4720/**
4721 * Implements lidt.
4722 *
4723 * @param iEffSeg The segment of the new idtr contents
4724 * @param GCPtrEffSrc The address of the new idtr contents.
4725 * @param enmEffOpSize The effective operand size.
4726 */
4727IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4728{
4729 if (pVCpu->iem.s.uCpl != 0)
4730 return iemRaiseGeneralProtectionFault0(pVCpu);
4731 Assert(!IEM_GET_CTX(pVCpu)->eflags.Bits.u1VM);
4732
4733 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
4734 {
4735 Log(("lidt: Guest intercept -> #VMEXIT\n"));
4736 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4737 }
4738
4739 /*
4740 * Fetch the limit and base address.
4741 */
4742 uint16_t cbLimit;
4743 RTGCPTR GCPtrBase;
4744 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4745 if (rcStrict == VINF_SUCCESS)
4746 {
4747 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4748 || X86_IS_CANONICAL(GCPtrBase))
4749 {
4750 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
4751 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4752 else
4753 {
4754 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4755 pCtx->idtr.cbIdt = cbLimit;
4756 pCtx->idtr.pIdt = GCPtrBase;
4757 }
4758 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4759 }
4760 else
4761 {
4762 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4763 return iemRaiseGeneralProtectionFault0(pVCpu);
4764 }
4765 }
4766 return rcStrict;
4767}
4768
4769
4770/**
4771 * Implements sidt.
4772 *
4773 * @param iEffSeg The segment where to store the idtr content.
4774 * @param GCPtrEffDst The address where to store the idtr content.
4775 */
4776IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4777{
4778 /*
4779 * Join paths with sgdt.
4780 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4781 * you really must know.
4782 */
4783 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4784 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pCtx->idtr.cbIdt, pCtx->idtr.pIdt, iEffSeg, GCPtrEffDst);
4785 if (rcStrict == VINF_SUCCESS)
4786 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4787 return rcStrict;
4788}
4789
4790
4791/**
4792 * Implements lldt.
4793 *
4794 * @param uNewLdt The new LDT selector value.
4795 */
4796IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
4797{
4798 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4799
4800 /*
4801 * Check preconditions.
4802 */
4803 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4804 {
4805 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
4806 return iemRaiseUndefinedOpcode(pVCpu);
4807 }
4808 if (pVCpu->iem.s.uCpl != 0)
4809 {
4810 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
4811 return iemRaiseGeneralProtectionFault0(pVCpu);
4812 }
4813 if (uNewLdt & X86_SEL_LDT)
4814 {
4815 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
4816 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
4817 }
4818
4819 /*
4820 * Now, loading a NULL selector is easy.
4821 */
4822 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
4823 {
4824 /* Nested-guest SVM intercept. */
4825 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4826 {
4827 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4828 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4829 }
4830
4831 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
4832 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
4833 CPUMSetGuestLDTR(pVCpu, uNewLdt);
4834 else
4835 pCtx->ldtr.Sel = uNewLdt;
4836 pCtx->ldtr.ValidSel = uNewLdt;
4837 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4838 if (IEM_FULL_VERIFICATION_REM_ENABLED(pVCpu))
4839 {
4840 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4841 pCtx->ldtr.u64Base = pCtx->ldtr.u32Limit = 0; /* For verfication against REM. */
4842 }
4843 else if (IEM_IS_GUEST_CPU_AMD(pVCpu))
4844 {
4845 /* AMD-V seems to leave the base and limit alone. */
4846 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4847 }
4848 else if (!IEM_FULL_VERIFICATION_REM_ENABLED(pVCpu))
4849 {
4850 /* VT-x (Intel 3960x) seems to be doing the following. */
4851 pCtx->ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
4852 pCtx->ldtr.u64Base = 0;
4853 pCtx->ldtr.u32Limit = UINT32_MAX;
4854 }
4855
4856 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4857 return VINF_SUCCESS;
4858 }
4859
4860 /*
4861 * Read the descriptor.
4862 */
4863 IEMSELDESC Desc;
4864 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
4865 if (rcStrict != VINF_SUCCESS)
4866 return rcStrict;
4867
4868 /* Check GPs first. */
4869 if (Desc.Legacy.Gen.u1DescType)
4870 {
4871 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4872 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4873 }
4874 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
4875 {
4876 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4877 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4878 }
4879 uint64_t u64Base;
4880 if (!IEM_IS_LONG_MODE(pVCpu))
4881 u64Base = X86DESC_BASE(&Desc.Legacy);
4882 else
4883 {
4884 if (Desc.Long.Gen.u5Zeros)
4885 {
4886 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
4887 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4888 }
4889
4890 u64Base = X86DESC64_BASE(&Desc.Long);
4891 if (!IEM_IS_CANONICAL(u64Base))
4892 {
4893 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
4894 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4895 }
4896 }
4897
4898 /* NP */
4899 if (!Desc.Legacy.Gen.u1Present)
4900 {
4901 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
4902 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
4903 }
4904
4905 /* Nested-guest SVM intercept. */
4906 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4907 {
4908 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4909 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4910 }
4911
4912 /*
4913 * It checks out alright, update the registers.
4914 */
4915/** @todo check if the actual value is loaded or if the RPL is dropped */
4916 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
4917 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4918 else
4919 pCtx->ldtr.Sel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4920 pCtx->ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4921 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4922 pCtx->ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4923 pCtx->ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
4924 pCtx->ldtr.u64Base = u64Base;
4925
4926 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4927 return VINF_SUCCESS;
4928}
4929
4930
4931/**
4932 * Implements lldt.
4933 *
4934 * @param uNewLdt The new LDT selector value.
4935 */
4936IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
4937{
4938 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
4939
4940 /*
4941 * Check preconditions.
4942 */
4943 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4944 {
4945 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
4946 return iemRaiseUndefinedOpcode(pVCpu);
4947 }
4948 if (pVCpu->iem.s.uCpl != 0)
4949 {
4950 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
4951 return iemRaiseGeneralProtectionFault0(pVCpu);
4952 }
4953 if (uNewTr & X86_SEL_LDT)
4954 {
4955 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
4956 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
4957 }
4958 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
4959 {
4960 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
4961 return iemRaiseGeneralProtectionFault0(pVCpu);
4962 }
4963 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
4964 {
4965 Log(("ltr: Guest intercept -> #VMEXIT\n"));
4966 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4967 }
4968
4969 /*
4970 * Read the descriptor.
4971 */
4972 IEMSELDESC Desc;
4973 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
4974 if (rcStrict != VINF_SUCCESS)
4975 return rcStrict;
4976
4977 /* Check GPs first. */
4978 if (Desc.Legacy.Gen.u1DescType)
4979 {
4980 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4981 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4982 }
4983 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
4984 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
4985 || IEM_IS_LONG_MODE(pVCpu)) )
4986 {
4987 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
4988 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4989 }
4990 uint64_t u64Base;
4991 if (!IEM_IS_LONG_MODE(pVCpu))
4992 u64Base = X86DESC_BASE(&Desc.Legacy);
4993 else
4994 {
4995 if (Desc.Long.Gen.u5Zeros)
4996 {
4997 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
4998 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
4999 }
5000
5001 u64Base = X86DESC64_BASE(&Desc.Long);
5002 if (!IEM_IS_CANONICAL(u64Base))
5003 {
5004 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5005 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5006 }
5007 }
5008
5009 /* NP */
5010 if (!Desc.Legacy.Gen.u1Present)
5011 {
5012 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5013 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5014 }
5015
5016 /*
5017 * Set it busy.
5018 * Note! Intel says this should lock down the whole descriptor, but we'll
5019 * restrict our selves to 32-bit for now due to lack of inline
5020 * assembly and such.
5021 */
5022 void *pvDesc;
5023 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pCtx->gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL), IEM_ACCESS_DATA_RW);
5024 if (rcStrict != VINF_SUCCESS)
5025 return rcStrict;
5026 switch ((uintptr_t)pvDesc & 3)
5027 {
5028 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5029 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5030 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5031 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5032 }
5033 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5034 if (rcStrict != VINF_SUCCESS)
5035 return rcStrict;
5036 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5037
5038 /*
5039 * It checks out alright, update the registers.
5040 */
5041/** @todo check if the actual value is loaded or if the RPL is dropped */
5042 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5043 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5044 else
5045 pCtx->tr.Sel = uNewTr & X86_SEL_MASK_OFF_RPL;
5046 pCtx->tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5047 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
5048 pCtx->tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5049 pCtx->tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5050 pCtx->tr.u64Base = u64Base;
5051
5052 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5053 return VINF_SUCCESS;
5054}
5055
5056
5057/**
5058 * Implements mov GReg,CRx.
5059 *
5060 * @param iGReg The general register to store the CRx value in.
5061 * @param iCrReg The CRx register to read (valid).
5062 */
5063IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5064{
5065 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5066 if (pVCpu->iem.s.uCpl != 0)
5067 return iemRaiseGeneralProtectionFault0(pVCpu);
5068 Assert(!pCtx->eflags.Bits.u1VM);
5069
5070 if (IEM_IS_SVM_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5071 {
5072 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5073 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5074 }
5075
5076 /* read it */
5077 uint64_t crX;
5078 switch (iCrReg)
5079 {
5080 case 0:
5081 crX = pCtx->cr0;
5082 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5083 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5084 break;
5085 case 2: crX = pCtx->cr2; break;
5086 case 3: crX = pCtx->cr3; break;
5087 case 4: crX = pCtx->cr4; break;
5088 case 8:
5089 {
5090#ifdef VBOX_WITH_NESTED_HWVIRT
5091 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5092 if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)
5093 {
5094 crX = pVmcbCtrl->IntCtrl.n.u8VTPR;
5095 break;
5096 }
5097#endif
5098 uint8_t uTpr;
5099 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5100 if (RT_SUCCESS(rc))
5101 crX = uTpr >> 4;
5102 else
5103 crX = 0;
5104 break;
5105 }
5106 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5107 }
5108
5109 /* store it */
5110 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5111 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5112 else
5113 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5114
5115 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5116 return VINF_SUCCESS;
5117}
5118
5119
5120/**
5121 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5122 *
5123 * @param iCrReg The CRx register to write (valid).
5124 * @param uNewCrX The new value.
5125 * @param enmAccessCrx The instruction that caused the CrX load.
5126 * @param iGReg The general register in case of a 'mov CRx,GReg'
5127 * instruction.
5128 */
5129IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5130{
5131 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5132 VBOXSTRICTRC rcStrict;
5133 int rc;
5134#ifndef VBOX_WITH_NESTED_HWVIRT
5135 RT_NOREF2(iGReg, enmAccessCrX);
5136#endif
5137
5138 /*
5139 * Try store it.
5140 * Unfortunately, CPUM only does a tiny bit of the work.
5141 */
5142 switch (iCrReg)
5143 {
5144 case 0:
5145 {
5146 /*
5147 * Perform checks.
5148 */
5149 uint64_t const uOldCrX = pCtx->cr0;
5150 uint32_t const fValid = X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
5151 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
5152 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG;
5153
5154 /* ET is hardcoded on 486 and later. */
5155 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5156 uNewCrX |= X86_CR0_ET;
5157 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5158 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5159 {
5160 uNewCrX &= fValid;
5161 uNewCrX |= X86_CR0_ET;
5162 }
5163 else
5164 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5165
5166 /* Check for reserved bits. */
5167 if (uNewCrX & ~(uint64_t)fValid)
5168 {
5169 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5170 return iemRaiseGeneralProtectionFault0(pVCpu);
5171 }
5172
5173 /* Check for invalid combinations. */
5174 if ( (uNewCrX & X86_CR0_PG)
5175 && !(uNewCrX & X86_CR0_PE) )
5176 {
5177 Log(("Trying to set CR0.PG without CR0.PE\n"));
5178 return iemRaiseGeneralProtectionFault0(pVCpu);
5179 }
5180
5181 if ( !(uNewCrX & X86_CR0_CD)
5182 && (uNewCrX & X86_CR0_NW) )
5183 {
5184 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5185 return iemRaiseGeneralProtectionFault0(pVCpu);
5186 }
5187
5188 if ( !(uNewCrX & X86_CR0_PG)
5189 && (pCtx->cr4 & X86_CR4_PCIDE))
5190 {
5191 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5192 return iemRaiseGeneralProtectionFault0(pVCpu);
5193 }
5194
5195 /* Long mode consistency checks. */
5196 if ( (uNewCrX & X86_CR0_PG)
5197 && !(uOldCrX & X86_CR0_PG)
5198 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
5199 {
5200 if (!(pCtx->cr4 & X86_CR4_PAE))
5201 {
5202 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5203 return iemRaiseGeneralProtectionFault0(pVCpu);
5204 }
5205 if (pCtx->cs.Attr.n.u1Long)
5206 {
5207 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5208 return iemRaiseGeneralProtectionFault0(pVCpu);
5209 }
5210 }
5211
5212 /** @todo check reserved PDPTR bits as AMD states. */
5213
5214 /*
5215 * SVM nested-guest CR0 write intercepts.
5216 */
5217 if (IEM_IS_SVM_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5218 {
5219 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5220 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5221 }
5222 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITES))
5223 {
5224 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5225 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5226 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5227 {
5228 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5229 Log(("iemCImpl_load_Cr%#x: TS/MP bit changed or lmsw instr: Guest intercept -> #VMEXIT\n", iCrReg));
5230 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CR0_SEL_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5231 }
5232 }
5233
5234 /*
5235 * Change CR0.
5236 */
5237 if (!IEM_VERIFICATION_ENABLED(pVCpu))
5238 CPUMSetGuestCR0(pVCpu, uNewCrX);
5239 else
5240 pCtx->cr0 = uNewCrX;
5241 Assert(pCtx->cr0 == uNewCrX);
5242
5243 /*
5244 * Change EFER.LMA if entering or leaving long mode.
5245 */
5246 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5247 && (pCtx->msrEFER & MSR_K6_EFER_LME) )
5248 {
5249 uint64_t NewEFER = pCtx->msrEFER;
5250 if (uNewCrX & X86_CR0_PG)
5251 NewEFER |= MSR_K6_EFER_LMA;
5252 else
5253 NewEFER &= ~MSR_K6_EFER_LMA;
5254
5255 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5256 CPUMSetGuestEFER(pVCpu, NewEFER);
5257 else
5258 pCtx->msrEFER = NewEFER;
5259 Assert(pCtx->msrEFER == NewEFER);
5260 }
5261
5262 /*
5263 * Inform PGM.
5264 */
5265 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5266 {
5267 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
5268 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
5269 {
5270 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
5271 AssertRCReturn(rc, rc);
5272 /* ignore informational status codes */
5273 }
5274 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
5275 }
5276 else
5277 rcStrict = VINF_SUCCESS;
5278
5279#ifdef IN_RC
5280 /* Return to ring-3 for rescheduling if WP or AM changes. */
5281 if ( rcStrict == VINF_SUCCESS
5282 && ( (uNewCrX & (X86_CR0_WP | X86_CR0_AM))
5283 != (uOldCrX & (X86_CR0_WP | X86_CR0_AM))) )
5284 rcStrict = VINF_EM_RESCHEDULE;
5285#endif
5286 break;
5287 }
5288
5289 /*
5290 * CR2 can be changed without any restrictions.
5291 */
5292 case 2:
5293 {
5294 if (IEM_IS_SVM_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5295 {
5296 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5297 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5298 }
5299 pCtx->cr2 = uNewCrX;
5300 rcStrict = VINF_SUCCESS;
5301 break;
5302 }
5303
5304 /*
5305 * CR3 is relatively simple, although AMD and Intel have different
5306 * accounts of how setting reserved bits are handled. We take intel's
5307 * word for the lower bits and AMD's for the high bits (63:52). The
5308 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5309 * on this.
5310 */
5311 /** @todo Testcase: Setting reserved bits in CR3, especially before
5312 * enabling paging. */
5313 case 3:
5314 {
5315 /* clear bit 63 from the source operand and indicate no invalidations are required. */
5316 if ( (pCtx->cr4 & X86_CR4_PCIDE)
5317 && (uNewCrX & RT_BIT_64(63)))
5318 {
5319 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
5320 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
5321 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
5322 * Paging-Structure Caches". */
5323 uNewCrX &= ~RT_BIT_64(63);
5324 }
5325
5326 /* check / mask the value. */
5327 if (uNewCrX & UINT64_C(0xfff0000000000000))
5328 {
5329 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
5330 return iemRaiseGeneralProtectionFault0(pVCpu);
5331 }
5332
5333 uint64_t fValid;
5334 if ( (pCtx->cr4 & X86_CR4_PAE)
5335 && (pCtx->msrEFER & MSR_K6_EFER_LME))
5336 fValid = UINT64_C(0x000fffffffffffff);
5337 else
5338 fValid = UINT64_C(0xffffffff);
5339 if (uNewCrX & ~fValid)
5340 {
5341 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
5342 uNewCrX, uNewCrX & ~fValid));
5343 uNewCrX &= fValid;
5344 }
5345
5346 if (IEM_IS_SVM_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
5347 {
5348 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5349 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
5350 }
5351
5352 /** @todo If we're in PAE mode we should check the PDPTRs for
5353 * invalid bits. */
5354
5355 /* Make the change. */
5356 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5357 {
5358 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
5359 AssertRCSuccessReturn(rc, rc);
5360 }
5361 else
5362 pCtx->cr3 = uNewCrX;
5363
5364 /* Inform PGM. */
5365 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5366 {
5367 if (pCtx->cr0 & X86_CR0_PG)
5368 {
5369 rc = PGMFlushTLB(pVCpu, pCtx->cr3, !(pCtx->cr4 & X86_CR4_PGE));
5370 AssertRCReturn(rc, rc);
5371 /* ignore informational status codes */
5372 }
5373 }
5374 rcStrict = VINF_SUCCESS;
5375 break;
5376 }
5377
5378 /*
5379 * CR4 is a bit more tedious as there are bits which cannot be cleared
5380 * under some circumstances and such.
5381 */
5382 case 4:
5383 {
5384 uint64_t const uOldCrX = pCtx->cr4;
5385
5386 /** @todo Shouldn't this look at the guest CPUID bits to determine
5387 * valid bits? e.g. if guest CPUID doesn't allow X86_CR4_OSXMMEEXCPT, we
5388 * should #GP(0). */
5389 /* reserved bits */
5390 uint32_t fValid = X86_CR4_VME | X86_CR4_PVI
5391 | X86_CR4_TSD | X86_CR4_DE
5392 | X86_CR4_PSE | X86_CR4_PAE
5393 | X86_CR4_MCE | X86_CR4_PGE
5394 | X86_CR4_PCE | X86_CR4_OSFXSR
5395 | X86_CR4_OSXMMEEXCPT;
5396 //if (xxx)
5397 // fValid |= X86_CR4_VMXE;
5398 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
5399 fValid |= X86_CR4_OSXSAVE;
5400 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPcid)
5401 fValid |= X86_CR4_PCIDE;
5402 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase)
5403 fValid |= X86_CR4_FSGSBASE;
5404 if (uNewCrX & ~(uint64_t)fValid)
5405 {
5406 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5407 return iemRaiseGeneralProtectionFault0(pVCpu);
5408 }
5409
5410 bool const fPcide = ((uNewCrX ^ uOldCrX) & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
5411 bool const fLongMode = CPUMIsGuestInLongModeEx(pCtx);
5412
5413 /* PCIDE check. */
5414 if ( fPcide
5415 && ( !fLongMode
5416 || (pCtx->cr3 & UINT64_C(0xfff))))
5417 {
5418 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pCtx->cr3 & UINT64_C(0xfff))));
5419 return iemRaiseGeneralProtectionFault0(pVCpu);
5420 }
5421
5422 /* PAE check. */
5423 if ( fLongMode
5424 && (uOldCrX & X86_CR4_PAE)
5425 && !(uNewCrX & X86_CR4_PAE))
5426 {
5427 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
5428 return iemRaiseGeneralProtectionFault0(pVCpu);
5429 }
5430
5431 if (IEM_IS_SVM_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
5432 {
5433 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5434 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
5435 }
5436
5437 /*
5438 * Change it.
5439 */
5440 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5441 {
5442 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
5443 AssertRCSuccessReturn(rc, rc);
5444 }
5445 else
5446 pCtx->cr4 = uNewCrX;
5447 Assert(pCtx->cr4 == uNewCrX);
5448
5449 /*
5450 * Notify SELM and PGM.
5451 */
5452 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5453 {
5454 /* SELM - VME may change things wrt to the TSS shadowing. */
5455 if ((uNewCrX ^ uOldCrX) & X86_CR4_VME)
5456 {
5457 Log(("iemCImpl_load_CrX: VME %d -> %d => Setting VMCPU_FF_SELM_SYNC_TSS\n",
5458 RT_BOOL(uOldCrX & X86_CR4_VME), RT_BOOL(uNewCrX & X86_CR4_VME) ));
5459#ifdef VBOX_WITH_RAW_MODE
5460 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
5461 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
5462#endif
5463 }
5464
5465 /* PGM - flushing and mode. */
5466 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
5467 {
5468 rc = PGMFlushTLB(pVCpu, pCtx->cr3, true /* global */);
5469 AssertRCReturn(rc, rc);
5470 /* ignore informational status codes */
5471 }
5472 rcStrict = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
5473 }
5474 else
5475 rcStrict = VINF_SUCCESS;
5476 break;
5477 }
5478
5479 /*
5480 * CR8 maps to the APIC TPR.
5481 */
5482 case 8:
5483 {
5484 if (uNewCrX & ~(uint64_t)0xf)
5485 {
5486 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
5487 return iemRaiseGeneralProtectionFault0(pVCpu);
5488 }
5489
5490 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
5491#ifdef VBOX_WITH_NESTED_HWVIRT
5492 if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5493 {
5494 if (IEM_IS_SVM_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
5495 {
5496 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5497 IEM_RETURN_SVM_CRX_VMEXIT(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
5498 }
5499
5500 PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5501 pVmcbCtrl->IntCtrl.n.u8VTPR = u8Tpr;
5502 if (pVmcbCtrl->IntCtrl.n.u1VIntrMasking)
5503 {
5504 rcStrict = VINF_SUCCESS;
5505 break;
5506 }
5507 }
5508#endif
5509 if (!IEM_FULL_VERIFICATION_ENABLED(pVCpu))
5510 APICSetTpr(pVCpu, u8Tpr);
5511 rcStrict = VINF_SUCCESS;
5512 break;
5513 }
5514
5515 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5516 }
5517
5518 /*
5519 * Advance the RIP on success.
5520 */
5521 if (RT_SUCCESS(rcStrict))
5522 {
5523 if (rcStrict != VINF_SUCCESS)
5524 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
5525 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5526 }
5527
5528 return rcStrict;
5529}
5530
5531
5532/**
5533 * Implements mov CRx,GReg.
5534 *
5535 * @param iCrReg The CRx register to write (valid).
5536 * @param iGReg The general register to load the DRx value from.
5537 */
5538IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
5539{
5540 if (pVCpu->iem.s.uCpl != 0)
5541 return iemRaiseGeneralProtectionFault0(pVCpu);
5542 Assert(!IEM_GET_CTX(pVCpu)->eflags.Bits.u1VM);
5543
5544 /*
5545 * Read the new value from the source register and call common worker.
5546 */
5547 uint64_t uNewCrX;
5548 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5549 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
5550 else
5551 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
5552 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
5553}
5554
5555
5556/**
5557 * Implements 'LMSW r/m16'
5558 *
5559 * @param u16NewMsw The new value.
5560 */
5561IEM_CIMPL_DEF_1(iemCImpl_lmsw, uint16_t, u16NewMsw)
5562{
5563 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5564
5565 if (pVCpu->iem.s.uCpl != 0)
5566 return iemRaiseGeneralProtectionFault0(pVCpu);
5567 Assert(!pCtx->eflags.Bits.u1VM);
5568
5569 /*
5570 * Compose the new CR0 value and call common worker.
5571 */
5572 uint64_t uNewCr0 = pCtx->cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5573 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5574 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
5575}
5576
5577
5578/**
5579 * Implements 'CLTS'.
5580 */
5581IEM_CIMPL_DEF_0(iemCImpl_clts)
5582{
5583 if (pVCpu->iem.s.uCpl != 0)
5584 return iemRaiseGeneralProtectionFault0(pVCpu);
5585
5586 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5587 uint64_t uNewCr0 = pCtx->cr0;
5588 uNewCr0 &= ~X86_CR0_TS;
5589 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
5590}
5591
5592
5593/**
5594 * Implements mov GReg,DRx.
5595 *
5596 * @param iGReg The general register to store the DRx value in.
5597 * @param iDrReg The DRx register to read (0-7).
5598 */
5599IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
5600{
5601 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5602
5603 /*
5604 * Check preconditions.
5605 */
5606
5607 /* Raise GPs. */
5608 if (pVCpu->iem.s.uCpl != 0)
5609 return iemRaiseGeneralProtectionFault0(pVCpu);
5610 Assert(!pCtx->eflags.Bits.u1VM);
5611
5612 if ( (iDrReg == 4 || iDrReg == 5)
5613 && (pCtx->cr4 & X86_CR4_DE) )
5614 {
5615 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
5616 return iemRaiseGeneralProtectionFault0(pVCpu);
5617 }
5618
5619 /* Raise #DB if general access detect is enabled. */
5620 if (pCtx->dr[7] & X86_DR7_GD)
5621 {
5622 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
5623 return iemRaiseDebugException(pVCpu);
5624 }
5625
5626 /*
5627 * Read the debug register and store it in the specified general register.
5628 */
5629 uint64_t drX;
5630 switch (iDrReg)
5631 {
5632 case 0: drX = pCtx->dr[0]; break;
5633 case 1: drX = pCtx->dr[1]; break;
5634 case 2: drX = pCtx->dr[2]; break;
5635 case 3: drX = pCtx->dr[3]; break;
5636 case 6:
5637 case 4:
5638 drX = pCtx->dr[6];
5639 drX |= X86_DR6_RA1_MASK;
5640 drX &= ~X86_DR6_RAZ_MASK;
5641 break;
5642 case 7:
5643 case 5:
5644 drX = pCtx->dr[7];
5645 drX |=X86_DR7_RA1_MASK;
5646 drX &= ~X86_DR7_RAZ_MASK;
5647 break;
5648 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5649 }
5650
5651 /** @todo SVM nested-guest intercept for DR8-DR15? */
5652 /*
5653 * Check for any SVM nested-guest intercepts for the DRx read.
5654 */
5655 if (IEM_IS_SVM_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
5656 {
5657 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
5658 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
5659 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
5660 }
5661
5662 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5663 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
5664 else
5665 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
5666
5667 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5668 return VINF_SUCCESS;
5669}
5670
5671
5672/**
5673 * Implements mov DRx,GReg.
5674 *
5675 * @param iDrReg The DRx register to write (valid).
5676 * @param iGReg The general register to load the DRx value from.
5677 */
5678IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
5679{
5680 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5681
5682 /*
5683 * Check preconditions.
5684 */
5685 if (pVCpu->iem.s.uCpl != 0)
5686 return iemRaiseGeneralProtectionFault0(pVCpu);
5687 Assert(!pCtx->eflags.Bits.u1VM);
5688
5689 if (iDrReg == 4 || iDrReg == 5)
5690 {
5691 if (pCtx->cr4 & X86_CR4_DE)
5692 {
5693 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
5694 return iemRaiseGeneralProtectionFault0(pVCpu);
5695 }
5696 iDrReg += 2;
5697 }
5698
5699 /* Raise #DB if general access detect is enabled. */
5700 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
5701 * \#GP? */
5702 if (pCtx->dr[7] & X86_DR7_GD)
5703 {
5704 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
5705 return iemRaiseDebugException(pVCpu);
5706 }
5707
5708 /*
5709 * Read the new value from the source register.
5710 */
5711 uint64_t uNewDrX;
5712 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5713 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
5714 else
5715 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
5716
5717 /*
5718 * Adjust it.
5719 */
5720 switch (iDrReg)
5721 {
5722 case 0:
5723 case 1:
5724 case 2:
5725 case 3:
5726 /* nothing to adjust */
5727 break;
5728
5729 case 6:
5730 if (uNewDrX & X86_DR6_MBZ_MASK)
5731 {
5732 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5733 return iemRaiseGeneralProtectionFault0(pVCpu);
5734 }
5735 uNewDrX |= X86_DR6_RA1_MASK;
5736 uNewDrX &= ~X86_DR6_RAZ_MASK;
5737 break;
5738
5739 case 7:
5740 if (uNewDrX & X86_DR7_MBZ_MASK)
5741 {
5742 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
5743 return iemRaiseGeneralProtectionFault0(pVCpu);
5744 }
5745 uNewDrX |= X86_DR7_RA1_MASK;
5746 uNewDrX &= ~X86_DR7_RAZ_MASK;
5747 break;
5748
5749 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5750 }
5751
5752 /** @todo SVM nested-guest intercept for DR8-DR15? */
5753 /*
5754 * Check for any SVM nested-guest intercepts for the DRx write.
5755 */
5756 if (IEM_IS_SVM_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
5757 {
5758 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
5759 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
5760 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
5761 }
5762
5763 /*
5764 * Do the actual setting.
5765 */
5766 if (!IEM_VERIFICATION_ENABLED(pVCpu))
5767 {
5768 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
5769 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
5770 }
5771 else
5772 pCtx->dr[iDrReg] = uNewDrX;
5773
5774 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5775 return VINF_SUCCESS;
5776}
5777
5778
5779/**
5780 * Implements 'INVLPG m'.
5781 *
5782 * @param GCPtrPage The effective address of the page to invalidate.
5783 * @remarks Updates the RIP.
5784 */
5785IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
5786{
5787 /* ring-0 only. */
5788 if (pVCpu->iem.s.uCpl != 0)
5789 return iemRaiseGeneralProtectionFault0(pVCpu);
5790 Assert(!IEM_GET_CTX(pVCpu)->eflags.Bits.u1VM);
5791
5792 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
5793 {
5794 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
5795 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPG,
5796 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
5797 }
5798
5799 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
5800 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5801
5802 if (rc == VINF_SUCCESS)
5803 return VINF_SUCCESS;
5804 if (rc == VINF_PGM_SYNC_CR3)
5805 return iemSetPassUpStatus(pVCpu, rc);
5806
5807 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
5808 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
5809 return rc;
5810}
5811
5812
5813/**
5814 * Implements INVPCID.
5815 *
5816 * @param uInvpcidType The invalidation type.
5817 * @param GCPtrInvpcidDesc The effective address of invpcid descriptor.
5818 * @remarks Updates the RIP.
5819 */
5820IEM_CIMPL_DEF_2(iemCImpl_invpcid, uint64_t, uInvpcidType, RTGCPTR, GCPtrInvpcidDesc)
5821{
5822 /*
5823 * Check preconditions.
5824 */
5825 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
5826 return iemRaiseUndefinedOpcode(pVCpu);
5827 if (pVCpu->iem.s.uCpl != 0)
5828 {
5829 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
5830 return iemRaiseGeneralProtectionFault0(pVCpu);
5831 }
5832 if (IEM_IS_V86_MODE(pVCpu))
5833 {
5834 Log(("invpcid: v8086 mode -> #GP(0)\n"));
5835 return iemRaiseGeneralProtectionFault0(pVCpu);
5836 }
5837 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
5838 {
5839 Log(("invpcid: invalid/unrecognized invpcid type %#x -> #GP(0)\n", uInvpcidType));
5840 return iemRaiseGeneralProtectionFault0(pVCpu);
5841 }
5842
5843 /*
5844 * Fetch the invpcid descriptor from guest memory.
5845 */
5846 RTUINT128U uDesc;
5847 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, pVCpu->iem.s.iEffSeg, GCPtrInvpcidDesc);
5848 if (rcStrict == VINF_SUCCESS)
5849 {
5850 /*
5851 * Validate the descriptor.
5852 */
5853 if (uDesc.s.Lo > 0xfff)
5854 {
5855 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
5856 return iemRaiseGeneralProtectionFault0(pVCpu);
5857 }
5858
5859 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
5860 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
5861 uint32_t const uCr4 = IEM_GET_CTX(pVCpu)->cr4;
5862 uint64_t const uCr3 = IEM_GET_CTX(pVCpu)->cr3;
5863 switch (uInvpcidType)
5864 {
5865 case X86_INVPCID_TYPE_INDV_ADDR:
5866 {
5867 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
5868 {
5869 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
5870 return iemRaiseGeneralProtectionFault0(pVCpu);
5871 }
5872 if ( !(uCr4 & X86_CR4_PCIDE)
5873 && uPcid != 0)
5874 {
5875 Log(("invpcid: invalid pcid %#x\n", uPcid));
5876 return iemRaiseGeneralProtectionFault0(pVCpu);
5877 }
5878
5879 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
5880 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
5881 break;
5882 }
5883
5884 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
5885 {
5886 if ( !(uCr4 & X86_CR4_PCIDE)
5887 && uPcid != 0)
5888 {
5889 Log(("invpcid: invalid pcid %#x\n", uPcid));
5890 return iemRaiseGeneralProtectionFault0(pVCpu);
5891 }
5892 /* Invalidate all mappings associated with PCID except global translations. */
5893 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
5894 break;
5895 }
5896
5897 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
5898 {
5899 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
5900 break;
5901 }
5902
5903 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
5904 {
5905 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
5906 break;
5907 }
5908 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5909 }
5910 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5911 }
5912 return rcStrict;
5913}
5914
5915
5916/**
5917 * Implements RDTSC.
5918 */
5919IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
5920{
5921 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5922
5923 /*
5924 * Check preconditions.
5925 */
5926 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
5927 return iemRaiseUndefinedOpcode(pVCpu);
5928
5929 if ( (pCtx->cr4 & X86_CR4_TSD)
5930 && pVCpu->iem.s.uCpl != 0)
5931 {
5932 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
5933 return iemRaiseGeneralProtectionFault0(pVCpu);
5934 }
5935
5936 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
5937 {
5938 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
5939 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5940 }
5941
5942 /*
5943 * Do the job.
5944 */
5945 uint64_t uTicks = TMCpuTickGet(pVCpu);
5946#ifdef VBOX_WITH_NESTED_HWVIRT
5947 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
5948#endif
5949 pCtx->rax = RT_LO_U32(uTicks);
5950 pCtx->rdx = RT_HI_U32(uTicks);
5951#ifdef IEM_VERIFICATION_MODE_FULL
5952 pVCpu->iem.s.fIgnoreRaxRdx = true;
5953#endif
5954
5955 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5956 return VINF_SUCCESS;
5957}
5958
5959
5960/**
5961 * Implements RDTSC.
5962 */
5963IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
5964{
5965 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
5966
5967 /*
5968 * Check preconditions.
5969 */
5970 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
5971 return iemRaiseUndefinedOpcode(pVCpu);
5972
5973 if ( (pCtx->cr4 & X86_CR4_TSD)
5974 && pVCpu->iem.s.uCpl != 0)
5975 {
5976 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
5977 return iemRaiseGeneralProtectionFault0(pVCpu);
5978 }
5979
5980 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
5981 {
5982 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
5983 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5984 }
5985
5986 /*
5987 * Do the job.
5988 * Query the MSR first in case of trips to ring-3.
5989 */
5990 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pCtx->rcx);
5991 if (rcStrict == VINF_SUCCESS)
5992 {
5993 /* Low dword of the TSC_AUX msr only. */
5994 pCtx->rcx &= UINT32_C(0xffffffff);
5995
5996 uint64_t uTicks = TMCpuTickGet(pVCpu);
5997#ifdef VBOX_WITH_NESTED_HWVIRT
5998 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
5999#endif
6000 pCtx->rax = RT_LO_U32(uTicks);
6001 pCtx->rdx = RT_HI_U32(uTicks);
6002#ifdef IEM_VERIFICATION_MODE_FULL
6003 pVCpu->iem.s.fIgnoreRaxRdx = true;
6004#endif
6005 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6006 }
6007 return rcStrict;
6008}
6009
6010
6011/**
6012 * Implements RDPMC.
6013 */
6014IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
6015{
6016 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6017 if ( pVCpu->iem.s.uCpl != 0
6018 && !(pCtx->cr4 & X86_CR4_PCE))
6019 return iemRaiseGeneralProtectionFault0(pVCpu);
6020
6021 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
6022 {
6023 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
6024 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6025 }
6026
6027 /** @todo Implement RDPMC for the regular guest execution case (the above only
6028 * handles nested-guest intercepts). */
6029 RT_NOREF(cbInstr);
6030 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
6031}
6032
6033
6034/**
6035 * Implements RDMSR.
6036 */
6037IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
6038{
6039 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6040
6041 /*
6042 * Check preconditions.
6043 */
6044 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6045 return iemRaiseUndefinedOpcode(pVCpu);
6046 if (pVCpu->iem.s.uCpl != 0)
6047 return iemRaiseGeneralProtectionFault0(pVCpu);
6048
6049 /*
6050 * Do the job.
6051 */
6052 RTUINT64U uValue;
6053 VBOXSTRICTRC rcStrict;
6054#ifdef VBOX_WITH_NESTED_HWVIRT
6055 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6056 {
6057 rcStrict = iemSvmHandleMsrIntercept(pVCpu, pCtx, pCtx->ecx, false /* fWrite */);
6058 if (rcStrict == VINF_SVM_VMEXIT)
6059 return VINF_SUCCESS;
6060 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6061 {
6062 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pCtx->ecx, VBOXSTRICTRC_VAL(rcStrict)));
6063 return rcStrict;
6064 }
6065 }
6066#endif
6067
6068 rcStrict = CPUMQueryGuestMsr(pVCpu, pCtx->ecx, &uValue.u);
6069 if (rcStrict == VINF_SUCCESS)
6070 {
6071 pCtx->rax = uValue.s.Lo;
6072 pCtx->rdx = uValue.s.Hi;
6073
6074 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6075 return VINF_SUCCESS;
6076 }
6077
6078#ifndef IN_RING3
6079 /* Deferred to ring-3. */
6080 if (rcStrict == VINF_CPUM_R3_MSR_READ)
6081 {
6082 Log(("IEM: rdmsr(%#x) -> ring-3\n", pCtx->ecx));
6083 return rcStrict;
6084 }
6085#else /* IN_RING3 */
6086 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6087 static uint32_t s_cTimes = 0;
6088 if (s_cTimes++ < 10)
6089 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx));
6090 else
6091#endif
6092 Log(("IEM: rdmsr(%#x) -> #GP(0)\n", pCtx->ecx));
6093 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6094 return iemRaiseGeneralProtectionFault0(pVCpu);
6095}
6096
6097
6098/**
6099 * Implements WRMSR.
6100 */
6101IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
6102{
6103 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6104
6105 /*
6106 * Check preconditions.
6107 */
6108 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6109 return iemRaiseUndefinedOpcode(pVCpu);
6110 if (pVCpu->iem.s.uCpl != 0)
6111 return iemRaiseGeneralProtectionFault0(pVCpu);
6112
6113 /*
6114 * Do the job.
6115 */
6116 RTUINT64U uValue;
6117 uValue.s.Lo = pCtx->eax;
6118 uValue.s.Hi = pCtx->edx;
6119
6120 VBOXSTRICTRC rcStrict;
6121#ifdef VBOX_WITH_NESTED_HWVIRT
6122 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6123 {
6124 rcStrict = iemSvmHandleMsrIntercept(pVCpu, pCtx, pCtx->ecx, true /* fWrite */);
6125 if (rcStrict == VINF_SVM_VMEXIT)
6126 return VINF_SUCCESS;
6127 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6128 {
6129 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pCtx->ecx, VBOXSTRICTRC_VAL(rcStrict)));
6130 return rcStrict;
6131 }
6132 }
6133#endif
6134
6135 if (!IEM_VERIFICATION_ENABLED(pVCpu))
6136 rcStrict = CPUMSetGuestMsr(pVCpu, pCtx->ecx, uValue.u);
6137 else
6138 {
6139#ifdef IN_RING3
6140 CPUMCTX CtxTmp = *pCtx;
6141 rcStrict = CPUMSetGuestMsr(pVCpu, pCtx->ecx, uValue.u);
6142 PCPUMCTX pCtx2 = CPUMQueryGuestCtxPtr(pVCpu);
6143 *pCtx = *pCtx2;
6144 *pCtx2 = CtxTmp;
6145#else
6146 AssertReleaseFailedReturn(VERR_IEM_IPE_2);
6147#endif
6148 }
6149 if (rcStrict == VINF_SUCCESS)
6150 {
6151 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6152 return VINF_SUCCESS;
6153 }
6154
6155#ifndef IN_RING3
6156 /* Deferred to ring-3. */
6157 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
6158 {
6159 Log(("IEM: wrmsr(%#x) -> ring-3\n", pCtx->ecx));
6160 return rcStrict;
6161 }
6162#else /* IN_RING3 */
6163 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6164 static uint32_t s_cTimes = 0;
6165 if (s_cTimes++ < 10)
6166 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo));
6167 else
6168#endif
6169 Log(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pCtx->ecx, uValue.s.Hi, uValue.s.Lo));
6170 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6171 return iemRaiseGeneralProtectionFault0(pVCpu);
6172}
6173
6174
6175/**
6176 * Implements 'IN eAX, port'.
6177 *
6178 * @param u16Port The source port.
6179 * @param cbReg The register size.
6180 */
6181IEM_CIMPL_DEF_2(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg)
6182{
6183 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6184
6185 /*
6186 * CPL check
6187 */
6188 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, pCtx, u16Port, cbReg);
6189 if (rcStrict != VINF_SUCCESS)
6190 return rcStrict;
6191
6192 /*
6193 * Check SVM nested-guest IO intercept.
6194 */
6195#ifdef VBOX_WITH_NESTED_HWVIRT
6196 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6197 {
6198 uint8_t cAddrSizeBits;
6199 switch (pVCpu->iem.s.enmEffAddrMode)
6200 {
6201 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6202 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6203 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6204 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6205 }
6206 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6207 false /* fRep */, false /* fStrIo */, cbInstr);
6208 if (rcStrict == VINF_SVM_VMEXIT)
6209 return VINF_SUCCESS;
6210 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6211 {
6212 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6213 VBOXSTRICTRC_VAL(rcStrict)));
6214 return rcStrict;
6215 }
6216 }
6217#endif
6218
6219 /*
6220 * Perform the I/O.
6221 */
6222 uint32_t u32Value;
6223 if (!IEM_VERIFICATION_ENABLED(pVCpu))
6224 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
6225 else
6226 rcStrict = iemVerifyFakeIOPortRead(pVCpu, u16Port, &u32Value, cbReg);
6227 if (IOM_SUCCESS(rcStrict))
6228 {
6229 switch (cbReg)
6230 {
6231 case 1: pCtx->al = (uint8_t)u32Value; break;
6232 case 2: pCtx->ax = (uint16_t)u32Value; break;
6233 case 4: pCtx->rax = u32Value; break;
6234 default: AssertFailedReturn(VERR_IEM_IPE_3);
6235 }
6236 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6237 pVCpu->iem.s.cPotentialExits++;
6238 if (rcStrict != VINF_SUCCESS)
6239 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6240 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6241
6242 /*
6243 * Check for I/O breakpoints.
6244 */
6245 uint32_t const uDr7 = pCtx->dr[7];
6246 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6247 && X86_DR7_ANY_RW_IO(uDr7)
6248 && (pCtx->cr4 & X86_CR4_DE))
6249 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6250 {
6251 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx, u16Port, cbReg);
6252 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6253 rcStrict = iemRaiseDebugException(pVCpu);
6254 }
6255 }
6256
6257 return rcStrict;
6258}
6259
6260
6261/**
6262 * Implements 'IN eAX, DX'.
6263 *
6264 * @param cbReg The register size.
6265 */
6266IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
6267{
6268 return IEM_CIMPL_CALL_2(iemCImpl_in, IEM_GET_CTX(pVCpu)->dx, cbReg);
6269}
6270
6271
6272/**
6273 * Implements 'OUT port, eAX'.
6274 *
6275 * @param u16Port The destination port.
6276 * @param cbReg The register size.
6277 */
6278IEM_CIMPL_DEF_2(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg)
6279{
6280 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6281
6282 /*
6283 * CPL check
6284 */
6285 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, pCtx, u16Port, cbReg);
6286 if (rcStrict != VINF_SUCCESS)
6287 return rcStrict;
6288
6289 /*
6290 * Check SVM nested-guest IO intercept.
6291 */
6292#ifdef VBOX_WITH_NESTED_HWVIRT
6293 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6294 {
6295 uint8_t cAddrSizeBits;
6296 switch (pVCpu->iem.s.enmEffAddrMode)
6297 {
6298 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6299 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6300 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6301 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6302 }
6303 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6304 false /* fRep */, false /* fStrIo */, cbInstr);
6305 if (rcStrict == VINF_SVM_VMEXIT)
6306 return VINF_SUCCESS;
6307 if (rcStrict != VINF_HM_INTERCEPT_NOT_ACTIVE)
6308 {
6309 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6310 VBOXSTRICTRC_VAL(rcStrict)));
6311 return rcStrict;
6312 }
6313 }
6314#endif
6315
6316 /*
6317 * Perform the I/O.
6318 */
6319 uint32_t u32Value;
6320 switch (cbReg)
6321 {
6322 case 1: u32Value = pCtx->al; break;
6323 case 2: u32Value = pCtx->ax; break;
6324 case 4: u32Value = pCtx->eax; break;
6325 default: AssertFailedReturn(VERR_IEM_IPE_4);
6326 }
6327 if (!IEM_VERIFICATION_ENABLED(pVCpu))
6328 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
6329 else
6330 rcStrict = iemVerifyFakeIOPortWrite(pVCpu, u16Port, u32Value, cbReg);
6331 if (IOM_SUCCESS(rcStrict))
6332 {
6333 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6334 pVCpu->iem.s.cPotentialExits++;
6335 if (rcStrict != VINF_SUCCESS)
6336 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6337 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6338
6339 /*
6340 * Check for I/O breakpoints.
6341 */
6342 uint32_t const uDr7 = pCtx->dr[7];
6343 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6344 && X86_DR7_ANY_RW_IO(uDr7)
6345 && (pCtx->cr4 & X86_CR4_DE))
6346 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6347 {
6348 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx, u16Port, cbReg);
6349 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6350 rcStrict = iemRaiseDebugException(pVCpu);
6351 }
6352 }
6353 return rcStrict;
6354}
6355
6356
6357/**
6358 * Implements 'OUT DX, eAX'.
6359 *
6360 * @param cbReg The register size.
6361 */
6362IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
6363{
6364 return IEM_CIMPL_CALL_2(iemCImpl_out, IEM_GET_CTX(pVCpu)->dx, cbReg);
6365}
6366
6367
6368/**
6369 * Implements 'CLI'.
6370 */
6371IEM_CIMPL_DEF_0(iemCImpl_cli)
6372{
6373 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6374 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu, pCtx);
6375 uint32_t const fEflOld = fEfl;
6376 if (pCtx->cr0 & X86_CR0_PE)
6377 {
6378 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6379 if (!(fEfl & X86_EFL_VM))
6380 {
6381 if (pVCpu->iem.s.uCpl <= uIopl)
6382 fEfl &= ~X86_EFL_IF;
6383 else if ( pVCpu->iem.s.uCpl == 3
6384 && (pCtx->cr4 & X86_CR4_PVI) )
6385 fEfl &= ~X86_EFL_VIF;
6386 else
6387 return iemRaiseGeneralProtectionFault0(pVCpu);
6388 }
6389 /* V8086 */
6390 else if (uIopl == 3)
6391 fEfl &= ~X86_EFL_IF;
6392 else if ( uIopl < 3
6393 && (pCtx->cr4 & X86_CR4_VME) )
6394 fEfl &= ~X86_EFL_VIF;
6395 else
6396 return iemRaiseGeneralProtectionFault0(pVCpu);
6397 }
6398 /* real mode */
6399 else
6400 fEfl &= ~X86_EFL_IF;
6401
6402 /* Commit. */
6403 IEMMISC_SET_EFL(pVCpu, pCtx, fEfl);
6404 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6405 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
6406 return VINF_SUCCESS;
6407}
6408
6409
6410/**
6411 * Implements 'STI'.
6412 */
6413IEM_CIMPL_DEF_0(iemCImpl_sti)
6414{
6415 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6416 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu, pCtx);
6417 uint32_t const fEflOld = fEfl;
6418
6419 if (pCtx->cr0 & X86_CR0_PE)
6420 {
6421 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6422 if (!(fEfl & X86_EFL_VM))
6423 {
6424 if (pVCpu->iem.s.uCpl <= uIopl)
6425 fEfl |= X86_EFL_IF;
6426 else if ( pVCpu->iem.s.uCpl == 3
6427 && (pCtx->cr4 & X86_CR4_PVI)
6428 && !(fEfl & X86_EFL_VIP) )
6429 fEfl |= X86_EFL_VIF;
6430 else
6431 return iemRaiseGeneralProtectionFault0(pVCpu);
6432 }
6433 /* V8086 */
6434 else if (uIopl == 3)
6435 fEfl |= X86_EFL_IF;
6436 else if ( uIopl < 3
6437 && (pCtx->cr4 & X86_CR4_VME)
6438 && !(fEfl & X86_EFL_VIP) )
6439 fEfl |= X86_EFL_VIF;
6440 else
6441 return iemRaiseGeneralProtectionFault0(pVCpu);
6442 }
6443 /* real mode */
6444 else
6445 fEfl |= X86_EFL_IF;
6446
6447 /* Commit. */
6448 IEMMISC_SET_EFL(pVCpu, pCtx, fEfl);
6449 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6450 if ((!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF)) || IEM_FULL_VERIFICATION_REM_ENABLED(pVCpu))
6451 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
6452 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
6453 return VINF_SUCCESS;
6454}
6455
6456
6457/**
6458 * Implements 'HLT'.
6459 */
6460IEM_CIMPL_DEF_0(iemCImpl_hlt)
6461{
6462 if (pVCpu->iem.s.uCpl != 0)
6463 return iemRaiseGeneralProtectionFault0(pVCpu);
6464
6465 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
6466 {
6467 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
6468 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6469 }
6470
6471 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6472 return VINF_EM_HALT;
6473}
6474
6475
6476/**
6477 * Implements 'MONITOR'.
6478 */
6479IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
6480{
6481 /*
6482 * Permission checks.
6483 */
6484 if (pVCpu->iem.s.uCpl != 0)
6485 {
6486 Log2(("monitor: CPL != 0\n"));
6487 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
6488 }
6489 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
6490 {
6491 Log2(("monitor: Not in CPUID\n"));
6492 return iemRaiseUndefinedOpcode(pVCpu);
6493 }
6494
6495 /*
6496 * Gather the operands and validate them.
6497 */
6498 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6499 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
6500 uint32_t uEcx = pCtx->ecx;
6501 uint32_t uEdx = pCtx->edx;
6502/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
6503 * \#GP first. */
6504 if (uEcx != 0)
6505 {
6506 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
6507 return iemRaiseGeneralProtectionFault0(pVCpu);
6508 }
6509
6510 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
6511 if (rcStrict != VINF_SUCCESS)
6512 return rcStrict;
6513
6514 RTGCPHYS GCPhysMem;
6515 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
6516 if (rcStrict != VINF_SUCCESS)
6517 return rcStrict;
6518
6519 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
6520 {
6521 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
6522 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6523 }
6524
6525 /*
6526 * Call EM to prepare the monitor/wait.
6527 */
6528 rcStrict = EMMonitorWaitPrepare(pVCpu, pCtx->rax, pCtx->rcx, pCtx->rdx, GCPhysMem);
6529 Assert(rcStrict == VINF_SUCCESS);
6530
6531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6532 return rcStrict;
6533}
6534
6535
6536/**
6537 * Implements 'MWAIT'.
6538 */
6539IEM_CIMPL_DEF_0(iemCImpl_mwait)
6540{
6541 /*
6542 * Permission checks.
6543 */
6544 if (pVCpu->iem.s.uCpl != 0)
6545 {
6546 Log2(("mwait: CPL != 0\n"));
6547 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
6548 * EFLAGS.VM then.) */
6549 return iemRaiseUndefinedOpcode(pVCpu);
6550 }
6551 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
6552 {
6553 Log2(("mwait: Not in CPUID\n"));
6554 return iemRaiseUndefinedOpcode(pVCpu);
6555 }
6556
6557 /*
6558 * Gather the operands and validate them.
6559 */
6560 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6561 uint32_t uEax = pCtx->eax;
6562 uint32_t uEcx = pCtx->ecx;
6563 if (uEcx != 0)
6564 {
6565 /* Only supported extension is break on IRQ when IF=0. */
6566 if (uEcx > 1)
6567 {
6568 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
6569 return iemRaiseGeneralProtectionFault0(pVCpu);
6570 }
6571 uint32_t fMWaitFeatures = 0;
6572 uint32_t uIgnore = 0;
6573 CPUMGetGuestCpuId(pVCpu, 5, 0, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
6574 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
6575 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
6576 {
6577 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
6578 return iemRaiseGeneralProtectionFault0(pVCpu);
6579 }
6580 }
6581
6582 /*
6583 * Check SVM nested-guest mwait intercepts.
6584 */
6585 if ( IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
6586 && EMMonitorIsArmed(pVCpu))
6587 {
6588 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
6589 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6590 }
6591 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
6592 {
6593 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
6594 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6595 }
6596
6597 /*
6598 * Call EM to prepare the monitor/wait.
6599 */
6600 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
6601
6602 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6603 return rcStrict;
6604}
6605
6606
6607/**
6608 * Implements 'SWAPGS'.
6609 */
6610IEM_CIMPL_DEF_0(iemCImpl_swapgs)
6611{
6612 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
6613
6614 /*
6615 * Permission checks.
6616 */
6617 if (pVCpu->iem.s.uCpl != 0)
6618 {
6619 Log2(("swapgs: CPL != 0\n"));
6620 return iemRaiseUndefinedOpcode(pVCpu);
6621 }
6622
6623 /*
6624 * Do the job.
6625 */
6626 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6627 uint64_t uOtherGsBase = pCtx->msrKERNELGSBASE;
6628 pCtx->msrKERNELGSBASE = pCtx->gs.u64Base;
6629 pCtx->gs.u64Base = uOtherGsBase;
6630
6631 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6632 return VINF_SUCCESS;
6633}
6634
6635
6636/**
6637 * Implements 'CPUID'.
6638 */
6639IEM_CIMPL_DEF_0(iemCImpl_cpuid)
6640{
6641 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6642
6643 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
6644 {
6645 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
6646 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6647 }
6648
6649 CPUMGetGuestCpuId(pVCpu, pCtx->eax, pCtx->ecx, &pCtx->eax, &pCtx->ebx, &pCtx->ecx, &pCtx->edx);
6650 pCtx->rax &= UINT32_C(0xffffffff);
6651 pCtx->rbx &= UINT32_C(0xffffffff);
6652 pCtx->rcx &= UINT32_C(0xffffffff);
6653 pCtx->rdx &= UINT32_C(0xffffffff);
6654
6655 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6656 return VINF_SUCCESS;
6657}
6658
6659
6660/**
6661 * Implements 'AAD'.
6662 *
6663 * @param bImm The immediate operand.
6664 */
6665IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
6666{
6667 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6668
6669 uint16_t const ax = pCtx->ax;
6670 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
6671 pCtx->ax = al;
6672 iemHlpUpdateArithEFlagsU8(pVCpu, al,
6673 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
6674 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
6675
6676 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6677 return VINF_SUCCESS;
6678}
6679
6680
6681/**
6682 * Implements 'AAM'.
6683 *
6684 * @param bImm The immediate operand. Cannot be 0.
6685 */
6686IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
6687{
6688 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6689 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
6690
6691 uint16_t const ax = pCtx->ax;
6692 uint8_t const al = (uint8_t)ax % bImm;
6693 uint8_t const ah = (uint8_t)ax / bImm;
6694 pCtx->ax = (ah << 8) + al;
6695 iemHlpUpdateArithEFlagsU8(pVCpu, al,
6696 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
6697 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
6698
6699 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6700 return VINF_SUCCESS;
6701}
6702
6703
6704/**
6705 * Implements 'DAA'.
6706 */
6707IEM_CIMPL_DEF_0(iemCImpl_daa)
6708{
6709 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6710
6711 uint8_t const al = pCtx->al;
6712 bool const fCarry = pCtx->eflags.Bits.u1CF;
6713
6714 if ( pCtx->eflags.Bits.u1AF
6715 || (al & 0xf) >= 10)
6716 {
6717 pCtx->al = al + 6;
6718 pCtx->eflags.Bits.u1AF = 1;
6719 }
6720 else
6721 pCtx->eflags.Bits.u1AF = 0;
6722
6723 if (al >= 0x9a || fCarry)
6724 {
6725 pCtx->al += 0x60;
6726 pCtx->eflags.Bits.u1CF = 1;
6727 }
6728 else
6729 pCtx->eflags.Bits.u1CF = 0;
6730
6731 iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6732 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6733 return VINF_SUCCESS;
6734}
6735
6736
6737/**
6738 * Implements 'DAS'.
6739 */
6740IEM_CIMPL_DEF_0(iemCImpl_das)
6741{
6742 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6743
6744 uint8_t const uInputAL = pCtx->al;
6745 bool const fCarry = pCtx->eflags.Bits.u1CF;
6746
6747 if ( pCtx->eflags.Bits.u1AF
6748 || (uInputAL & 0xf) >= 10)
6749 {
6750 pCtx->eflags.Bits.u1AF = 1;
6751 if (uInputAL < 6)
6752 pCtx->eflags.Bits.u1CF = 1;
6753 pCtx->al = uInputAL - 6;
6754 }
6755 else
6756 {
6757 pCtx->eflags.Bits.u1AF = 0;
6758 pCtx->eflags.Bits.u1CF = 0;
6759 }
6760
6761 if (uInputAL >= 0x9a || fCarry)
6762 {
6763 pCtx->al -= 0x60;
6764 pCtx->eflags.Bits.u1CF = 1;
6765 }
6766
6767 iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6768 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6769 return VINF_SUCCESS;
6770}
6771
6772
6773/**
6774 * Implements 'AAA'.
6775 */
6776IEM_CIMPL_DEF_0(iemCImpl_aaa)
6777{
6778 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6779
6780 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
6781 {
6782 if ( pCtx->eflags.Bits.u1AF
6783 || (pCtx->ax & 0xf) >= 10)
6784 {
6785 iemAImpl_add_u16(&pCtx->ax, 0x106, &pCtx->eflags.u32);
6786 pCtx->eflags.Bits.u1AF = 1;
6787 pCtx->eflags.Bits.u1CF = 1;
6788#ifdef IEM_VERIFICATION_MODE_FULL
6789 pVCpu->iem.s.fUndefinedEFlags |= X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF;
6790#endif
6791 }
6792 else
6793 {
6794 iemHlpUpdateArithEFlagsU16(pVCpu, pCtx->ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6795 pCtx->eflags.Bits.u1AF = 0;
6796 pCtx->eflags.Bits.u1CF = 0;
6797 }
6798 pCtx->ax &= UINT16_C(0xff0f);
6799 }
6800 else
6801 {
6802 if ( pCtx->eflags.Bits.u1AF
6803 || (pCtx->ax & 0xf) >= 10)
6804 {
6805 pCtx->ax += UINT16_C(0x106);
6806 pCtx->eflags.Bits.u1AF = 1;
6807 pCtx->eflags.Bits.u1CF = 1;
6808 }
6809 else
6810 {
6811 pCtx->eflags.Bits.u1AF = 0;
6812 pCtx->eflags.Bits.u1CF = 0;
6813 }
6814 pCtx->ax &= UINT16_C(0xff0f);
6815 iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6816 }
6817
6818 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6819 return VINF_SUCCESS;
6820}
6821
6822
6823/**
6824 * Implements 'AAS'.
6825 */
6826IEM_CIMPL_DEF_0(iemCImpl_aas)
6827{
6828 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6829
6830 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
6831 {
6832 if ( pCtx->eflags.Bits.u1AF
6833 || (pCtx->ax & 0xf) >= 10)
6834 {
6835 iemAImpl_sub_u16(&pCtx->ax, 0x106, &pCtx->eflags.u32);
6836 pCtx->eflags.Bits.u1AF = 1;
6837 pCtx->eflags.Bits.u1CF = 1;
6838#ifdef IEM_VERIFICATION_MODE_FULL
6839 pVCpu->iem.s.fUndefinedEFlags |= X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF;
6840#endif
6841 }
6842 else
6843 {
6844 iemHlpUpdateArithEFlagsU16(pVCpu, pCtx->ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6845 pCtx->eflags.Bits.u1AF = 0;
6846 pCtx->eflags.Bits.u1CF = 0;
6847 }
6848 pCtx->ax &= UINT16_C(0xff0f);
6849 }
6850 else
6851 {
6852 if ( pCtx->eflags.Bits.u1AF
6853 || (pCtx->ax & 0xf) >= 10)
6854 {
6855 pCtx->ax -= UINT16_C(0x106);
6856 pCtx->eflags.Bits.u1AF = 1;
6857 pCtx->eflags.Bits.u1CF = 1;
6858 }
6859 else
6860 {
6861 pCtx->eflags.Bits.u1AF = 0;
6862 pCtx->eflags.Bits.u1CF = 0;
6863 }
6864 pCtx->ax &= UINT16_C(0xff0f);
6865 iemHlpUpdateArithEFlagsU8(pVCpu, pCtx->al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
6866 }
6867
6868 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6869 return VINF_SUCCESS;
6870}
6871
6872
6873/**
6874 * Implements the 16-bit version of 'BOUND'.
6875 *
6876 * @note We have separate 16-bit and 32-bit variants of this function due to
6877 * the decoder using unsigned parameters, whereas we want signed one to
6878 * do the job. This is significant for a recompiler.
6879 */
6880IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
6881{
6882 /*
6883 * Check if the index is inside the bounds, otherwise raise #BR.
6884 */
6885 if ( idxArray >= idxLowerBound
6886 && idxArray <= idxUpperBound)
6887 {
6888 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6889 return VINF_SUCCESS;
6890 }
6891
6892 return iemRaiseBoundRangeExceeded(pVCpu);
6893}
6894
6895
6896/**
6897 * Implements the 32-bit version of 'BOUND'.
6898 */
6899IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
6900{
6901 /*
6902 * Check if the index is inside the bounds, otherwise raise #BR.
6903 */
6904 if ( idxArray >= idxLowerBound
6905 && idxArray <= idxUpperBound)
6906 {
6907 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6908 return VINF_SUCCESS;
6909 }
6910
6911 return iemRaiseBoundRangeExceeded(pVCpu);
6912}
6913
6914
6915
6916/*
6917 * Instantiate the various string operation combinations.
6918 */
6919#define OP_SIZE 8
6920#define ADDR_SIZE 16
6921#include "IEMAllCImplStrInstr.cpp.h"
6922#define OP_SIZE 8
6923#define ADDR_SIZE 32
6924#include "IEMAllCImplStrInstr.cpp.h"
6925#define OP_SIZE 8
6926#define ADDR_SIZE 64
6927#include "IEMAllCImplStrInstr.cpp.h"
6928
6929#define OP_SIZE 16
6930#define ADDR_SIZE 16
6931#include "IEMAllCImplStrInstr.cpp.h"
6932#define OP_SIZE 16
6933#define ADDR_SIZE 32
6934#include "IEMAllCImplStrInstr.cpp.h"
6935#define OP_SIZE 16
6936#define ADDR_SIZE 64
6937#include "IEMAllCImplStrInstr.cpp.h"
6938
6939#define OP_SIZE 32
6940#define ADDR_SIZE 16
6941#include "IEMAllCImplStrInstr.cpp.h"
6942#define OP_SIZE 32
6943#define ADDR_SIZE 32
6944#include "IEMAllCImplStrInstr.cpp.h"
6945#define OP_SIZE 32
6946#define ADDR_SIZE 64
6947#include "IEMAllCImplStrInstr.cpp.h"
6948
6949#define OP_SIZE 64
6950#define ADDR_SIZE 32
6951#include "IEMAllCImplStrInstr.cpp.h"
6952#define OP_SIZE 64
6953#define ADDR_SIZE 64
6954#include "IEMAllCImplStrInstr.cpp.h"
6955
6956
6957/**
6958 * Implements 'XGETBV'.
6959 */
6960IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
6961{
6962 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6963 if (pCtx->cr4 & X86_CR4_OSXSAVE)
6964 {
6965 uint32_t uEcx = pCtx->ecx;
6966 switch (uEcx)
6967 {
6968 case 0:
6969 break;
6970
6971 case 1: /** @todo Implement XCR1 support. */
6972 default:
6973 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
6974 return iemRaiseGeneralProtectionFault0(pVCpu);
6975
6976 }
6977 pCtx->rax = RT_LO_U32(pCtx->aXcr[uEcx]);
6978 pCtx->rdx = RT_HI_U32(pCtx->aXcr[uEcx]);
6979
6980 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6981 return VINF_SUCCESS;
6982 }
6983 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
6984 return iemRaiseUndefinedOpcode(pVCpu);
6985}
6986
6987
6988/**
6989 * Implements 'XSETBV'.
6990 */
6991IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
6992{
6993 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
6994 if (pCtx->cr4 & X86_CR4_OSXSAVE)
6995 {
6996 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
6997 {
6998 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
6999 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7000 }
7001
7002 if (pVCpu->iem.s.uCpl == 0)
7003 {
7004 uint32_t uEcx = pCtx->ecx;
7005 uint64_t uNewValue = RT_MAKE_U64(pCtx->eax, pCtx->edx);
7006 switch (uEcx)
7007 {
7008 case 0:
7009 {
7010 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
7011 if (rc == VINF_SUCCESS)
7012 break;
7013 Assert(rc == VERR_CPUM_RAISE_GP_0);
7014 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7015 return iemRaiseGeneralProtectionFault0(pVCpu);
7016 }
7017
7018 case 1: /** @todo Implement XCR1 support. */
7019 default:
7020 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7021 return iemRaiseGeneralProtectionFault0(pVCpu);
7022
7023 }
7024
7025 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7026 return VINF_SUCCESS;
7027 }
7028
7029 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
7030 return iemRaiseGeneralProtectionFault0(pVCpu);
7031 }
7032 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
7033 return iemRaiseUndefinedOpcode(pVCpu);
7034}
7035
7036#ifdef IN_RING3
7037
7038/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
7039struct IEMCIMPLCX16ARGS
7040{
7041 PRTUINT128U pu128Dst;
7042 PRTUINT128U pu128RaxRdx;
7043 PRTUINT128U pu128RbxRcx;
7044 uint32_t *pEFlags;
7045# ifdef VBOX_STRICT
7046 uint32_t cCalls;
7047# endif
7048};
7049
7050/**
7051 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
7052 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
7053 */
7054static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPU pVCpu, void *pvUser)
7055{
7056 RT_NOREF(pVM, pVCpu);
7057 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
7058# ifdef VBOX_STRICT
7059 Assert(pArgs->cCalls == 0);
7060 pArgs->cCalls++;
7061# endif
7062
7063 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
7064 return VINF_SUCCESS;
7065}
7066
7067#endif /* IN_RING3 */
7068
7069/**
7070 * Implements 'CMPXCHG16B' fallback using rendezvous.
7071 */
7072IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
7073 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
7074{
7075#ifdef IN_RING3
7076 struct IEMCIMPLCX16ARGS Args;
7077 Args.pu128Dst = pu128Dst;
7078 Args.pu128RaxRdx = pu128RaxRdx;
7079 Args.pu128RbxRcx = pu128RbxRcx;
7080 Args.pEFlags = pEFlags;
7081# ifdef VBOX_STRICT
7082 Args.cCalls = 0;
7083# endif
7084 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
7085 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
7086 Assert(Args.cCalls == 1);
7087 if (rcStrict == VINF_SUCCESS)
7088 {
7089 /* Duplicated tail code. */
7090 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
7091 if (rcStrict == VINF_SUCCESS)
7092 {
7093 PCPUMCTX pCtx = pVCpu->iem.s.CTX_SUFF(pCtx);
7094 pCtx->eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
7095 if (!(*pEFlags & X86_EFL_ZF))
7096 {
7097 pCtx->rax = pu128RaxRdx->s.Lo;
7098 pCtx->rdx = pu128RaxRdx->s.Hi;
7099 }
7100 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7101 }
7102 }
7103 return rcStrict;
7104#else
7105 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7106 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
7107#endif
7108}
7109
7110
7111/**
7112 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
7113 *
7114 * This is implemented in C because it triggers a load like behviour without
7115 * actually reading anything. Since that's not so common, it's implemented
7116 * here.
7117 *
7118 * @param iEffSeg The effective segment.
7119 * @param GCPtrEff The address of the image.
7120 */
7121IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7122{
7123 /*
7124 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
7125 */
7126 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
7127 if (rcStrict == VINF_SUCCESS)
7128 {
7129 RTGCPHYS GCPhysMem;
7130 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7131 if (rcStrict == VINF_SUCCESS)
7132 {
7133 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7134 return VINF_SUCCESS;
7135 }
7136 }
7137
7138 return rcStrict;
7139}
7140
7141
7142/**
7143 * Implements 'FINIT' and 'FNINIT'.
7144 *
7145 * @param fCheckXcpts Whether to check for umasked pending exceptions or
7146 * not.
7147 */
7148IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
7149{
7150 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7151
7152 if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
7153 return iemRaiseDeviceNotAvailable(pVCpu);
7154
7155 NOREF(fCheckXcpts); /** @todo trigger pending exceptions:
7156 if (fCheckXcpts && TODO )
7157 return iemRaiseMathFault(pVCpu);
7158 */
7159
7160 PX86XSAVEAREA pXState = pCtx->CTX_SUFF(pXState);
7161 pXState->x87.FCW = 0x37f;
7162 pXState->x87.FSW = 0;
7163 pXState->x87.FTW = 0x00; /* 0 - empty. */
7164 pXState->x87.FPUDP = 0;
7165 pXState->x87.DS = 0; //??
7166 pXState->x87.Rsrvd2= 0;
7167 pXState->x87.FPUIP = 0;
7168 pXState->x87.CS = 0; //??
7169 pXState->x87.Rsrvd1= 0;
7170 pXState->x87.FOP = 0;
7171
7172 iemHlpUsedFpu(pVCpu);
7173 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7174 return VINF_SUCCESS;
7175}
7176
7177
7178/**
7179 * Implements 'FXSAVE'.
7180 *
7181 * @param iEffSeg The effective segment.
7182 * @param GCPtrEff The address of the image.
7183 * @param enmEffOpSize The operand size (only REX.W really matters).
7184 */
7185IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7186{
7187 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7188
7189 /*
7190 * Raise exceptions.
7191 */
7192 if (pCtx->cr0 & X86_CR0_EM)
7193 return iemRaiseUndefinedOpcode(pVCpu);
7194 if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
7195 return iemRaiseDeviceNotAvailable(pVCpu);
7196 if (GCPtrEff & 15)
7197 {
7198 /** @todo CPU/VM detection possible! \#AC might not be signal for
7199 * all/any misalignment sizes, intel says its an implementation detail. */
7200 if ( (pCtx->cr0 & X86_CR0_AM)
7201 && pCtx->eflags.Bits.u1AC
7202 && pVCpu->iem.s.uCpl == 3)
7203 return iemRaiseAlignmentCheckException(pVCpu);
7204 return iemRaiseGeneralProtectionFault0(pVCpu);
7205 }
7206
7207 /*
7208 * Access the memory.
7209 */
7210 void *pvMem512;
7211 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7212 if (rcStrict != VINF_SUCCESS)
7213 return rcStrict;
7214 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7215 PCX86FXSTATE pSrc = &pCtx->CTX_SUFF(pXState)->x87;
7216
7217 /*
7218 * Store the registers.
7219 */
7220 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7221 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
7222
7223 /* common for all formats */
7224 pDst->FCW = pSrc->FCW;
7225 pDst->FSW = pSrc->FSW;
7226 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7227 pDst->FOP = pSrc->FOP;
7228 pDst->MXCSR = pSrc->MXCSR;
7229 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7230 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7231 {
7232 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
7233 * them for now... */
7234 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7235 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7236 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7237 pDst->aRegs[i].au32[3] = 0;
7238 }
7239
7240 /* FPU IP, CS, DP and DS. */
7241 pDst->FPUIP = pSrc->FPUIP;
7242 pDst->CS = pSrc->CS;
7243 pDst->FPUDP = pSrc->FPUDP;
7244 pDst->DS = pSrc->DS;
7245 if (enmEffOpSize == IEMMODE_64BIT)
7246 {
7247 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7248 pDst->Rsrvd1 = pSrc->Rsrvd1;
7249 pDst->Rsrvd2 = pSrc->Rsrvd2;
7250 pDst->au32RsrvdForSoftware[0] = 0;
7251 }
7252 else
7253 {
7254 pDst->Rsrvd1 = 0;
7255 pDst->Rsrvd2 = 0;
7256 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
7257 }
7258
7259 /* XMM registers. */
7260 if ( !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
7261 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7262 || pVCpu->iem.s.uCpl != 0)
7263 {
7264 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7265 for (uint32_t i = 0; i < cXmmRegs; i++)
7266 pDst->aXMM[i] = pSrc->aXMM[i];
7267 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7268 * right? */
7269 }
7270
7271 /*
7272 * Commit the memory.
7273 */
7274 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7275 if (rcStrict != VINF_SUCCESS)
7276 return rcStrict;
7277
7278 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7279 return VINF_SUCCESS;
7280}
7281
7282
7283/**
7284 * Implements 'FXRSTOR'.
7285 *
7286 * @param GCPtrEff The address of the image.
7287 * @param enmEffOpSize The operand size (only REX.W really matters).
7288 */
7289IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7290{
7291 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7292
7293 /*
7294 * Raise exceptions.
7295 */
7296 if (pCtx->cr0 & X86_CR0_EM)
7297 return iemRaiseUndefinedOpcode(pVCpu);
7298 if (pCtx->cr0 & (X86_CR0_TS | X86_CR0_EM))
7299 return iemRaiseDeviceNotAvailable(pVCpu);
7300 if (GCPtrEff & 15)
7301 {
7302 /** @todo CPU/VM detection possible! \#AC might not be signal for
7303 * all/any misalignment sizes, intel says its an implementation detail. */
7304 if ( (pCtx->cr0 & X86_CR0_AM)
7305 && pCtx->eflags.Bits.u1AC
7306 && pVCpu->iem.s.uCpl == 3)
7307 return iemRaiseAlignmentCheckException(pVCpu);
7308 return iemRaiseGeneralProtectionFault0(pVCpu);
7309 }
7310
7311 /*
7312 * Access the memory.
7313 */
7314 void *pvMem512;
7315 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
7316 if (rcStrict != VINF_SUCCESS)
7317 return rcStrict;
7318 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
7319 PX86FXSTATE pDst = &pCtx->CTX_SUFF(pXState)->x87;
7320
7321 /*
7322 * Check the state for stuff which will #GP(0).
7323 */
7324 uint32_t const fMXCSR = pSrc->MXCSR;
7325 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7326 if (fMXCSR & ~fMXCSR_MASK)
7327 {
7328 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
7329 return iemRaiseGeneralProtectionFault0(pVCpu);
7330 }
7331
7332 /*
7333 * Load the registers.
7334 */
7335 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7336 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
7337
7338 /* common for all formats */
7339 pDst->FCW = pSrc->FCW;
7340 pDst->FSW = pSrc->FSW;
7341 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7342 pDst->FOP = pSrc->FOP;
7343 pDst->MXCSR = fMXCSR;
7344 /* (MXCSR_MASK is read-only) */
7345 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
7346 {
7347 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7348 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7349 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7350 pDst->aRegs[i].au32[3] = 0;
7351 }
7352
7353 /* FPU IP, CS, DP and DS. */
7354 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7355 {
7356 pDst->FPUIP = pSrc->FPUIP;
7357 pDst->CS = pSrc->CS;
7358 pDst->Rsrvd1 = pSrc->Rsrvd1;
7359 pDst->FPUDP = pSrc->FPUDP;
7360 pDst->DS = pSrc->DS;
7361 pDst->Rsrvd2 = pSrc->Rsrvd2;
7362 }
7363 else
7364 {
7365 pDst->FPUIP = pSrc->FPUIP;
7366 pDst->CS = pSrc->CS;
7367 pDst->Rsrvd1 = 0;
7368 pDst->FPUDP = pSrc->FPUDP;
7369 pDst->DS = pSrc->DS;
7370 pDst->Rsrvd2 = 0;
7371 }
7372
7373 /* XMM registers. */
7374 if ( !(pCtx->msrEFER & MSR_K6_EFER_FFXSR)
7375 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7376 || pVCpu->iem.s.uCpl != 0)
7377 {
7378 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7379 for (uint32_t i = 0; i < cXmmRegs; i++)
7380 pDst->aXMM[i] = pSrc->aXMM[i];
7381 }
7382
7383 /*
7384 * Commit the memory.
7385 */
7386 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
7387 if (rcStrict != VINF_SUCCESS)
7388 return rcStrict;
7389
7390 iemHlpUsedFpu(pVCpu);
7391 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7392 return VINF_SUCCESS;
7393}
7394
7395
7396/**
7397 * Implements 'XSAVE'.
7398 *
7399 * @param iEffSeg The effective segment.
7400 * @param GCPtrEff The address of the image.
7401 * @param enmEffOpSize The operand size (only REX.W really matters).
7402 */
7403IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7404{
7405 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7406
7407 /*
7408 * Raise exceptions.
7409 */
7410 if (!(pCtx->cr4 & X86_CR4_OSXSAVE))
7411 return iemRaiseUndefinedOpcode(pVCpu);
7412 if (pCtx->cr0 & X86_CR0_TS)
7413 return iemRaiseDeviceNotAvailable(pVCpu);
7414 if (GCPtrEff & 63)
7415 {
7416 /** @todo CPU/VM detection possible! \#AC might not be signal for
7417 * all/any misalignment sizes, intel says its an implementation detail. */
7418 if ( (pCtx->cr0 & X86_CR0_AM)
7419 && pCtx->eflags.Bits.u1AC
7420 && pVCpu->iem.s.uCpl == 3)
7421 return iemRaiseAlignmentCheckException(pVCpu);
7422 return iemRaiseGeneralProtectionFault0(pVCpu);
7423 }
7424
7425 /*
7426 * Calc the requested mask
7427 */
7428 uint64_t const fReqComponents = RT_MAKE_U64(pCtx->eax, pCtx->edx) & pCtx->aXcr[0];
7429 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7430 uint64_t const fXInUse = pCtx->aXcr[0];
7431
7432/** @todo figure out the exact protocol for the memory access. Currently we
7433 * just need this crap to work halfways to make it possible to test
7434 * AVX instructions. */
7435/** @todo figure out the XINUSE and XMODIFIED */
7436
7437 /*
7438 * Access the x87 memory state.
7439 */
7440 /* The x87+SSE state. */
7441 void *pvMem512;
7442 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7443 if (rcStrict != VINF_SUCCESS)
7444 return rcStrict;
7445 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7446 PCX86FXSTATE pSrc = &pCtx->CTX_SUFF(pXState)->x87;
7447
7448 /* The header. */
7449 PX86XSAVEHDR pHdr;
7450 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW);
7451 if (rcStrict != VINF_SUCCESS)
7452 return rcStrict;
7453
7454 /*
7455 * Store the X87 state.
7456 */
7457 if (fReqComponents & XSAVE_C_X87)
7458 {
7459 /* common for all formats */
7460 pDst->FCW = pSrc->FCW;
7461 pDst->FSW = pSrc->FSW;
7462 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7463 pDst->FOP = pSrc->FOP;
7464 pDst->FPUIP = pSrc->FPUIP;
7465 pDst->CS = pSrc->CS;
7466 pDst->FPUDP = pSrc->FPUDP;
7467 pDst->DS = pSrc->DS;
7468 if (enmEffOpSize == IEMMODE_64BIT)
7469 {
7470 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7471 pDst->Rsrvd1 = pSrc->Rsrvd1;
7472 pDst->Rsrvd2 = pSrc->Rsrvd2;
7473 pDst->au32RsrvdForSoftware[0] = 0;
7474 }
7475 else
7476 {
7477 pDst->Rsrvd1 = 0;
7478 pDst->Rsrvd2 = 0;
7479 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
7480 }
7481 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7482 {
7483 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
7484 * them for now... */
7485 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7486 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7487 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7488 pDst->aRegs[i].au32[3] = 0;
7489 }
7490
7491 }
7492
7493 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
7494 {
7495 pDst->MXCSR = pSrc->MXCSR;
7496 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7497 }
7498
7499 if (fReqComponents & XSAVE_C_SSE)
7500 {
7501 /* XMM registers. */
7502 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7503 for (uint32_t i = 0; i < cXmmRegs; i++)
7504 pDst->aXMM[i] = pSrc->aXMM[i];
7505 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7506 * right? */
7507 }
7508
7509 /* Commit the x87 state bits. (probably wrong) */
7510 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7511 if (rcStrict != VINF_SUCCESS)
7512 return rcStrict;
7513
7514 /*
7515 * Store AVX state.
7516 */
7517 if (fReqComponents & XSAVE_C_YMM)
7518 {
7519 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
7520 AssertLogRelReturn(pCtx->aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
7521 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
7522 PX86XSAVEYMMHI pCompDst;
7523 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pCtx->aoffXState[XSAVE_C_YMM_BIT],
7524 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7525 if (rcStrict != VINF_SUCCESS)
7526 return rcStrict;
7527
7528 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7529 for (uint32_t i = 0; i < cXmmRegs; i++)
7530 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
7531
7532 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7533 if (rcStrict != VINF_SUCCESS)
7534 return rcStrict;
7535 }
7536
7537 /*
7538 * Update the header.
7539 */
7540 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
7541 | (fReqComponents & fXInUse);
7542
7543 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
7544 if (rcStrict != VINF_SUCCESS)
7545 return rcStrict;
7546
7547 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7548 return VINF_SUCCESS;
7549}
7550
7551
7552/**
7553 * Implements 'XRSTOR'.
7554 *
7555 * @param iEffSeg The effective segment.
7556 * @param GCPtrEff The address of the image.
7557 * @param enmEffOpSize The operand size (only REX.W really matters).
7558 */
7559IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7560{
7561 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7562
7563 /*
7564 * Raise exceptions.
7565 */
7566 if (!(pCtx->cr4 & X86_CR4_OSXSAVE))
7567 return iemRaiseUndefinedOpcode(pVCpu);
7568 if (pCtx->cr0 & X86_CR0_TS)
7569 return iemRaiseDeviceNotAvailable(pVCpu);
7570 if (GCPtrEff & 63)
7571 {
7572 /** @todo CPU/VM detection possible! \#AC might not be signal for
7573 * all/any misalignment sizes, intel says its an implementation detail. */
7574 if ( (pCtx->cr0 & X86_CR0_AM)
7575 && pCtx->eflags.Bits.u1AC
7576 && pVCpu->iem.s.uCpl == 3)
7577 return iemRaiseAlignmentCheckException(pVCpu);
7578 return iemRaiseGeneralProtectionFault0(pVCpu);
7579 }
7580
7581/** @todo figure out the exact protocol for the memory access. Currently we
7582 * just need this crap to work halfways to make it possible to test
7583 * AVX instructions. */
7584/** @todo figure out the XINUSE and XMODIFIED */
7585
7586 /*
7587 * Access the x87 memory state.
7588 */
7589 /* The x87+SSE state. */
7590 void *pvMem512;
7591 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
7592 if (rcStrict != VINF_SUCCESS)
7593 return rcStrict;
7594 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
7595 PX86FXSTATE pDst = &pCtx->CTX_SUFF(pXState)->x87;
7596
7597 /*
7598 * Calc the requested mask
7599 */
7600 PX86XSAVEHDR pHdrDst = &pCtx->CTX_SUFF(pXState)->Hdr;
7601 PCX86XSAVEHDR pHdrSrc;
7602 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_R);
7603 if (rcStrict != VINF_SUCCESS)
7604 return rcStrict;
7605
7606 uint64_t const fReqComponents = RT_MAKE_U64(pCtx->eax, pCtx->edx) & pCtx->aXcr[0];
7607 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7608 //uint64_t const fXInUse = pCtx->aXcr[0];
7609 uint64_t const fRstorMask = pHdrSrc->bmXState;
7610 uint64_t const fCompMask = pHdrSrc->bmXComp;
7611
7612 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7613
7614 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7615
7616 /* We won't need this any longer. */
7617 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
7618 if (rcStrict != VINF_SUCCESS)
7619 return rcStrict;
7620
7621 /*
7622 * Store the X87 state.
7623 */
7624 if (fReqComponents & XSAVE_C_X87)
7625 {
7626 if (fRstorMask & XSAVE_C_X87)
7627 {
7628 pDst->FCW = pSrc->FCW;
7629 pDst->FSW = pSrc->FSW;
7630 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7631 pDst->FOP = pSrc->FOP;
7632 pDst->FPUIP = pSrc->FPUIP;
7633 pDst->CS = pSrc->CS;
7634 pDst->FPUDP = pSrc->FPUDP;
7635 pDst->DS = pSrc->DS;
7636 if (enmEffOpSize == IEMMODE_64BIT)
7637 {
7638 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7639 pDst->Rsrvd1 = pSrc->Rsrvd1;
7640 pDst->Rsrvd2 = pSrc->Rsrvd2;
7641 }
7642 else
7643 {
7644 pDst->Rsrvd1 = 0;
7645 pDst->Rsrvd2 = 0;
7646 }
7647 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7648 {
7649 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7650 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7651 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7652 pDst->aRegs[i].au32[3] = 0;
7653 }
7654 }
7655 else
7656 {
7657 pDst->FCW = 0x37f;
7658 pDst->FSW = 0;
7659 pDst->FTW = 0x00; /* 0 - empty. */
7660 pDst->FPUDP = 0;
7661 pDst->DS = 0; //??
7662 pDst->Rsrvd2= 0;
7663 pDst->FPUIP = 0;
7664 pDst->CS = 0; //??
7665 pDst->Rsrvd1= 0;
7666 pDst->FOP = 0;
7667 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
7668 {
7669 pDst->aRegs[i].au32[0] = 0;
7670 pDst->aRegs[i].au32[1] = 0;
7671 pDst->aRegs[i].au32[2] = 0;
7672 pDst->aRegs[i].au32[3] = 0;
7673 }
7674 }
7675 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
7676 }
7677
7678 /* MXCSR */
7679 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
7680 {
7681 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
7682 pDst->MXCSR = pSrc->MXCSR;
7683 else
7684 pDst->MXCSR = 0x1f80;
7685 }
7686
7687 /* XMM registers. */
7688 if (fReqComponents & XSAVE_C_SSE)
7689 {
7690 if (fRstorMask & XSAVE_C_SSE)
7691 {
7692 for (uint32_t i = 0; i < cXmmRegs; i++)
7693 pDst->aXMM[i] = pSrc->aXMM[i];
7694 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7695 * right? */
7696 }
7697 else
7698 {
7699 for (uint32_t i = 0; i < cXmmRegs; i++)
7700 {
7701 pDst->aXMM[i].au64[0] = 0;
7702 pDst->aXMM[i].au64[1] = 0;
7703 }
7704 }
7705 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
7706 }
7707
7708 /* Unmap the x87 state bits (so we've don't run out of mapping). */
7709 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
7710 if (rcStrict != VINF_SUCCESS)
7711 return rcStrict;
7712
7713 /*
7714 * Restore AVX state.
7715 */
7716 if (fReqComponents & XSAVE_C_YMM)
7717 {
7718 AssertLogRelReturn(pCtx->aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
7719 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
7720
7721 if (fRstorMask & XSAVE_C_YMM)
7722 {
7723 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
7724 PCX86XSAVEYMMHI pCompSrc;
7725 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
7726 iEffSeg, GCPtrEff + pCtx->aoffXState[XSAVE_C_YMM_BIT], IEM_ACCESS_DATA_R);
7727 if (rcStrict != VINF_SUCCESS)
7728 return rcStrict;
7729
7730 for (uint32_t i = 0; i < cXmmRegs; i++)
7731 {
7732 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
7733 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
7734 }
7735
7736 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
7737 if (rcStrict != VINF_SUCCESS)
7738 return rcStrict;
7739 }
7740 else
7741 {
7742 for (uint32_t i = 0; i < cXmmRegs; i++)
7743 {
7744 pCompDst->aYmmHi[i].au64[0] = 0;
7745 pCompDst->aYmmHi[i].au64[1] = 0;
7746 }
7747 }
7748 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
7749 }
7750
7751 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7752 return VINF_SUCCESS;
7753}
7754
7755
7756
7757
7758/**
7759 * Implements 'STMXCSR'.
7760 *
7761 * @param GCPtrEff The address of the image.
7762 */
7763IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7764{
7765 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7766
7767 /*
7768 * Raise exceptions.
7769 */
7770 if ( !(pCtx->cr0 & X86_CR0_EM)
7771 && (pCtx->cr4 & X86_CR4_OSFXSR))
7772 {
7773 if (!(pCtx->cr0 & X86_CR0_TS))
7774 {
7775 /*
7776 * Do the job.
7777 */
7778 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pCtx->CTX_SUFF(pXState)->x87.MXCSR);
7779 if (rcStrict == VINF_SUCCESS)
7780 {
7781 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7782 return VINF_SUCCESS;
7783 }
7784 return rcStrict;
7785 }
7786 return iemRaiseDeviceNotAvailable(pVCpu);
7787 }
7788 return iemRaiseUndefinedOpcode(pVCpu);
7789}
7790
7791
7792/**
7793 * Implements 'VSTMXCSR'.
7794 *
7795 * @param GCPtrEff The address of the image.
7796 */
7797IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7798{
7799 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7800
7801 /*
7802 * Raise exceptions.
7803 */
7804 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
7805 ? (pCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
7806 : !(pCtx->cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
7807 && (pCtx->cr4 & X86_CR4_OSXSAVE))
7808 {
7809 if (!(pCtx->cr0 & X86_CR0_TS))
7810 {
7811 /*
7812 * Do the job.
7813 */
7814 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pCtx->CTX_SUFF(pXState)->x87.MXCSR);
7815 if (rcStrict == VINF_SUCCESS)
7816 {
7817 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7818 return VINF_SUCCESS;
7819 }
7820 return rcStrict;
7821 }
7822 return iemRaiseDeviceNotAvailable(pVCpu);
7823 }
7824 return iemRaiseUndefinedOpcode(pVCpu);
7825}
7826
7827
7828/**
7829 * Implements 'LDMXCSR'.
7830 *
7831 * @param GCPtrEff The address of the image.
7832 */
7833IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7834{
7835 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
7836
7837 /*
7838 * Raise exceptions.
7839 */
7840 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
7841 * happen after or before \#UD and \#EM? */
7842 if ( !(pCtx->cr0 & X86_CR0_EM)
7843 && (pCtx->cr4 & X86_CR4_OSFXSR))
7844 {
7845 if (!(pCtx->cr0 & X86_CR0_TS))
7846 {
7847 /*
7848 * Do the job.
7849 */
7850 uint32_t fNewMxCsr;
7851 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
7852 if (rcStrict == VINF_SUCCESS)
7853 {
7854 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7855 if (!(fNewMxCsr & ~fMxCsrMask))
7856 {
7857 pCtx->CTX_SUFF(pXState)->x87.MXCSR = fNewMxCsr;
7858 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7859 return VINF_SUCCESS;
7860 }
7861 Log(("lddmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
7862 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
7863 return iemRaiseGeneralProtectionFault0(pVCpu);
7864 }
7865 return rcStrict;
7866 }
7867 return iemRaiseDeviceNotAvailable(pVCpu);
7868 }
7869 return iemRaiseUndefinedOpcode(pVCpu);
7870}
7871
7872
7873/**
7874 * Commmon routine for fnstenv and fnsave.
7875 *
7876 * @param uPtr Where to store the state.
7877 * @param pCtx The CPU context.
7878 */
7879static void iemCImplCommonFpuStoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr, PCCPUMCTX pCtx)
7880{
7881 PCX86FXSTATE pSrcX87 = &pCtx->CTX_SUFF(pXState)->x87;
7882 if (enmEffOpSize == IEMMODE_16BIT)
7883 {
7884 uPtr.pu16[0] = pSrcX87->FCW;
7885 uPtr.pu16[1] = pSrcX87->FSW;
7886 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
7887 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
7888 {
7889 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
7890 * protected mode or long mode and we save it in real mode? And vice
7891 * versa? And with 32-bit operand size? I think CPU is storing the
7892 * effective address ((CS << 4) + IP) in the offset register and not
7893 * doing any address calculations here. */
7894 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
7895 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
7896 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
7897 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
7898 }
7899 else
7900 {
7901 uPtr.pu16[3] = pSrcX87->FPUIP;
7902 uPtr.pu16[4] = pSrcX87->CS;
7903 uPtr.pu16[5] = pSrcX87->FPUDP;
7904 uPtr.pu16[6] = pSrcX87->DS;
7905 }
7906 }
7907 else
7908 {
7909 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
7910 uPtr.pu16[0*2] = pSrcX87->FCW;
7911 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
7912 uPtr.pu16[1*2] = pSrcX87->FSW;
7913 uPtr.pu16[1*2+1] = 0xffff;
7914 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
7915 uPtr.pu16[2*2+1] = 0xffff;
7916 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
7917 {
7918 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
7919 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
7920 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
7921 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
7922 }
7923 else
7924 {
7925 uPtr.pu32[3] = pSrcX87->FPUIP;
7926 uPtr.pu16[4*2] = pSrcX87->CS;
7927 uPtr.pu16[4*2+1] = pSrcX87->FOP;
7928 uPtr.pu32[5] = pSrcX87->FPUDP;
7929 uPtr.pu16[6*2] = pSrcX87->DS;
7930 uPtr.pu16[6*2+1] = 0xffff;
7931 }
7932 }
7933}
7934
7935
7936/**
7937 * Commmon routine for fldenv and frstor
7938 *
7939 * @param uPtr Where to store the state.
7940 * @param pCtx The CPU context.
7941 */
7942static void iemCImplCommonFpuRestoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr, PCPUMCTX pCtx)
7943{
7944 PX86FXSTATE pDstX87 = &pCtx->CTX_SUFF(pXState)->x87;
7945 if (enmEffOpSize == IEMMODE_16BIT)
7946 {
7947 pDstX87->FCW = uPtr.pu16[0];
7948 pDstX87->FSW = uPtr.pu16[1];
7949 pDstX87->FTW = uPtr.pu16[2];
7950 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
7951 {
7952 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
7953 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
7954 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
7955 pDstX87->CS = 0;
7956 pDstX87->Rsrvd1= 0;
7957 pDstX87->DS = 0;
7958 pDstX87->Rsrvd2= 0;
7959 }
7960 else
7961 {
7962 pDstX87->FPUIP = uPtr.pu16[3];
7963 pDstX87->CS = uPtr.pu16[4];
7964 pDstX87->Rsrvd1= 0;
7965 pDstX87->FPUDP = uPtr.pu16[5];
7966 pDstX87->DS = uPtr.pu16[6];
7967 pDstX87->Rsrvd2= 0;
7968 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
7969 }
7970 }
7971 else
7972 {
7973 pDstX87->FCW = uPtr.pu16[0*2];
7974 pDstX87->FSW = uPtr.pu16[1*2];
7975 pDstX87->FTW = uPtr.pu16[2*2];
7976 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
7977 {
7978 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
7979 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
7980 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
7981 pDstX87->CS = 0;
7982 pDstX87->Rsrvd1= 0;
7983 pDstX87->DS = 0;
7984 pDstX87->Rsrvd2= 0;
7985 }
7986 else
7987 {
7988 pDstX87->FPUIP = uPtr.pu32[3];
7989 pDstX87->CS = uPtr.pu16[4*2];
7990 pDstX87->Rsrvd1= 0;
7991 pDstX87->FOP = uPtr.pu16[4*2+1];
7992 pDstX87->FPUDP = uPtr.pu32[5];
7993 pDstX87->DS = uPtr.pu16[6*2];
7994 pDstX87->Rsrvd2= 0;
7995 }
7996 }
7997
7998 /* Make adjustments. */
7999 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
8000 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
8001 iemFpuRecalcExceptionStatus(pDstX87);
8002 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
8003 * exceptions are pending after loading the saved state? */
8004}
8005
8006
8007/**
8008 * Implements 'FNSTENV'.
8009 *
8010 * @param enmEffOpSize The operand size (only REX.W really matters).
8011 * @param iEffSeg The effective segment register for @a GCPtrEff.
8012 * @param GCPtrEffDst The address of the image.
8013 */
8014IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8015{
8016 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8017 RTPTRUNION uPtr;
8018 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8019 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8020 if (rcStrict != VINF_SUCCESS)
8021 return rcStrict;
8022
8023 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr, pCtx);
8024
8025 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8026 if (rcStrict != VINF_SUCCESS)
8027 return rcStrict;
8028
8029 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8030 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8031 return VINF_SUCCESS;
8032}
8033
8034
8035/**
8036 * Implements 'FNSAVE'.
8037 *
8038 * @param GCPtrEffDst The address of the image.
8039 * @param enmEffOpSize The operand size.
8040 */
8041IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8042{
8043 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8044 RTPTRUNION uPtr;
8045 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8046 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8047 if (rcStrict != VINF_SUCCESS)
8048 return rcStrict;
8049
8050 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
8051 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr, pCtx);
8052 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8053 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8054 {
8055 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
8056 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
8057 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
8058 }
8059
8060 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8061 if (rcStrict != VINF_SUCCESS)
8062 return rcStrict;
8063
8064 /*
8065 * Re-initialize the FPU context.
8066 */
8067 pFpuCtx->FCW = 0x37f;
8068 pFpuCtx->FSW = 0;
8069 pFpuCtx->FTW = 0x00; /* 0 - empty */
8070 pFpuCtx->FPUDP = 0;
8071 pFpuCtx->DS = 0;
8072 pFpuCtx->Rsrvd2= 0;
8073 pFpuCtx->FPUIP = 0;
8074 pFpuCtx->CS = 0;
8075 pFpuCtx->Rsrvd1= 0;
8076 pFpuCtx->FOP = 0;
8077
8078 iemHlpUsedFpu(pVCpu);
8079 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8080 return VINF_SUCCESS;
8081}
8082
8083
8084
8085/**
8086 * Implements 'FLDENV'.
8087 *
8088 * @param enmEffOpSize The operand size (only REX.W really matters).
8089 * @param iEffSeg The effective segment register for @a GCPtrEff.
8090 * @param GCPtrEffSrc The address of the image.
8091 */
8092IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8093{
8094 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8095 RTCPTRUNION uPtr;
8096 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8097 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8098 if (rcStrict != VINF_SUCCESS)
8099 return rcStrict;
8100
8101 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr, pCtx);
8102
8103 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8104 if (rcStrict != VINF_SUCCESS)
8105 return rcStrict;
8106
8107 iemHlpUsedFpu(pVCpu);
8108 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8109 return VINF_SUCCESS;
8110}
8111
8112
8113/**
8114 * Implements 'FRSTOR'.
8115 *
8116 * @param GCPtrEffSrc The address of the image.
8117 * @param enmEffOpSize The operand size.
8118 */
8119IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8120{
8121 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8122 RTCPTRUNION uPtr;
8123 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8124 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8125 if (rcStrict != VINF_SUCCESS)
8126 return rcStrict;
8127
8128 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
8129 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr, pCtx);
8130 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8131 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8132 {
8133 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
8134 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
8135 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
8136 pFpuCtx->aRegs[i].au32[3] = 0;
8137 }
8138
8139 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8140 if (rcStrict != VINF_SUCCESS)
8141 return rcStrict;
8142
8143 iemHlpUsedFpu(pVCpu);
8144 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8145 return VINF_SUCCESS;
8146}
8147
8148
8149/**
8150 * Implements 'FLDCW'.
8151 *
8152 * @param u16Fcw The new FCW.
8153 */
8154IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
8155{
8156 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8157
8158 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
8159 /** @todo Testcase: Try see what happens when trying to set undefined bits
8160 * (other than 6 and 7). Currently ignoring them. */
8161 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
8162 * according to FSW. (This is was is currently implemented.) */
8163 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
8164 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
8165 iemFpuRecalcExceptionStatus(pFpuCtx);
8166
8167 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8168 iemHlpUsedFpu(pVCpu);
8169 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8170 return VINF_SUCCESS;
8171}
8172
8173
8174
8175/**
8176 * Implements the underflow case of fxch.
8177 *
8178 * @param iStReg The other stack register.
8179 */
8180IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
8181{
8182 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8183
8184 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
8185 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
8186 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8187 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
8188
8189 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
8190 * registers are read as QNaN and then exchanged. This could be
8191 * wrong... */
8192 if (pFpuCtx->FCW & X86_FCW_IM)
8193 {
8194 if (RT_BIT(iReg1) & pFpuCtx->FTW)
8195 {
8196 if (RT_BIT(iReg2) & pFpuCtx->FTW)
8197 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8198 else
8199 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
8200 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
8201 }
8202 else
8203 {
8204 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
8205 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8206 }
8207 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
8208 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
8209 }
8210 else
8211 {
8212 /* raise underflow exception, don't change anything. */
8213 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
8214 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8215 }
8216
8217 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pCtx, pFpuCtx);
8218 iemHlpUsedFpu(pVCpu);
8219 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8220 return VINF_SUCCESS;
8221}
8222
8223
8224/**
8225 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
8226 *
8227 * @param cToAdd 1 or 7.
8228 */
8229IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
8230{
8231 PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
8232 Assert(iStReg < 8);
8233
8234 /*
8235 * Raise exceptions.
8236 */
8237 if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
8238 return iemRaiseDeviceNotAvailable(pVCpu);
8239
8240 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
8241 uint16_t u16Fsw = pFpuCtx->FSW;
8242 if (u16Fsw & X86_FSW_ES)
8243 return iemRaiseMathFault(pVCpu);
8244
8245 /*
8246 * Check if any of the register accesses causes #SF + #IA.
8247 */
8248 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
8249 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8250 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
8251 {
8252 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
8253 NOREF(u32Eflags);
8254
8255 pFpuCtx->FSW &= ~X86_FSW_C1;
8256 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
8257 if ( !(u16Fsw & X86_FSW_IE)
8258 || (pFpuCtx->FCW & X86_FCW_IM) )
8259 {
8260 pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8261 pCtx->eflags.u |= pCtx->eflags.u & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8262 }
8263 }
8264 else if (pFpuCtx->FCW & X86_FCW_IM)
8265 {
8266 /* Masked underflow. */
8267 pFpuCtx->FSW &= ~X86_FSW_C1;
8268 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
8269 pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8270 pCtx->eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
8271 }
8272 else
8273 {
8274 /* Raise underflow - don't touch EFLAGS or TOP. */
8275 pFpuCtx->FSW &= ~X86_FSW_C1;
8276 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8277 fPop = false;
8278 }
8279
8280 /*
8281 * Pop if necessary.
8282 */
8283 if (fPop)
8284 {
8285 pFpuCtx->FTW &= ~RT_BIT(iReg1);
8286 pFpuCtx->FSW &= X86_FSW_TOP_MASK;
8287 pFpuCtx->FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
8288 }
8289
8290 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pCtx, pFpuCtx);
8291 iemHlpUsedFpu(pVCpu);
8292 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8293 return VINF_SUCCESS;
8294}
8295
8296/** @} */
8297
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