VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h@ 74679

Last change on this file since 74679 was 74661, checked in by vboxsync, 6 years ago

VMM/IEM: Nested VMX: bugref:9180 VM-exit bits; Added IN/OUT intercepts.
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File size: 314.5 KB
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1/* $Id: IEMAllCImpl.cpp.h 74661 2018-10-08 09:46:26Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#include "IEMAllCImplSvmInstr.cpp.h"
19#include "IEMAllCImplVmxInstr.cpp.h"
20
21
22/** @name Misc Helpers
23 * @{
24 */
25
26
27/**
28 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
29 *
30 * @returns Strict VBox status code.
31 *
32 * @param pVCpu The cross context virtual CPU structure of the calling thread.
33 * @param u16Port The port number.
34 * @param cbOperand The operand size.
35 */
36static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbOperand)
37{
38 /* The TSS bits we're interested in are the same on 386 and AMD64. */
39 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
40 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
41 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
42 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
43
44 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
45
46 /*
47 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
48 */
49 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
50 if (RT_UNLIKELY( pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
51 && pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
52 {
53 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
54 u16Port, cbOperand, pVCpu->cpum.GstCtx.tr.Attr.n.u4Type, pVCpu->cpum.GstCtx.tr.Attr.u));
55 return iemRaiseGeneralProtectionFault0(pVCpu);
56 }
57
58 /*
59 * Read the bitmap offset (may #PF).
60 */
61 uint16_t offBitmap;
62 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
63 pVCpu->cpum.GstCtx.tr.u64Base + RT_UOFFSETOF(X86TSS64, offIoBitmap));
64 if (rcStrict != VINF_SUCCESS)
65 {
66 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
67 return rcStrict;
68 }
69
70 /*
71 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
72 * describes the CPU actually reading two bytes regardless of whether the
73 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
74 */
75 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
76 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
77 * for instance sizeof(X86TSS32). */
78 if (offFirstBit + 1 > pVCpu->cpum.GstCtx.tr.u32Limit) /* the limit is inclusive */
79 {
80 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
81 offFirstBit, pVCpu->cpum.GstCtx.tr.u32Limit));
82 return iemRaiseGeneralProtectionFault0(pVCpu);
83 }
84
85 /*
86 * Read the necessary bits.
87 */
88 /** @todo Test the assertion in the intel manual that the CPU reads two
89 * bytes. The question is how this works wrt to #PF and #GP on the
90 * 2nd byte when it's not required. */
91 uint16_t bmBytes = UINT16_MAX;
92 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base + offFirstBit);
93 if (rcStrict != VINF_SUCCESS)
94 {
95 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
96 return rcStrict;
97 }
98
99 /*
100 * Perform the check.
101 */
102 uint16_t fPortMask = (1 << cbOperand) - 1;
103 bmBytes >>= (u16Port & 7);
104 if (bmBytes & fPortMask)
105 {
106 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
107 u16Port, cbOperand, bmBytes, fPortMask));
108 return iemRaiseGeneralProtectionFault0(pVCpu);
109 }
110
111 return VINF_SUCCESS;
112}
113
114
115/**
116 * Checks if we are allowed to access the given I/O port, raising the
117 * appropriate exceptions if we aren't (or if the I/O bitmap is not
118 * accessible).
119 *
120 * @returns Strict VBox status code.
121 *
122 * @param pVCpu The cross context virtual CPU structure of the calling thread.
123 * @param u16Port The port number.
124 * @param cbOperand The operand size.
125 */
126DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPU pVCpu, uint16_t u16Port, uint8_t cbOperand)
127{
128 X86EFLAGS Efl;
129 Efl.u = IEMMISC_GET_EFL(pVCpu);
130 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
131 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
132 || Efl.Bits.u1VM) )
133 return iemHlpCheckPortIOPermissionBitmap(pVCpu, u16Port, cbOperand);
134 return VINF_SUCCESS;
135}
136
137
138#if 0
139/**
140 * Calculates the parity bit.
141 *
142 * @returns true if the bit is set, false if not.
143 * @param u8Result The least significant byte of the result.
144 */
145static bool iemHlpCalcParityFlag(uint8_t u8Result)
146{
147 /*
148 * Parity is set if the number of bits in the least significant byte of
149 * the result is even.
150 */
151 uint8_t cBits;
152 cBits = u8Result & 1; /* 0 */
153 u8Result >>= 1;
154 cBits += u8Result & 1;
155 u8Result >>= 1;
156 cBits += u8Result & 1;
157 u8Result >>= 1;
158 cBits += u8Result & 1;
159 u8Result >>= 1;
160 cBits += u8Result & 1; /* 4 */
161 u8Result >>= 1;
162 cBits += u8Result & 1;
163 u8Result >>= 1;
164 cBits += u8Result & 1;
165 u8Result >>= 1;
166 cBits += u8Result & 1;
167 return !(cBits & 1);
168}
169#endif /* not used */
170
171
172/**
173 * Updates the specified flags according to a 8-bit result.
174 *
175 * @param pVCpu The cross context virtual CPU structure of the calling thread.
176 * @param u8Result The result to set the flags according to.
177 * @param fToUpdate The flags to update.
178 * @param fUndefined The flags that are specified as undefined.
179 */
180static void iemHlpUpdateArithEFlagsU8(PVMCPU pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
181{
182 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
183 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
184 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
185 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
186}
187
188
189/**
190 * Updates the specified flags according to a 16-bit result.
191 *
192 * @param pVCpu The cross context virtual CPU structure of the calling thread.
193 * @param u16Result The result to set the flags according to.
194 * @param fToUpdate The flags to update.
195 * @param fUndefined The flags that are specified as undefined.
196 */
197static void iemHlpUpdateArithEFlagsU16(PVMCPU pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
198{
199 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
200 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
201 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
202 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
203}
204
205
206/**
207 * Helper used by iret.
208 *
209 * @param pVCpu The cross context virtual CPU structure of the calling thread.
210 * @param uCpl The new CPL.
211 * @param pSReg Pointer to the segment register.
212 */
213static void iemHlpAdjustSelectorForNewCpl(PVMCPU pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
214{
215#ifdef VBOX_WITH_RAW_MODE_NOT_R0
216 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg))
217 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, pSReg);
218#else
219 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
220#endif
221 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
222
223 if ( uCpl > pSReg->Attr.n.u2Dpl
224 && pSReg->Attr.n.u1DescType /* code or data, not system */
225 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
226 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
227 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
228}
229
230
231/**
232 * Indicates that we have modified the FPU state.
233 *
234 * @param pVCpu The cross context virtual CPU structure of the calling thread.
235 */
236DECLINLINE(void) iemHlpUsedFpu(PVMCPU pVCpu)
237{
238 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
239}
240
241/** @} */
242
243/** @name C Implementations
244 * @{
245 */
246
247/**
248 * Implements a 16-bit popa.
249 */
250IEM_CIMPL_DEF_0(iemCImpl_popa_16)
251{
252 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
253 RTGCPTR GCPtrLast = GCPtrStart + 15;
254 VBOXSTRICTRC rcStrict;
255
256 /*
257 * The docs are a bit hard to comprehend here, but it looks like we wrap
258 * around in real mode as long as none of the individual "popa" crosses the
259 * end of the stack segment. In protected mode we check the whole access
260 * in one go. For efficiency, only do the word-by-word thing if we're in
261 * danger of wrapping around.
262 */
263 /** @todo do popa boundary / wrap-around checks. */
264 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
265 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
266 {
267 /* word-by-word */
268 RTUINT64U TmpRsp;
269 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
270 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.di, &TmpRsp);
271 if (rcStrict == VINF_SUCCESS)
272 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.si, &TmpRsp);
273 if (rcStrict == VINF_SUCCESS)
274 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bp, &TmpRsp);
275 if (rcStrict == VINF_SUCCESS)
276 {
277 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
278 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bx, &TmpRsp);
279 }
280 if (rcStrict == VINF_SUCCESS)
281 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.dx, &TmpRsp);
282 if (rcStrict == VINF_SUCCESS)
283 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.cx, &TmpRsp);
284 if (rcStrict == VINF_SUCCESS)
285 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.ax, &TmpRsp);
286 if (rcStrict == VINF_SUCCESS)
287 {
288 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
290 }
291 }
292 else
293 {
294 uint16_t const *pa16Mem = NULL;
295 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
296 if (rcStrict == VINF_SUCCESS)
297 {
298 pVCpu->cpum.GstCtx.di = pa16Mem[7 - X86_GREG_xDI];
299 pVCpu->cpum.GstCtx.si = pa16Mem[7 - X86_GREG_xSI];
300 pVCpu->cpum.GstCtx.bp = pa16Mem[7 - X86_GREG_xBP];
301 /* skip sp */
302 pVCpu->cpum.GstCtx.bx = pa16Mem[7 - X86_GREG_xBX];
303 pVCpu->cpum.GstCtx.dx = pa16Mem[7 - X86_GREG_xDX];
304 pVCpu->cpum.GstCtx.cx = pa16Mem[7 - X86_GREG_xCX];
305 pVCpu->cpum.GstCtx.ax = pa16Mem[7 - X86_GREG_xAX];
306 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
307 if (rcStrict == VINF_SUCCESS)
308 {
309 iemRegAddToRsp(pVCpu, 16);
310 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
311 }
312 }
313 }
314 return rcStrict;
315}
316
317
318/**
319 * Implements a 32-bit popa.
320 */
321IEM_CIMPL_DEF_0(iemCImpl_popa_32)
322{
323 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
324 RTGCPTR GCPtrLast = GCPtrStart + 31;
325 VBOXSTRICTRC rcStrict;
326
327 /*
328 * The docs are a bit hard to comprehend here, but it looks like we wrap
329 * around in real mode as long as none of the individual "popa" crosses the
330 * end of the stack segment. In protected mode we check the whole access
331 * in one go. For efficiency, only do the word-by-word thing if we're in
332 * danger of wrapping around.
333 */
334 /** @todo do popa boundary / wrap-around checks. */
335 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
336 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
337 {
338 /* word-by-word */
339 RTUINT64U TmpRsp;
340 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
341 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edi, &TmpRsp);
342 if (rcStrict == VINF_SUCCESS)
343 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.esi, &TmpRsp);
344 if (rcStrict == VINF_SUCCESS)
345 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebp, &TmpRsp);
346 if (rcStrict == VINF_SUCCESS)
347 {
348 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
349 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebx, &TmpRsp);
350 }
351 if (rcStrict == VINF_SUCCESS)
352 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edx, &TmpRsp);
353 if (rcStrict == VINF_SUCCESS)
354 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ecx, &TmpRsp);
355 if (rcStrict == VINF_SUCCESS)
356 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.eax, &TmpRsp);
357 if (rcStrict == VINF_SUCCESS)
358 {
359#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
360 pVCpu->cpum.GstCtx.rdi &= UINT32_MAX;
361 pVCpu->cpum.GstCtx.rsi &= UINT32_MAX;
362 pVCpu->cpum.GstCtx.rbp &= UINT32_MAX;
363 pVCpu->cpum.GstCtx.rbx &= UINT32_MAX;
364 pVCpu->cpum.GstCtx.rdx &= UINT32_MAX;
365 pVCpu->cpum.GstCtx.rcx &= UINT32_MAX;
366 pVCpu->cpum.GstCtx.rax &= UINT32_MAX;
367#endif
368 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
369 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
370 }
371 }
372 else
373 {
374 uint32_t const *pa32Mem;
375 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R);
376 if (rcStrict == VINF_SUCCESS)
377 {
378 pVCpu->cpum.GstCtx.rdi = pa32Mem[7 - X86_GREG_xDI];
379 pVCpu->cpum.GstCtx.rsi = pa32Mem[7 - X86_GREG_xSI];
380 pVCpu->cpum.GstCtx.rbp = pa32Mem[7 - X86_GREG_xBP];
381 /* skip esp */
382 pVCpu->cpum.GstCtx.rbx = pa32Mem[7 - X86_GREG_xBX];
383 pVCpu->cpum.GstCtx.rdx = pa32Mem[7 - X86_GREG_xDX];
384 pVCpu->cpum.GstCtx.rcx = pa32Mem[7 - X86_GREG_xCX];
385 pVCpu->cpum.GstCtx.rax = pa32Mem[7 - X86_GREG_xAX];
386 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
387 if (rcStrict == VINF_SUCCESS)
388 {
389 iemRegAddToRsp(pVCpu, 32);
390 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
391 }
392 }
393 }
394 return rcStrict;
395}
396
397
398/**
399 * Implements a 16-bit pusha.
400 */
401IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
402{
403 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
404 RTGCPTR GCPtrBottom = GCPtrTop - 15;
405 VBOXSTRICTRC rcStrict;
406
407 /*
408 * The docs are a bit hard to comprehend here, but it looks like we wrap
409 * around in real mode as long as none of the individual "pushd" crosses the
410 * end of the stack segment. In protected mode we check the whole access
411 * in one go. For efficiency, only do the word-by-word thing if we're in
412 * danger of wrapping around.
413 */
414 /** @todo do pusha boundary / wrap-around checks. */
415 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
416 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
417 {
418 /* word-by-word */
419 RTUINT64U TmpRsp;
420 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
421 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.ax, &TmpRsp);
422 if (rcStrict == VINF_SUCCESS)
423 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.cx, &TmpRsp);
424 if (rcStrict == VINF_SUCCESS)
425 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.dx, &TmpRsp);
426 if (rcStrict == VINF_SUCCESS)
427 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bx, &TmpRsp);
428 if (rcStrict == VINF_SUCCESS)
429 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.sp, &TmpRsp);
430 if (rcStrict == VINF_SUCCESS)
431 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bp, &TmpRsp);
432 if (rcStrict == VINF_SUCCESS)
433 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.si, &TmpRsp);
434 if (rcStrict == VINF_SUCCESS)
435 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.di, &TmpRsp);
436 if (rcStrict == VINF_SUCCESS)
437 {
438 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
439 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
440 }
441 }
442 else
443 {
444 GCPtrBottom--;
445 uint16_t *pa16Mem = NULL;
446 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
447 if (rcStrict == VINF_SUCCESS)
448 {
449 pa16Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.di;
450 pa16Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.si;
451 pa16Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.bp;
452 pa16Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.sp;
453 pa16Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.bx;
454 pa16Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.dx;
455 pa16Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.cx;
456 pa16Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.ax;
457 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
458 if (rcStrict == VINF_SUCCESS)
459 {
460 iemRegSubFromRsp(pVCpu, 16);
461 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
462 }
463 }
464 }
465 return rcStrict;
466}
467
468
469/**
470 * Implements a 32-bit pusha.
471 */
472IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
473{
474 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
475 RTGCPTR GCPtrBottom = GCPtrTop - 31;
476 VBOXSTRICTRC rcStrict;
477
478 /*
479 * The docs are a bit hard to comprehend here, but it looks like we wrap
480 * around in real mode as long as none of the individual "pusha" crosses the
481 * end of the stack segment. In protected mode we check the whole access
482 * in one go. For efficiency, only do the word-by-word thing if we're in
483 * danger of wrapping around.
484 */
485 /** @todo do pusha boundary / wrap-around checks. */
486 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
487 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
488 {
489 /* word-by-word */
490 RTUINT64U TmpRsp;
491 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
492 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.eax, &TmpRsp);
493 if (rcStrict == VINF_SUCCESS)
494 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ecx, &TmpRsp);
495 if (rcStrict == VINF_SUCCESS)
496 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edx, &TmpRsp);
497 if (rcStrict == VINF_SUCCESS)
498 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebx, &TmpRsp);
499 if (rcStrict == VINF_SUCCESS)
500 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esp, &TmpRsp);
501 if (rcStrict == VINF_SUCCESS)
502 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebp, &TmpRsp);
503 if (rcStrict == VINF_SUCCESS)
504 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esi, &TmpRsp);
505 if (rcStrict == VINF_SUCCESS)
506 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edi, &TmpRsp);
507 if (rcStrict == VINF_SUCCESS)
508 {
509 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
510 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
511 }
512 }
513 else
514 {
515 GCPtrBottom--;
516 uint32_t *pa32Mem;
517 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W);
518 if (rcStrict == VINF_SUCCESS)
519 {
520 pa32Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.edi;
521 pa32Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.esi;
522 pa32Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.ebp;
523 pa32Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.esp;
524 pa32Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.ebx;
525 pa32Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.edx;
526 pa32Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.ecx;
527 pa32Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.eax;
528 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
529 if (rcStrict == VINF_SUCCESS)
530 {
531 iemRegSubFromRsp(pVCpu, 32);
532 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
533 }
534 }
535 }
536 return rcStrict;
537}
538
539
540/**
541 * Implements pushf.
542 *
543 *
544 * @param enmEffOpSize The effective operand size.
545 */
546IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
547{
548 VBOXSTRICTRC rcStrict;
549
550 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
551 {
552 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
553 IEM_SVM_UPDATE_NRIP(pVCpu);
554 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
555 }
556
557 /*
558 * If we're in V8086 mode some care is required (which is why we're in
559 * doing this in a C implementation).
560 */
561 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
562 if ( (fEfl & X86_EFL_VM)
563 && X86_EFL_GET_IOPL(fEfl) != 3 )
564 {
565 Assert(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE);
566 if ( enmEffOpSize != IEMMODE_16BIT
567 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
568 return iemRaiseGeneralProtectionFault0(pVCpu);
569 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
570 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
571 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
572 }
573 else
574 {
575
576 /*
577 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
578 */
579 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
580
581 switch (enmEffOpSize)
582 {
583 case IEMMODE_16BIT:
584 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
585 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
586 fEfl |= UINT16_C(0xf000);
587 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
588 break;
589 case IEMMODE_32BIT:
590 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
591 break;
592 case IEMMODE_64BIT:
593 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
594 break;
595 IEM_NOT_REACHED_DEFAULT_CASE_RET();
596 }
597 }
598 if (rcStrict != VINF_SUCCESS)
599 return rcStrict;
600
601 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
602 return VINF_SUCCESS;
603}
604
605
606/**
607 * Implements popf.
608 *
609 * @param enmEffOpSize The effective operand size.
610 */
611IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
612{
613 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu);
614 VBOXSTRICTRC rcStrict;
615 uint32_t fEflNew;
616
617 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
618 {
619 Log2(("popf: Guest intercept -> #VMEXIT\n"));
620 IEM_SVM_UPDATE_NRIP(pVCpu);
621 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
622 }
623
624 /*
625 * V8086 is special as usual.
626 */
627 if (fEflOld & X86_EFL_VM)
628 {
629 /*
630 * Almost anything goes if IOPL is 3.
631 */
632 if (X86_EFL_GET_IOPL(fEflOld) == 3)
633 {
634 switch (enmEffOpSize)
635 {
636 case IEMMODE_16BIT:
637 {
638 uint16_t u16Value;
639 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
640 if (rcStrict != VINF_SUCCESS)
641 return rcStrict;
642 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
643 break;
644 }
645 case IEMMODE_32BIT:
646 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
647 if (rcStrict != VINF_SUCCESS)
648 return rcStrict;
649 break;
650 IEM_NOT_REACHED_DEFAULT_CASE_RET();
651 }
652
653 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
654 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
655 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
656 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
657 }
658 /*
659 * Interrupt flag virtualization with CR4.VME=1.
660 */
661 else if ( enmEffOpSize == IEMMODE_16BIT
662 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
663 {
664 uint16_t u16Value;
665 RTUINT64U TmpRsp;
666 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
667 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
668 if (rcStrict != VINF_SUCCESS)
669 return rcStrict;
670
671 /** @todo Is the popf VME #GP(0) delivered after updating RSP+RIP
672 * or before? */
673 if ( ( (u16Value & X86_EFL_IF)
674 && (fEflOld & X86_EFL_VIP))
675 || (u16Value & X86_EFL_TF) )
676 return iemRaiseGeneralProtectionFault0(pVCpu);
677
678 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
679 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
680 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
681 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
682
683 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
684 }
685 else
686 return iemRaiseGeneralProtectionFault0(pVCpu);
687
688 }
689 /*
690 * Not in V8086 mode.
691 */
692 else
693 {
694 /* Pop the flags. */
695 switch (enmEffOpSize)
696 {
697 case IEMMODE_16BIT:
698 {
699 uint16_t u16Value;
700 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
701 if (rcStrict != VINF_SUCCESS)
702 return rcStrict;
703 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
704
705 /*
706 * Ancient CPU adjustments:
707 * - 8086, 80186, V20/30:
708 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
709 * practical reasons (masking below). We add them when pushing flags.
710 * - 80286:
711 * The NT and IOPL flags cannot be popped from real mode and are
712 * therefore always zero (since a 286 can never exit from PM and
713 * their initial value is zero). This changed on a 386 and can
714 * therefore be used to detect 286 or 386 CPU in real mode.
715 */
716 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
717 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
718 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
719 break;
720 }
721 case IEMMODE_32BIT:
722 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
723 if (rcStrict != VINF_SUCCESS)
724 return rcStrict;
725 break;
726 case IEMMODE_64BIT:
727 {
728 uint64_t u64Value;
729 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
730 if (rcStrict != VINF_SUCCESS)
731 return rcStrict;
732 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
733 break;
734 }
735 IEM_NOT_REACHED_DEFAULT_CASE_RET();
736 }
737
738 /* Merge them with the current flags. */
739 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
740 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
741 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
742 || pVCpu->iem.s.uCpl == 0)
743 {
744 fEflNew &= fPopfBits;
745 fEflNew |= ~fPopfBits & fEflOld;
746 }
747 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
748 {
749 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
750 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
751 }
752 else
753 {
754 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
755 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
756 }
757 }
758
759 /*
760 * Commit the flags.
761 */
762 Assert(fEflNew & RT_BIT_32(1));
763 IEMMISC_SET_EFL(pVCpu, fEflNew);
764 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
765
766 return VINF_SUCCESS;
767}
768
769
770/**
771 * Implements an indirect call.
772 *
773 * @param uNewPC The new program counter (RIP) value (loaded from the
774 * operand).
775 * @param enmEffOpSize The effective operand size.
776 */
777IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
778{
779 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
780 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
781 return iemRaiseGeneralProtectionFault0(pVCpu);
782
783 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
784 if (rcStrict != VINF_SUCCESS)
785 return rcStrict;
786
787 pVCpu->cpum.GstCtx.rip = uNewPC;
788 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
789
790#ifndef IEM_WITH_CODE_TLB
791 /* Flush the prefetch buffer. */
792 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
793#endif
794 return VINF_SUCCESS;
795}
796
797
798/**
799 * Implements a 16-bit relative call.
800 *
801 * @param offDisp The displacment offset.
802 */
803IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
804{
805 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
806 uint16_t uNewPC = uOldPC + offDisp;
807 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
808 return iemRaiseGeneralProtectionFault0(pVCpu);
809
810 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
811 if (rcStrict != VINF_SUCCESS)
812 return rcStrict;
813
814 pVCpu->cpum.GstCtx.rip = uNewPC;
815 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
816
817#ifndef IEM_WITH_CODE_TLB
818 /* Flush the prefetch buffer. */
819 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
820#endif
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Implements a 32-bit indirect call.
827 *
828 * @param uNewPC The new program counter (RIP) value (loaded from the
829 * operand).
830 * @param enmEffOpSize The effective operand size.
831 */
832IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
833{
834 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
835 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
836 return iemRaiseGeneralProtectionFault0(pVCpu);
837
838 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
839 if (rcStrict != VINF_SUCCESS)
840 return rcStrict;
841
842#if defined(IN_RING3) && defined(VBOX_WITH_RAW_MODE) && defined(VBOX_WITH_CALL_RECORD)
843 /*
844 * CASM hook for recording interesting indirect calls.
845 */
846 if ( !pVCpu->cpum.GstCtx.eflags.Bits.u1IF
847 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
848 && !CSAMIsEnabled(pVCpu->CTX_SUFF(pVM))
849 && pVCpu->iem.s.uCpl == 0)
850 {
851 EMSTATE enmState = EMGetState(pVCpu);
852 if ( enmState == EMSTATE_IEM_THEN_REM
853 || enmState == EMSTATE_IEM
854 || enmState == EMSTATE_REM)
855 CSAMR3RecordCallAddress(pVCpu->CTX_SUFF(pVM), pVCpu->cpum.GstCtx.eip);
856 }
857#endif
858
859 pVCpu->cpum.GstCtx.rip = uNewPC;
860 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
861
862#ifndef IEM_WITH_CODE_TLB
863 /* Flush the prefetch buffer. */
864 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
865#endif
866 return VINF_SUCCESS;
867}
868
869
870/**
871 * Implements a 32-bit relative call.
872 *
873 * @param offDisp The displacment offset.
874 */
875IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
876{
877 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
878 uint32_t uNewPC = uOldPC + offDisp;
879 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
880 return iemRaiseGeneralProtectionFault0(pVCpu);
881
882 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
883 if (rcStrict != VINF_SUCCESS)
884 return rcStrict;
885
886 pVCpu->cpum.GstCtx.rip = uNewPC;
887 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
888
889#ifndef IEM_WITH_CODE_TLB
890 /* Flush the prefetch buffer. */
891 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
892#endif
893 return VINF_SUCCESS;
894}
895
896
897/**
898 * Implements a 64-bit indirect call.
899 *
900 * @param uNewPC The new program counter (RIP) value (loaded from the
901 * operand).
902 * @param enmEffOpSize The effective operand size.
903 */
904IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
905{
906 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
907 if (!IEM_IS_CANONICAL(uNewPC))
908 return iemRaiseGeneralProtectionFault0(pVCpu);
909
910 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
911 if (rcStrict != VINF_SUCCESS)
912 return rcStrict;
913
914 pVCpu->cpum.GstCtx.rip = uNewPC;
915 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
916
917#ifndef IEM_WITH_CODE_TLB
918 /* Flush the prefetch buffer. */
919 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
920#endif
921 return VINF_SUCCESS;
922}
923
924
925/**
926 * Implements a 64-bit relative call.
927 *
928 * @param offDisp The displacment offset.
929 */
930IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
931{
932 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
933 uint64_t uNewPC = uOldPC + offDisp;
934 if (!IEM_IS_CANONICAL(uNewPC))
935 return iemRaiseNotCanonical(pVCpu);
936
937 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
938 if (rcStrict != VINF_SUCCESS)
939 return rcStrict;
940
941 pVCpu->cpum.GstCtx.rip = uNewPC;
942 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
943
944#ifndef IEM_WITH_CODE_TLB
945 /* Flush the prefetch buffer. */
946 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
947#endif
948
949 return VINF_SUCCESS;
950}
951
952
953/**
954 * Implements far jumps and calls thru task segments (TSS).
955 *
956 * @param uSel The selector.
957 * @param enmBranch The kind of branching we're performing.
958 * @param enmEffOpSize The effective operand size.
959 * @param pDesc The descriptor corresponding to @a uSel. The type is
960 * task gate.
961 */
962IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
963{
964#ifndef IEM_IMPLEMENTS_TASKSWITCH
965 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
966#else
967 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
968 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
969 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
970 RT_NOREF_PV(enmEffOpSize);
971 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
972
973 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
974 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
975 {
976 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
977 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
978 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
979 }
980
981 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
982 * far calls (see iemCImpl_callf). Most likely in both cases it should be
983 * checked here, need testcases. */
984 if (!pDesc->Legacy.Gen.u1Present)
985 {
986 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
987 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
988 }
989
990 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
991 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
992 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
993#endif
994}
995
996
997/**
998 * Implements far jumps and calls thru task gates.
999 *
1000 * @param uSel The selector.
1001 * @param enmBranch The kind of branching we're performing.
1002 * @param enmEffOpSize The effective operand size.
1003 * @param pDesc The descriptor corresponding to @a uSel. The type is
1004 * task gate.
1005 */
1006IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1007{
1008#ifndef IEM_IMPLEMENTS_TASKSWITCH
1009 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1010#else
1011 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1012 RT_NOREF_PV(enmEffOpSize);
1013 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1014
1015 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1016 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1017 {
1018 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1019 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1020 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1021 }
1022
1023 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1024 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1025 * checked here, need testcases. */
1026 if (!pDesc->Legacy.Gen.u1Present)
1027 {
1028 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1029 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1030 }
1031
1032 /*
1033 * Fetch the new TSS descriptor from the GDT.
1034 */
1035 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1036 if (uSelTss & X86_SEL_LDT)
1037 {
1038 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1039 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1040 }
1041
1042 IEMSELDESC TssDesc;
1043 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1044 if (rcStrict != VINF_SUCCESS)
1045 return rcStrict;
1046
1047 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1048 {
1049 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1050 TssDesc.Legacy.Gate.u4Type));
1051 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1052 }
1053
1054 if (!TssDesc.Legacy.Gate.u1Present)
1055 {
1056 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1057 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1058 }
1059
1060 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1061 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1062 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1063#endif
1064}
1065
1066
1067/**
1068 * Implements far jumps and calls thru call gates.
1069 *
1070 * @param uSel The selector.
1071 * @param enmBranch The kind of branching we're performing.
1072 * @param enmEffOpSize The effective operand size.
1073 * @param pDesc The descriptor corresponding to @a uSel. The type is
1074 * call gate.
1075 */
1076IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1077{
1078#define IEM_IMPLEMENTS_CALLGATE
1079#ifndef IEM_IMPLEMENTS_CALLGATE
1080 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1081#else
1082 RT_NOREF_PV(enmEffOpSize);
1083 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1084
1085 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1086 * inter-privilege calls and are much more complex.
1087 *
1088 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1089 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1090 * must be 16-bit or 32-bit.
1091 */
1092 /** @todo: effective operand size is probably irrelevant here, only the
1093 * call gate bitness matters??
1094 */
1095 VBOXSTRICTRC rcStrict;
1096 RTPTRUNION uPtrRet;
1097 uint64_t uNewRsp;
1098 uint64_t uNewRip;
1099 uint64_t u64Base;
1100 uint32_t cbLimit;
1101 RTSEL uNewCS;
1102 IEMSELDESC DescCS;
1103
1104 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1105 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1106 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1107 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1108
1109 /* Determine the new instruction pointer from the gate descriptor. */
1110 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1111 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1112 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1113
1114 /* Perform DPL checks on the gate descriptor. */
1115 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1116 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1117 {
1118 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1119 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1120 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1121 }
1122
1123 /** @todo does this catch NULL selectors, too? */
1124 if (!pDesc->Legacy.Gen.u1Present)
1125 {
1126 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1127 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1128 }
1129
1130 /*
1131 * Fetch the target CS descriptor from the GDT or LDT.
1132 */
1133 uNewCS = pDesc->Legacy.Gate.u16Sel;
1134 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1135 if (rcStrict != VINF_SUCCESS)
1136 return rcStrict;
1137
1138 /* Target CS must be a code selector. */
1139 if ( !DescCS.Legacy.Gen.u1DescType
1140 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1141 {
1142 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1143 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1144 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1145 }
1146
1147 /* Privilege checks on target CS. */
1148 if (enmBranch == IEMBRANCH_JUMP)
1149 {
1150 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1151 {
1152 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1153 {
1154 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1155 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1156 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1157 }
1158 }
1159 else
1160 {
1161 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1162 {
1163 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1164 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1165 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1166 }
1167 }
1168 }
1169 else
1170 {
1171 Assert(enmBranch == IEMBRANCH_CALL);
1172 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1173 {
1174 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1175 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1176 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1177 }
1178 }
1179
1180 /* Additional long mode checks. */
1181 if (IEM_IS_LONG_MODE(pVCpu))
1182 {
1183 if (!DescCS.Legacy.Gen.u1Long)
1184 {
1185 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1186 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1187 }
1188
1189 /* L vs D. */
1190 if ( DescCS.Legacy.Gen.u1Long
1191 && DescCS.Legacy.Gen.u1DefBig)
1192 {
1193 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1194 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1195 }
1196 }
1197
1198 if (!DescCS.Legacy.Gate.u1Present)
1199 {
1200 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1201 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1202 }
1203
1204 if (enmBranch == IEMBRANCH_JUMP)
1205 {
1206 /** @todo: This is very similar to regular far jumps; merge! */
1207 /* Jumps are fairly simple... */
1208
1209 /* Chop the high bits off if 16-bit gate (Intel says so). */
1210 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1211 uNewRip = (uint16_t)uNewRip;
1212
1213 /* Limit check for non-long segments. */
1214 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1215 if (DescCS.Legacy.Gen.u1Long)
1216 u64Base = 0;
1217 else
1218 {
1219 if (uNewRip > cbLimit)
1220 {
1221 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1222 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1223 }
1224 u64Base = X86DESC_BASE(&DescCS.Legacy);
1225 }
1226
1227 /* Canonical address check. */
1228 if (!IEM_IS_CANONICAL(uNewRip))
1229 {
1230 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1231 return iemRaiseNotCanonical(pVCpu);
1232 }
1233
1234 /*
1235 * Ok, everything checked out fine. Now set the accessed bit before
1236 * committing the result into CS, CSHID and RIP.
1237 */
1238 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1239 {
1240 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1241 if (rcStrict != VINF_SUCCESS)
1242 return rcStrict;
1243 /** @todo check what VT-x and AMD-V does. */
1244 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1245 }
1246
1247 /* commit */
1248 pVCpu->cpum.GstCtx.rip = uNewRip;
1249 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1250 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1251 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1252 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1253 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1254 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1255 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1256 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1257 }
1258 else
1259 {
1260 Assert(enmBranch == IEMBRANCH_CALL);
1261 /* Calls are much more complicated. */
1262
1263 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1264 {
1265 uint16_t offNewStack; /* Offset of new stack in TSS. */
1266 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1267 uint8_t uNewCSDpl;
1268 uint8_t cbWords;
1269 RTSEL uNewSS;
1270 RTSEL uOldSS;
1271 uint64_t uOldRsp;
1272 IEMSELDESC DescSS;
1273 RTPTRUNION uPtrTSS;
1274 RTGCPTR GCPtrTSS;
1275 RTPTRUNION uPtrParmWds;
1276 RTGCPTR GCPtrParmWds;
1277
1278 /* More privilege. This is the fun part. */
1279 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1280
1281 /*
1282 * Determine new SS:rSP from the TSS.
1283 */
1284 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
1285
1286 /* Figure out where the new stack pointer is stored in the TSS. */
1287 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1288 if (!IEM_IS_LONG_MODE(pVCpu))
1289 {
1290 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1291 {
1292 offNewStack = RT_UOFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1293 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1294 }
1295 else
1296 {
1297 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1298 offNewStack = RT_UOFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1299 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1300 }
1301 }
1302 else
1303 {
1304 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1305 offNewStack = RT_UOFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1306 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1307 }
1308
1309 /* Check against TSS limit. */
1310 if ((uint16_t)(offNewStack + cbNewStack - 1) > pVCpu->cpum.GstCtx.tr.u32Limit)
1311 {
1312 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pVCpu->cpum.GstCtx.tr.u32Limit));
1313 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pVCpu->cpum.GstCtx.tr.Sel);
1314 }
1315
1316 GCPtrTSS = pVCpu->cpum.GstCtx.tr.u64Base + offNewStack;
1317 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R);
1318 if (rcStrict != VINF_SUCCESS)
1319 {
1320 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1321 return rcStrict;
1322 }
1323
1324 if (!IEM_IS_LONG_MODE(pVCpu))
1325 {
1326 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1327 {
1328 uNewRsp = uPtrTSS.pu32[0];
1329 uNewSS = uPtrTSS.pu16[2];
1330 }
1331 else
1332 {
1333 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1334 uNewRsp = uPtrTSS.pu16[0];
1335 uNewSS = uPtrTSS.pu16[1];
1336 }
1337 }
1338 else
1339 {
1340 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1341 /* SS will be a NULL selector, but that's valid. */
1342 uNewRsp = uPtrTSS.pu64[0];
1343 uNewSS = uNewCSDpl;
1344 }
1345
1346 /* Done with the TSS now. */
1347 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1348 if (rcStrict != VINF_SUCCESS)
1349 {
1350 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1351 return rcStrict;
1352 }
1353
1354 /* Only used outside of long mode. */
1355 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1356
1357 /* If EFER.LMA is 0, there's extra work to do. */
1358 if (!IEM_IS_LONG_MODE(pVCpu))
1359 {
1360 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1361 {
1362 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1363 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1364 }
1365
1366 /* Grab the new SS descriptor. */
1367 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1368 if (rcStrict != VINF_SUCCESS)
1369 return rcStrict;
1370
1371 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1372 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1373 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1374 {
1375 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1376 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1377 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1378 }
1379
1380 /* Ensure new SS is a writable data segment. */
1381 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1382 {
1383 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1384 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1385 }
1386
1387 if (!DescSS.Legacy.Gen.u1Present)
1388 {
1389 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1390 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1391 }
1392 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1393 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1394 else
1395 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1396 }
1397 else
1398 {
1399 /* Just grab the new (NULL) SS descriptor. */
1400 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1401 * like we do... */
1402 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1403 if (rcStrict != VINF_SUCCESS)
1404 return rcStrict;
1405
1406 cbNewStack = sizeof(uint64_t) * 4;
1407 }
1408
1409 /** @todo: According to Intel, new stack is checked for enough space first,
1410 * then switched. According to AMD, the stack is switched first and
1411 * then pushes might fault!
1412 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1413 * incoming stack #PF happens before actual stack switch. AMD is
1414 * either lying or implicitly assumes that new state is committed
1415 * only if and when an instruction doesn't fault.
1416 */
1417
1418 /** @todo: According to AMD, CS is loaded first, then SS.
1419 * According to Intel, it's the other way around!?
1420 */
1421
1422 /** @todo: Intel and AMD disagree on when exactly the CPL changes! */
1423
1424 /* Set the accessed bit before committing new SS. */
1425 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1426 {
1427 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1428 if (rcStrict != VINF_SUCCESS)
1429 return rcStrict;
1430 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1431 }
1432
1433 /* Remember the old SS:rSP and their linear address. */
1434 uOldSS = pVCpu->cpum.GstCtx.ss.Sel;
1435 uOldRsp = pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig ? pVCpu->cpum.GstCtx.rsp : pVCpu->cpum.GstCtx.sp;
1436
1437 GCPtrParmWds = pVCpu->cpum.GstCtx.ss.u64Base + uOldRsp;
1438
1439 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1440 or #PF, the former is not implemented in this workaround. */
1441 /** @todo Proper fix callgate target stack exceptions. */
1442 /** @todo testcase: Cover callgates with partially or fully inaccessible
1443 * target stacks. */
1444 void *pvNewFrame;
1445 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1446 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW);
1447 if (rcStrict != VINF_SUCCESS)
1448 {
1449 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1450 return rcStrict;
1451 }
1452 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1453 if (rcStrict != VINF_SUCCESS)
1454 {
1455 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1456 return rcStrict;
1457 }
1458
1459 /* Commit new SS:rSP. */
1460 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
1461 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
1462 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1463 pVCpu->cpum.GstCtx.ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1464 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1465 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
1466 pVCpu->cpum.GstCtx.rsp = uNewRsp;
1467 pVCpu->iem.s.uCpl = uNewCSDpl;
1468 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
1469 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1470
1471 /* At this point the stack access must not fail because new state was already committed. */
1472 /** @todo this can still fail due to SS.LIMIT not check. */
1473 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1474 &uPtrRet.pv, &uNewRsp);
1475 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1476 VERR_INTERNAL_ERROR_5);
1477
1478 if (!IEM_IS_LONG_MODE(pVCpu))
1479 {
1480 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1481 {
1482 /* Push the old CS:rIP. */
1483 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1484 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1485
1486 if (cbWords)
1487 {
1488 /* Map the relevant chunk of the old stack. */
1489 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1490 if (rcStrict != VINF_SUCCESS)
1491 {
1492 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1493 return rcStrict;
1494 }
1495
1496 /* Copy the parameter (d)words. */
1497 for (int i = 0; i < cbWords; ++i)
1498 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1499
1500 /* Unmap the old stack. */
1501 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1502 if (rcStrict != VINF_SUCCESS)
1503 {
1504 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1505 return rcStrict;
1506 }
1507 }
1508
1509 /* Push the old SS:rSP. */
1510 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1511 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1512 }
1513 else
1514 {
1515 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1516
1517 /* Push the old CS:rIP. */
1518 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1519 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1520
1521 if (cbWords)
1522 {
1523 /* Map the relevant chunk of the old stack. */
1524 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds, IEM_ACCESS_DATA_R);
1525 if (rcStrict != VINF_SUCCESS)
1526 {
1527 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1528 return rcStrict;
1529 }
1530
1531 /* Copy the parameter words. */
1532 for (int i = 0; i < cbWords; ++i)
1533 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1534
1535 /* Unmap the old stack. */
1536 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1537 if (rcStrict != VINF_SUCCESS)
1538 {
1539 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1540 return rcStrict;
1541 }
1542 }
1543
1544 /* Push the old SS:rSP. */
1545 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1546 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1547 }
1548 }
1549 else
1550 {
1551 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1552
1553 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1554 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1555 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1556 uPtrRet.pu64[2] = uOldRsp;
1557 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1558 }
1559
1560 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1561 if (rcStrict != VINF_SUCCESS)
1562 {
1563 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1564 return rcStrict;
1565 }
1566
1567 /* Chop the high bits off if 16-bit gate (Intel says so). */
1568 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1569 uNewRip = (uint16_t)uNewRip;
1570
1571 /* Limit / canonical check. */
1572 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1573 if (!IEM_IS_LONG_MODE(pVCpu))
1574 {
1575 if (uNewRip > cbLimit)
1576 {
1577 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1578 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1579 }
1580 u64Base = X86DESC_BASE(&DescCS.Legacy);
1581 }
1582 else
1583 {
1584 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1585 if (!IEM_IS_CANONICAL(uNewRip))
1586 {
1587 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1588 return iemRaiseNotCanonical(pVCpu);
1589 }
1590 u64Base = 0;
1591 }
1592
1593 /*
1594 * Now set the accessed bit before
1595 * writing the return address to the stack and committing the result into
1596 * CS, CSHID and RIP.
1597 */
1598 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1599 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1600 {
1601 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1602 if (rcStrict != VINF_SUCCESS)
1603 return rcStrict;
1604 /** @todo check what VT-x and AMD-V does. */
1605 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1606 }
1607
1608 /* Commit new CS:rIP. */
1609 pVCpu->cpum.GstCtx.rip = uNewRip;
1610 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1611 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1612 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1613 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1614 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1615 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1616 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1617 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1618 }
1619 else
1620 {
1621 /* Same privilege. */
1622 /** @todo: This is very similar to regular far calls; merge! */
1623
1624 /* Check stack first - may #SS(0). */
1625 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1626 * 16-bit code cause a two or four byte CS to be pushed? */
1627 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1628 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1629 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1630 &uPtrRet.pv, &uNewRsp);
1631 if (rcStrict != VINF_SUCCESS)
1632 return rcStrict;
1633
1634 /* Chop the high bits off if 16-bit gate (Intel says so). */
1635 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1636 uNewRip = (uint16_t)uNewRip;
1637
1638 /* Limit / canonical check. */
1639 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1640 if (!IEM_IS_LONG_MODE(pVCpu))
1641 {
1642 if (uNewRip > cbLimit)
1643 {
1644 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1645 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1646 }
1647 u64Base = X86DESC_BASE(&DescCS.Legacy);
1648 }
1649 else
1650 {
1651 if (!IEM_IS_CANONICAL(uNewRip))
1652 {
1653 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1654 return iemRaiseNotCanonical(pVCpu);
1655 }
1656 u64Base = 0;
1657 }
1658
1659 /*
1660 * Now set the accessed bit before
1661 * writing the return address to the stack and committing the result into
1662 * CS, CSHID and RIP.
1663 */
1664 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1665 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1666 {
1667 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1668 if (rcStrict != VINF_SUCCESS)
1669 return rcStrict;
1670 /** @todo check what VT-x and AMD-V does. */
1671 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1672 }
1673
1674 /* stack */
1675 if (!IEM_IS_LONG_MODE(pVCpu))
1676 {
1677 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1678 {
1679 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1680 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1681 }
1682 else
1683 {
1684 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1685 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1686 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1687 }
1688 }
1689 else
1690 {
1691 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1692 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1693 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1694 }
1695
1696 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1697 if (rcStrict != VINF_SUCCESS)
1698 return rcStrict;
1699
1700 /* commit */
1701 pVCpu->cpum.GstCtx.rip = uNewRip;
1702 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1703 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1704 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1705 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1706 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1707 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1708 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1709 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1710 }
1711 }
1712 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1713
1714 /* Flush the prefetch buffer. */
1715# ifdef IEM_WITH_CODE_TLB
1716 pVCpu->iem.s.pbInstrBuf = NULL;
1717# else
1718 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1719# endif
1720 return VINF_SUCCESS;
1721#endif
1722}
1723
1724
1725/**
1726 * Implements far jumps and calls thru system selectors.
1727 *
1728 * @param uSel The selector.
1729 * @param enmBranch The kind of branching we're performing.
1730 * @param enmEffOpSize The effective operand size.
1731 * @param pDesc The descriptor corresponding to @a uSel.
1732 */
1733IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1734{
1735 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1736 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1737 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1738
1739 if (IEM_IS_LONG_MODE(pVCpu))
1740 switch (pDesc->Legacy.Gen.u4Type)
1741 {
1742 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1743 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1744
1745 default:
1746 case AMD64_SEL_TYPE_SYS_LDT:
1747 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1748 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1749 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1750 case AMD64_SEL_TYPE_SYS_INT_GATE:
1751 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1752 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1753 }
1754
1755 switch (pDesc->Legacy.Gen.u4Type)
1756 {
1757 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1758 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1759 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1760
1761 case X86_SEL_TYPE_SYS_TASK_GATE:
1762 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1763
1764 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1765 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1766 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1767
1768 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1769 Log(("branch %04x -> busy 286 TSS\n", uSel));
1770 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1771
1772 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1773 Log(("branch %04x -> busy 386 TSS\n", uSel));
1774 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1775
1776 default:
1777 case X86_SEL_TYPE_SYS_LDT:
1778 case X86_SEL_TYPE_SYS_286_INT_GATE:
1779 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1780 case X86_SEL_TYPE_SYS_386_INT_GATE:
1781 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1782 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1783 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1784 }
1785}
1786
1787
1788/**
1789 * Implements far jumps.
1790 *
1791 * @param uSel The selector.
1792 * @param offSeg The segment offset.
1793 * @param enmEffOpSize The effective operand size.
1794 */
1795IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1796{
1797 NOREF(cbInstr);
1798 Assert(offSeg <= UINT32_MAX);
1799
1800 /*
1801 * Real mode and V8086 mode are easy. The only snag seems to be that
1802 * CS.limit doesn't change and the limit check is done against the current
1803 * limit.
1804 */
1805 /** @todo Robert Collins claims (The Segment Descriptor Cache, DDJ August
1806 * 1998) that up to and including the Intel 486, far control
1807 * transfers in real mode set default CS attributes (0x93) and also
1808 * set a 64K segment limit. Starting with the Pentium, the
1809 * attributes and limit are left alone but the access rights are
1810 * ignored. We only implement the Pentium+ behavior.
1811 * */
1812 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1813 {
1814 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1815 if (offSeg > pVCpu->cpum.GstCtx.cs.u32Limit)
1816 {
1817 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1818 return iemRaiseGeneralProtectionFault0(pVCpu);
1819 }
1820
1821 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1822 pVCpu->cpum.GstCtx.rip = offSeg;
1823 else
1824 pVCpu->cpum.GstCtx.rip = offSeg & UINT16_MAX;
1825 pVCpu->cpum.GstCtx.cs.Sel = uSel;
1826 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
1827 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1828 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
1829 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1830 return VINF_SUCCESS;
1831 }
1832
1833 /*
1834 * Protected mode. Need to parse the specified descriptor...
1835 */
1836 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1837 {
1838 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1839 return iemRaiseGeneralProtectionFault0(pVCpu);
1840 }
1841
1842 /* Fetch the descriptor. */
1843 IEMSELDESC Desc;
1844 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1845 if (rcStrict != VINF_SUCCESS)
1846 return rcStrict;
1847
1848 /* Is it there? */
1849 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1850 {
1851 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1852 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1853 }
1854
1855 /*
1856 * Deal with it according to its type. We do the standard code selectors
1857 * here and dispatch the system selectors to worker functions.
1858 */
1859 if (!Desc.Legacy.Gen.u1DescType)
1860 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1861
1862 /* Only code segments. */
1863 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1864 {
1865 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1866 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1867 }
1868
1869 /* L vs D. */
1870 if ( Desc.Legacy.Gen.u1Long
1871 && Desc.Legacy.Gen.u1DefBig
1872 && IEM_IS_LONG_MODE(pVCpu))
1873 {
1874 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1875 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1876 }
1877
1878 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1879 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1880 {
1881 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1882 {
1883 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1884 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1885 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1886 }
1887 }
1888 else
1889 {
1890 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1891 {
1892 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1893 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1894 }
1895 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1896 {
1897 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1898 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1899 }
1900 }
1901
1902 /* Chop the high bits if 16-bit (Intel says so). */
1903 if (enmEffOpSize == IEMMODE_16BIT)
1904 offSeg &= UINT16_MAX;
1905
1906 /* Limit check. (Should alternatively check for non-canonical addresses
1907 here, but that is ruled out by offSeg being 32-bit, right?) */
1908 uint64_t u64Base;
1909 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1910 if (Desc.Legacy.Gen.u1Long)
1911 u64Base = 0;
1912 else
1913 {
1914 if (offSeg > cbLimit)
1915 {
1916 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1917 /** @todo: Intel says this is #GP(0)! */
1918 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1919 }
1920 u64Base = X86DESC_BASE(&Desc.Legacy);
1921 }
1922
1923 /*
1924 * Ok, everything checked out fine. Now set the accessed bit before
1925 * committing the result into CS, CSHID and RIP.
1926 */
1927 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1928 {
1929 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1930 if (rcStrict != VINF_SUCCESS)
1931 return rcStrict;
1932 /** @todo check what VT-x and AMD-V does. */
1933 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1934 }
1935
1936 /* commit */
1937 pVCpu->cpum.GstCtx.rip = offSeg;
1938 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1939 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1940 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1941 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1942 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1943 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1944 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1945 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1946 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1947 /** @todo check if the hidden bits are loaded correctly for 64-bit
1948 * mode. */
1949
1950 /* Flush the prefetch buffer. */
1951#ifdef IEM_WITH_CODE_TLB
1952 pVCpu->iem.s.pbInstrBuf = NULL;
1953#else
1954 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1955#endif
1956
1957 return VINF_SUCCESS;
1958}
1959
1960
1961/**
1962 * Implements far calls.
1963 *
1964 * This very similar to iemCImpl_FarJmp.
1965 *
1966 * @param uSel The selector.
1967 * @param offSeg The segment offset.
1968 * @param enmEffOpSize The operand size (in case we need it).
1969 */
1970IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1971{
1972 VBOXSTRICTRC rcStrict;
1973 uint64_t uNewRsp;
1974 RTPTRUNION uPtrRet;
1975
1976 /*
1977 * Real mode and V8086 mode are easy. The only snag seems to be that
1978 * CS.limit doesn't change and the limit check is done against the current
1979 * limit.
1980 */
1981 /** @todo See comment for similar code in iemCImpl_FarJmp */
1982 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1983 {
1984 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1985
1986 /* Check stack first - may #SS(0). */
1987 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
1988 &uPtrRet.pv, &uNewRsp);
1989 if (rcStrict != VINF_SUCCESS)
1990 return rcStrict;
1991
1992 /* Check the target address range. */
1993 if (offSeg > UINT32_MAX)
1994 return iemRaiseGeneralProtectionFault0(pVCpu);
1995
1996 /* Everything is fine, push the return address. */
1997 if (enmEffOpSize == IEMMODE_16BIT)
1998 {
1999 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2000 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2001 }
2002 else
2003 {
2004 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2005 uPtrRet.pu16[2] = pVCpu->cpum.GstCtx.cs.Sel;
2006 }
2007 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2008 if (rcStrict != VINF_SUCCESS)
2009 return rcStrict;
2010
2011 /* Branch. */
2012 pVCpu->cpum.GstCtx.rip = offSeg;
2013 pVCpu->cpum.GstCtx.cs.Sel = uSel;
2014 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
2015 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2016 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
2017 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2018 return VINF_SUCCESS;
2019 }
2020
2021 /*
2022 * Protected mode. Need to parse the specified descriptor...
2023 */
2024 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2025 {
2026 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2027 return iemRaiseGeneralProtectionFault0(pVCpu);
2028 }
2029
2030 /* Fetch the descriptor. */
2031 IEMSELDESC Desc;
2032 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2033 if (rcStrict != VINF_SUCCESS)
2034 return rcStrict;
2035
2036 /*
2037 * Deal with it according to its type. We do the standard code selectors
2038 * here and dispatch the system selectors to worker functions.
2039 */
2040 if (!Desc.Legacy.Gen.u1DescType)
2041 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2042
2043 /* Only code segments. */
2044 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2045 {
2046 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2047 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2048 }
2049
2050 /* L vs D. */
2051 if ( Desc.Legacy.Gen.u1Long
2052 && Desc.Legacy.Gen.u1DefBig
2053 && IEM_IS_LONG_MODE(pVCpu))
2054 {
2055 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2056 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2057 }
2058
2059 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2060 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2061 {
2062 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2063 {
2064 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2065 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2066 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2067 }
2068 }
2069 else
2070 {
2071 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2072 {
2073 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2074 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2075 }
2076 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2077 {
2078 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2079 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2080 }
2081 }
2082
2083 /* Is it there? */
2084 if (!Desc.Legacy.Gen.u1Present)
2085 {
2086 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2087 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2088 }
2089
2090 /* Check stack first - may #SS(0). */
2091 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2092 * 16-bit code cause a two or four byte CS to be pushed? */
2093 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2094 enmEffOpSize == IEMMODE_64BIT ? 8+8
2095 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2096 &uPtrRet.pv, &uNewRsp);
2097 if (rcStrict != VINF_SUCCESS)
2098 return rcStrict;
2099
2100 /* Chop the high bits if 16-bit (Intel says so). */
2101 if (enmEffOpSize == IEMMODE_16BIT)
2102 offSeg &= UINT16_MAX;
2103
2104 /* Limit / canonical check. */
2105 uint64_t u64Base;
2106 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2107 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2108 {
2109 if (!IEM_IS_CANONICAL(offSeg))
2110 {
2111 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2112 return iemRaiseNotCanonical(pVCpu);
2113 }
2114 u64Base = 0;
2115 }
2116 else
2117 {
2118 if (offSeg > cbLimit)
2119 {
2120 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2121 /** @todo: Intel says this is #GP(0)! */
2122 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2123 }
2124 u64Base = X86DESC_BASE(&Desc.Legacy);
2125 }
2126
2127 /*
2128 * Now set the accessed bit before
2129 * writing the return address to the stack and committing the result into
2130 * CS, CSHID and RIP.
2131 */
2132 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2133 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2134 {
2135 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2136 if (rcStrict != VINF_SUCCESS)
2137 return rcStrict;
2138 /** @todo check what VT-x and AMD-V does. */
2139 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2140 }
2141
2142 /* stack */
2143 if (enmEffOpSize == IEMMODE_16BIT)
2144 {
2145 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2146 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2147 }
2148 else if (enmEffOpSize == IEMMODE_32BIT)
2149 {
2150 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2151 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2152 }
2153 else
2154 {
2155 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
2156 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2157 }
2158 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2159 if (rcStrict != VINF_SUCCESS)
2160 return rcStrict;
2161
2162 /* commit */
2163 pVCpu->cpum.GstCtx.rip = offSeg;
2164 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2165 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
2166 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
2167 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2168 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2169 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
2170 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2171 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2172 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2173 /** @todo check if the hidden bits are loaded correctly for 64-bit
2174 * mode. */
2175
2176 /* Flush the prefetch buffer. */
2177#ifdef IEM_WITH_CODE_TLB
2178 pVCpu->iem.s.pbInstrBuf = NULL;
2179#else
2180 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2181#endif
2182 return VINF_SUCCESS;
2183}
2184
2185
2186/**
2187 * Implements retf.
2188 *
2189 * @param enmEffOpSize The effective operand size.
2190 * @param cbPop The amount of arguments to pop from the stack
2191 * (bytes).
2192 */
2193IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2194{
2195 VBOXSTRICTRC rcStrict;
2196 RTCPTRUNION uPtrFrame;
2197 uint64_t uNewRsp;
2198 uint64_t uNewRip;
2199 uint16_t uNewCs;
2200 NOREF(cbInstr);
2201
2202 /*
2203 * Read the stack values first.
2204 */
2205 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2206 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2207 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2208 if (rcStrict != VINF_SUCCESS)
2209 return rcStrict;
2210 if (enmEffOpSize == IEMMODE_16BIT)
2211 {
2212 uNewRip = uPtrFrame.pu16[0];
2213 uNewCs = uPtrFrame.pu16[1];
2214 }
2215 else if (enmEffOpSize == IEMMODE_32BIT)
2216 {
2217 uNewRip = uPtrFrame.pu32[0];
2218 uNewCs = uPtrFrame.pu16[2];
2219 }
2220 else
2221 {
2222 uNewRip = uPtrFrame.pu64[0];
2223 uNewCs = uPtrFrame.pu16[4];
2224 }
2225 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2226 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2227 { /* extremely likely */ }
2228 else
2229 return rcStrict;
2230
2231 /*
2232 * Real mode and V8086 mode are easy.
2233 */
2234 /** @todo See comment for similar code in iemCImpl_FarJmp */
2235 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2236 {
2237 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2238 /** @todo check how this is supposed to work if sp=0xfffe. */
2239
2240 /* Check the limit of the new EIP. */
2241 /** @todo Intel pseudo code only does the limit check for 16-bit
2242 * operands, AMD does not make any distinction. What is right? */
2243 if (uNewRip > pVCpu->cpum.GstCtx.cs.u32Limit)
2244 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2245
2246 /* commit the operation. */
2247 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2248 pVCpu->cpum.GstCtx.rip = uNewRip;
2249 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2250 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2251 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2252 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2253 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2254 if (cbPop)
2255 iemRegAddToRsp(pVCpu, cbPop);
2256 return VINF_SUCCESS;
2257 }
2258
2259 /*
2260 * Protected mode is complicated, of course.
2261 */
2262 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2263 {
2264 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2265 return iemRaiseGeneralProtectionFault0(pVCpu);
2266 }
2267
2268 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
2269
2270 /* Fetch the descriptor. */
2271 IEMSELDESC DescCs;
2272 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2273 if (rcStrict != VINF_SUCCESS)
2274 return rcStrict;
2275
2276 /* Can only return to a code selector. */
2277 if ( !DescCs.Legacy.Gen.u1DescType
2278 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2279 {
2280 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2281 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2282 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2283 }
2284
2285 /* L vs D. */
2286 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2287 && DescCs.Legacy.Gen.u1DefBig
2288 && IEM_IS_LONG_MODE(pVCpu))
2289 {
2290 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2291 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2292 }
2293
2294 /* DPL/RPL/CPL checks. */
2295 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2296 {
2297 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2298 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2299 }
2300
2301 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2302 {
2303 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2304 {
2305 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2306 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2307 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2308 }
2309 }
2310 else
2311 {
2312 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2313 {
2314 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2315 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2316 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2317 }
2318 }
2319
2320 /* Is it there? */
2321 if (!DescCs.Legacy.Gen.u1Present)
2322 {
2323 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2324 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2325 }
2326
2327 /*
2328 * Return to outer privilege? (We'll typically have entered via a call gate.)
2329 */
2330 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2331 {
2332 /* Read the outer stack pointer stored *after* the parameters. */
2333 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop + cbRetPtr, &uPtrFrame.pv, &uNewRsp);
2334 if (rcStrict != VINF_SUCCESS)
2335 return rcStrict;
2336
2337 uPtrFrame.pu8 += cbPop; /* Skip the parameters. */
2338
2339 uint16_t uNewOuterSs;
2340 uint64_t uNewOuterRsp;
2341 if (enmEffOpSize == IEMMODE_16BIT)
2342 {
2343 uNewOuterRsp = uPtrFrame.pu16[0];
2344 uNewOuterSs = uPtrFrame.pu16[1];
2345 }
2346 else if (enmEffOpSize == IEMMODE_32BIT)
2347 {
2348 uNewOuterRsp = uPtrFrame.pu32[0];
2349 uNewOuterSs = uPtrFrame.pu16[2];
2350 }
2351 else
2352 {
2353 uNewOuterRsp = uPtrFrame.pu64[0];
2354 uNewOuterSs = uPtrFrame.pu16[4];
2355 }
2356 uPtrFrame.pu8 -= cbPop; /* Put uPtrFrame back the way it was. */
2357 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2358 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2359 { /* extremely likely */ }
2360 else
2361 return rcStrict;
2362
2363 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2364 and read the selector. */
2365 IEMSELDESC DescSs;
2366 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2367 {
2368 if ( !DescCs.Legacy.Gen.u1Long
2369 || (uNewOuterSs & X86_SEL_RPL) == 3)
2370 {
2371 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2372 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2373 return iemRaiseGeneralProtectionFault0(pVCpu);
2374 }
2375 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2376 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2377 }
2378 else
2379 {
2380 /* Fetch the descriptor for the new stack segment. */
2381 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2382 if (rcStrict != VINF_SUCCESS)
2383 return rcStrict;
2384 }
2385
2386 /* Check that RPL of stack and code selectors match. */
2387 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2388 {
2389 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2390 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2391 }
2392
2393 /* Must be a writable data segment. */
2394 if ( !DescSs.Legacy.Gen.u1DescType
2395 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2396 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2397 {
2398 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2399 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2400 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2401 }
2402
2403 /* L vs D. (Not mentioned by intel.) */
2404 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2405 && DescSs.Legacy.Gen.u1DefBig
2406 && IEM_IS_LONG_MODE(pVCpu))
2407 {
2408 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2409 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2410 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2411 }
2412
2413 /* DPL/RPL/CPL checks. */
2414 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2415 {
2416 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2417 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2418 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2419 }
2420
2421 /* Is it there? */
2422 if (!DescSs.Legacy.Gen.u1Present)
2423 {
2424 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2425 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2426 }
2427
2428 /* Calc SS limit.*/
2429 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2430
2431 /* Is RIP canonical or within CS.limit? */
2432 uint64_t u64Base;
2433 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2434
2435 /** @todo Testcase: Is this correct? */
2436 if ( DescCs.Legacy.Gen.u1Long
2437 && IEM_IS_LONG_MODE(pVCpu) )
2438 {
2439 if (!IEM_IS_CANONICAL(uNewRip))
2440 {
2441 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2442 return iemRaiseNotCanonical(pVCpu);
2443 }
2444 u64Base = 0;
2445 }
2446 else
2447 {
2448 if (uNewRip > cbLimitCs)
2449 {
2450 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2451 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2452 /** @todo: Intel says this is #GP(0)! */
2453 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2454 }
2455 u64Base = X86DESC_BASE(&DescCs.Legacy);
2456 }
2457
2458 /*
2459 * Now set the accessed bit before
2460 * writing the return address to the stack and committing the result into
2461 * CS, CSHID and RIP.
2462 */
2463 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2464 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2465 {
2466 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2467 if (rcStrict != VINF_SUCCESS)
2468 return rcStrict;
2469 /** @todo check what VT-x and AMD-V does. */
2470 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2471 }
2472 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2473 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2474 {
2475 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2476 if (rcStrict != VINF_SUCCESS)
2477 return rcStrict;
2478 /** @todo check what VT-x and AMD-V does. */
2479 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2480 }
2481
2482 /* commit */
2483 if (enmEffOpSize == IEMMODE_16BIT)
2484 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2485 else
2486 pVCpu->cpum.GstCtx.rip = uNewRip;
2487 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2488 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2489 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2490 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2491 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2492 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2493 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2494 pVCpu->cpum.GstCtx.ss.Sel = uNewOuterSs;
2495 pVCpu->cpum.GstCtx.ss.ValidSel = uNewOuterSs;
2496 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
2497 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2498 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
2499 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2500 pVCpu->cpum.GstCtx.ss.u64Base = 0;
2501 else
2502 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2503 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2504 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewOuterRsp;
2505 else
2506 pVCpu->cpum.GstCtx.rsp = uNewOuterRsp;
2507
2508 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2509 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
2510 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
2511 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
2512 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
2513
2514 /** @todo check if the hidden bits are loaded correctly for 64-bit
2515 * mode. */
2516
2517 if (cbPop)
2518 iemRegAddToRsp(pVCpu, cbPop);
2519 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2520
2521 /* Done! */
2522 }
2523 /*
2524 * Return to the same privilege level
2525 */
2526 else
2527 {
2528 /* Limit / canonical check. */
2529 uint64_t u64Base;
2530 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2531
2532 /** @todo Testcase: Is this correct? */
2533 if ( DescCs.Legacy.Gen.u1Long
2534 && IEM_IS_LONG_MODE(pVCpu) )
2535 {
2536 if (!IEM_IS_CANONICAL(uNewRip))
2537 {
2538 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2539 return iemRaiseNotCanonical(pVCpu);
2540 }
2541 u64Base = 0;
2542 }
2543 else
2544 {
2545 if (uNewRip > cbLimitCs)
2546 {
2547 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2548 /** @todo: Intel says this is #GP(0)! */
2549 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2550 }
2551 u64Base = X86DESC_BASE(&DescCs.Legacy);
2552 }
2553
2554 /*
2555 * Now set the accessed bit before
2556 * writing the return address to the stack and committing the result into
2557 * CS, CSHID and RIP.
2558 */
2559 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2560 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2561 {
2562 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2563 if (rcStrict != VINF_SUCCESS)
2564 return rcStrict;
2565 /** @todo check what VT-x and AMD-V does. */
2566 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2567 }
2568
2569 /* commit */
2570 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2571 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
2572 else
2573 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2574 if (enmEffOpSize == IEMMODE_16BIT)
2575 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2576 else
2577 pVCpu->cpum.GstCtx.rip = uNewRip;
2578 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2579 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2580 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2581 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2582 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2583 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2584 /** @todo check if the hidden bits are loaded correctly for 64-bit
2585 * mode. */
2586 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2587 if (cbPop)
2588 iemRegAddToRsp(pVCpu, cbPop);
2589 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2590 }
2591
2592 /* Flush the prefetch buffer. */
2593#ifdef IEM_WITH_CODE_TLB
2594 pVCpu->iem.s.pbInstrBuf = NULL;
2595#else
2596 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2597#endif
2598 return VINF_SUCCESS;
2599}
2600
2601
2602/**
2603 * Implements retn.
2604 *
2605 * We're doing this in C because of the \#GP that might be raised if the popped
2606 * program counter is out of bounds.
2607 *
2608 * @param enmEffOpSize The effective operand size.
2609 * @param cbPop The amount of arguments to pop from the stack
2610 * (bytes).
2611 */
2612IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2613{
2614 NOREF(cbInstr);
2615
2616 /* Fetch the RSP from the stack. */
2617 VBOXSTRICTRC rcStrict;
2618 RTUINT64U NewRip;
2619 RTUINT64U NewRsp;
2620 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2621
2622 switch (enmEffOpSize)
2623 {
2624 case IEMMODE_16BIT:
2625 NewRip.u = 0;
2626 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2627 break;
2628 case IEMMODE_32BIT:
2629 NewRip.u = 0;
2630 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2631 break;
2632 case IEMMODE_64BIT:
2633 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2634 break;
2635 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2636 }
2637 if (rcStrict != VINF_SUCCESS)
2638 return rcStrict;
2639
2640 /* Check the new RSP before loading it. */
2641 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2642 * of it. The canonical test is performed here and for call. */
2643 if (enmEffOpSize != IEMMODE_64BIT)
2644 {
2645 if (NewRip.DWords.dw0 > pVCpu->cpum.GstCtx.cs.u32Limit)
2646 {
2647 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pVCpu->cpum.GstCtx.cs.u32Limit));
2648 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2649 }
2650 }
2651 else
2652 {
2653 if (!IEM_IS_CANONICAL(NewRip.u))
2654 {
2655 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2656 return iemRaiseNotCanonical(pVCpu);
2657 }
2658 }
2659
2660 /* Apply cbPop */
2661 if (cbPop)
2662 iemRegAddToRspEx(pVCpu, &NewRsp, cbPop);
2663
2664 /* Commit it. */
2665 pVCpu->cpum.GstCtx.rip = NewRip.u;
2666 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2667 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2668
2669 /* Flush the prefetch buffer. */
2670#ifndef IEM_WITH_CODE_TLB
2671 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2672#endif
2673
2674 return VINF_SUCCESS;
2675}
2676
2677
2678/**
2679 * Implements enter.
2680 *
2681 * We're doing this in C because the instruction is insane, even for the
2682 * u8NestingLevel=0 case dealing with the stack is tedious.
2683 *
2684 * @param enmEffOpSize The effective operand size.
2685 */
2686IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2687{
2688 /* Push RBP, saving the old value in TmpRbp. */
2689 RTUINT64U NewRsp; NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2690 RTUINT64U TmpRbp; TmpRbp.u = pVCpu->cpum.GstCtx.rbp;
2691 RTUINT64U NewRbp;
2692 VBOXSTRICTRC rcStrict;
2693 if (enmEffOpSize == IEMMODE_64BIT)
2694 {
2695 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2696 NewRbp = NewRsp;
2697 }
2698 else if (enmEffOpSize == IEMMODE_32BIT)
2699 {
2700 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2701 NewRbp = NewRsp;
2702 }
2703 else
2704 {
2705 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2706 NewRbp = TmpRbp;
2707 NewRbp.Words.w0 = NewRsp.Words.w0;
2708 }
2709 if (rcStrict != VINF_SUCCESS)
2710 return rcStrict;
2711
2712 /* Copy the parameters (aka nesting levels by Intel). */
2713 cParameters &= 0x1f;
2714 if (cParameters > 0)
2715 {
2716 switch (enmEffOpSize)
2717 {
2718 case IEMMODE_16BIT:
2719 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2720 TmpRbp.DWords.dw0 -= 2;
2721 else
2722 TmpRbp.Words.w0 -= 2;
2723 do
2724 {
2725 uint16_t u16Tmp;
2726 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2727 if (rcStrict != VINF_SUCCESS)
2728 break;
2729 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2730 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2731 break;
2732
2733 case IEMMODE_32BIT:
2734 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2735 TmpRbp.DWords.dw0 -= 4;
2736 else
2737 TmpRbp.Words.w0 -= 4;
2738 do
2739 {
2740 uint32_t u32Tmp;
2741 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2742 if (rcStrict != VINF_SUCCESS)
2743 break;
2744 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2745 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2746 break;
2747
2748 case IEMMODE_64BIT:
2749 TmpRbp.u -= 8;
2750 do
2751 {
2752 uint64_t u64Tmp;
2753 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2754 if (rcStrict != VINF_SUCCESS)
2755 break;
2756 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2757 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2758 break;
2759
2760 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2761 }
2762 if (rcStrict != VINF_SUCCESS)
2763 return VINF_SUCCESS;
2764
2765 /* Push the new RBP */
2766 if (enmEffOpSize == IEMMODE_64BIT)
2767 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2768 else if (enmEffOpSize == IEMMODE_32BIT)
2769 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2770 else
2771 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2772 if (rcStrict != VINF_SUCCESS)
2773 return rcStrict;
2774
2775 }
2776
2777 /* Recalc RSP. */
2778 iemRegSubFromRspEx(pVCpu, &NewRsp, cbFrame);
2779
2780 /** @todo Should probe write access at the new RSP according to AMD. */
2781
2782 /* Commit it. */
2783 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2784 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2785 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2786
2787 return VINF_SUCCESS;
2788}
2789
2790
2791
2792/**
2793 * Implements leave.
2794 *
2795 * We're doing this in C because messing with the stack registers is annoying
2796 * since they depends on SS attributes.
2797 *
2798 * @param enmEffOpSize The effective operand size.
2799 */
2800IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2801{
2802 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2803 RTUINT64U NewRsp;
2804 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2805 NewRsp.u = pVCpu->cpum.GstCtx.rbp;
2806 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2807 NewRsp.u = pVCpu->cpum.GstCtx.ebp;
2808 else
2809 {
2810 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2811 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2812 NewRsp.Words.w0 = pVCpu->cpum.GstCtx.bp;
2813 }
2814
2815 /* Pop RBP according to the operand size. */
2816 VBOXSTRICTRC rcStrict;
2817 RTUINT64U NewRbp;
2818 switch (enmEffOpSize)
2819 {
2820 case IEMMODE_16BIT:
2821 NewRbp.u = pVCpu->cpum.GstCtx.rbp;
2822 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2823 break;
2824 case IEMMODE_32BIT:
2825 NewRbp.u = 0;
2826 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2827 break;
2828 case IEMMODE_64BIT:
2829 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2830 break;
2831 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2832 }
2833 if (rcStrict != VINF_SUCCESS)
2834 return rcStrict;
2835
2836
2837 /* Commit it. */
2838 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2839 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2840 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2841
2842 return VINF_SUCCESS;
2843}
2844
2845
2846/**
2847 * Implements int3 and int XX.
2848 *
2849 * @param u8Int The interrupt vector number.
2850 * @param enmInt The int instruction type.
2851 */
2852IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2853{
2854 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2855 return iemRaiseXcptOrInt(pVCpu,
2856 cbInstr,
2857 u8Int,
2858 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2859 0,
2860 0);
2861}
2862
2863
2864/**
2865 * Implements iret for real mode and V8086 mode.
2866 *
2867 * @param enmEffOpSize The effective operand size.
2868 */
2869IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2870{
2871 X86EFLAGS Efl;
2872 Efl.u = IEMMISC_GET_EFL(pVCpu);
2873 NOREF(cbInstr);
2874
2875 /*
2876 * iret throws an exception if VME isn't enabled.
2877 */
2878 if ( Efl.Bits.u1VM
2879 && Efl.Bits.u2IOPL != 3
2880 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
2881 return iemRaiseGeneralProtectionFault0(pVCpu);
2882
2883 /*
2884 * Do the stack bits, but don't commit RSP before everything checks
2885 * out right.
2886 */
2887 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2888 VBOXSTRICTRC rcStrict;
2889 RTCPTRUNION uFrame;
2890 uint16_t uNewCs;
2891 uint32_t uNewEip;
2892 uint32_t uNewFlags;
2893 uint64_t uNewRsp;
2894 if (enmEffOpSize == IEMMODE_32BIT)
2895 {
2896 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
2897 if (rcStrict != VINF_SUCCESS)
2898 return rcStrict;
2899 uNewEip = uFrame.pu32[0];
2900 if (uNewEip > UINT16_MAX)
2901 return iemRaiseGeneralProtectionFault0(pVCpu);
2902
2903 uNewCs = (uint16_t)uFrame.pu32[1];
2904 uNewFlags = uFrame.pu32[2];
2905 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2906 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2907 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2908 | X86_EFL_ID;
2909 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2910 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2911 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2912 }
2913 else
2914 {
2915 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
2916 if (rcStrict != VINF_SUCCESS)
2917 return rcStrict;
2918 uNewEip = uFrame.pu16[0];
2919 uNewCs = uFrame.pu16[1];
2920 uNewFlags = uFrame.pu16[2];
2921 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2922 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2923 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2924 /** @todo The intel pseudo code does not indicate what happens to
2925 * reserved flags. We just ignore them. */
2926 /* Ancient CPU adjustments: See iemCImpl_popf. */
2927 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2928 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2929 }
2930 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2931 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2932 { /* extremely likely */ }
2933 else
2934 return rcStrict;
2935
2936 /** @todo Check how this is supposed to work if sp=0xfffe. */
2937 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2938 uNewCs, uNewEip, uNewFlags, uNewRsp));
2939
2940 /*
2941 * Check the limit of the new EIP.
2942 */
2943 /** @todo Only the AMD pseudo code check the limit here, what's
2944 * right? */
2945 if (uNewEip > pVCpu->cpum.GstCtx.cs.u32Limit)
2946 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2947
2948 /*
2949 * V8086 checks and flag adjustments
2950 */
2951 if (Efl.Bits.u1VM)
2952 {
2953 if (Efl.Bits.u2IOPL == 3)
2954 {
2955 /* Preserve IOPL and clear RF. */
2956 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
2957 uNewFlags |= Efl.u & (X86_EFL_IOPL);
2958 }
2959 else if ( enmEffOpSize == IEMMODE_16BIT
2960 && ( !(uNewFlags & X86_EFL_IF)
2961 || !Efl.Bits.u1VIP )
2962 && !(uNewFlags & X86_EFL_TF) )
2963 {
2964 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
2965 uNewFlags &= ~X86_EFL_VIF;
2966 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
2967 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
2968 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
2969 }
2970 else
2971 return iemRaiseGeneralProtectionFault0(pVCpu);
2972 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
2973 }
2974
2975 /*
2976 * Commit the operation.
2977 */
2978#ifdef DBGFTRACE_ENABLED
2979 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
2980 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
2981#endif
2982 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2983 pVCpu->cpum.GstCtx.rip = uNewEip;
2984 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2985 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2986 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2987 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2988 /** @todo do we load attribs and limit as well? */
2989 Assert(uNewFlags & X86_EFL_1);
2990 IEMMISC_SET_EFL(pVCpu, uNewFlags);
2991
2992 /* Flush the prefetch buffer. */
2993#ifdef IEM_WITH_CODE_TLB
2994 pVCpu->iem.s.pbInstrBuf = NULL;
2995#else
2996 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2997#endif
2998
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/**
3004 * Loads a segment register when entering V8086 mode.
3005 *
3006 * @param pSReg The segment register.
3007 * @param uSeg The segment to load.
3008 */
3009static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3010{
3011 pSReg->Sel = uSeg;
3012 pSReg->ValidSel = uSeg;
3013 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3014 pSReg->u64Base = (uint32_t)uSeg << 4;
3015 pSReg->u32Limit = 0xffff;
3016 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3017 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3018 * IRET'ing to V8086. */
3019}
3020
3021
3022/**
3023 * Implements iret for protected mode returning to V8086 mode.
3024 *
3025 * @param uNewEip The new EIP.
3026 * @param uNewCs The new CS.
3027 * @param uNewFlags The new EFLAGS.
3028 * @param uNewRsp The RSP after the initial IRET frame.
3029 *
3030 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3031 */
3032IEM_CIMPL_DEF_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp)
3033{
3034 RT_NOREF_PV(cbInstr);
3035 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
3036
3037 /*
3038 * Pop the V8086 specific frame bits off the stack.
3039 */
3040 VBOXSTRICTRC rcStrict;
3041 RTCPTRUNION uFrame;
3042 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 24, &uFrame.pv, &uNewRsp);
3043 if (rcStrict != VINF_SUCCESS)
3044 return rcStrict;
3045 uint32_t uNewEsp = uFrame.pu32[0];
3046 uint16_t uNewSs = uFrame.pu32[1];
3047 uint16_t uNewEs = uFrame.pu32[2];
3048 uint16_t uNewDs = uFrame.pu32[3];
3049 uint16_t uNewFs = uFrame.pu32[4];
3050 uint16_t uNewGs = uFrame.pu32[5];
3051 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3052 if (rcStrict != VINF_SUCCESS)
3053 return rcStrict;
3054
3055 /*
3056 * Commit the operation.
3057 */
3058 uNewFlags &= X86_EFL_LIVE_MASK;
3059 uNewFlags |= X86_EFL_RA1_MASK;
3060#ifdef DBGFTRACE_ENABLED
3061 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3062 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3063#endif
3064 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3065
3066 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3067 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.cs, uNewCs);
3068 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ss, uNewSs);
3069 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.es, uNewEs);
3070 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ds, uNewDs);
3071 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.fs, uNewFs);
3072 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.gs, uNewGs);
3073 pVCpu->cpum.GstCtx.rip = (uint16_t)uNewEip;
3074 pVCpu->cpum.GstCtx.rsp = uNewEsp; /** @todo check this out! */
3075 pVCpu->iem.s.uCpl = 3;
3076
3077 /* Flush the prefetch buffer. */
3078#ifdef IEM_WITH_CODE_TLB
3079 pVCpu->iem.s.pbInstrBuf = NULL;
3080#else
3081 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3082#endif
3083
3084 return VINF_SUCCESS;
3085}
3086
3087
3088/**
3089 * Implements iret for protected mode returning via a nested task.
3090 *
3091 * @param enmEffOpSize The effective operand size.
3092 */
3093IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3094{
3095 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3096#ifndef IEM_IMPLEMENTS_TASKSWITCH
3097 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3098#else
3099 RT_NOREF_PV(enmEffOpSize);
3100
3101 /*
3102 * Read the segment selector in the link-field of the current TSS.
3103 */
3104 RTSEL uSelRet;
3105 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base);
3106 if (rcStrict != VINF_SUCCESS)
3107 return rcStrict;
3108
3109 /*
3110 * Fetch the returning task's TSS descriptor from the GDT.
3111 */
3112 if (uSelRet & X86_SEL_LDT)
3113 {
3114 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3115 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3116 }
3117
3118 IEMSELDESC TssDesc;
3119 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3120 if (rcStrict != VINF_SUCCESS)
3121 return rcStrict;
3122
3123 if (TssDesc.Legacy.Gate.u1DescType)
3124 {
3125 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3126 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3127 }
3128
3129 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3130 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3131 {
3132 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3133 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3134 }
3135
3136 if (!TssDesc.Legacy.Gate.u1Present)
3137 {
3138 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3139 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3140 }
3141
3142 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
3143 return iemTaskSwitch(pVCpu, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3144 0 /* uCr2 */, uSelRet, &TssDesc);
3145#endif
3146}
3147
3148
3149/**
3150 * Implements iret for protected mode
3151 *
3152 * @param enmEffOpSize The effective operand size.
3153 */
3154IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3155{
3156 NOREF(cbInstr);
3157 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3158
3159 /*
3160 * Nested task return.
3161 */
3162 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3163 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3164
3165 /*
3166 * Normal return.
3167 *
3168 * Do the stack bits, but don't commit RSP before everything checks
3169 * out right.
3170 */
3171 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3172 VBOXSTRICTRC rcStrict;
3173 RTCPTRUNION uFrame;
3174 uint16_t uNewCs;
3175 uint32_t uNewEip;
3176 uint32_t uNewFlags;
3177 uint64_t uNewRsp;
3178 if (enmEffOpSize == IEMMODE_32BIT)
3179 {
3180 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, &uFrame.pv, &uNewRsp);
3181 if (rcStrict != VINF_SUCCESS)
3182 return rcStrict;
3183 uNewEip = uFrame.pu32[0];
3184 uNewCs = (uint16_t)uFrame.pu32[1];
3185 uNewFlags = uFrame.pu32[2];
3186 }
3187 else
3188 {
3189 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, &uFrame.pv, &uNewRsp);
3190 if (rcStrict != VINF_SUCCESS)
3191 return rcStrict;
3192 uNewEip = uFrame.pu16[0];
3193 uNewCs = uFrame.pu16[1];
3194 uNewFlags = uFrame.pu16[2];
3195 }
3196 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3197 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3198 { /* extremely likely */ }
3199 else
3200 return rcStrict;
3201 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3202
3203 /*
3204 * We're hopefully not returning to V8086 mode...
3205 */
3206 if ( (uNewFlags & X86_EFL_VM)
3207 && pVCpu->iem.s.uCpl == 0)
3208 {
3209 Assert(enmEffOpSize == IEMMODE_32BIT);
3210 return IEM_CIMPL_CALL_4(iemCImpl_iret_prot_v8086, uNewEip, uNewCs, uNewFlags, uNewRsp);
3211 }
3212
3213 /*
3214 * Protected mode.
3215 */
3216 /* Read the CS descriptor. */
3217 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3218 {
3219 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3220 return iemRaiseGeneralProtectionFault0(pVCpu);
3221 }
3222
3223 IEMSELDESC DescCS;
3224 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3225 if (rcStrict != VINF_SUCCESS)
3226 {
3227 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3228 return rcStrict;
3229 }
3230
3231 /* Must be a code descriptor. */
3232 if (!DescCS.Legacy.Gen.u1DescType)
3233 {
3234 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3235 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3236 }
3237 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3238 {
3239 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3240 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3241 }
3242
3243#ifdef VBOX_WITH_RAW_MODE_NOT_R0
3244 /* Raw ring-0 and ring-1 compression adjustments for PATM performance tricks and other CS leaks. */
3245 PVM pVM = pVCpu->CTX_SUFF(pVM);
3246 if (EMIsRawRing0Enabled(pVM) && VM_IS_RAW_MODE_ENABLED(pVM))
3247 {
3248 if ((uNewCs & X86_SEL_RPL) == 1)
3249 {
3250 if ( pVCpu->iem.s.uCpl == 0
3251 && ( !EMIsRawRing1Enabled(pVM)
3252 || pVCpu->cpum.GstCtx.cs.Sel == (uNewCs & X86_SEL_MASK_OFF_RPL)) )
3253 {
3254 Log(("iret: Ring-0 compression fix: uNewCS=%#x -> %#x\n", uNewCs, uNewCs & X86_SEL_MASK_OFF_RPL));
3255 uNewCs &= X86_SEL_MASK_OFF_RPL;
3256 }
3257# ifdef LOG_ENABLED
3258 else if (pVCpu->iem.s.uCpl <= 1 && EMIsRawRing1Enabled(pVM))
3259 Log(("iret: uNewCs=%#x genuine return to ring-1.\n", uNewCs));
3260# endif
3261 }
3262 else if ( (uNewCs & X86_SEL_RPL) == 2
3263 && EMIsRawRing1Enabled(pVM)
3264 && pVCpu->iem.s.uCpl <= 1)
3265 {
3266 Log(("iret: Ring-1 compression fix: uNewCS=%#x -> %#x\n", uNewCs, (uNewCs & X86_SEL_MASK_OFF_RPL) | 1));
3267 uNewCs = (uNewCs & X86_SEL_MASK_OFF_RPL) | 2;
3268 }
3269 }
3270#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
3271
3272
3273 /* Privilege checks. */
3274 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3275 {
3276 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3277 {
3278 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3279 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3280 }
3281 }
3282 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3283 {
3284 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3285 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3286 }
3287 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3288 {
3289 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3290 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3291 }
3292
3293 /* Present? */
3294 if (!DescCS.Legacy.Gen.u1Present)
3295 {
3296 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3297 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3298 }
3299
3300 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3301
3302 /*
3303 * Return to outer level?
3304 */
3305 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3306 {
3307 uint16_t uNewSS;
3308 uint32_t uNewESP;
3309 if (enmEffOpSize == IEMMODE_32BIT)
3310 {
3311 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 8, &uFrame.pv, &uNewRsp);
3312 if (rcStrict != VINF_SUCCESS)
3313 return rcStrict;
3314/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3315 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3316 * bit of the popped SS selector it turns out. */
3317 uNewESP = uFrame.pu32[0];
3318 uNewSS = (uint16_t)uFrame.pu32[1];
3319 }
3320 else
3321 {
3322 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 4, &uFrame.pv, &uNewRsp);
3323 if (rcStrict != VINF_SUCCESS)
3324 return rcStrict;
3325 uNewESP = uFrame.pu16[0];
3326 uNewSS = uFrame.pu16[1];
3327 }
3328 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3329 if (rcStrict != VINF_SUCCESS)
3330 return rcStrict;
3331 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3332
3333 /* Read the SS descriptor. */
3334 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3335 {
3336 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3337 return iemRaiseGeneralProtectionFault0(pVCpu);
3338 }
3339
3340 IEMSELDESC DescSS;
3341 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3342 if (rcStrict != VINF_SUCCESS)
3343 {
3344 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3345 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3346 return rcStrict;
3347 }
3348
3349 /* Privilege checks. */
3350 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3351 {
3352 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3353 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3354 }
3355 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3356 {
3357 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3358 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3359 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3360 }
3361
3362 /* Must be a writeable data segment descriptor. */
3363 if (!DescSS.Legacy.Gen.u1DescType)
3364 {
3365 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3366 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3367 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3368 }
3369 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3370 {
3371 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3372 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3373 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3374 }
3375
3376 /* Present? */
3377 if (!DescSS.Legacy.Gen.u1Present)
3378 {
3379 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3380 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3381 }
3382
3383 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3384
3385 /* Check EIP. */
3386 if (uNewEip > cbLimitCS)
3387 {
3388 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3389 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3390 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3391 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3392 }
3393
3394 /*
3395 * Commit the changes, marking CS and SS accessed first since
3396 * that may fail.
3397 */
3398 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3399 {
3400 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3401 if (rcStrict != VINF_SUCCESS)
3402 return rcStrict;
3403 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3404 }
3405 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3406 {
3407 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3408 if (rcStrict != VINF_SUCCESS)
3409 return rcStrict;
3410 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3411 }
3412
3413 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3414 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3415 if (enmEffOpSize != IEMMODE_16BIT)
3416 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3417 if (pVCpu->iem.s.uCpl == 0)
3418 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3419 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3420 fEFlagsMask |= X86_EFL_IF;
3421 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3422 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3423 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3424 fEFlagsNew &= ~fEFlagsMask;
3425 fEFlagsNew |= uNewFlags & fEFlagsMask;
3426#ifdef DBGFTRACE_ENABLED
3427 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3428 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3429 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3430#endif
3431
3432 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3433 pVCpu->cpum.GstCtx.rip = uNewEip;
3434 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3435 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3436 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3437 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3438 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3439 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3440 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3441
3442 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
3443 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
3444 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3445 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3446 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3447 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3448 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3449 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewESP;
3450 else
3451 pVCpu->cpum.GstCtx.rsp = uNewESP;
3452
3453 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3454 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
3455 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
3456 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
3457 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
3458
3459 /* Done! */
3460
3461 }
3462 /*
3463 * Return to the same level.
3464 */
3465 else
3466 {
3467 /* Check EIP. */
3468 if (uNewEip > cbLimitCS)
3469 {
3470 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3471 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3472 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3473 }
3474
3475 /*
3476 * Commit the changes, marking CS first since it may fail.
3477 */
3478 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3479 {
3480 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3481 if (rcStrict != VINF_SUCCESS)
3482 return rcStrict;
3483 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3484 }
3485
3486 X86EFLAGS NewEfl;
3487 NewEfl.u = IEMMISC_GET_EFL(pVCpu);
3488 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3489 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3490 if (enmEffOpSize != IEMMODE_16BIT)
3491 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3492 if (pVCpu->iem.s.uCpl == 0)
3493 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3494 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3495 fEFlagsMask |= X86_EFL_IF;
3496 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3497 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3498 NewEfl.u &= ~fEFlagsMask;
3499 NewEfl.u |= fEFlagsMask & uNewFlags;
3500#ifdef DBGFTRACE_ENABLED
3501 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3502 pVCpu->iem.s.uCpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3503 uNewCs, uNewEip, uNewFlags, pVCpu->cpum.GstCtx.ss.Sel, uNewRsp);
3504#endif
3505
3506 IEMMISC_SET_EFL(pVCpu, NewEfl.u);
3507 pVCpu->cpum.GstCtx.rip = uNewEip;
3508 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3509 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3510 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3511 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3512 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3513 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3514 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3515 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3516 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3517 else
3518 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3519 /* Done! */
3520 }
3521
3522 /* Flush the prefetch buffer. */
3523#ifdef IEM_WITH_CODE_TLB
3524 pVCpu->iem.s.pbInstrBuf = NULL;
3525#else
3526 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3527#endif
3528
3529 return VINF_SUCCESS;
3530}
3531
3532
3533/**
3534 * Implements iret for long mode
3535 *
3536 * @param enmEffOpSize The effective operand size.
3537 */
3538IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3539{
3540 NOREF(cbInstr);
3541
3542 /*
3543 * Nested task return is not supported in long mode.
3544 */
3545 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3546 {
3547 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.eflags.u));
3548 return iemRaiseGeneralProtectionFault0(pVCpu);
3549 }
3550
3551 /*
3552 * Normal return.
3553 *
3554 * Do the stack bits, but don't commit RSP before everything checks
3555 * out right.
3556 */
3557 VBOXSTRICTRC rcStrict;
3558 RTCPTRUNION uFrame;
3559 uint64_t uNewRip;
3560 uint16_t uNewCs;
3561 uint16_t uNewSs;
3562 uint32_t uNewFlags;
3563 uint64_t uNewRsp;
3564 if (enmEffOpSize == IEMMODE_64BIT)
3565 {
3566 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, &uFrame.pv, &uNewRsp);
3567 if (rcStrict != VINF_SUCCESS)
3568 return rcStrict;
3569 uNewRip = uFrame.pu64[0];
3570 uNewCs = (uint16_t)uFrame.pu64[1];
3571 uNewFlags = (uint32_t)uFrame.pu64[2];
3572 uNewRsp = uFrame.pu64[3];
3573 uNewSs = (uint16_t)uFrame.pu64[4];
3574 }
3575 else if (enmEffOpSize == IEMMODE_32BIT)
3576 {
3577 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, &uFrame.pv, &uNewRsp);
3578 if (rcStrict != VINF_SUCCESS)
3579 return rcStrict;
3580 uNewRip = uFrame.pu32[0];
3581 uNewCs = (uint16_t)uFrame.pu32[1];
3582 uNewFlags = uFrame.pu32[2];
3583 uNewRsp = uFrame.pu32[3];
3584 uNewSs = (uint16_t)uFrame.pu32[4];
3585 }
3586 else
3587 {
3588 Assert(enmEffOpSize == IEMMODE_16BIT);
3589 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, &uFrame.pv, &uNewRsp);
3590 if (rcStrict != VINF_SUCCESS)
3591 return rcStrict;
3592 uNewRip = uFrame.pu16[0];
3593 uNewCs = uFrame.pu16[1];
3594 uNewFlags = uFrame.pu16[2];
3595 uNewRsp = uFrame.pu16[3];
3596 uNewSs = uFrame.pu16[4];
3597 }
3598 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3599 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3600 { /* extremely like */ }
3601 else
3602 return rcStrict;
3603 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3604
3605 /*
3606 * Check stuff.
3607 */
3608 /* Read the CS descriptor. */
3609 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3610 {
3611 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3612 return iemRaiseGeneralProtectionFault0(pVCpu);
3613 }
3614
3615 IEMSELDESC DescCS;
3616 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3617 if (rcStrict != VINF_SUCCESS)
3618 {
3619 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3620 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3621 return rcStrict;
3622 }
3623
3624 /* Must be a code descriptor. */
3625 if ( !DescCS.Legacy.Gen.u1DescType
3626 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3627 {
3628 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3629 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3630 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3631 }
3632
3633 /* Privilege checks. */
3634 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3635 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3636 {
3637 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3638 {
3639 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3640 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3641 }
3642 }
3643 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3644 {
3645 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3646 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3647 }
3648 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3649 {
3650 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3651 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3652 }
3653
3654 /* Present? */
3655 if (!DescCS.Legacy.Gen.u1Present)
3656 {
3657 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3658 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3659 }
3660
3661 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3662
3663 /* Read the SS descriptor. */
3664 IEMSELDESC DescSS;
3665 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3666 {
3667 if ( !DescCS.Legacy.Gen.u1Long
3668 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3669 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3670 {
3671 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3672 return iemRaiseGeneralProtectionFault0(pVCpu);
3673 }
3674 DescSS.Legacy.u = 0;
3675 }
3676 else
3677 {
3678 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3679 if (rcStrict != VINF_SUCCESS)
3680 {
3681 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3682 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3683 return rcStrict;
3684 }
3685 }
3686
3687 /* Privilege checks. */
3688 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3689 {
3690 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3691 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3692 }
3693
3694 uint32_t cbLimitSs;
3695 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3696 cbLimitSs = UINT32_MAX;
3697 else
3698 {
3699 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3700 {
3701 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3702 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3703 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3704 }
3705
3706 /* Must be a writeable data segment descriptor. */
3707 if (!DescSS.Legacy.Gen.u1DescType)
3708 {
3709 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3710 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3711 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3712 }
3713 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3714 {
3715 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3716 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3717 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3718 }
3719
3720 /* Present? */
3721 if (!DescSS.Legacy.Gen.u1Present)
3722 {
3723 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3724 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3725 }
3726 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3727 }
3728
3729 /* Check EIP. */
3730 if (DescCS.Legacy.Gen.u1Long)
3731 {
3732 if (!IEM_IS_CANONICAL(uNewRip))
3733 {
3734 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3735 uNewCs, uNewRip, uNewSs, uNewRsp));
3736 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3737 }
3738 }
3739 else
3740 {
3741 if (uNewRip > cbLimitCS)
3742 {
3743 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3744 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3745 /** @todo: Which is it, #GP(0) or #GP(sel)? */
3746 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3747 }
3748 }
3749
3750 /*
3751 * Commit the changes, marking CS and SS accessed first since
3752 * that may fail.
3753 */
3754 /** @todo where exactly are these actually marked accessed by a real CPU? */
3755 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3756 {
3757 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3758 if (rcStrict != VINF_SUCCESS)
3759 return rcStrict;
3760 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3761 }
3762 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3763 {
3764 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3765 if (rcStrict != VINF_SUCCESS)
3766 return rcStrict;
3767 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3768 }
3769
3770 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3771 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3772 if (enmEffOpSize != IEMMODE_16BIT)
3773 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3774 if (pVCpu->iem.s.uCpl == 0)
3775 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3776 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3777 fEFlagsMask |= X86_EFL_IF;
3778 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3779 fEFlagsNew &= ~fEFlagsMask;
3780 fEFlagsNew |= uNewFlags & fEFlagsMask;
3781#ifdef DBGFTRACE_ENABLED
3782 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3783 pVCpu->iem.s.uCpl, uNewCpl, pVCpu->cpum.GstCtx.rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3784#endif
3785
3786 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3787 pVCpu->cpum.GstCtx.rip = uNewRip;
3788 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3789 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3790 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3791 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3792 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3793 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3794 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3795 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
3796 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3797 else
3798 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3799 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3800 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3801 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3802 {
3803 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3804 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3805 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3806 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3807 Log2(("iretq new SS: NULL\n"));
3808 }
3809 else
3810 {
3811 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3812 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3813 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3814 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3815 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
3816 }
3817
3818 if (pVCpu->iem.s.uCpl != uNewCpl)
3819 {
3820 pVCpu->iem.s.uCpl = uNewCpl;
3821 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.ds);
3822 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.es);
3823 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.fs);
3824 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.gs);
3825 }
3826
3827 /* Flush the prefetch buffer. */
3828#ifdef IEM_WITH_CODE_TLB
3829 pVCpu->iem.s.pbInstrBuf = NULL;
3830#else
3831 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3832#endif
3833
3834 return VINF_SUCCESS;
3835}
3836
3837
3838/**
3839 * Implements iret.
3840 *
3841 * @param enmEffOpSize The effective operand size.
3842 */
3843IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3844{
3845 /*
3846 * First, clear NMI blocking, if any, before causing any exceptions.
3847 * See Intel spec. 6.7.1 "Handling Multiple NMIs".
3848 */
3849 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
3850
3851 /*
3852 * The SVM nested-guest intercept for iret takes priority over all exceptions,
3853 * see AMD spec. "15.9 Instruction Intercepts".
3854 */
3855 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3856 {
3857 Log(("iret: Guest intercept -> #VMEXIT\n"));
3858 IEM_SVM_UPDATE_NRIP(pVCpu);
3859 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3860 }
3861
3862 /*
3863 * Call a mode specific worker.
3864 */
3865 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3866 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3867 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
3868 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3869 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3870 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3871}
3872
3873
3874/**
3875 * Implements SYSCALL (AMD and Intel64).
3876 *
3877 * @param enmEffOpSize The effective operand size.
3878 */
3879IEM_CIMPL_DEF_0(iemCImpl_syscall)
3880{
3881 /*
3882 * Check preconditions.
3883 *
3884 * Note that CPUs described in the documentation may load a few odd values
3885 * into CS and SS than we allow here. This has yet to be checked on real
3886 * hardware.
3887 */
3888 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
3889 {
3890 Log(("syscall: Not enabled in EFER -> #UD\n"));
3891 return iemRaiseUndefinedOpcode(pVCpu);
3892 }
3893 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
3894 {
3895 Log(("syscall: Protected mode is required -> #GP(0)\n"));
3896 return iemRaiseGeneralProtectionFault0(pVCpu);
3897 }
3898 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
3899 {
3900 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3901 return iemRaiseUndefinedOpcode(pVCpu);
3902 }
3903
3904 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
3905
3906 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
3907 /** @todo what about LDT selectors? Shouldn't matter, really. */
3908 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
3909 uint16_t uNewSs = uNewCs + 8;
3910 if (uNewCs == 0 || uNewSs == 0)
3911 {
3912 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
3913 return iemRaiseGeneralProtectionFault0(pVCpu);
3914 }
3915
3916 /* Long mode and legacy mode differs. */
3917 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
3918 {
3919 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.msrLSTAR : pVCpu->cpum.GstCtx. msrCSTAR;
3920
3921 /* This test isn't in the docs, but I'm not trusting the guys writing
3922 the MSRs to have validated the values as canonical like they should. */
3923 if (!IEM_IS_CANONICAL(uNewRip))
3924 {
3925 Log(("syscall: Only available in long mode on intel -> #UD\n"));
3926 return iemRaiseUndefinedOpcode(pVCpu);
3927 }
3928
3929 /*
3930 * Commit it.
3931 */
3932 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
3933 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.rip + cbInstr;
3934 pVCpu->cpum.GstCtx.rip = uNewRip;
3935
3936 pVCpu->cpum.GstCtx.rflags.u &= ~X86_EFL_RF;
3937 pVCpu->cpum.GstCtx.r11 = pVCpu->cpum.GstCtx.rflags.u;
3938 pVCpu->cpum.GstCtx.rflags.u &= ~pVCpu->cpum.GstCtx.msrSFMASK;
3939 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
3940
3941 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3942 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3943 }
3944 else
3945 {
3946 /*
3947 * Commit it.
3948 */
3949 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
3950 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
3951 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.eip + cbInstr;
3952 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
3953 pVCpu->cpum.GstCtx.rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
3954
3955 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
3956 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
3957 }
3958 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3959 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3960 pVCpu->cpum.GstCtx.cs.u64Base = 0;
3961 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
3962 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3963
3964 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3965 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3966 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3967 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3968 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3969
3970 /* Flush the prefetch buffer. */
3971#ifdef IEM_WITH_CODE_TLB
3972 pVCpu->iem.s.pbInstrBuf = NULL;
3973#else
3974 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3975#endif
3976
3977 return VINF_SUCCESS;
3978}
3979
3980
3981/**
3982 * Implements SYSRET (AMD and Intel64).
3983 */
3984IEM_CIMPL_DEF_0(iemCImpl_sysret)
3985
3986{
3987 RT_NOREF_PV(cbInstr);
3988
3989 /*
3990 * Check preconditions.
3991 *
3992 * Note that CPUs described in the documentation may load a few odd values
3993 * into CS and SS than we allow here. This has yet to be checked on real
3994 * hardware.
3995 */
3996 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
3997 {
3998 Log(("sysret: Not enabled in EFER -> #UD\n"));
3999 return iemRaiseUndefinedOpcode(pVCpu);
4000 }
4001 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4002 {
4003 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4004 return iemRaiseUndefinedOpcode(pVCpu);
4005 }
4006 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4007 {
4008 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4009 return iemRaiseGeneralProtectionFault0(pVCpu);
4010 }
4011 if (pVCpu->iem.s.uCpl != 0)
4012 {
4013 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4014 return iemRaiseGeneralProtectionFault0(pVCpu);
4015 }
4016
4017 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4018
4019 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4020 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4021 uint16_t uNewSs = uNewCs + 8;
4022 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4023 uNewCs += 16;
4024 if (uNewCs == 0 || uNewSs == 0)
4025 {
4026 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4027 return iemRaiseGeneralProtectionFault0(pVCpu);
4028 }
4029
4030 /*
4031 * Commit it.
4032 */
4033 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4034 {
4035 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4036 {
4037 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
4038 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
4039 /* Note! We disregard intel manual regarding the RCX cananonical
4040 check, ask intel+xen why AMD doesn't do it. */
4041 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4042 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4043 | (3 << X86DESCATTR_DPL_SHIFT);
4044 }
4045 else
4046 {
4047 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
4048 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
4049 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.ecx;
4050 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4051 | (3 << X86DESCATTR_DPL_SHIFT);
4052 }
4053 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4054 * what it really ignores. RF and VM are hinted at being zero, by AMD. */
4055 pVCpu->cpum.GstCtx.rflags.u = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4056 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4057 }
4058 else
4059 {
4060 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
4061 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4062 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_IF;
4063 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4064 | (3 << X86DESCATTR_DPL_SHIFT);
4065 }
4066 pVCpu->cpum.GstCtx.cs.Sel = uNewCs | 3;
4067 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs | 3;
4068 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4069 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4070 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4071
4072 pVCpu->cpum.GstCtx.ss.Sel = uNewSs | 3;
4073 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs | 3;
4074 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4075 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4076 pVCpu->cpum.GstCtx.ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4077 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4078 * on sysret. */
4079
4080 /* Flush the prefetch buffer. */
4081#ifdef IEM_WITH_CODE_TLB
4082 pVCpu->iem.s.pbInstrBuf = NULL;
4083#else
4084 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4085#endif
4086
4087 return VINF_SUCCESS;
4088}
4089
4090
4091/**
4092 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4093 *
4094 * @param iSegReg The segment register number (valid).
4095 * @param uSel The new selector value.
4096 */
4097IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4098{
4099 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
4100 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4101 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4102
4103 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4104
4105 /*
4106 * Real mode and V8086 mode are easy.
4107 */
4108 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4109 {
4110 *pSel = uSel;
4111 pHid->u64Base = (uint32_t)uSel << 4;
4112 pHid->ValidSel = uSel;
4113 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4114#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4115 /** @todo Does the CPU actually load limits and attributes in the
4116 * real/V8086 mode segment load case? It doesn't for CS in far
4117 * jumps... Affects unreal mode. */
4118 pHid->u32Limit = 0xffff;
4119 pHid->Attr.u = 0;
4120 pHid->Attr.n.u1Present = 1;
4121 pHid->Attr.n.u1DescType = 1;
4122 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4123 ? X86_SEL_TYPE_RW
4124 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4125#endif
4126 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4128 return VINF_SUCCESS;
4129 }
4130
4131 /*
4132 * Protected mode.
4133 *
4134 * Check if it's a null segment selector value first, that's OK for DS, ES,
4135 * FS and GS. If not null, then we have to load and parse the descriptor.
4136 */
4137 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4138 {
4139 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4140 if (iSegReg == X86_SREG_SS)
4141 {
4142 /* In 64-bit kernel mode, the stack can be 0 because of the way
4143 interrupts are dispatched. AMD seems to have a slighly more
4144 relaxed relationship to SS.RPL than intel does. */
4145 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4146 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4147 || pVCpu->iem.s.uCpl > 2
4148 || ( uSel != pVCpu->iem.s.uCpl
4149 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4150 {
4151 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4152 return iemRaiseGeneralProtectionFault0(pVCpu);
4153 }
4154 }
4155
4156 *pSel = uSel; /* Not RPL, remember :-) */
4157 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4158 if (iSegReg == X86_SREG_SS)
4159 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4160
4161 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4162 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4163
4164 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4165 return VINF_SUCCESS;
4166 }
4167
4168 /* Fetch the descriptor. */
4169 IEMSELDESC Desc;
4170 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4171 if (rcStrict != VINF_SUCCESS)
4172 return rcStrict;
4173
4174 /* Check GPs first. */
4175 if (!Desc.Legacy.Gen.u1DescType)
4176 {
4177 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4178 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4179 }
4180 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4181 {
4182 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4183 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4184 {
4185 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4186 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4187 }
4188 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4189 {
4190 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4191 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4192 }
4193 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4194 {
4195 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4196 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4197 }
4198 }
4199 else
4200 {
4201 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4202 {
4203 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4204 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4205 }
4206 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4207 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4208 {
4209#if 0 /* this is what intel says. */
4210 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4211 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4212 {
4213 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4214 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4215 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4216 }
4217#else /* this is what makes more sense. */
4218 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4219 {
4220 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4221 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4222 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4223 }
4224 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4225 {
4226 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4227 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4228 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4229 }
4230#endif
4231 }
4232 }
4233
4234 /* Is it there? */
4235 if (!Desc.Legacy.Gen.u1Present)
4236 {
4237 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4238 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4239 }
4240
4241 /* The base and limit. */
4242 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4243 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4244
4245 /*
4246 * Ok, everything checked out fine. Now set the accessed bit before
4247 * committing the result into the registers.
4248 */
4249 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4250 {
4251 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4252 if (rcStrict != VINF_SUCCESS)
4253 return rcStrict;
4254 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4255 }
4256
4257 /* commit */
4258 *pSel = uSel;
4259 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4260 pHid->u32Limit = cbLimit;
4261 pHid->u64Base = u64Base;
4262 pHid->ValidSel = uSel;
4263 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4264
4265 /** @todo check if the hidden bits are loaded correctly for 64-bit
4266 * mode. */
4267 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4268
4269 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4270 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4271 return VINF_SUCCESS;
4272}
4273
4274
4275/**
4276 * Implements 'mov SReg, r/m'.
4277 *
4278 * @param iSegReg The segment register number (valid).
4279 * @param uSel The new selector value.
4280 */
4281IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4282{
4283 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4284 if (rcStrict == VINF_SUCCESS)
4285 {
4286 if (iSegReg == X86_SREG_SS)
4287 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4288 }
4289 return rcStrict;
4290}
4291
4292
4293/**
4294 * Implements 'pop SReg'.
4295 *
4296 * @param iSegReg The segment register number (valid).
4297 * @param enmEffOpSize The efficient operand size (valid).
4298 */
4299IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4300{
4301 VBOXSTRICTRC rcStrict;
4302
4303 /*
4304 * Read the selector off the stack and join paths with mov ss, reg.
4305 */
4306 RTUINT64U TmpRsp;
4307 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
4308 switch (enmEffOpSize)
4309 {
4310 case IEMMODE_16BIT:
4311 {
4312 uint16_t uSel;
4313 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4314 if (rcStrict == VINF_SUCCESS)
4315 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4316 break;
4317 }
4318
4319 case IEMMODE_32BIT:
4320 {
4321 uint32_t u32Value;
4322 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4323 if (rcStrict == VINF_SUCCESS)
4324 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4325 break;
4326 }
4327
4328 case IEMMODE_64BIT:
4329 {
4330 uint64_t u64Value;
4331 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4332 if (rcStrict == VINF_SUCCESS)
4333 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4334 break;
4335 }
4336 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4337 }
4338
4339 /*
4340 * Commit the stack on success.
4341 */
4342 if (rcStrict == VINF_SUCCESS)
4343 {
4344 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
4345 if (iSegReg == X86_SREG_SS)
4346 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
4347 }
4348 return rcStrict;
4349}
4350
4351
4352/**
4353 * Implements lgs, lfs, les, lds & lss.
4354 */
4355IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg,
4356 uint16_t, uSel,
4357 uint64_t, offSeg,
4358 uint8_t, iSegReg,
4359 uint8_t, iGReg,
4360 IEMMODE, enmEffOpSize)
4361{
4362 /*
4363 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4364 */
4365 /** @todo verify and test that mov, pop and lXs works the segment
4366 * register loading in the exact same way. */
4367 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4368 if (rcStrict == VINF_SUCCESS)
4369 {
4370 switch (enmEffOpSize)
4371 {
4372 case IEMMODE_16BIT:
4373 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4374 break;
4375 case IEMMODE_32BIT:
4376 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4377 break;
4378 case IEMMODE_64BIT:
4379 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4380 break;
4381 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4382 }
4383 }
4384
4385 return rcStrict;
4386}
4387
4388
4389/**
4390 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4391 *
4392 * @retval VINF_SUCCESS on success.
4393 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4394 * @retval iemMemFetchSysU64 return value.
4395 *
4396 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4397 * @param uSel The selector value.
4398 * @param fAllowSysDesc Whether system descriptors are OK or not.
4399 * @param pDesc Where to return the descriptor on success.
4400 */
4401static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPU pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4402{
4403 pDesc->Long.au64[0] = 0;
4404 pDesc->Long.au64[1] = 0;
4405
4406 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4407 return VINF_IEM_SELECTOR_NOT_OK;
4408
4409 /* Within the table limits? */
4410 RTGCPTR GCPtrBase;
4411 if (uSel & X86_SEL_LDT)
4412 {
4413 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4414 if ( !pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Present
4415 || (uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.ldtr.u32Limit )
4416 return VINF_IEM_SELECTOR_NOT_OK;
4417 GCPtrBase = pVCpu->cpum.GstCtx.ldtr.u64Base;
4418 }
4419 else
4420 {
4421 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4422 if ((uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.gdtr.cbGdt)
4423 return VINF_IEM_SELECTOR_NOT_OK;
4424 GCPtrBase = pVCpu->cpum.GstCtx.gdtr.pGdt;
4425 }
4426
4427 /* Fetch the descriptor. */
4428 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4429 if (rcStrict != VINF_SUCCESS)
4430 return rcStrict;
4431 if (!pDesc->Legacy.Gen.u1DescType)
4432 {
4433 if (!fAllowSysDesc)
4434 return VINF_IEM_SELECTOR_NOT_OK;
4435 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4436 {
4437 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4438 if (rcStrict != VINF_SUCCESS)
4439 return rcStrict;
4440 }
4441
4442 }
4443
4444 return VINF_SUCCESS;
4445}
4446
4447
4448/**
4449 * Implements verr (fWrite = false) and verw (fWrite = true).
4450 */
4451IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4452{
4453 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4454
4455 /** @todo figure whether the accessed bit is set or not. */
4456
4457 bool fAccessible = true;
4458 IEMSELDESC Desc;
4459 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4460 if (rcStrict == VINF_SUCCESS)
4461 {
4462 /* Check the descriptor, order doesn't matter much here. */
4463 if ( !Desc.Legacy.Gen.u1DescType
4464 || !Desc.Legacy.Gen.u1Present)
4465 fAccessible = false;
4466 else
4467 {
4468 if ( fWrite
4469 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4470 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4471 fAccessible = false;
4472
4473 /** @todo testcase for the conforming behavior. */
4474 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4475 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4476 {
4477 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4478 fAccessible = false;
4479 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4480 fAccessible = false;
4481 }
4482 }
4483
4484 }
4485 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4486 fAccessible = false;
4487 else
4488 return rcStrict;
4489
4490 /* commit */
4491 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible;
4492
4493 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4494 return VINF_SUCCESS;
4495}
4496
4497
4498/**
4499 * Implements LAR and LSL with 64-bit operand size.
4500 *
4501 * @returns VINF_SUCCESS.
4502 * @param pu16Dst Pointer to the destination register.
4503 * @param uSel The selector to load details for.
4504 * @param fIsLar true = LAR, false = LSL.
4505 */
4506IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4507{
4508 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4509
4510 /** @todo figure whether the accessed bit is set or not. */
4511
4512 bool fDescOk = true;
4513 IEMSELDESC Desc;
4514 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, true /*fAllowSysDesc*/, &Desc);
4515 if (rcStrict == VINF_SUCCESS)
4516 {
4517 /*
4518 * Check the descriptor type.
4519 */
4520 if (!Desc.Legacy.Gen.u1DescType)
4521 {
4522 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4523 {
4524 if (Desc.Long.Gen.u5Zeros)
4525 fDescOk = false;
4526 else
4527 switch (Desc.Long.Gen.u4Type)
4528 {
4529 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4530 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4531 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4532 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4533 break;
4534 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4535 fDescOk = fIsLar;
4536 break;
4537 default:
4538 fDescOk = false;
4539 break;
4540 }
4541 }
4542 else
4543 {
4544 switch (Desc.Long.Gen.u4Type)
4545 {
4546 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4547 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4548 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4549 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4550 case X86_SEL_TYPE_SYS_LDT:
4551 break;
4552 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4553 case X86_SEL_TYPE_SYS_TASK_GATE:
4554 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4555 fDescOk = fIsLar;
4556 break;
4557 default:
4558 fDescOk = false;
4559 break;
4560 }
4561 }
4562 }
4563 if (fDescOk)
4564 {
4565 /*
4566 * Check the RPL/DPL/CPL interaction..
4567 */
4568 /** @todo testcase for the conforming behavior. */
4569 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4570 || !Desc.Legacy.Gen.u1DescType)
4571 {
4572 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4573 fDescOk = false;
4574 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4575 fDescOk = false;
4576 }
4577 }
4578
4579 if (fDescOk)
4580 {
4581 /*
4582 * All fine, start committing the result.
4583 */
4584 if (fIsLar)
4585 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4586 else
4587 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
4588 }
4589
4590 }
4591 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4592 fDescOk = false;
4593 else
4594 return rcStrict;
4595
4596 /* commit flags value and advance rip. */
4597 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk;
4598 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4599
4600 return VINF_SUCCESS;
4601}
4602
4603
4604/**
4605 * Implements LAR and LSL with 16-bit operand size.
4606 *
4607 * @returns VINF_SUCCESS.
4608 * @param pu16Dst Pointer to the destination register.
4609 * @param u16Sel The selector to load details for.
4610 * @param fIsLar true = LAR, false = LSL.
4611 */
4612IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
4613{
4614 uint64_t u64TmpDst = *pu16Dst;
4615 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
4616 *pu16Dst = u64TmpDst;
4617 return VINF_SUCCESS;
4618}
4619
4620
4621/**
4622 * Implements lgdt.
4623 *
4624 * @param iEffSeg The segment of the new gdtr contents
4625 * @param GCPtrEffSrc The address of the new gdtr contents.
4626 * @param enmEffOpSize The effective operand size.
4627 */
4628IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4629{
4630 if (pVCpu->iem.s.uCpl != 0)
4631 return iemRaiseGeneralProtectionFault0(pVCpu);
4632 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
4633
4634 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
4635 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
4636 {
4637 Log(("lgdt: Guest intercept -> VM-exit\n"));
4638 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_LGDT, cbInstr);
4639 }
4640
4641 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
4642 {
4643 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
4644 IEM_SVM_UPDATE_NRIP(pVCpu);
4645 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4646 }
4647
4648 /*
4649 * Fetch the limit and base address.
4650 */
4651 uint16_t cbLimit;
4652 RTGCPTR GCPtrBase;
4653 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4654 if (rcStrict == VINF_SUCCESS)
4655 {
4656 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4657 || X86_IS_CANONICAL(GCPtrBase))
4658 {
4659 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4660 if (rcStrict == VINF_SUCCESS)
4661 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4662 }
4663 else
4664 {
4665 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4666 return iemRaiseGeneralProtectionFault0(pVCpu);
4667 }
4668 }
4669 return rcStrict;
4670}
4671
4672
4673/**
4674 * Implements sgdt.
4675 *
4676 * @param iEffSeg The segment where to store the gdtr content.
4677 * @param GCPtrEffDst The address where to store the gdtr content.
4678 */
4679IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4680{
4681 /*
4682 * Join paths with sidt.
4683 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4684 * you really must know.
4685 */
4686 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
4687 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
4688 {
4689 Log(("sgdt: Guest intercept -> VM-exit\n"));
4690 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_SGDT, cbInstr);
4691 }
4692
4693 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_READS))
4694 {
4695 Log(("sgdt: Guest intercept -> #VMEXIT\n"));
4696 IEM_SVM_UPDATE_NRIP(pVCpu);
4697 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4698 }
4699
4700 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4701 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst);
4702 if (rcStrict == VINF_SUCCESS)
4703 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4704 return rcStrict;
4705}
4706
4707
4708/**
4709 * Implements lidt.
4710 *
4711 * @param iEffSeg The segment of the new idtr contents
4712 * @param GCPtrEffSrc The address of the new idtr contents.
4713 * @param enmEffOpSize The effective operand size.
4714 */
4715IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
4716{
4717 if (pVCpu->iem.s.uCpl != 0)
4718 return iemRaiseGeneralProtectionFault0(pVCpu);
4719 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
4720
4721 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
4722 {
4723 Log(("lidt: Guest intercept -> #VMEXIT\n"));
4724 IEM_SVM_UPDATE_NRIP(pVCpu);
4725 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4726 }
4727
4728 /*
4729 * Fetch the limit and base address.
4730 */
4731 uint16_t cbLimit;
4732 RTGCPTR GCPtrBase;
4733 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
4734 if (rcStrict == VINF_SUCCESS)
4735 {
4736 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4737 || X86_IS_CANONICAL(GCPtrBase))
4738 {
4739 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4740 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4741 }
4742 else
4743 {
4744 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
4745 return iemRaiseGeneralProtectionFault0(pVCpu);
4746 }
4747 }
4748 return rcStrict;
4749}
4750
4751
4752/**
4753 * Implements sidt.
4754 *
4755 * @param iEffSeg The segment where to store the idtr content.
4756 * @param GCPtrEffDst The address where to store the idtr content.
4757 */
4758IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4759{
4760 /*
4761 * Join paths with sgdt.
4762 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
4763 * you really must know.
4764 */
4765 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_READS))
4766 {
4767 Log(("sidt: Guest intercept -> #VMEXIT\n"));
4768 IEM_SVM_UPDATE_NRIP(pVCpu);
4769 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4770 }
4771
4772 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_IDTR);
4773 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst);
4774 if (rcStrict == VINF_SUCCESS)
4775 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4776 return rcStrict;
4777}
4778
4779
4780/**
4781 * Implements lldt.
4782 *
4783 * @param uNewLdt The new LDT selector value.
4784 */
4785IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
4786{
4787 /*
4788 * Check preconditions.
4789 */
4790 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4791 {
4792 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
4793 return iemRaiseUndefinedOpcode(pVCpu);
4794 }
4795 if (pVCpu->iem.s.uCpl != 0)
4796 {
4797 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
4798 return iemRaiseGeneralProtectionFault0(pVCpu);
4799 }
4800 /* Nested-guest VMX intercept. */
4801 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
4802 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
4803 {
4804 Log(("lldt: Guest intercept -> VM-exit\n"));
4805 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LLDT, cbInstr);
4806 }
4807 if (uNewLdt & X86_SEL_LDT)
4808 {
4809 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
4810 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
4811 }
4812
4813 /*
4814 * Now, loading a NULL selector is easy.
4815 */
4816 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
4817 {
4818 /* Nested-guest SVM intercept. */
4819 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4820 {
4821 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4822 IEM_SVM_UPDATE_NRIP(pVCpu);
4823 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4824 }
4825
4826 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
4827 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_LDTR;
4828 CPUMSetGuestLDTR(pVCpu, uNewLdt);
4829 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt;
4830 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4831 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
4832 {
4833 /* AMD-V seems to leave the base and limit alone. */
4834 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
4835 }
4836 else
4837 {
4838 /* VT-x (Intel 3960x) seems to be doing the following. */
4839 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
4840 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
4841 pVCpu->cpum.GstCtx.ldtr.u32Limit = UINT32_MAX;
4842 }
4843
4844 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4845 return VINF_SUCCESS;
4846 }
4847
4848 /*
4849 * Read the descriptor.
4850 */
4851 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR);
4852 IEMSELDESC Desc;
4853 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
4854 if (rcStrict != VINF_SUCCESS)
4855 return rcStrict;
4856
4857 /* Check GPs first. */
4858 if (Desc.Legacy.Gen.u1DescType)
4859 {
4860 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4861 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4862 }
4863 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
4864 {
4865 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
4866 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4867 }
4868 uint64_t u64Base;
4869 if (!IEM_IS_LONG_MODE(pVCpu))
4870 u64Base = X86DESC_BASE(&Desc.Legacy);
4871 else
4872 {
4873 if (Desc.Long.Gen.u5Zeros)
4874 {
4875 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
4876 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4877 }
4878
4879 u64Base = X86DESC64_BASE(&Desc.Long);
4880 if (!IEM_IS_CANONICAL(u64Base))
4881 {
4882 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
4883 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4884 }
4885 }
4886
4887 /* NP */
4888 if (!Desc.Legacy.Gen.u1Present)
4889 {
4890 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
4891 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
4892 }
4893
4894 /* Nested-guest SVM intercept. */
4895 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
4896 {
4897 Log(("lldt: Guest intercept -> #VMEXIT\n"));
4898 IEM_SVM_UPDATE_NRIP(pVCpu);
4899 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
4900 }
4901
4902 /*
4903 * It checks out alright, update the registers.
4904 */
4905/** @todo check if the actual value is loaded or if the RPL is dropped */
4906 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
4907 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
4908 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4909 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4910 pVCpu->cpum.GstCtx.ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
4911 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
4912
4913 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4914 return VINF_SUCCESS;
4915}
4916
4917
4918/**
4919 * Implements sldt GReg
4920 *
4921 * @param iGReg The general register to store the CRx value in.
4922 * @param enmEffOpSize The operand size.
4923 */
4924IEM_CIMPL_DEF_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
4925{
4926 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
4927 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
4928 {
4929 Log(("sldt: Guest intercept -> VM-exit\n"));
4930 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_SLDT, cbInstr);
4931 }
4932
4933 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
4934
4935 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4936 switch (enmEffOpSize)
4937 {
4938 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4939 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4940 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
4941 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4942 }
4943 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4944 return VINF_SUCCESS;
4945}
4946
4947
4948/**
4949 * Implements sldt mem.
4950 *
4951 * @param iGReg The general register to store the CRx value in.
4952 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
4953 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
4954 */
4955IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
4956{
4957 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
4958
4959 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4960 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel);
4961 if (rcStrict == VINF_SUCCESS)
4962 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4963 return rcStrict;
4964}
4965
4966
4967/**
4968 * Implements ltr.
4969 *
4970 * @param uNewTr The new TSS selector value.
4971 */
4972IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
4973{
4974 /*
4975 * Check preconditions.
4976 */
4977 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4978 {
4979 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
4980 return iemRaiseUndefinedOpcode(pVCpu);
4981 }
4982 if (pVCpu->iem.s.uCpl != 0)
4983 {
4984 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
4985 return iemRaiseGeneralProtectionFault0(pVCpu);
4986 }
4987 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
4988 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
4989 {
4990 Log(("ltr: Guest intercept -> VM-exit\n"));
4991 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LTR, cbInstr);
4992 }
4993 if (uNewTr & X86_SEL_LDT)
4994 {
4995 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
4996 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
4997 }
4998 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
4999 {
5000 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
5001 return iemRaiseGeneralProtectionFault0(pVCpu);
5002 }
5003 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
5004 {
5005 Log(("ltr: Guest intercept -> #VMEXIT\n"));
5006 IEM_SVM_UPDATE_NRIP(pVCpu);
5007 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5008 }
5009
5010 /*
5011 * Read the descriptor.
5012 */
5013 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_TR);
5014 IEMSELDESC Desc;
5015 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
5016 if (rcStrict != VINF_SUCCESS)
5017 return rcStrict;
5018
5019 /* Check GPs first. */
5020 if (Desc.Legacy.Gen.u1DescType)
5021 {
5022 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5023 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5024 }
5025 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
5026 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
5027 || IEM_IS_LONG_MODE(pVCpu)) )
5028 {
5029 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5030 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5031 }
5032 uint64_t u64Base;
5033 if (!IEM_IS_LONG_MODE(pVCpu))
5034 u64Base = X86DESC_BASE(&Desc.Legacy);
5035 else
5036 {
5037 if (Desc.Long.Gen.u5Zeros)
5038 {
5039 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
5040 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5041 }
5042
5043 u64Base = X86DESC64_BASE(&Desc.Long);
5044 if (!IEM_IS_CANONICAL(u64Base))
5045 {
5046 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5047 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5048 }
5049 }
5050
5051 /* NP */
5052 if (!Desc.Legacy.Gen.u1Present)
5053 {
5054 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5055 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5056 }
5057
5058 /*
5059 * Set it busy.
5060 * Note! Intel says this should lock down the whole descriptor, but we'll
5061 * restrict our selves to 32-bit for now due to lack of inline
5062 * assembly and such.
5063 */
5064 void *pvDesc;
5065 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pVCpu->cpum.GstCtx.gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL), IEM_ACCESS_DATA_RW);
5066 if (rcStrict != VINF_SUCCESS)
5067 return rcStrict;
5068 switch ((uintptr_t)pvDesc & 3)
5069 {
5070 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5071 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5072 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5073 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5074 }
5075 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5076 if (rcStrict != VINF_SUCCESS)
5077 return rcStrict;
5078 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5079
5080 /*
5081 * It checks out alright, update the registers.
5082 */
5083/** @todo check if the actual value is loaded or if the RPL is dropped */
5084 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5085 pVCpu->cpum.GstCtx.tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5086 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5087 pVCpu->cpum.GstCtx.tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5088 pVCpu->cpum.GstCtx.tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5089 pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
5090
5091 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5092 return VINF_SUCCESS;
5093}
5094
5095
5096/**
5097 * Implements str GReg
5098 *
5099 * @param iGReg The general register to store the CRx value in.
5100 * @param enmEffOpSize The operand size.
5101 */
5102IEM_CIMPL_DEF_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5103{
5104 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5105 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5106 {
5107 Log(("str_reg: Guest intercept -> VM-exit\n"));
5108 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5109 }
5110
5111 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5112
5113 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5114 switch (enmEffOpSize)
5115 {
5116 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5117 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5118 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5119 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5120 }
5121 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5122 return VINF_SUCCESS;
5123}
5124
5125
5126/**
5127 * Implements str mem.
5128 *
5129 * @param iGReg The general register to store the CRx value in.
5130 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5131 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5132 */
5133IEM_CIMPL_DEF_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5134{
5135 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5136 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5137 {
5138 Log(("str_mem: Guest intercept -> VM-exit\n"));
5139 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5140 }
5141
5142 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5143
5144 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5145 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel);
5146 if (rcStrict == VINF_SUCCESS)
5147 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5148 return rcStrict;
5149}
5150
5151
5152/**
5153 * Implements mov GReg,CRx.
5154 *
5155 * @param iGReg The general register to store the CRx value in.
5156 * @param iCrReg The CRx register to read (valid).
5157 */
5158IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5159{
5160 if (pVCpu->iem.s.uCpl != 0)
5161 return iemRaiseGeneralProtectionFault0(pVCpu);
5162 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5163
5164 if (IEM_SVM_IS_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5165 {
5166 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5167 IEM_SVM_UPDATE_NRIP(pVCpu);
5168 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5169 }
5170
5171 /* Read it. */
5172 uint64_t crX;
5173 switch (iCrReg)
5174 {
5175 case 0:
5176 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5177 crX = pVCpu->cpum.GstCtx.cr0;
5178 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5179 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5180 break;
5181 case 2:
5182 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR2);
5183 crX = pVCpu->cpum.GstCtx.cr2;
5184 break;
5185 case 3:
5186 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5187 crX = pVCpu->cpum.GstCtx.cr3;
5188 break;
5189 case 4:
5190 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5191 crX = pVCpu->cpum.GstCtx.cr4;
5192 break;
5193 case 8:
5194 {
5195 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5196#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5197 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5198 {
5199 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr8(pVCpu, iGReg, cbInstr);
5200 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5201 return rcStrict;
5202
5203 /*
5204 * If the Mov-from-CR8 doesn't cause a VM-exit, bits 7:4 of the VTPR is copied
5205 * to bits 0:3 of the destination operand. Bits 63:4 of the destination operand
5206 * are cleared.
5207 *
5208 * See Intel Spec. 29.3 "Virtualizing CR8-based TPR Accesses"
5209 */
5210 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
5211 {
5212 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5213 crX = (uVTpr >> 4) & 0xf;
5214 break;
5215 }
5216 }
5217#endif
5218#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5219 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5220 {
5221 PCSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5222 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5223 {
5224 crX = pVmcbCtrl->IntCtrl.n.u8VTPR & 0xf;
5225 break;
5226 }
5227 }
5228#endif
5229 uint8_t uTpr;
5230 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5231 if (RT_SUCCESS(rc))
5232 crX = uTpr >> 4;
5233 else
5234 crX = 0;
5235 break;
5236 }
5237 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5238 }
5239
5240#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5241 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5242 {
5243 switch (iCrReg)
5244 {
5245 case 0:
5246 case 4:
5247 {
5248 /* CR0/CR4 reads are subject to masking when in VMX non-root mode. */
5249 crX = iemVmxMaskCr0CR4(pVCpu, iCrReg, crX);
5250 break;
5251 }
5252
5253 case 3:
5254 {
5255 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr3(pVCpu, iGReg, cbInstr);
5256 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5257 return rcStrict;
5258 break;
5259 }
5260 }
5261 }
5262#endif
5263
5264 /* Store it. */
5265 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5266 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5267 else
5268 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5269
5270 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5271 return VINF_SUCCESS;
5272}
5273
5274
5275/**
5276 * Implements smsw GReg
5277 *
5278 * @param iGReg The general register to store the CRx value in.
5279 * @param enmEffOpSize The operand size.
5280 */
5281IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5282{
5283 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5284
5285 switch (enmEffOpSize)
5286 {
5287 case IEMMODE_16BIT:
5288 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5289 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0;
5290 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5291 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xffe0;
5292 else
5293 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xfff0;
5294 break;
5295
5296 case IEMMODE_32BIT:
5297 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)pVCpu->cpum.GstCtx.cr0;
5298 break;
5299
5300 case IEMMODE_64BIT:
5301 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.cr0;
5302 break;
5303
5304 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5305 }
5306
5307 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5308 return VINF_SUCCESS;
5309}
5310
5311
5312/**
5313 * Implements smsw mem.
5314 *
5315 * @param iGReg The general register to store the CR0 value in.
5316 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5317 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5318 */
5319IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5320{
5321 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5322
5323 uint16_t u16Value;
5324 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5325 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0;
5326 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5327 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xffe0;
5328 else
5329 u16Value = (uint16_t)pVCpu->cpum.GstCtx.cr0 | 0xfff0;
5330
5331 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value);
5332 if (rcStrict == VINF_SUCCESS)
5333 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5334 return rcStrict;
5335}
5336
5337
5338/**
5339 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5340 *
5341 * @param iCrReg The CRx register to write (valid).
5342 * @param uNewCrX The new value.
5343 * @param enmAccessCrx The instruction that caused the CrX load.
5344 * @param iGReg The general register in case of a 'mov CRx,GReg'
5345 * instruction.
5346 */
5347IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5348{
5349 VBOXSTRICTRC rcStrict;
5350 int rc;
5351#ifndef VBOX_WITH_NESTED_HWVIRT_SVM
5352 RT_NOREF2(iGReg, enmAccessCrX);
5353#endif
5354
5355 /*
5356 * Try store it.
5357 * Unfortunately, CPUM only does a tiny bit of the work.
5358 */
5359 switch (iCrReg)
5360 {
5361 case 0:
5362 {
5363 /*
5364 * Perform checks.
5365 */
5366 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5367
5368 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr0;
5369 uint32_t const fValid = X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS
5370 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM
5371 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG;
5372
5373 /* ET is hardcoded on 486 and later. */
5374 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5375 uNewCrX |= X86_CR0_ET;
5376 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5377 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5378 {
5379 uNewCrX &= fValid;
5380 uNewCrX |= X86_CR0_ET;
5381 }
5382 else
5383 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5384
5385 /* Check for reserved bits. */
5386 if (uNewCrX & ~(uint64_t)fValid)
5387 {
5388 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5389 return iemRaiseGeneralProtectionFault0(pVCpu);
5390 }
5391
5392 /* Check for invalid combinations. */
5393 if ( (uNewCrX & X86_CR0_PG)
5394 && !(uNewCrX & X86_CR0_PE) )
5395 {
5396 Log(("Trying to set CR0.PG without CR0.PE\n"));
5397 return iemRaiseGeneralProtectionFault0(pVCpu);
5398 }
5399
5400 if ( !(uNewCrX & X86_CR0_CD)
5401 && (uNewCrX & X86_CR0_NW) )
5402 {
5403 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5404 return iemRaiseGeneralProtectionFault0(pVCpu);
5405 }
5406
5407 if ( !(uNewCrX & X86_CR0_PG)
5408 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE))
5409 {
5410 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5411 return iemRaiseGeneralProtectionFault0(pVCpu);
5412 }
5413
5414 /* Long mode consistency checks. */
5415 if ( (uNewCrX & X86_CR0_PG)
5416 && !(uOldCrX & X86_CR0_PG)
5417 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5418 {
5419 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE))
5420 {
5421 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5422 return iemRaiseGeneralProtectionFault0(pVCpu);
5423 }
5424 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long)
5425 {
5426 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5427 return iemRaiseGeneralProtectionFault0(pVCpu);
5428 }
5429 }
5430
5431 /* Check for bits that must remain set or cleared in VMX operation,
5432 see Intel spec. 23.8 "Restrictions on VMX operation". */
5433 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5434 {
5435 uint32_t const uCr0Fixed0 = CPUMGetGuestIa32VmxCr0Fixed0(pVCpu);
5436 if ((uNewCrX & uCr0Fixed0) != uCr0Fixed0)
5437 {
5438 Log(("Trying to clear reserved CR0 bits in VMX operation: NewCr0=%#llx MB1=%#llx\n", uNewCrX, uCr0Fixed0));
5439 return iemRaiseGeneralProtectionFault0(pVCpu);
5440 }
5441
5442 uint32_t const uCr0Fixed1 = CPUMGetGuestIa32VmxCr0Fixed1(pVCpu);
5443 if (uNewCrX & ~uCr0Fixed1)
5444 {
5445 Log(("Trying to set reserved CR0 bits in VMX operation: NewCr0=%#llx MB0=%#llx\n", uNewCrX, uCr0Fixed1));
5446 return iemRaiseGeneralProtectionFault0(pVCpu);
5447 }
5448 }
5449
5450 /** @todo check reserved PDPTR bits as AMD states. */
5451
5452 /*
5453 * SVM nested-guest CR0 write intercepts.
5454 */
5455 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5456 {
5457 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5458 IEM_SVM_UPDATE_NRIP(pVCpu);
5459 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5460 }
5461 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5462 {
5463 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5464 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5465 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5466 {
5467 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5468 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg));
5469 IEM_SVM_UPDATE_NRIP(pVCpu);
5470 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg);
5471 }
5472 }
5473
5474 /*
5475 * Change CR0.
5476 */
5477 CPUMSetGuestCR0(pVCpu, uNewCrX);
5478 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCrX);
5479
5480 /*
5481 * Change EFER.LMA if entering or leaving long mode.
5482 */
5483 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5484 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5485 {
5486 uint64_t NewEFER = pVCpu->cpum.GstCtx.msrEFER;
5487 if (uNewCrX & X86_CR0_PG)
5488 NewEFER |= MSR_K6_EFER_LMA;
5489 else
5490 NewEFER &= ~MSR_K6_EFER_LMA;
5491
5492 CPUMSetGuestEFER(pVCpu, NewEFER);
5493 Assert(pVCpu->cpum.GstCtx.msrEFER == NewEFER);
5494 }
5495
5496 /*
5497 * Inform PGM.
5498 */
5499 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
5500 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)) )
5501 {
5502 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5503 AssertRCReturn(rc, rc);
5504 /* ignore informational status codes */
5505 }
5506 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
5507
5508#ifdef IN_RC
5509 /* Return to ring-3 for rescheduling if WP or AM changes. */
5510 if ( rcStrict == VINF_SUCCESS
5511 && ( (uNewCrX & (X86_CR0_WP | X86_CR0_AM))
5512 != (uOldCrX & (X86_CR0_WP | X86_CR0_AM))) )
5513 rcStrict = VINF_EM_RESCHEDULE;
5514#endif
5515 break;
5516 }
5517
5518 /*
5519 * CR2 can be changed without any restrictions.
5520 */
5521 case 2:
5522 {
5523 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5524 {
5525 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5526 IEM_SVM_UPDATE_NRIP(pVCpu);
5527 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5528 }
5529 pVCpu->cpum.GstCtx.cr2 = uNewCrX;
5530 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_CR2;
5531 rcStrict = VINF_SUCCESS;
5532 break;
5533 }
5534
5535 /*
5536 * CR3 is relatively simple, although AMD and Intel have different
5537 * accounts of how setting reserved bits are handled. We take intel's
5538 * word for the lower bits and AMD's for the high bits (63:52). The
5539 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5540 * on this.
5541 */
5542 /** @todo Testcase: Setting reserved bits in CR3, especially before
5543 * enabling paging. */
5544 case 3:
5545 {
5546 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5547
5548 /* Bit 63 being clear in the source operand with PCIDE indicates no invalidations are required. */
5549 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
5550 && (uNewCrX & RT_BIT_64(63)))
5551 {
5552 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
5553 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
5554 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
5555 * Paging-Structure Caches". */
5556 uNewCrX &= ~RT_BIT_64(63);
5557 }
5558
5559 /* Check / mask the value. */
5560 if (uNewCrX & UINT64_C(0xfff0000000000000))
5561 {
5562 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
5563 return iemRaiseGeneralProtectionFault0(pVCpu);
5564 }
5565
5566 uint64_t fValid;
5567 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
5568 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME))
5569 fValid = UINT64_C(0x000fffffffffffff);
5570 else
5571 fValid = UINT64_C(0xffffffff);
5572 if (uNewCrX & ~fValid)
5573 {
5574 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
5575 uNewCrX, uNewCrX & ~fValid));
5576 uNewCrX &= fValid;
5577 }
5578
5579 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
5580 {
5581 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5582 IEM_SVM_UPDATE_NRIP(pVCpu);
5583 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
5584 }
5585
5586 /** @todo If we're in PAE mode we should check the PDPTRs for
5587 * invalid bits. */
5588
5589 /* Make the change. */
5590 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
5591 AssertRCSuccessReturn(rc, rc);
5592
5593 /* Inform PGM. */
5594 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
5595 {
5596 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PGE));
5597 AssertRCReturn(rc, rc);
5598 /* ignore informational status codes */
5599 }
5600 rcStrict = VINF_SUCCESS;
5601 break;
5602 }
5603
5604 /*
5605 * CR4 is a bit more tedious as there are bits which cannot be cleared
5606 * under some circumstances and such.
5607 */
5608 case 4:
5609 {
5610 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5611 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr4;
5612
5613 /** @todo Shouldn't this look at the guest CPUID bits to determine
5614 * valid bits? e.g. if guest CPUID doesn't allow X86_CR4_OSXMMEEXCPT, we
5615 * should #GP(0). */
5616 /* reserved bits */
5617 uint32_t fValid = X86_CR4_VME | X86_CR4_PVI
5618 | X86_CR4_TSD | X86_CR4_DE
5619 | X86_CR4_PSE | X86_CR4_PAE
5620 | X86_CR4_MCE | X86_CR4_PGE
5621 | X86_CR4_PCE | X86_CR4_OSFXSR
5622 | X86_CR4_OSXMMEEXCPT;
5623 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVmx)
5624 fValid |= X86_CR4_VMXE;
5625 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fXSaveRstor)
5626 fValid |= X86_CR4_OSXSAVE;
5627 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPcid)
5628 fValid |= X86_CR4_PCIDE;
5629 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase)
5630 fValid |= X86_CR4_FSGSBASE;
5631 if (uNewCrX & ~(uint64_t)fValid)
5632 {
5633 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5634 return iemRaiseGeneralProtectionFault0(pVCpu);
5635 }
5636
5637 bool const fPcide = ((uNewCrX ^ uOldCrX) & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
5638 bool const fLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
5639
5640 /* PCIDE check. */
5641 if ( fPcide
5642 && ( !fLongMode
5643 || (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))))
5644 {
5645 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))));
5646 return iemRaiseGeneralProtectionFault0(pVCpu);
5647 }
5648
5649 /* PAE check. */
5650 if ( fLongMode
5651 && (uOldCrX & X86_CR4_PAE)
5652 && !(uNewCrX & X86_CR4_PAE))
5653 {
5654 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
5655 return iemRaiseGeneralProtectionFault0(pVCpu);
5656 }
5657
5658 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
5659 {
5660 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5661 IEM_SVM_UPDATE_NRIP(pVCpu);
5662 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
5663 }
5664
5665 /* Check for bits that must remain set or cleared in VMX operation,
5666 see Intel spec. 23.8 "Restrictions on VMX operation". */
5667 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5668 {
5669 uint32_t const uCr4Fixed0 = CPUMGetGuestIa32VmxCr4Fixed0(pVCpu);
5670 if ((uNewCrX & uCr4Fixed0) != uCr4Fixed0)
5671 {
5672 Log(("Trying to clear reserved CR4 bits in VMX operation: NewCr4=%#llx MB1=%#llx\n", uNewCrX, uCr4Fixed0));
5673 return iemRaiseGeneralProtectionFault0(pVCpu);
5674 }
5675
5676 uint32_t const uCr4Fixed1 = CPUMGetGuestIa32VmxCr4Fixed1(pVCpu);
5677 if (uNewCrX & ~uCr4Fixed1)
5678 {
5679 Log(("Trying to set reserved CR4 bits in VMX operation: NewCr4=%#llx MB0=%#llx\n", uNewCrX, uCr4Fixed1));
5680 return iemRaiseGeneralProtectionFault0(pVCpu);
5681 }
5682 }
5683
5684 /*
5685 * Change it.
5686 */
5687 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
5688 AssertRCSuccessReturn(rc, rc);
5689 Assert(pVCpu->cpum.GstCtx.cr4 == uNewCrX);
5690
5691 /*
5692 * Notify SELM and PGM.
5693 */
5694 /* SELM - VME may change things wrt to the TSS shadowing. */
5695 if ((uNewCrX ^ uOldCrX) & X86_CR4_VME)
5696 {
5697 Log(("iemCImpl_load_CrX: VME %d -> %d => Setting VMCPU_FF_SELM_SYNC_TSS\n",
5698 RT_BOOL(uOldCrX & X86_CR4_VME), RT_BOOL(uNewCrX & X86_CR4_VME) ));
5699#ifdef VBOX_WITH_RAW_MODE
5700 if (VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)))
5701 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
5702#endif
5703 }
5704
5705 /* PGM - flushing and mode. */
5706 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
5707 {
5708 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5709 AssertRCReturn(rc, rc);
5710 /* ignore informational status codes */
5711 }
5712 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
5713 break;
5714 }
5715
5716 /*
5717 * CR8 maps to the APIC TPR.
5718 */
5719 case 8:
5720 {
5721 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5722 if (uNewCrX & ~(uint64_t)0xf)
5723 {
5724 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
5725 return iemRaiseGeneralProtectionFault0(pVCpu);
5726 }
5727
5728#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5729 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5730 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
5731 {
5732 /*
5733 * If the Mov-to-CR8 doesn't cause a VM-exit, bits 0:3 of the source operand
5734 * is copied to bits 7:4 of the VTPR. Bits 0:3 and bits 31:8 of the VTPR are
5735 * cleared. Following this the processor performs TPR virtualization.
5736 *
5737 * See Intel Spec. 29.3 "Virtualizing CR8-based TPR Accesses"
5738 */
5739 uint32_t const uVTpr = (uNewCrX & 0xf) << 4;
5740 iemVmxVirtApicWriteRaw32(pVCpu, uVTpr, XAPIC_OFF_TPR);
5741 rcStrict = iemVmxVmexitTprVirtualization(pVCpu, cbInstr);
5742 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5743 return rcStrict;
5744 rcStrict = VINF_SUCCESS;
5745 break;
5746 }
5747#endif
5748
5749#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5750 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5751 {
5752 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
5753 {
5754 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5755 IEM_SVM_UPDATE_NRIP(pVCpu);
5756 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
5757 }
5758
5759 PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
5760 pVmcbCtrl->IntCtrl.n.u8VTPR = uNewCrX;
5761 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5762 {
5763 rcStrict = VINF_SUCCESS;
5764 break;
5765 }
5766 }
5767#endif
5768 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
5769 APICSetTpr(pVCpu, u8Tpr);
5770 rcStrict = VINF_SUCCESS;
5771 break;
5772 }
5773
5774 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5775 }
5776
5777 /*
5778 * Advance the RIP on success.
5779 */
5780 if (RT_SUCCESS(rcStrict))
5781 {
5782 if (rcStrict != VINF_SUCCESS)
5783 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
5784 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5785 }
5786
5787 return rcStrict;
5788}
5789
5790
5791/**
5792 * Implements mov CRx,GReg.
5793 *
5794 * @param iCrReg The CRx register to write (valid).
5795 * @param iGReg The general register to load the CRx value from.
5796 */
5797IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
5798{
5799 if (pVCpu->iem.s.uCpl != 0)
5800 return iemRaiseGeneralProtectionFault0(pVCpu);
5801 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5802
5803 /*
5804 * Read the new value from the source register and call common worker.
5805 */
5806 uint64_t uNewCrX;
5807 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5808 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
5809 else
5810 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
5811
5812#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5813 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5814 {
5815 VBOXSTRICTRC rcStrict = VINF_VMX_INTERCEPT_NOT_ACTIVE;
5816 switch (iCrReg)
5817 {
5818 case 0:
5819 case 4: rcStrict = iemVmxVmexitInstrMovToCr0Cr4(pVCpu, iCrReg, &uNewCrX, iGReg, cbInstr); break;
5820 case 3: rcStrict = iemVmxVmexitInstrMovToCr3(pVCpu, uNewCrX, iGReg, cbInstr); break;
5821 case 8: rcStrict = iemVmxVmexitInstrMovToCr8(pVCpu, iGReg, cbInstr); break;
5822 }
5823 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5824 return rcStrict;
5825 }
5826#endif
5827
5828 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
5829}
5830
5831
5832/**
5833 * Implements 'LMSW r/m16'
5834 *
5835 * @param u16NewMsw The new value.
5836 * @param GCPtrEffDst The guest-linear address of the source operand in case
5837 * of a memory operand. For register operand, pass
5838 * NIL_RTGCPTR.
5839 */
5840IEM_CIMPL_DEF_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst)
5841{
5842 if (pVCpu->iem.s.uCpl != 0)
5843 return iemRaiseGeneralProtectionFault0(pVCpu);
5844 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5845 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5846
5847#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5848 /* Check nested-guest VMX intercept and get updated MSW if there's no VM-exit. */
5849 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5850 {
5851 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrLmsw(pVCpu, pVCpu->cpum.GstCtx.cr0, &u16NewMsw, GCPtrEffDst, cbInstr);
5852 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5853 return rcStrict;
5854 }
5855#else
5856 RT_NOREF_PV(GCPtrEffDst);
5857#endif
5858
5859 /*
5860 * Compose the new CR0 value and call common worker.
5861 */
5862 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5863 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
5864 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
5865}
5866
5867
5868/**
5869 * Implements 'CLTS'.
5870 */
5871IEM_CIMPL_DEF_0(iemCImpl_clts)
5872{
5873 if (pVCpu->iem.s.uCpl != 0)
5874 return iemRaiseGeneralProtectionFault0(pVCpu);
5875
5876 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5877 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0;
5878 uNewCr0 &= ~X86_CR0_TS;
5879
5880#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5881 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5882 {
5883 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrClts(pVCpu, cbInstr);
5884 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
5885 uNewCr0 |= (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS);
5886 else if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5887 return rcStrict;
5888 }
5889#endif
5890
5891 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
5892}
5893
5894
5895/**
5896 * Implements mov GReg,DRx.
5897 *
5898 * @param iGReg The general register to store the DRx value in.
5899 * @param iDrReg The DRx register to read (0-7).
5900 */
5901IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
5902{
5903 /*
5904 * Check preconditions.
5905 */
5906
5907 /* Raise GPs. */
5908 if (pVCpu->iem.s.uCpl != 0)
5909 return iemRaiseGeneralProtectionFault0(pVCpu);
5910 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5911 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
5912
5913 if ( (iDrReg == 4 || iDrReg == 5)
5914 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
5915 {
5916 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
5917 return iemRaiseGeneralProtectionFault0(pVCpu);
5918 }
5919
5920 /* Raise #DB if general access detect is enabled. */
5921 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
5922 {
5923 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
5924 return iemRaiseDebugException(pVCpu);
5925 }
5926
5927 /*
5928 * Read the debug register and store it in the specified general register.
5929 */
5930 uint64_t drX;
5931 switch (iDrReg)
5932 {
5933 case 0:
5934 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5935 drX = pVCpu->cpum.GstCtx.dr[0];
5936 break;
5937 case 1:
5938 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5939 drX = pVCpu->cpum.GstCtx.dr[1];
5940 break;
5941 case 2:
5942 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5943 drX = pVCpu->cpum.GstCtx.dr[2];
5944 break;
5945 case 3:
5946 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
5947 drX = pVCpu->cpum.GstCtx.dr[3];
5948 break;
5949 case 6:
5950 case 4:
5951 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
5952 drX = pVCpu->cpum.GstCtx.dr[6];
5953 drX |= X86_DR6_RA1_MASK;
5954 drX &= ~X86_DR6_RAZ_MASK;
5955 break;
5956 case 7:
5957 case 5:
5958 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
5959 drX = pVCpu->cpum.GstCtx.dr[7];
5960 drX |=X86_DR7_RA1_MASK;
5961 drX &= ~X86_DR7_RAZ_MASK;
5962 break;
5963 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5964 }
5965
5966 /** @todo SVM nested-guest intercept for DR8-DR15? */
5967 /*
5968 * Check for any SVM nested-guest intercepts for the DRx read.
5969 */
5970 if (IEM_SVM_IS_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
5971 {
5972 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
5973 IEM_SVM_UPDATE_NRIP(pVCpu);
5974 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
5975 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
5976 }
5977
5978 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5979 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
5980 else
5981 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
5982
5983 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5984 return VINF_SUCCESS;
5985}
5986
5987
5988/**
5989 * Implements mov DRx,GReg.
5990 *
5991 * @param iDrReg The DRx register to write (valid).
5992 * @param iGReg The general register to load the DRx value from.
5993 */
5994IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
5995{
5996 /*
5997 * Check preconditions.
5998 */
5999 if (pVCpu->iem.s.uCpl != 0)
6000 return iemRaiseGeneralProtectionFault0(pVCpu);
6001 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6002 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
6003
6004 if (iDrReg == 4 || iDrReg == 5)
6005 {
6006 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
6007 {
6008 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
6009 return iemRaiseGeneralProtectionFault0(pVCpu);
6010 }
6011 iDrReg += 2;
6012 }
6013
6014 /* Raise #DB if general access detect is enabled. */
6015 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
6016 * \#GP? */
6017 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6018 {
6019 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
6020 return iemRaiseDebugException(pVCpu);
6021 }
6022
6023 /*
6024 * Read the new value from the source register.
6025 */
6026 uint64_t uNewDrX;
6027 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6028 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
6029 else
6030 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
6031
6032 /*
6033 * Adjust it.
6034 */
6035 switch (iDrReg)
6036 {
6037 case 0:
6038 case 1:
6039 case 2:
6040 case 3:
6041 /* nothing to adjust */
6042 break;
6043
6044 case 6:
6045 if (uNewDrX & X86_DR6_MBZ_MASK)
6046 {
6047 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6048 return iemRaiseGeneralProtectionFault0(pVCpu);
6049 }
6050 uNewDrX |= X86_DR6_RA1_MASK;
6051 uNewDrX &= ~X86_DR6_RAZ_MASK;
6052 break;
6053
6054 case 7:
6055 if (uNewDrX & X86_DR7_MBZ_MASK)
6056 {
6057 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6058 return iemRaiseGeneralProtectionFault0(pVCpu);
6059 }
6060 uNewDrX |= X86_DR7_RA1_MASK;
6061 uNewDrX &= ~X86_DR7_RAZ_MASK;
6062 break;
6063
6064 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6065 }
6066
6067 /** @todo SVM nested-guest intercept for DR8-DR15? */
6068 /*
6069 * Check for any SVM nested-guest intercepts for the DRx write.
6070 */
6071 if (IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
6072 {
6073 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
6074 IEM_SVM_UPDATE_NRIP(pVCpu);
6075 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
6076 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6077 }
6078
6079 /*
6080 * Do the actual setting.
6081 */
6082 if (iDrReg < 4)
6083 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6084 else if (iDrReg == 6)
6085 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6086
6087 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
6088 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
6089
6090 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6091 return VINF_SUCCESS;
6092}
6093
6094
6095/**
6096 * Implements 'INVLPG m'.
6097 *
6098 * @param GCPtrPage The effective address of the page to invalidate.
6099 * @remarks Updates the RIP.
6100 */
6101IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
6102{
6103 /* ring-0 only. */
6104 if (pVCpu->iem.s.uCpl != 0)
6105 return iemRaiseGeneralProtectionFault0(pVCpu);
6106 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6107 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6108
6109#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6110 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6111 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6112 {
6113 Log(("invlpg: Guest intercept (%RGp) -> VM-exit\n", GCPtrPage));
6114 return iemVmxVmexitInstrInvlpg(pVCpu, GCPtrPage, cbInstr);
6115 }
6116#endif
6117
6118 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
6119 {
6120 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
6121 IEM_SVM_UPDATE_NRIP(pVCpu);
6122 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG,
6123 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
6124 }
6125
6126 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
6127 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6128
6129 if (rc == VINF_SUCCESS)
6130 return VINF_SUCCESS;
6131 if (rc == VINF_PGM_SYNC_CR3)
6132 return iemSetPassUpStatus(pVCpu, rc);
6133
6134 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
6135 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
6136 return rc;
6137}
6138
6139
6140/**
6141 * Implements INVPCID.
6142 *
6143 * @param iEffSeg The segment of the invpcid descriptor.
6144 * @param GCPtrInvpcidDesc The address of invpcid descriptor.
6145 * @param uInvpcidType The invalidation type.
6146 * @remarks Updates the RIP.
6147 */
6148IEM_CIMPL_DEF_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint8_t, uInvpcidType)
6149{
6150 /*
6151 * Check preconditions.
6152 */
6153 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
6154 return iemRaiseUndefinedOpcode(pVCpu);
6155
6156 /* When in VMX non-root mode and INVPCID is not enabled, it results in #UD. */
6157 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6158 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_INVPCID))
6159 {
6160 Log(("invpcid: Not enabled for nested-guest execution -> #UD\n"));
6161 return iemRaiseUndefinedOpcode(pVCpu);
6162 }
6163
6164 if (pVCpu->iem.s.uCpl != 0)
6165 {
6166 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
6167 return iemRaiseGeneralProtectionFault0(pVCpu);
6168 }
6169
6170 if (IEM_IS_V86_MODE(pVCpu))
6171 {
6172 Log(("invpcid: v8086 mode -> #GP(0)\n"));
6173 return iemRaiseGeneralProtectionFault0(pVCpu);
6174 }
6175
6176 /*
6177 * Check nested-guest intercept.
6178 *
6179 * INVPCID causes a VM-exit if "enable INVPCID" and "INVLPG exiting" are
6180 * both set. We have already checked the former earlier in this function.
6181 *
6182 * CPL checks take priority over VM-exit.
6183 * See Intel spec. "25.1.1 Relative Priority of Faults and VM Exits".
6184 */
6185 /** @todo r=ramshankar: NSTVMX: I'm not entirely certain if V86 mode check has
6186 * higher or lower priority than a VM-exit, we assume higher for the time
6187 * being. */
6188 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6189 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6190 {
6191 Log(("invpcid: Guest intercept -> #VM-exit\n"));
6192 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_INVPCID, VMXINSTRID_NONE, cbInstr);
6193 }
6194
6195 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
6196 {
6197 Log(("invpcid: invalid/unrecognized invpcid type %#x -> #GP(0)\n", uInvpcidType));
6198 return iemRaiseGeneralProtectionFault0(pVCpu);
6199 }
6200 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6201
6202 /*
6203 * Fetch the invpcid descriptor from guest memory.
6204 */
6205 RTUINT128U uDesc;
6206 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvpcidDesc);
6207 if (rcStrict == VINF_SUCCESS)
6208 {
6209 /*
6210 * Validate the descriptor.
6211 */
6212 if (uDesc.s.Lo > 0xfff)
6213 {
6214 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
6215 return iemRaiseGeneralProtectionFault0(pVCpu);
6216 }
6217
6218 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
6219 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
6220 uint32_t const uCr4 = pVCpu->cpum.GstCtx.cr4;
6221 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
6222 switch (uInvpcidType)
6223 {
6224 case X86_INVPCID_TYPE_INDV_ADDR:
6225 {
6226 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
6227 {
6228 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
6229 return iemRaiseGeneralProtectionFault0(pVCpu);
6230 }
6231 if ( !(uCr4 & X86_CR4_PCIDE)
6232 && uPcid != 0)
6233 {
6234 Log(("invpcid: invalid pcid %#x\n", uPcid));
6235 return iemRaiseGeneralProtectionFault0(pVCpu);
6236 }
6237
6238 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
6239 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6240 break;
6241 }
6242
6243 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
6244 {
6245 if ( !(uCr4 & X86_CR4_PCIDE)
6246 && uPcid != 0)
6247 {
6248 Log(("invpcid: invalid pcid %#x\n", uPcid));
6249 return iemRaiseGeneralProtectionFault0(pVCpu);
6250 }
6251 /* Invalidate all mappings associated with PCID except global translations. */
6252 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6253 break;
6254 }
6255
6256 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
6257 {
6258 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
6259 break;
6260 }
6261
6262 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
6263 {
6264 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6265 break;
6266 }
6267 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6268 }
6269 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6270 }
6271 return rcStrict;
6272}
6273
6274
6275/**
6276 * Implements INVD.
6277 */
6278IEM_CIMPL_DEF_0(iemCImpl_invd)
6279{
6280 if (pVCpu->iem.s.uCpl != 0)
6281 {
6282 Log(("invd: CPL != 0 -> #GP(0)\n"));
6283 return iemRaiseGeneralProtectionFault0(pVCpu);
6284 }
6285
6286 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
6287
6288 /* We currently take no action here. */
6289 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6290 return VINF_SUCCESS;
6291}
6292
6293
6294/**
6295 * Implements WBINVD.
6296 */
6297IEM_CIMPL_DEF_0(iemCImpl_wbinvd)
6298{
6299 if (pVCpu->iem.s.uCpl != 0)
6300 {
6301 Log(("wbinvd: CPL != 0 -> #GP(0)\n"));
6302 return iemRaiseGeneralProtectionFault0(pVCpu);
6303 }
6304
6305 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
6306
6307 /* We currently take no action here. */
6308 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6309 return VINF_SUCCESS;
6310}
6311
6312
6313/** Opcode 0x0f 0xaa. */
6314IEM_CIMPL_DEF_0(iemCImpl_rsm)
6315{
6316 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6317 NOREF(cbInstr);
6318 return iemRaiseUndefinedOpcode(pVCpu);
6319}
6320
6321
6322/**
6323 * Implements RDTSC.
6324 */
6325IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
6326{
6327 /*
6328 * Check preconditions.
6329 */
6330 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
6331 return iemRaiseUndefinedOpcode(pVCpu);
6332
6333 if (pVCpu->iem.s.uCpl != 0)
6334 {
6335 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6336 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6337 {
6338 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6339 return iemRaiseGeneralProtectionFault0(pVCpu);
6340 }
6341 }
6342
6343 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6344 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6345 {
6346 Log(("rdtsc: Guest intercept -> VM-exit\n"));
6347 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSC, cbInstr);
6348 }
6349
6350 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
6351 {
6352 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
6353 IEM_SVM_UPDATE_NRIP(pVCpu);
6354 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6355 }
6356
6357 /*
6358 * Do the job.
6359 */
6360 uint64_t uTicks = TMCpuTickGet(pVCpu);
6361#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6362 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6363#endif
6364 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6365 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6366 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
6367 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6368 return VINF_SUCCESS;
6369}
6370
6371
6372/**
6373 * Implements RDTSC.
6374 */
6375IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
6376{
6377 /*
6378 * Check preconditions.
6379 */
6380 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
6381 return iemRaiseUndefinedOpcode(pVCpu);
6382
6383 if (pVCpu->iem.s.uCpl != 0)
6384 {
6385 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6386 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6387 {
6388 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6389 return iemRaiseGeneralProtectionFault0(pVCpu);
6390 }
6391 }
6392
6393 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6394 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_RDTSCP))
6395 {
6396 Log(("rdtscp: Guest intercept -> VM-exit\n"));
6397 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSCP, cbInstr);
6398 }
6399 else if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
6400 {
6401 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
6402 IEM_SVM_UPDATE_NRIP(pVCpu);
6403 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6404 }
6405
6406 /*
6407 * Do the job.
6408 * Query the MSR first in case of trips to ring-3.
6409 */
6410 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
6411 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pVCpu->cpum.GstCtx.rcx);
6412 if (rcStrict == VINF_SUCCESS)
6413 {
6414 /* Low dword of the TSC_AUX msr only. */
6415 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
6416
6417 uint64_t uTicks = TMCpuTickGet(pVCpu);
6418#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6419 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6420#endif
6421 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6422 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6423 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
6424 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6425 }
6426 return rcStrict;
6427}
6428
6429
6430/**
6431 * Implements RDPMC.
6432 */
6433IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
6434{
6435 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6436
6437 if ( pVCpu->iem.s.uCpl != 0
6438 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCE))
6439 return iemRaiseGeneralProtectionFault0(pVCpu);
6440
6441 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6442 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDPMC_EXIT))
6443 {
6444 Log(("rdpmc: Guest intercept -> VM-exit\n"));
6445 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDPMC, cbInstr);
6446 }
6447
6448 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
6449 {
6450 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
6451 IEM_SVM_UPDATE_NRIP(pVCpu);
6452 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6453 }
6454
6455 /** @todo Emulate performance counters, for now just return 0. */
6456 pVCpu->cpum.GstCtx.rax = 0;
6457 pVCpu->cpum.GstCtx.rdx = 0;
6458 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
6459 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
6460 * ecx but see @bugref{3472}! */
6461
6462 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6463 return VINF_SUCCESS;
6464}
6465
6466
6467/**
6468 * Implements RDMSR.
6469 */
6470IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
6471{
6472 /*
6473 * Check preconditions.
6474 */
6475 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6476 return iemRaiseUndefinedOpcode(pVCpu);
6477 if (pVCpu->iem.s.uCpl != 0)
6478 return iemRaiseGeneralProtectionFault0(pVCpu);
6479
6480 /*
6481 * Check nested-guest intercepts.
6482 */
6483#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6484 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6485 {
6486 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_RDMSR, pVCpu->cpum.GstCtx.ecx))
6487 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDMSR, cbInstr);
6488
6489 /** @todo NSTVMX: Handle other x2APIC MSRs in VMX non-root mode. Perhaps having a
6490 * dedicated virtual-APIC device might be better... */
6491 if ( pVCpu->cpum.GstCtx.ecx == MSR_IA32_X2APIC_TPR
6492 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
6493 {
6494 uint32_t const uVTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
6495 pVCpu->cpum.GstCtx.rax = uVTpr;
6496 pVCpu->cpum.GstCtx.rdx = 0;
6497 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6498 return VINF_SUCCESS;
6499 }
6500 }
6501#endif
6502
6503#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6504 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6505 {
6506 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */);
6507 if (rcStrict == VINF_SVM_VMEXIT)
6508 return VINF_SUCCESS;
6509 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
6510 {
6511 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
6512 return rcStrict;
6513 }
6514 }
6515#endif
6516
6517 /*
6518 * Do the job.
6519 */
6520 RTUINT64U uValue;
6521 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
6522 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
6523
6524 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, &uValue.u);
6525 if (rcStrict == VINF_SUCCESS)
6526 {
6527 pVCpu->cpum.GstCtx.rax = uValue.s.Lo;
6528 pVCpu->cpum.GstCtx.rdx = uValue.s.Hi;
6529 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
6530
6531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6532 return VINF_SUCCESS;
6533 }
6534
6535#ifndef IN_RING3
6536 /* Deferred to ring-3. */
6537 if (rcStrict == VINF_CPUM_R3_MSR_READ)
6538 {
6539 Log(("IEM: rdmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
6540 return rcStrict;
6541 }
6542#endif
6543
6544 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6545 if (pVCpu->iem.s.cLogRelRdMsr < 32)
6546 {
6547 pVCpu->iem.s.cLogRelRdMsr++;
6548 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
6549 }
6550 else
6551 Log(( "IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
6552 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6553 return iemRaiseGeneralProtectionFault0(pVCpu);
6554}
6555
6556
6557/**
6558 * Implements WRMSR.
6559 */
6560IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
6561{
6562 /*
6563 * Check preconditions.
6564 */
6565 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
6566 return iemRaiseUndefinedOpcode(pVCpu);
6567 if (pVCpu->iem.s.uCpl != 0)
6568 return iemRaiseGeneralProtectionFault0(pVCpu);
6569
6570 RTUINT64U uValue;
6571 uValue.s.Lo = pVCpu->cpum.GstCtx.eax;
6572 uValue.s.Hi = pVCpu->cpum.GstCtx.edx;
6573
6574 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
6575 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
6576
6577 /*
6578 * Check nested-guest intercepts.
6579 */
6580#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6581 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6582 {
6583 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_WRMSR, pVCpu->cpum.GstCtx.ecx))
6584 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WRMSR, cbInstr);
6585
6586 /* Check x2APIC MSRs first. */
6587 if (IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
6588 {
6589 switch (pVCpu->cpum.GstCtx.ecx)
6590 {
6591 case MSR_IA32_X2APIC_TPR:
6592 {
6593 if ( !uValue.s.Hi
6594 && !(uValue.s.Lo & UINT32_C(0xffffff00)))
6595 {
6596 uint32_t const uVTpr = uValue.s.Lo;
6597 iemVmxVirtApicWriteRaw32(pVCpu, uVTpr, XAPIC_OFF_TPR);
6598 VBOXSTRICTRC rcStrict = iemVmxVmexitTprVirtualization(pVCpu, cbInstr);
6599 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6600 return rcStrict;
6601 return VINF_SUCCESS;
6602 }
6603 Log(("IEM: Invalid TPR MSR write (%#x,%#x) -> #GP(0)\n", uValue.s.Hi, uValue.s.Lo));
6604 return iemRaiseGeneralProtectionFault0(pVCpu);
6605 }
6606
6607 case MSR_IA32_X2APIC_EOI:
6608 case MSR_IA32_X2APIC_SELF_IPI:
6609 {
6610 /** @todo NSTVMX: EOI and Self-IPI virtualization. */
6611 break;
6612 }
6613 }
6614 }
6615 else if (pVCpu->cpum.GstCtx.ecx == MSR_IA32_BIOS_UPDT_TRIG)
6616 {
6617 /** @todo NSTVMX: We must not allow any microcode updates in VMX non-root mode.
6618 * Since we don't implement this MSR anyway it's currently not a problem.
6619 * If we do, we should probably move this check to the MSR handler. */
6620 }
6621 else if (pVCpu->cpum.GstCtx.ecx == MSR_IA32_RTIT_CTL)
6622 {
6623 /** @todo NSTVMX: We don't support Intel PT yet. When we do, this MSR must #GP
6624 * when IntelPT is not supported in VMX. */
6625 }
6626 }
6627#endif
6628
6629#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6630 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
6631 {
6632 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, true /* fWrite */);
6633 if (rcStrict == VINF_SVM_VMEXIT)
6634 return VINF_SUCCESS;
6635 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
6636 {
6637 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
6638 return rcStrict;
6639 }
6640 }
6641#endif
6642
6643 /*
6644 * Do the job.
6645 */
6646 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, uValue.u);
6647 if (rcStrict == VINF_SUCCESS)
6648 {
6649 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6650 return VINF_SUCCESS;
6651 }
6652
6653#ifndef IN_RING3
6654 /* Deferred to ring-3. */
6655 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
6656 {
6657 Log(("IEM: wrmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
6658 return rcStrict;
6659 }
6660#endif
6661
6662 /* Often a unimplemented MSR or MSR bit, so worth logging. */
6663 if (pVCpu->iem.s.cLogRelWrMsr < 32)
6664 {
6665 pVCpu->iem.s.cLogRelWrMsr++;
6666 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx, uValue.s.Hi, uValue.s.Lo));
6667 }
6668 else
6669 Log(( "IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx, uValue.s.Hi, uValue.s.Lo));
6670 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
6671 return iemRaiseGeneralProtectionFault0(pVCpu);
6672}
6673
6674
6675/**
6676 * Implements 'IN eAX, port'.
6677 *
6678 * @param u16Port The source port.
6679 * @param fImm Whether the port was specified through an immediate operand
6680 * or the implicit DX register.
6681 * @param cbReg The register size.
6682 */
6683IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
6684{
6685 /*
6686 * CPL check
6687 */
6688 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
6689 if (rcStrict != VINF_SUCCESS)
6690 return rcStrict;
6691
6692 /*
6693 * Check VMX nested-guest IO intercept.
6694 */
6695#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6696 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6697 {
6698 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, fImm, cbReg, cbInstr);
6699 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6700 return rcStrict;
6701 }
6702#else
6703 RT_NOREF(fImm);
6704#endif
6705
6706 /*
6707 * Check SVM nested-guest IO intercept.
6708 */
6709#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6710 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6711 {
6712 uint8_t cAddrSizeBits;
6713 switch (pVCpu->iem.s.enmEffAddrMode)
6714 {
6715 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6716 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6717 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6718 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6719 }
6720 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6721 false /* fRep */, false /* fStrIo */, cbInstr);
6722 if (rcStrict == VINF_SVM_VMEXIT)
6723 return VINF_SUCCESS;
6724 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
6725 {
6726 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6727 VBOXSTRICTRC_VAL(rcStrict)));
6728 return rcStrict;
6729 }
6730 }
6731#endif
6732
6733 /*
6734 * Perform the I/O.
6735 */
6736 uint32_t u32Value = 0;
6737 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
6738 if (IOM_SUCCESS(rcStrict))
6739 {
6740 switch (cbReg)
6741 {
6742 case 1: pVCpu->cpum.GstCtx.al = (uint8_t)u32Value; break;
6743 case 2: pVCpu->cpum.GstCtx.ax = (uint16_t)u32Value; break;
6744 case 4: pVCpu->cpum.GstCtx.rax = u32Value; break;
6745 default: AssertFailedReturn(VERR_IEM_IPE_3);
6746 }
6747 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6748 pVCpu->iem.s.cPotentialExits++;
6749 if (rcStrict != VINF_SUCCESS)
6750 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6751 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6752
6753 /*
6754 * Check for I/O breakpoints.
6755 */
6756 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
6757 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6758 && X86_DR7_ANY_RW_IO(uDr7)
6759 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
6760 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6761 {
6762 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
6763 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
6764 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6765 rcStrict = iemRaiseDebugException(pVCpu);
6766 }
6767 }
6768
6769 return rcStrict;
6770}
6771
6772
6773/**
6774 * Implements 'IN eAX, DX'.
6775 *
6776 * @param cbReg The register size.
6777 */
6778IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
6779{
6780 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
6781}
6782
6783
6784/**
6785 * Implements 'OUT port, eAX'.
6786 *
6787 * @param u16Port The destination port.
6788 * @param fImm Whether the port was specified through an immediate operand
6789 * or the implicit DX register.
6790 * @param cbReg The register size.
6791 */
6792IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
6793{
6794 /*
6795 * CPL check
6796 */
6797 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
6798 if (rcStrict != VINF_SUCCESS)
6799 return rcStrict;
6800
6801 /*
6802 * Check VMX nested-guest I/O intercept.
6803 */
6804#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6805 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6806 {
6807 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, fImm, cbReg, cbInstr);
6808 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6809 return rcStrict;
6810 }
6811#else
6812 RT_NOREF(fImm);
6813#endif
6814
6815 /*
6816 * Check SVM nested-guest I/O intercept.
6817 */
6818#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6819 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
6820 {
6821 uint8_t cAddrSizeBits;
6822 switch (pVCpu->iem.s.enmEffAddrMode)
6823 {
6824 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
6825 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
6826 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
6827 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6828 }
6829 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
6830 false /* fRep */, false /* fStrIo */, cbInstr);
6831 if (rcStrict == VINF_SVM_VMEXIT)
6832 return VINF_SUCCESS;
6833 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
6834 {
6835 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
6836 VBOXSTRICTRC_VAL(rcStrict)));
6837 return rcStrict;
6838 }
6839 }
6840#endif
6841
6842 /*
6843 * Perform the I/O.
6844 */
6845 uint32_t u32Value;
6846 switch (cbReg)
6847 {
6848 case 1: u32Value = pVCpu->cpum.GstCtx.al; break;
6849 case 2: u32Value = pVCpu->cpum.GstCtx.ax; break;
6850 case 4: u32Value = pVCpu->cpum.GstCtx.eax; break;
6851 default: AssertFailedReturn(VERR_IEM_IPE_4);
6852 }
6853 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
6854 if (IOM_SUCCESS(rcStrict))
6855 {
6856 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6857 pVCpu->iem.s.cPotentialExits++;
6858 if (rcStrict != VINF_SUCCESS)
6859 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6860 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
6861
6862 /*
6863 * Check for I/O breakpoints.
6864 */
6865 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
6866 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6867 && X86_DR7_ANY_RW_IO(uDr7)
6868 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
6869 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
6870 {
6871 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
6872 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
6873 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
6874 rcStrict = iemRaiseDebugException(pVCpu);
6875 }
6876 }
6877 return rcStrict;
6878}
6879
6880
6881/**
6882 * Implements 'OUT DX, eAX'.
6883 *
6884 * @param cbReg The register size.
6885 */
6886IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
6887{
6888 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
6889}
6890
6891
6892/**
6893 * Implements 'CLI'.
6894 */
6895IEM_CIMPL_DEF_0(iemCImpl_cli)
6896{
6897 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
6898 uint32_t const fEflOld = fEfl;
6899
6900 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
6901 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
6902 {
6903 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6904 if (!(fEfl & X86_EFL_VM))
6905 {
6906 if (pVCpu->iem.s.uCpl <= uIopl)
6907 fEfl &= ~X86_EFL_IF;
6908 else if ( pVCpu->iem.s.uCpl == 3
6909 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI) )
6910 fEfl &= ~X86_EFL_VIF;
6911 else
6912 return iemRaiseGeneralProtectionFault0(pVCpu);
6913 }
6914 /* V8086 */
6915 else if (uIopl == 3)
6916 fEfl &= ~X86_EFL_IF;
6917 else if ( uIopl < 3
6918 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
6919 fEfl &= ~X86_EFL_VIF;
6920 else
6921 return iemRaiseGeneralProtectionFault0(pVCpu);
6922 }
6923 /* real mode */
6924 else
6925 fEfl &= ~X86_EFL_IF;
6926
6927 /* Commit. */
6928 IEMMISC_SET_EFL(pVCpu, fEfl);
6929 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6930 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
6931 return VINF_SUCCESS;
6932}
6933
6934
6935/**
6936 * Implements 'STI'.
6937 */
6938IEM_CIMPL_DEF_0(iemCImpl_sti)
6939{
6940 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
6941 uint32_t const fEflOld = fEfl;
6942
6943 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
6944 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
6945 {
6946 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
6947 if (!(fEfl & X86_EFL_VM))
6948 {
6949 if (pVCpu->iem.s.uCpl <= uIopl)
6950 fEfl |= X86_EFL_IF;
6951 else if ( pVCpu->iem.s.uCpl == 3
6952 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI)
6953 && !(fEfl & X86_EFL_VIP) )
6954 fEfl |= X86_EFL_VIF;
6955 else
6956 return iemRaiseGeneralProtectionFault0(pVCpu);
6957 }
6958 /* V8086 */
6959 else if (uIopl == 3)
6960 fEfl |= X86_EFL_IF;
6961 else if ( uIopl < 3
6962 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME)
6963 && !(fEfl & X86_EFL_VIP) )
6964 fEfl |= X86_EFL_VIF;
6965 else
6966 return iemRaiseGeneralProtectionFault0(pVCpu);
6967 }
6968 /* real mode */
6969 else
6970 fEfl |= X86_EFL_IF;
6971
6972 /* Commit. */
6973 IEMMISC_SET_EFL(pVCpu, fEfl);
6974 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6975 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF))
6976 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
6977 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
6978 return VINF_SUCCESS;
6979}
6980
6981
6982/**
6983 * Implements 'HLT'.
6984 */
6985IEM_CIMPL_DEF_0(iemCImpl_hlt)
6986{
6987 if (pVCpu->iem.s.uCpl != 0)
6988 return iemRaiseGeneralProtectionFault0(pVCpu);
6989
6990 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6991 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_HLT_EXIT))
6992 {
6993 Log2(("hlt: Guest intercept -> VM-exit\n"));
6994 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_HLT, cbInstr);
6995 }
6996
6997 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
6998 {
6999 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
7000 IEM_SVM_UPDATE_NRIP(pVCpu);
7001 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7002 }
7003
7004 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7005 return VINF_EM_HALT;
7006}
7007
7008
7009/**
7010 * Implements 'MONITOR'.
7011 */
7012IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
7013{
7014 /*
7015 * Permission checks.
7016 */
7017 if (pVCpu->iem.s.uCpl != 0)
7018 {
7019 Log2(("monitor: CPL != 0\n"));
7020 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
7021 }
7022 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7023 {
7024 Log2(("monitor: Not in CPUID\n"));
7025 return iemRaiseUndefinedOpcode(pVCpu);
7026 }
7027
7028 /*
7029 * Check VMX guest-intercept.
7030 * This should be considered a fault-like VM-exit.
7031 * See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
7032 */
7033 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7034 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MONITOR_EXIT))
7035 {
7036 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7037 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_MONITOR, cbInstr);
7038 }
7039
7040 /*
7041 * Gather the operands and validate them.
7042 */
7043 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
7044 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7045 uint32_t uEdx = pVCpu->cpum.GstCtx.edx;
7046/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
7047 * \#GP first. */
7048 if (uEcx != 0)
7049 {
7050 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
7051 return iemRaiseGeneralProtectionFault0(pVCpu);
7052 }
7053
7054 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
7055 if (rcStrict != VINF_SUCCESS)
7056 return rcStrict;
7057
7058 RTGCPHYS GCPhysMem;
7059 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7060 if (rcStrict != VINF_SUCCESS)
7061 return rcStrict;
7062
7063 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
7064 {
7065 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7066 IEM_SVM_UPDATE_NRIP(pVCpu);
7067 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7068 }
7069
7070 /*
7071 * Call EM to prepare the monitor/wait.
7072 */
7073 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem);
7074 Assert(rcStrict == VINF_SUCCESS);
7075
7076 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7077 return rcStrict;
7078}
7079
7080
7081/**
7082 * Implements 'MWAIT'.
7083 */
7084IEM_CIMPL_DEF_0(iemCImpl_mwait)
7085{
7086 /*
7087 * Permission checks.
7088 */
7089 if (pVCpu->iem.s.uCpl != 0)
7090 {
7091 Log2(("mwait: CPL != 0\n"));
7092 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
7093 * EFLAGS.VM then.) */
7094 return iemRaiseUndefinedOpcode(pVCpu);
7095 }
7096 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7097 {
7098 Log2(("mwait: Not in CPUID\n"));
7099 return iemRaiseUndefinedOpcode(pVCpu);
7100 }
7101
7102 /*
7103 * Gather the operands and validate them.
7104 */
7105 uint32_t uEax = pVCpu->cpum.GstCtx.eax;
7106 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7107 if (uEcx != 0)
7108 {
7109 /* Only supported extension is break on IRQ when IF=0. */
7110 if (uEcx > 1)
7111 {
7112 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
7113 return iemRaiseGeneralProtectionFault0(pVCpu);
7114 }
7115 uint32_t fMWaitFeatures = 0;
7116 uint32_t uIgnore = 0;
7117 CPUMGetGuestCpuId(pVCpu, 5, 0, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
7118 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7119 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7120 {
7121 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
7122 return iemRaiseGeneralProtectionFault0(pVCpu);
7123 }
7124 }
7125
7126 /*
7127 * Check SVM nested-guest mwait intercepts.
7128 */
7129 if ( IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
7130 && EMMonitorIsArmed(pVCpu))
7131 {
7132 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
7133 IEM_SVM_UPDATE_NRIP(pVCpu);
7134 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7135 }
7136 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
7137 {
7138 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
7139 IEM_SVM_UPDATE_NRIP(pVCpu);
7140 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7141 }
7142
7143 /*
7144 * Call EM to prepare the monitor/wait.
7145 */
7146 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
7147
7148 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7149 return rcStrict;
7150}
7151
7152
7153/**
7154 * Implements 'SWAPGS'.
7155 */
7156IEM_CIMPL_DEF_0(iemCImpl_swapgs)
7157{
7158 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
7159
7160 /*
7161 * Permission checks.
7162 */
7163 if (pVCpu->iem.s.uCpl != 0)
7164 {
7165 Log2(("swapgs: CPL != 0\n"));
7166 return iemRaiseUndefinedOpcode(pVCpu);
7167 }
7168
7169 /*
7170 * Do the job.
7171 */
7172 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_GS);
7173 uint64_t uOtherGsBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
7174 pVCpu->cpum.GstCtx.msrKERNELGSBASE = pVCpu->cpum.GstCtx.gs.u64Base;
7175 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase;
7176
7177 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7178 return VINF_SUCCESS;
7179}
7180
7181
7182/**
7183 * Implements 'CPUID'.
7184 */
7185IEM_CIMPL_DEF_0(iemCImpl_cpuid)
7186{
7187 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7188 {
7189 Log2(("cpuid: Guest intercept -> VM-exit\n"));
7190 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_CPUID, cbInstr);
7191 }
7192
7193 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
7194 {
7195 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
7196 IEM_SVM_UPDATE_NRIP(pVCpu);
7197 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7198 }
7199
7200 CPUMGetGuestCpuId(pVCpu, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx,
7201 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx, &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7202 pVCpu->cpum.GstCtx.rax &= UINT32_C(0xffffffff);
7203 pVCpu->cpum.GstCtx.rbx &= UINT32_C(0xffffffff);
7204 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7205 pVCpu->cpum.GstCtx.rdx &= UINT32_C(0xffffffff);
7206 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
7207
7208 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7209 pVCpu->iem.s.cPotentialExits++;
7210 return VINF_SUCCESS;
7211}
7212
7213
7214/**
7215 * Implements 'AAD'.
7216 *
7217 * @param bImm The immediate operand.
7218 */
7219IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
7220{
7221 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7222 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
7223 pVCpu->cpum.GstCtx.ax = al;
7224 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7225 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7226 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7227
7228 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7229 return VINF_SUCCESS;
7230}
7231
7232
7233/**
7234 * Implements 'AAM'.
7235 *
7236 * @param bImm The immediate operand. Cannot be 0.
7237 */
7238IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
7239{
7240 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
7241
7242 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7243 uint8_t const al = (uint8_t)ax % bImm;
7244 uint8_t const ah = (uint8_t)ax / bImm;
7245 pVCpu->cpum.GstCtx.ax = (ah << 8) + al;
7246 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7247 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7248 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7249
7250 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7251 return VINF_SUCCESS;
7252}
7253
7254
7255/**
7256 * Implements 'DAA'.
7257 */
7258IEM_CIMPL_DEF_0(iemCImpl_daa)
7259{
7260 uint8_t const al = pVCpu->cpum.GstCtx.al;
7261 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7262
7263 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7264 || (al & 0xf) >= 10)
7265 {
7266 pVCpu->cpum.GstCtx.al = al + 6;
7267 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7268 }
7269 else
7270 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7271
7272 if (al >= 0x9a || fCarry)
7273 {
7274 pVCpu->cpum.GstCtx.al += 0x60;
7275 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7276 }
7277 else
7278 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7279
7280 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7281 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7282 return VINF_SUCCESS;
7283}
7284
7285
7286/**
7287 * Implements 'DAS'.
7288 */
7289IEM_CIMPL_DEF_0(iemCImpl_das)
7290{
7291 uint8_t const uInputAL = pVCpu->cpum.GstCtx.al;
7292 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7293
7294 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7295 || (uInputAL & 0xf) >= 10)
7296 {
7297 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7298 if (uInputAL < 6)
7299 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7300 pVCpu->cpum.GstCtx.al = uInputAL - 6;
7301 }
7302 else
7303 {
7304 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7305 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7306 }
7307
7308 if (uInputAL >= 0x9a || fCarry)
7309 {
7310 pVCpu->cpum.GstCtx.al -= 0x60;
7311 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7312 }
7313
7314 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7315 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7316 return VINF_SUCCESS;
7317}
7318
7319
7320/**
7321 * Implements 'AAA'.
7322 */
7323IEM_CIMPL_DEF_0(iemCImpl_aaa)
7324{
7325 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
7326 {
7327 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7328 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7329 {
7330 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
7331 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7332 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7333 }
7334 else
7335 {
7336 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7337 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7338 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7339 }
7340 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7341 }
7342 else
7343 {
7344 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7345 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7346 {
7347 pVCpu->cpum.GstCtx.ax += UINT16_C(0x106);
7348 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7349 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7350 }
7351 else
7352 {
7353 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7354 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7355 }
7356 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7357 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7358 }
7359
7360 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7361 return VINF_SUCCESS;
7362}
7363
7364
7365/**
7366 * Implements 'AAS'.
7367 */
7368IEM_CIMPL_DEF_0(iemCImpl_aas)
7369{
7370 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
7371 {
7372 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7373 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7374 {
7375 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.u32);
7376 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7377 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7378 }
7379 else
7380 {
7381 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7382 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7383 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7384 }
7385 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7386 }
7387 else
7388 {
7389 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7390 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
7391 {
7392 pVCpu->cpum.GstCtx.ax -= UINT16_C(0x106);
7393 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7394 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7395 }
7396 else
7397 {
7398 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7399 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7400 }
7401 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
7402 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7403 }
7404
7405 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7406 return VINF_SUCCESS;
7407}
7408
7409
7410/**
7411 * Implements the 16-bit version of 'BOUND'.
7412 *
7413 * @note We have separate 16-bit and 32-bit variants of this function due to
7414 * the decoder using unsigned parameters, whereas we want signed one to
7415 * do the job. This is significant for a recompiler.
7416 */
7417IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
7418{
7419 /*
7420 * Check if the index is inside the bounds, otherwise raise #BR.
7421 */
7422 if ( idxArray >= idxLowerBound
7423 && idxArray <= idxUpperBound)
7424 {
7425 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7426 return VINF_SUCCESS;
7427 }
7428
7429 return iemRaiseBoundRangeExceeded(pVCpu);
7430}
7431
7432
7433/**
7434 * Implements the 32-bit version of 'BOUND'.
7435 */
7436IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
7437{
7438 /*
7439 * Check if the index is inside the bounds, otherwise raise #BR.
7440 */
7441 if ( idxArray >= idxLowerBound
7442 && idxArray <= idxUpperBound)
7443 {
7444 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7445 return VINF_SUCCESS;
7446 }
7447
7448 return iemRaiseBoundRangeExceeded(pVCpu);
7449}
7450
7451
7452
7453/*
7454 * Instantiate the various string operation combinations.
7455 */
7456#define OP_SIZE 8
7457#define ADDR_SIZE 16
7458#include "IEMAllCImplStrInstr.cpp.h"
7459#define OP_SIZE 8
7460#define ADDR_SIZE 32
7461#include "IEMAllCImplStrInstr.cpp.h"
7462#define OP_SIZE 8
7463#define ADDR_SIZE 64
7464#include "IEMAllCImplStrInstr.cpp.h"
7465
7466#define OP_SIZE 16
7467#define ADDR_SIZE 16
7468#include "IEMAllCImplStrInstr.cpp.h"
7469#define OP_SIZE 16
7470#define ADDR_SIZE 32
7471#include "IEMAllCImplStrInstr.cpp.h"
7472#define OP_SIZE 16
7473#define ADDR_SIZE 64
7474#include "IEMAllCImplStrInstr.cpp.h"
7475
7476#define OP_SIZE 32
7477#define ADDR_SIZE 16
7478#include "IEMAllCImplStrInstr.cpp.h"
7479#define OP_SIZE 32
7480#define ADDR_SIZE 32
7481#include "IEMAllCImplStrInstr.cpp.h"
7482#define OP_SIZE 32
7483#define ADDR_SIZE 64
7484#include "IEMAllCImplStrInstr.cpp.h"
7485
7486#define OP_SIZE 64
7487#define ADDR_SIZE 32
7488#include "IEMAllCImplStrInstr.cpp.h"
7489#define OP_SIZE 64
7490#define ADDR_SIZE 64
7491#include "IEMAllCImplStrInstr.cpp.h"
7492
7493
7494/**
7495 * Implements 'XGETBV'.
7496 */
7497IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
7498{
7499 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
7500 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
7501 {
7502 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7503 switch (uEcx)
7504 {
7505 case 0:
7506 break;
7507
7508 case 1: /** @todo Implement XCR1 support. */
7509 default:
7510 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
7511 return iemRaiseGeneralProtectionFault0(pVCpu);
7512
7513 }
7514 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
7515 pVCpu->cpum.GstCtx.rax = RT_LO_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
7516 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
7517
7518 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7519 return VINF_SUCCESS;
7520 }
7521 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
7522 return iemRaiseUndefinedOpcode(pVCpu);
7523}
7524
7525
7526/**
7527 * Implements 'XSETBV'.
7528 */
7529IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
7530{
7531 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
7532 {
7533 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
7534 {
7535 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
7536 IEM_SVM_UPDATE_NRIP(pVCpu);
7537 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7538 }
7539
7540 if (pVCpu->iem.s.uCpl == 0)
7541 {
7542 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
7543
7544 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7545 uint64_t uNewValue = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx);
7546 switch (uEcx)
7547 {
7548 case 0:
7549 {
7550 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
7551 if (rc == VINF_SUCCESS)
7552 break;
7553 Assert(rc == VERR_CPUM_RAISE_GP_0);
7554 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7555 return iemRaiseGeneralProtectionFault0(pVCpu);
7556 }
7557
7558 case 1: /** @todo Implement XCR1 support. */
7559 default:
7560 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
7561 return iemRaiseGeneralProtectionFault0(pVCpu);
7562
7563 }
7564
7565 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7566 return VINF_SUCCESS;
7567 }
7568
7569 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
7570 return iemRaiseGeneralProtectionFault0(pVCpu);
7571 }
7572 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
7573 return iemRaiseUndefinedOpcode(pVCpu);
7574}
7575
7576#ifdef IN_RING3
7577
7578/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
7579struct IEMCIMPLCX16ARGS
7580{
7581 PRTUINT128U pu128Dst;
7582 PRTUINT128U pu128RaxRdx;
7583 PRTUINT128U pu128RbxRcx;
7584 uint32_t *pEFlags;
7585# ifdef VBOX_STRICT
7586 uint32_t cCalls;
7587# endif
7588};
7589
7590/**
7591 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
7592 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
7593 */
7594static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPU pVCpu, void *pvUser)
7595{
7596 RT_NOREF(pVM, pVCpu);
7597 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
7598# ifdef VBOX_STRICT
7599 Assert(pArgs->cCalls == 0);
7600 pArgs->cCalls++;
7601# endif
7602
7603 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
7604 return VINF_SUCCESS;
7605}
7606
7607#endif /* IN_RING3 */
7608
7609/**
7610 * Implements 'CMPXCHG16B' fallback using rendezvous.
7611 */
7612IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
7613 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
7614{
7615#ifdef IN_RING3
7616 struct IEMCIMPLCX16ARGS Args;
7617 Args.pu128Dst = pu128Dst;
7618 Args.pu128RaxRdx = pu128RaxRdx;
7619 Args.pu128RbxRcx = pu128RbxRcx;
7620 Args.pEFlags = pEFlags;
7621# ifdef VBOX_STRICT
7622 Args.cCalls = 0;
7623# endif
7624 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
7625 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
7626 Assert(Args.cCalls == 1);
7627 if (rcStrict == VINF_SUCCESS)
7628 {
7629 /* Duplicated tail code. */
7630 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
7631 if (rcStrict == VINF_SUCCESS)
7632 {
7633 pVCpu->cpum.GstCtx.eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
7634 if (!(*pEFlags & X86_EFL_ZF))
7635 {
7636 pVCpu->cpum.GstCtx.rax = pu128RaxRdx->s.Lo;
7637 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi;
7638 }
7639 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7640 }
7641 }
7642 return rcStrict;
7643#else
7644 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
7645 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
7646#endif
7647}
7648
7649
7650/**
7651 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
7652 *
7653 * This is implemented in C because it triggers a load like behviour without
7654 * actually reading anything. Since that's not so common, it's implemented
7655 * here.
7656 *
7657 * @param iEffSeg The effective segment.
7658 * @param GCPtrEff The address of the image.
7659 */
7660IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
7661{
7662 /*
7663 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
7664 */
7665 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
7666 if (rcStrict == VINF_SUCCESS)
7667 {
7668 RTGCPHYS GCPhysMem;
7669 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7670 if (rcStrict == VINF_SUCCESS)
7671 {
7672 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7673 return VINF_SUCCESS;
7674 }
7675 }
7676
7677 return rcStrict;
7678}
7679
7680
7681/**
7682 * Implements 'FINIT' and 'FNINIT'.
7683 *
7684 * @param fCheckXcpts Whether to check for umasked pending exceptions or
7685 * not.
7686 */
7687IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
7688{
7689 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
7690 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
7691 return iemRaiseDeviceNotAvailable(pVCpu);
7692
7693 iemFpuActualizeStateForChange(pVCpu);
7694 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87);
7695
7696 NOREF(fCheckXcpts); /** @todo trigger pending exceptions:
7697 if (fCheckXcpts && TODO )
7698 return iemRaiseMathFault(pVCpu);
7699 */
7700
7701 PX86XSAVEAREA pXState = pVCpu->cpum.GstCtx.CTX_SUFF(pXState);
7702 pXState->x87.FCW = 0x37f;
7703 pXState->x87.FSW = 0;
7704 pXState->x87.FTW = 0x00; /* 0 - empty. */
7705 pXState->x87.FPUDP = 0;
7706 pXState->x87.DS = 0; //??
7707 pXState->x87.Rsrvd2= 0;
7708 pXState->x87.FPUIP = 0;
7709 pXState->x87.CS = 0; //??
7710 pXState->x87.Rsrvd1= 0;
7711 pXState->x87.FOP = 0;
7712
7713 iemHlpUsedFpu(pVCpu);
7714 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7715 return VINF_SUCCESS;
7716}
7717
7718
7719/**
7720 * Implements 'FXSAVE'.
7721 *
7722 * @param iEffSeg The effective segment.
7723 * @param GCPtrEff The address of the image.
7724 * @param enmEffOpSize The operand size (only REX.W really matters).
7725 */
7726IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7727{
7728 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
7729
7730 /*
7731 * Raise exceptions.
7732 */
7733 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
7734 return iemRaiseUndefinedOpcode(pVCpu);
7735 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
7736 return iemRaiseDeviceNotAvailable(pVCpu);
7737 if (GCPtrEff & 15)
7738 {
7739 /** @todo CPU/VM detection possible! \#AC might not be signal for
7740 * all/any misalignment sizes, intel says its an implementation detail. */
7741 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7742 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7743 && pVCpu->iem.s.uCpl == 3)
7744 return iemRaiseAlignmentCheckException(pVCpu);
7745 return iemRaiseGeneralProtectionFault0(pVCpu);
7746 }
7747
7748 /*
7749 * Access the memory.
7750 */
7751 void *pvMem512;
7752 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7753 if (rcStrict != VINF_SUCCESS)
7754 return rcStrict;
7755 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7756 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7757
7758 /*
7759 * Store the registers.
7760 */
7761 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7762 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
7763
7764 /* common for all formats */
7765 pDst->FCW = pSrc->FCW;
7766 pDst->FSW = pSrc->FSW;
7767 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7768 pDst->FOP = pSrc->FOP;
7769 pDst->MXCSR = pSrc->MXCSR;
7770 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7771 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
7772 {
7773 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
7774 * them for now... */
7775 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7776 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7777 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7778 pDst->aRegs[i].au32[3] = 0;
7779 }
7780
7781 /* FPU IP, CS, DP and DS. */
7782 pDst->FPUIP = pSrc->FPUIP;
7783 pDst->CS = pSrc->CS;
7784 pDst->FPUDP = pSrc->FPUDP;
7785 pDst->DS = pSrc->DS;
7786 if (enmEffOpSize == IEMMODE_64BIT)
7787 {
7788 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
7789 pDst->Rsrvd1 = pSrc->Rsrvd1;
7790 pDst->Rsrvd2 = pSrc->Rsrvd2;
7791 pDst->au32RsrvdForSoftware[0] = 0;
7792 }
7793 else
7794 {
7795 pDst->Rsrvd1 = 0;
7796 pDst->Rsrvd2 = 0;
7797 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
7798 }
7799
7800 /* XMM registers. */
7801 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
7802 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7803 || pVCpu->iem.s.uCpl != 0)
7804 {
7805 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7806 for (uint32_t i = 0; i < cXmmRegs; i++)
7807 pDst->aXMM[i] = pSrc->aXMM[i];
7808 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
7809 * right? */
7810 }
7811
7812 /*
7813 * Commit the memory.
7814 */
7815 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7816 if (rcStrict != VINF_SUCCESS)
7817 return rcStrict;
7818
7819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7820 return VINF_SUCCESS;
7821}
7822
7823
7824/**
7825 * Implements 'FXRSTOR'.
7826 *
7827 * @param GCPtrEff The address of the image.
7828 * @param enmEffOpSize The operand size (only REX.W really matters).
7829 */
7830IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7831{
7832 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
7833
7834 /*
7835 * Raise exceptions.
7836 */
7837 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
7838 return iemRaiseUndefinedOpcode(pVCpu);
7839 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
7840 return iemRaiseDeviceNotAvailable(pVCpu);
7841 if (GCPtrEff & 15)
7842 {
7843 /** @todo CPU/VM detection possible! \#AC might not be signal for
7844 * all/any misalignment sizes, intel says its an implementation detail. */
7845 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7846 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7847 && pVCpu->iem.s.uCpl == 3)
7848 return iemRaiseAlignmentCheckException(pVCpu);
7849 return iemRaiseGeneralProtectionFault0(pVCpu);
7850 }
7851
7852 /*
7853 * Access the memory.
7854 */
7855 void *pvMem512;
7856 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
7857 if (rcStrict != VINF_SUCCESS)
7858 return rcStrict;
7859 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
7860 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7861
7862 /*
7863 * Check the state for stuff which will #GP(0).
7864 */
7865 uint32_t const fMXCSR = pSrc->MXCSR;
7866 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
7867 if (fMXCSR & ~fMXCSR_MASK)
7868 {
7869 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
7870 return iemRaiseGeneralProtectionFault0(pVCpu);
7871 }
7872
7873 /*
7874 * Load the registers.
7875 */
7876 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
7877 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
7878
7879 /* common for all formats */
7880 pDst->FCW = pSrc->FCW;
7881 pDst->FSW = pSrc->FSW;
7882 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
7883 pDst->FOP = pSrc->FOP;
7884 pDst->MXCSR = fMXCSR;
7885 /* (MXCSR_MASK is read-only) */
7886 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
7887 {
7888 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
7889 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
7890 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
7891 pDst->aRegs[i].au32[3] = 0;
7892 }
7893
7894 /* FPU IP, CS, DP and DS. */
7895 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
7896 {
7897 pDst->FPUIP = pSrc->FPUIP;
7898 pDst->CS = pSrc->CS;
7899 pDst->Rsrvd1 = pSrc->Rsrvd1;
7900 pDst->FPUDP = pSrc->FPUDP;
7901 pDst->DS = pSrc->DS;
7902 pDst->Rsrvd2 = pSrc->Rsrvd2;
7903 }
7904 else
7905 {
7906 pDst->FPUIP = pSrc->FPUIP;
7907 pDst->CS = pSrc->CS;
7908 pDst->Rsrvd1 = 0;
7909 pDst->FPUDP = pSrc->FPUDP;
7910 pDst->DS = pSrc->DS;
7911 pDst->Rsrvd2 = 0;
7912 }
7913
7914 /* XMM registers. */
7915 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
7916 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
7917 || pVCpu->iem.s.uCpl != 0)
7918 {
7919 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
7920 for (uint32_t i = 0; i < cXmmRegs; i++)
7921 pDst->aXMM[i] = pSrc->aXMM[i];
7922 }
7923
7924 /*
7925 * Commit the memory.
7926 */
7927 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
7928 if (rcStrict != VINF_SUCCESS)
7929 return rcStrict;
7930
7931 iemHlpUsedFpu(pVCpu);
7932 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7933 return VINF_SUCCESS;
7934}
7935
7936
7937/**
7938 * Implements 'XSAVE'.
7939 *
7940 * @param iEffSeg The effective segment.
7941 * @param GCPtrEff The address of the image.
7942 * @param enmEffOpSize The operand size (only REX.W really matters).
7943 */
7944IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
7945{
7946 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
7947
7948 /*
7949 * Raise exceptions.
7950 */
7951 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
7952 return iemRaiseUndefinedOpcode(pVCpu);
7953 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
7954 return iemRaiseDeviceNotAvailable(pVCpu);
7955 if (GCPtrEff & 63)
7956 {
7957 /** @todo CPU/VM detection possible! \#AC might not be signal for
7958 * all/any misalignment sizes, intel says its an implementation detail. */
7959 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
7960 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
7961 && pVCpu->iem.s.uCpl == 3)
7962 return iemRaiseAlignmentCheckException(pVCpu);
7963 return iemRaiseGeneralProtectionFault0(pVCpu);
7964 }
7965
7966 /*
7967 * Calc the requested mask
7968 */
7969 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
7970 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
7971 uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
7972
7973/** @todo figure out the exact protocol for the memory access. Currently we
7974 * just need this crap to work halfways to make it possible to test
7975 * AVX instructions. */
7976/** @todo figure out the XINUSE and XMODIFIED */
7977
7978 /*
7979 * Access the x87 memory state.
7980 */
7981 /* The x87+SSE state. */
7982 void *pvMem512;
7983 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
7984 if (rcStrict != VINF_SUCCESS)
7985 return rcStrict;
7986 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
7987 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
7988
7989 /* The header. */
7990 PX86XSAVEHDR pHdr;
7991 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW);
7992 if (rcStrict != VINF_SUCCESS)
7993 return rcStrict;
7994
7995 /*
7996 * Store the X87 state.
7997 */
7998 if (fReqComponents & XSAVE_C_X87)
7999 {
8000 /* common for all formats */
8001 pDst->FCW = pSrc->FCW;
8002 pDst->FSW = pSrc->FSW;
8003 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8004 pDst->FOP = pSrc->FOP;
8005 pDst->FPUIP = pSrc->FPUIP;
8006 pDst->CS = pSrc->CS;
8007 pDst->FPUDP = pSrc->FPUDP;
8008 pDst->DS = pSrc->DS;
8009 if (enmEffOpSize == IEMMODE_64BIT)
8010 {
8011 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8012 pDst->Rsrvd1 = pSrc->Rsrvd1;
8013 pDst->Rsrvd2 = pSrc->Rsrvd2;
8014 pDst->au32RsrvdForSoftware[0] = 0;
8015 }
8016 else
8017 {
8018 pDst->Rsrvd1 = 0;
8019 pDst->Rsrvd2 = 0;
8020 pDst->au32RsrvdForSoftware[0] = X86_FXSTATE_RSVD_32BIT_MAGIC;
8021 }
8022 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8023 {
8024 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8025 * them for now... */
8026 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8027 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8028 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8029 pDst->aRegs[i].au32[3] = 0;
8030 }
8031
8032 }
8033
8034 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8035 {
8036 pDst->MXCSR = pSrc->MXCSR;
8037 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8038 }
8039
8040 if (fReqComponents & XSAVE_C_SSE)
8041 {
8042 /* XMM registers. */
8043 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8044 for (uint32_t i = 0; i < cXmmRegs; i++)
8045 pDst->aXMM[i] = pSrc->aXMM[i];
8046 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8047 * right? */
8048 }
8049
8050 /* Commit the x87 state bits. (probably wrong) */
8051 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8052 if (rcStrict != VINF_SUCCESS)
8053 return rcStrict;
8054
8055 /*
8056 * Store AVX state.
8057 */
8058 if (fReqComponents & XSAVE_C_YMM)
8059 {
8060 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8061 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8062 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
8063 PX86XSAVEYMMHI pCompDst;
8064 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8065 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8066 if (rcStrict != VINF_SUCCESS)
8067 return rcStrict;
8068
8069 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8070 for (uint32_t i = 0; i < cXmmRegs; i++)
8071 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
8072
8073 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8074 if (rcStrict != VINF_SUCCESS)
8075 return rcStrict;
8076 }
8077
8078 /*
8079 * Update the header.
8080 */
8081 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
8082 | (fReqComponents & fXInUse);
8083
8084 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
8085 if (rcStrict != VINF_SUCCESS)
8086 return rcStrict;
8087
8088 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8089 return VINF_SUCCESS;
8090}
8091
8092
8093/**
8094 * Implements 'XRSTOR'.
8095 *
8096 * @param iEffSeg The effective segment.
8097 * @param GCPtrEff The address of the image.
8098 * @param enmEffOpSize The operand size (only REX.W really matters).
8099 */
8100IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8101{
8102 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8103
8104 /*
8105 * Raise exceptions.
8106 */
8107 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8108 return iemRaiseUndefinedOpcode(pVCpu);
8109 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8110 return iemRaiseDeviceNotAvailable(pVCpu);
8111 if (GCPtrEff & 63)
8112 {
8113 /** @todo CPU/VM detection possible! \#AC might not be signal for
8114 * all/any misalignment sizes, intel says its an implementation detail. */
8115 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
8116 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
8117 && pVCpu->iem.s.uCpl == 3)
8118 return iemRaiseAlignmentCheckException(pVCpu);
8119 return iemRaiseGeneralProtectionFault0(pVCpu);
8120 }
8121
8122/** @todo figure out the exact protocol for the memory access. Currently we
8123 * just need this crap to work halfways to make it possible to test
8124 * AVX instructions. */
8125/** @todo figure out the XINUSE and XMODIFIED */
8126
8127 /*
8128 * Access the x87 memory state.
8129 */
8130 /* The x87+SSE state. */
8131 void *pvMem512;
8132 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R);
8133 if (rcStrict != VINF_SUCCESS)
8134 return rcStrict;
8135 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8136 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8137
8138 /*
8139 * Calc the requested mask
8140 */
8141 PX86XSAVEHDR pHdrDst = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->Hdr;
8142 PCX86XSAVEHDR pHdrSrc;
8143 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_R);
8144 if (rcStrict != VINF_SUCCESS)
8145 return rcStrict;
8146
8147 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8148 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8149 //uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8150 uint64_t const fRstorMask = pHdrSrc->bmXState;
8151 uint64_t const fCompMask = pHdrSrc->bmXComp;
8152
8153 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8154
8155 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8156
8157 /* We won't need this any longer. */
8158 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
8159 if (rcStrict != VINF_SUCCESS)
8160 return rcStrict;
8161
8162 /*
8163 * Store the X87 state.
8164 */
8165 if (fReqComponents & XSAVE_C_X87)
8166 {
8167 if (fRstorMask & XSAVE_C_X87)
8168 {
8169 pDst->FCW = pSrc->FCW;
8170 pDst->FSW = pSrc->FSW;
8171 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8172 pDst->FOP = pSrc->FOP;
8173 pDst->FPUIP = pSrc->FPUIP;
8174 pDst->CS = pSrc->CS;
8175 pDst->FPUDP = pSrc->FPUDP;
8176 pDst->DS = pSrc->DS;
8177 if (enmEffOpSize == IEMMODE_64BIT)
8178 {
8179 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8180 pDst->Rsrvd1 = pSrc->Rsrvd1;
8181 pDst->Rsrvd2 = pSrc->Rsrvd2;
8182 }
8183 else
8184 {
8185 pDst->Rsrvd1 = 0;
8186 pDst->Rsrvd2 = 0;
8187 }
8188 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8189 {
8190 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8191 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8192 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8193 pDst->aRegs[i].au32[3] = 0;
8194 }
8195 }
8196 else
8197 {
8198 pDst->FCW = 0x37f;
8199 pDst->FSW = 0;
8200 pDst->FTW = 0x00; /* 0 - empty. */
8201 pDst->FPUDP = 0;
8202 pDst->DS = 0; //??
8203 pDst->Rsrvd2= 0;
8204 pDst->FPUIP = 0;
8205 pDst->CS = 0; //??
8206 pDst->Rsrvd1= 0;
8207 pDst->FOP = 0;
8208 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8209 {
8210 pDst->aRegs[i].au32[0] = 0;
8211 pDst->aRegs[i].au32[1] = 0;
8212 pDst->aRegs[i].au32[2] = 0;
8213 pDst->aRegs[i].au32[3] = 0;
8214 }
8215 }
8216 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
8217 }
8218
8219 /* MXCSR */
8220 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8221 {
8222 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
8223 pDst->MXCSR = pSrc->MXCSR;
8224 else
8225 pDst->MXCSR = 0x1f80;
8226 }
8227
8228 /* XMM registers. */
8229 if (fReqComponents & XSAVE_C_SSE)
8230 {
8231 if (fRstorMask & XSAVE_C_SSE)
8232 {
8233 for (uint32_t i = 0; i < cXmmRegs; i++)
8234 pDst->aXMM[i] = pSrc->aXMM[i];
8235 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8236 * right? */
8237 }
8238 else
8239 {
8240 for (uint32_t i = 0; i < cXmmRegs; i++)
8241 {
8242 pDst->aXMM[i].au64[0] = 0;
8243 pDst->aXMM[i].au64[1] = 0;
8244 }
8245 }
8246 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
8247 }
8248
8249 /* Unmap the x87 state bits (so we've don't run out of mapping). */
8250 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8251 if (rcStrict != VINF_SUCCESS)
8252 return rcStrict;
8253
8254 /*
8255 * Restore AVX state.
8256 */
8257 if (fReqComponents & XSAVE_C_YMM)
8258 {
8259 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8260 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
8261
8262 if (fRstorMask & XSAVE_C_YMM)
8263 {
8264 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8265 PCX86XSAVEYMMHI pCompSrc;
8266 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
8267 iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT], IEM_ACCESS_DATA_R);
8268 if (rcStrict != VINF_SUCCESS)
8269 return rcStrict;
8270
8271 for (uint32_t i = 0; i < cXmmRegs; i++)
8272 {
8273 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
8274 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
8275 }
8276
8277 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
8278 if (rcStrict != VINF_SUCCESS)
8279 return rcStrict;
8280 }
8281 else
8282 {
8283 for (uint32_t i = 0; i < cXmmRegs; i++)
8284 {
8285 pCompDst->aYmmHi[i].au64[0] = 0;
8286 pCompDst->aYmmHi[i].au64[1] = 0;
8287 }
8288 }
8289 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
8290 }
8291
8292 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8293 return VINF_SUCCESS;
8294}
8295
8296
8297
8298
8299/**
8300 * Implements 'STMXCSR'.
8301 *
8302 * @param GCPtrEff The address of the image.
8303 */
8304IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8305{
8306 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8307
8308 /*
8309 * Raise exceptions.
8310 */
8311 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8312 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
8313 {
8314 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8315 {
8316 /*
8317 * Do the job.
8318 */
8319 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR);
8320 if (rcStrict == VINF_SUCCESS)
8321 {
8322 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8323 return VINF_SUCCESS;
8324 }
8325 return rcStrict;
8326 }
8327 return iemRaiseDeviceNotAvailable(pVCpu);
8328 }
8329 return iemRaiseUndefinedOpcode(pVCpu);
8330}
8331
8332
8333/**
8334 * Implements 'VSTMXCSR'.
8335 *
8336 * @param GCPtrEff The address of the image.
8337 */
8338IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8339{
8340 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_XCRx);
8341
8342 /*
8343 * Raise exceptions.
8344 */
8345 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
8346 ? (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
8347 : !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
8348 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8349 {
8350 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8351 {
8352 /*
8353 * Do the job.
8354 */
8355 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR);
8356 if (rcStrict == VINF_SUCCESS)
8357 {
8358 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8359 return VINF_SUCCESS;
8360 }
8361 return rcStrict;
8362 }
8363 return iemRaiseDeviceNotAvailable(pVCpu);
8364 }
8365 return iemRaiseUndefinedOpcode(pVCpu);
8366}
8367
8368
8369/**
8370 * Implements 'LDMXCSR'.
8371 *
8372 * @param GCPtrEff The address of the image.
8373 */
8374IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8375{
8376 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8377
8378 /*
8379 * Raise exceptions.
8380 */
8381 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
8382 * happen after or before \#UD and \#EM? */
8383 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
8384 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
8385 {
8386 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
8387 {
8388 /*
8389 * Do the job.
8390 */
8391 uint32_t fNewMxCsr;
8392 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
8393 if (rcStrict == VINF_SUCCESS)
8394 {
8395 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8396 if (!(fNewMxCsr & ~fMxCsrMask))
8397 {
8398 pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87.MXCSR = fNewMxCsr;
8399 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8400 return VINF_SUCCESS;
8401 }
8402 Log(("lddmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
8403 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
8404 return iemRaiseGeneralProtectionFault0(pVCpu);
8405 }
8406 return rcStrict;
8407 }
8408 return iemRaiseDeviceNotAvailable(pVCpu);
8409 }
8410 return iemRaiseUndefinedOpcode(pVCpu);
8411}
8412
8413
8414/**
8415 * Commmon routine for fnstenv and fnsave.
8416 *
8417 * @param pVCpu The cross context virtual CPU structure of the calling thread.
8418 * @param enmEffOpSize The effective operand size.
8419 * @param uPtr Where to store the state.
8420 */
8421static void iemCImplCommonFpuStoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr)
8422{
8423 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8424 PCX86FXSTATE pSrcX87 = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8425 if (enmEffOpSize == IEMMODE_16BIT)
8426 {
8427 uPtr.pu16[0] = pSrcX87->FCW;
8428 uPtr.pu16[1] = pSrcX87->FSW;
8429 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
8430 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8431 {
8432 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
8433 * protected mode or long mode and we save it in real mode? And vice
8434 * versa? And with 32-bit operand size? I think CPU is storing the
8435 * effective address ((CS << 4) + IP) in the offset register and not
8436 * doing any address calculations here. */
8437 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
8438 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
8439 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
8440 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
8441 }
8442 else
8443 {
8444 uPtr.pu16[3] = pSrcX87->FPUIP;
8445 uPtr.pu16[4] = pSrcX87->CS;
8446 uPtr.pu16[5] = pSrcX87->FPUDP;
8447 uPtr.pu16[6] = pSrcX87->DS;
8448 }
8449 }
8450 else
8451 {
8452 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
8453 uPtr.pu16[0*2] = pSrcX87->FCW;
8454 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
8455 uPtr.pu16[1*2] = pSrcX87->FSW;
8456 uPtr.pu16[1*2+1] = 0xffff;
8457 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
8458 uPtr.pu16[2*2+1] = 0xffff;
8459 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8460 {
8461 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
8462 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
8463 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
8464 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
8465 }
8466 else
8467 {
8468 uPtr.pu32[3] = pSrcX87->FPUIP;
8469 uPtr.pu16[4*2] = pSrcX87->CS;
8470 uPtr.pu16[4*2+1] = pSrcX87->FOP;
8471 uPtr.pu32[5] = pSrcX87->FPUDP;
8472 uPtr.pu16[6*2] = pSrcX87->DS;
8473 uPtr.pu16[6*2+1] = 0xffff;
8474 }
8475 }
8476}
8477
8478
8479/**
8480 * Commmon routine for fldenv and frstor
8481 *
8482 * @param pVCpu The cross context virtual CPU structure of the calling thread.
8483 * @param enmEffOpSize The effective operand size.
8484 * @param uPtr Where to store the state.
8485 */
8486static void iemCImplCommonFpuRestoreEnv(PVMCPU pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr)
8487{
8488 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8489 PX86FXSTATE pDstX87 = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8490 if (enmEffOpSize == IEMMODE_16BIT)
8491 {
8492 pDstX87->FCW = uPtr.pu16[0];
8493 pDstX87->FSW = uPtr.pu16[1];
8494 pDstX87->FTW = uPtr.pu16[2];
8495 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8496 {
8497 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
8498 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
8499 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
8500 pDstX87->CS = 0;
8501 pDstX87->Rsrvd1= 0;
8502 pDstX87->DS = 0;
8503 pDstX87->Rsrvd2= 0;
8504 }
8505 else
8506 {
8507 pDstX87->FPUIP = uPtr.pu16[3];
8508 pDstX87->CS = uPtr.pu16[4];
8509 pDstX87->Rsrvd1= 0;
8510 pDstX87->FPUDP = uPtr.pu16[5];
8511 pDstX87->DS = uPtr.pu16[6];
8512 pDstX87->Rsrvd2= 0;
8513 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
8514 }
8515 }
8516 else
8517 {
8518 pDstX87->FCW = uPtr.pu16[0*2];
8519 pDstX87->FSW = uPtr.pu16[1*2];
8520 pDstX87->FTW = uPtr.pu16[2*2];
8521 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
8522 {
8523 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
8524 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
8525 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
8526 pDstX87->CS = 0;
8527 pDstX87->Rsrvd1= 0;
8528 pDstX87->DS = 0;
8529 pDstX87->Rsrvd2= 0;
8530 }
8531 else
8532 {
8533 pDstX87->FPUIP = uPtr.pu32[3];
8534 pDstX87->CS = uPtr.pu16[4*2];
8535 pDstX87->Rsrvd1= 0;
8536 pDstX87->FOP = uPtr.pu16[4*2+1];
8537 pDstX87->FPUDP = uPtr.pu32[5];
8538 pDstX87->DS = uPtr.pu16[6*2];
8539 pDstX87->Rsrvd2= 0;
8540 }
8541 }
8542
8543 /* Make adjustments. */
8544 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
8545 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
8546 iemFpuRecalcExceptionStatus(pDstX87);
8547 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
8548 * exceptions are pending after loading the saved state? */
8549}
8550
8551
8552/**
8553 * Implements 'FNSTENV'.
8554 *
8555 * @param enmEffOpSize The operand size (only REX.W really matters).
8556 * @param iEffSeg The effective segment register for @a GCPtrEff.
8557 * @param GCPtrEffDst The address of the image.
8558 */
8559IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8560{
8561 RTPTRUNION uPtr;
8562 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8563 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8564 if (rcStrict != VINF_SUCCESS)
8565 return rcStrict;
8566
8567 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
8568
8569 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8570 if (rcStrict != VINF_SUCCESS)
8571 return rcStrict;
8572
8573 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8574 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8575 return VINF_SUCCESS;
8576}
8577
8578
8579/**
8580 * Implements 'FNSAVE'.
8581 *
8582 * @param GCPtrEffDst The address of the image.
8583 * @param enmEffOpSize The operand size.
8584 */
8585IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
8586{
8587 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8588
8589 RTPTRUNION uPtr;
8590 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8591 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8592 if (rcStrict != VINF_SUCCESS)
8593 return rcStrict;
8594
8595 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8596 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
8597 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8598 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8599 {
8600 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
8601 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
8602 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
8603 }
8604
8605 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8606 if (rcStrict != VINF_SUCCESS)
8607 return rcStrict;
8608
8609 /*
8610 * Re-initialize the FPU context.
8611 */
8612 pFpuCtx->FCW = 0x37f;
8613 pFpuCtx->FSW = 0;
8614 pFpuCtx->FTW = 0x00; /* 0 - empty */
8615 pFpuCtx->FPUDP = 0;
8616 pFpuCtx->DS = 0;
8617 pFpuCtx->Rsrvd2= 0;
8618 pFpuCtx->FPUIP = 0;
8619 pFpuCtx->CS = 0;
8620 pFpuCtx->Rsrvd1= 0;
8621 pFpuCtx->FOP = 0;
8622
8623 iemHlpUsedFpu(pVCpu);
8624 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8625 return VINF_SUCCESS;
8626}
8627
8628
8629
8630/**
8631 * Implements 'FLDENV'.
8632 *
8633 * @param enmEffOpSize The operand size (only REX.W really matters).
8634 * @param iEffSeg The effective segment register for @a GCPtrEff.
8635 * @param GCPtrEffSrc The address of the image.
8636 */
8637IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8638{
8639 RTCPTRUNION uPtr;
8640 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
8641 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8642 if (rcStrict != VINF_SUCCESS)
8643 return rcStrict;
8644
8645 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
8646
8647 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8648 if (rcStrict != VINF_SUCCESS)
8649 return rcStrict;
8650
8651 iemHlpUsedFpu(pVCpu);
8652 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8653 return VINF_SUCCESS;
8654}
8655
8656
8657/**
8658 * Implements 'FRSTOR'.
8659 *
8660 * @param GCPtrEffSrc The address of the image.
8661 * @param enmEffOpSize The operand size.
8662 */
8663IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
8664{
8665 RTCPTRUNION uPtr;
8666 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
8667 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R);
8668 if (rcStrict != VINF_SUCCESS)
8669 return rcStrict;
8670
8671 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8672 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
8673 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
8674 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
8675 {
8676 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
8677 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
8678 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
8679 pFpuCtx->aRegs[i].au32[3] = 0;
8680 }
8681
8682 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
8683 if (rcStrict != VINF_SUCCESS)
8684 return rcStrict;
8685
8686 iemHlpUsedFpu(pVCpu);
8687 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8688 return VINF_SUCCESS;
8689}
8690
8691
8692/**
8693 * Implements 'FLDCW'.
8694 *
8695 * @param u16Fcw The new FCW.
8696 */
8697IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
8698{
8699 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8700
8701 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
8702 /** @todo Testcase: Try see what happens when trying to set undefined bits
8703 * (other than 6 and 7). Currently ignoring them. */
8704 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
8705 * according to FSW. (This is was is currently implemented.) */
8706 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8707 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
8708 iemFpuRecalcExceptionStatus(pFpuCtx);
8709
8710 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
8711 iemHlpUsedFpu(pVCpu);
8712 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8713 return VINF_SUCCESS;
8714}
8715
8716
8717
8718/**
8719 * Implements the underflow case of fxch.
8720 *
8721 * @param iStReg The other stack register.
8722 */
8723IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
8724{
8725 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8726
8727 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8728 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
8729 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8730 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
8731
8732 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
8733 * registers are read as QNaN and then exchanged. This could be
8734 * wrong... */
8735 if (pFpuCtx->FCW & X86_FCW_IM)
8736 {
8737 if (RT_BIT(iReg1) & pFpuCtx->FTW)
8738 {
8739 if (RT_BIT(iReg2) & pFpuCtx->FTW)
8740 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8741 else
8742 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
8743 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
8744 }
8745 else
8746 {
8747 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
8748 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
8749 }
8750 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
8751 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
8752 }
8753 else
8754 {
8755 /* raise underflow exception, don't change anything. */
8756 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
8757 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8758 }
8759
8760 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
8761 iemHlpUsedFpu(pVCpu);
8762 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8763 return VINF_SUCCESS;
8764}
8765
8766
8767/**
8768 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
8769 *
8770 * @param cToAdd 1 or 7.
8771 */
8772IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
8773{
8774 Assert(iStReg < 8);
8775 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
8776
8777 /*
8778 * Raise exceptions.
8779 */
8780 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
8781 return iemRaiseDeviceNotAvailable(pVCpu);
8782
8783 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.CTX_SUFF(pXState)->x87;
8784 uint16_t u16Fsw = pFpuCtx->FSW;
8785 if (u16Fsw & X86_FSW_ES)
8786 return iemRaiseMathFault(pVCpu);
8787
8788 /*
8789 * Check if any of the register accesses causes #SF + #IA.
8790 */
8791 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
8792 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
8793 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
8794 {
8795 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
8796 NOREF(u32Eflags);
8797
8798 pFpuCtx->FSW &= ~X86_FSW_C1;
8799 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
8800 if ( !(u16Fsw & X86_FSW_IE)
8801 || (pFpuCtx->FCW & X86_FCW_IM) )
8802 {
8803 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8804 pVCpu->cpum.GstCtx.eflags.u |= pVCpu->cpum.GstCtx.eflags.u & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8805 }
8806 }
8807 else if (pFpuCtx->FCW & X86_FCW_IM)
8808 {
8809 /* Masked underflow. */
8810 pFpuCtx->FSW &= ~X86_FSW_C1;
8811 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
8812 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
8813 pVCpu->cpum.GstCtx.eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
8814 }
8815 else
8816 {
8817 /* Raise underflow - don't touch EFLAGS or TOP. */
8818 pFpuCtx->FSW &= ~X86_FSW_C1;
8819 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
8820 fPop = false;
8821 }
8822
8823 /*
8824 * Pop if necessary.
8825 */
8826 if (fPop)
8827 {
8828 pFpuCtx->FTW &= ~RT_BIT(iReg1);
8829 pFpuCtx->FSW &= X86_FSW_TOP_MASK;
8830 pFpuCtx->FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
8831 }
8832
8833 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
8834 iemHlpUsedFpu(pVCpu);
8835 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8836 return VINF_SUCCESS;
8837}
8838
8839/** @} */
8840
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