VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp@ 97231

Last change on this file since 97231 was 97231, checked in by vboxsync, 2 years ago

VMM/CPUM: Define our own X86EFLAGS/X86RFLAGS structures so we can use reserved bits for internal state.
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1/* $Id: IEMAllCImpl.cpp 97231 2022-10-19 09:12:57Z vboxsync $ */
2/** @file
3 * IEM - Instruction Implementation in C/C++ (code include).
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_IEM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/apic.h>
37#include <VBox/vmm/pdm.h>
38#include <VBox/vmm/pgm.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/hm.h>
42#include <VBox/vmm/nem.h>
43#include <VBox/vmm/gim.h>
44#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
45# include <VBox/vmm/em.h>
46# include <VBox/vmm/hm_svm.h>
47#endif
48#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
49# include <VBox/vmm/hmvmxinline.h>
50#endif
51#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
52# include <VBox/vmm/cpuidcall.h>
53#endif
54#include <VBox/vmm/tm.h>
55#include <VBox/vmm/dbgf.h>
56#include <VBox/vmm/dbgftrace.h>
57#include "IEMInternal.h"
58#include <VBox/vmm/vmcc.h>
59#include <VBox/log.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62#include <VBox/dis.h>
63#include <VBox/disopcode.h>
64#include <iprt/asm-math.h>
65#include <iprt/assert.h>
66#include <iprt/string.h>
67#include <iprt/x86.h>
68
69#include "IEMInline.h"
70
71
72/** @name Misc Helpers
73 * @{
74 */
75
76
77/**
78 * Worker function for iemHlpCheckPortIOPermission, don't call directly.
79 *
80 * @returns Strict VBox status code.
81 *
82 * @param pVCpu The cross context virtual CPU structure of the calling thread.
83 * @param u16Port The port number.
84 * @param cbOperand The operand size.
85 */
86static VBOXSTRICTRC iemHlpCheckPortIOPermissionBitmap(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
87{
88 /* The TSS bits we're interested in are the same on 386 and AMD64. */
89 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_BUSY == X86_SEL_TYPE_SYS_386_TSS_BUSY);
90 AssertCompile(AMD64_SEL_TYPE_SYS_TSS_AVAIL == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
91 AssertCompileMembersAtSameOffset(X86TSS32, offIoBitmap, X86TSS64, offIoBitmap);
92 AssertCompile(sizeof(X86TSS32) == sizeof(X86TSS64));
93
94 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
95
96 /*
97 * Check the TSS type, 16-bit TSSes doesn't have any I/O permission bitmap.
98 */
99 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
100 if (RT_UNLIKELY( pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_BUSY
101 && pVCpu->cpum.GstCtx.tr.Attr.n.u4Type != AMD64_SEL_TYPE_SYS_TSS_AVAIL))
102 {
103 Log(("iemHlpCheckPortIOPermissionBitmap: Port=%#x cb=%d - TSS type %#x (attr=%#x) has no I/O bitmap -> #GP(0)\n",
104 u16Port, cbOperand, pVCpu->cpum.GstCtx.tr.Attr.n.u4Type, pVCpu->cpum.GstCtx.tr.Attr.u));
105 return iemRaiseGeneralProtectionFault0(pVCpu);
106 }
107
108 /*
109 * Read the bitmap offset (may #PF).
110 */
111 uint16_t offBitmap;
112 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &offBitmap, UINT8_MAX,
113 pVCpu->cpum.GstCtx.tr.u64Base + RT_UOFFSETOF(X86TSS64, offIoBitmap));
114 if (rcStrict != VINF_SUCCESS)
115 {
116 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading offIoBitmap (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
117 return rcStrict;
118 }
119
120 /*
121 * The bit range from u16Port to (u16Port + cbOperand - 1), however intel
122 * describes the CPU actually reading two bytes regardless of whether the
123 * bit range crosses a byte boundrary. Thus the + 1 in the test below.
124 */
125 uint32_t offFirstBit = (uint32_t)u16Port / 8 + offBitmap;
126 /** @todo check if real CPUs ensures that offBitmap has a minimum value of
127 * for instance sizeof(X86TSS32). */
128 if (offFirstBit + 1 > pVCpu->cpum.GstCtx.tr.u32Limit) /* the limit is inclusive */
129 {
130 Log(("iemHlpCheckPortIOPermissionBitmap: offFirstBit=%#x + 1 is beyond u32Limit=%#x -> #GP(0)\n",
131 offFirstBit, pVCpu->cpum.GstCtx.tr.u32Limit));
132 return iemRaiseGeneralProtectionFault0(pVCpu);
133 }
134
135 /*
136 * Read the necessary bits.
137 */
138 /** @todo Test the assertion in the intel manual that the CPU reads two
139 * bytes. The question is how this works wrt to \#PF and \#GP on the
140 * 2nd byte when it's not required. */
141 uint16_t bmBytes = UINT16_MAX;
142 rcStrict = iemMemFetchSysU16(pVCpu, &bmBytes, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base + offFirstBit);
143 if (rcStrict != VINF_SUCCESS)
144 {
145 Log(("iemHlpCheckPortIOPermissionBitmap: Error reading I/O bitmap @%#x (%Rrc)\n", offFirstBit, VBOXSTRICTRC_VAL(rcStrict)));
146 return rcStrict;
147 }
148
149 /*
150 * Perform the check.
151 */
152 uint16_t fPortMask = (1 << cbOperand) - 1;
153 bmBytes >>= (u16Port & 7);
154 if (bmBytes & fPortMask)
155 {
156 Log(("iemHlpCheckPortIOPermissionBitmap: u16Port=%#x LB %u - access denied (bm=%#x mask=%#x) -> #GP(0)\n",
157 u16Port, cbOperand, bmBytes, fPortMask));
158 return iemRaiseGeneralProtectionFault0(pVCpu);
159 }
160
161 return VINF_SUCCESS;
162}
163
164
165/**
166 * Checks if we are allowed to access the given I/O port, raising the
167 * appropriate exceptions if we aren't (or if the I/O bitmap is not
168 * accessible).
169 *
170 * @returns Strict VBox status code.
171 *
172 * @param pVCpu The cross context virtual CPU structure of the calling thread.
173 * @param u16Port The port number.
174 * @param cbOperand The operand size.
175 */
176DECLINLINE(VBOXSTRICTRC) iemHlpCheckPortIOPermission(PVMCPUCC pVCpu, uint16_t u16Port, uint8_t cbOperand)
177{
178 X86EFLAGS Efl;
179 Efl.u = IEMMISC_GET_EFL(pVCpu);
180 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
181 && ( pVCpu->iem.s.uCpl > Efl.Bits.u2IOPL
182 || Efl.Bits.u1VM) )
183 return iemHlpCheckPortIOPermissionBitmap(pVCpu, u16Port, cbOperand);
184 return VINF_SUCCESS;
185}
186
187
188#if 0
189/**
190 * Calculates the parity bit.
191 *
192 * @returns true if the bit is set, false if not.
193 * @param u8Result The least significant byte of the result.
194 */
195static bool iemHlpCalcParityFlag(uint8_t u8Result)
196{
197 /*
198 * Parity is set if the number of bits in the least significant byte of
199 * the result is even.
200 */
201 uint8_t cBits;
202 cBits = u8Result & 1; /* 0 */
203 u8Result >>= 1;
204 cBits += u8Result & 1;
205 u8Result >>= 1;
206 cBits += u8Result & 1;
207 u8Result >>= 1;
208 cBits += u8Result & 1;
209 u8Result >>= 1;
210 cBits += u8Result & 1; /* 4 */
211 u8Result >>= 1;
212 cBits += u8Result & 1;
213 u8Result >>= 1;
214 cBits += u8Result & 1;
215 u8Result >>= 1;
216 cBits += u8Result & 1;
217 return !(cBits & 1);
218}
219#endif /* not used */
220
221
222/**
223 * Updates the specified flags according to a 8-bit result.
224 *
225 * @param pVCpu The cross context virtual CPU structure of the calling thread.
226 * @param u8Result The result to set the flags according to.
227 * @param fToUpdate The flags to update.
228 * @param fUndefined The flags that are specified as undefined.
229 */
230static void iemHlpUpdateArithEFlagsU8(PVMCPUCC pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
231{
232 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
233 iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
234 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
235 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
236}
237
238
239/**
240 * Updates the specified flags according to a 16-bit result.
241 *
242 * @param pVCpu The cross context virtual CPU structure of the calling thread.
243 * @param u16Result The result to set the flags according to.
244 * @param fToUpdate The flags to update.
245 * @param fUndefined The flags that are specified as undefined.
246 */
247static void iemHlpUpdateArithEFlagsU16(PVMCPUCC pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
248{
249 uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
250 iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
251 pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
252 pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
253}
254
255
256/**
257 * Helper used by iret.
258 *
259 * @param pVCpu The cross context virtual CPU structure of the calling thread.
260 * @param uCpl The new CPL.
261 * @param pSReg Pointer to the segment register.
262 */
263static void iemHlpAdjustSelectorForNewCpl(PVMCPUCC pVCpu, uint8_t uCpl, PCPUMSELREG pSReg)
264{
265 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
266 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
267
268 if ( uCpl > pSReg->Attr.n.u2Dpl
269 && pSReg->Attr.n.u1DescType /* code or data, not system */
270 && (pSReg->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
271 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) /* not conforming code */
272 iemHlpLoadNullDataSelectorProt(pVCpu, pSReg, 0);
273}
274
275
276/**
277 * Indicates that we have modified the FPU state.
278 *
279 * @param pVCpu The cross context virtual CPU structure of the calling thread.
280 */
281DECLINLINE(void) iemHlpUsedFpu(PVMCPUCC pVCpu)
282{
283 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
284}
285
286/** @} */
287
288/** @name C Implementations
289 * @{
290 */
291
292/**
293 * Implements a 16-bit popa.
294 */
295IEM_CIMPL_DEF_0(iemCImpl_popa_16)
296{
297 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
298 RTGCPTR GCPtrLast = GCPtrStart + 15;
299 VBOXSTRICTRC rcStrict;
300
301 /*
302 * The docs are a bit hard to comprehend here, but it looks like we wrap
303 * around in real mode as long as none of the individual "popa" crosses the
304 * end of the stack segment. In protected mode we check the whole access
305 * in one go. For efficiency, only do the word-by-word thing if we're in
306 * danger of wrapping around.
307 */
308 /** @todo do popa boundary / wrap-around checks. */
309 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
310 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
311 {
312 /* word-by-word */
313 RTUINT64U TmpRsp;
314 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
315 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.di, &TmpRsp);
316 if (rcStrict == VINF_SUCCESS)
317 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.si, &TmpRsp);
318 if (rcStrict == VINF_SUCCESS)
319 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bp, &TmpRsp);
320 if (rcStrict == VINF_SUCCESS)
321 {
322 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
323 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.bx, &TmpRsp);
324 }
325 if (rcStrict == VINF_SUCCESS)
326 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.dx, &TmpRsp);
327 if (rcStrict == VINF_SUCCESS)
328 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.cx, &TmpRsp);
329 if (rcStrict == VINF_SUCCESS)
330 rcStrict = iemMemStackPopU16Ex(pVCpu, &pVCpu->cpum.GstCtx.ax, &TmpRsp);
331 if (rcStrict == VINF_SUCCESS)
332 {
333 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
334 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
335 }
336 }
337 else
338 {
339 uint16_t const *pa16Mem = NULL;
340 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa16Mem) - 1);
341 if (rcStrict == VINF_SUCCESS)
342 {
343 pVCpu->cpum.GstCtx.di = pa16Mem[7 - X86_GREG_xDI];
344 pVCpu->cpum.GstCtx.si = pa16Mem[7 - X86_GREG_xSI];
345 pVCpu->cpum.GstCtx.bp = pa16Mem[7 - X86_GREG_xBP];
346 /* skip sp */
347 pVCpu->cpum.GstCtx.bx = pa16Mem[7 - X86_GREG_xBX];
348 pVCpu->cpum.GstCtx.dx = pa16Mem[7 - X86_GREG_xDX];
349 pVCpu->cpum.GstCtx.cx = pa16Mem[7 - X86_GREG_xCX];
350 pVCpu->cpum.GstCtx.ax = pa16Mem[7 - X86_GREG_xAX];
351 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_R);
352 if (rcStrict == VINF_SUCCESS)
353 {
354 iemRegAddToRsp(pVCpu, 16);
355 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
356 }
357 }
358 }
359 return rcStrict;
360}
361
362
363/**
364 * Implements a 32-bit popa.
365 */
366IEM_CIMPL_DEF_0(iemCImpl_popa_32)
367{
368 RTGCPTR GCPtrStart = iemRegGetEffRsp(pVCpu);
369 RTGCPTR GCPtrLast = GCPtrStart + 31;
370 VBOXSTRICTRC rcStrict;
371
372 /*
373 * The docs are a bit hard to comprehend here, but it looks like we wrap
374 * around in real mode as long as none of the individual "popa" crosses the
375 * end of the stack segment. In protected mode we check the whole access
376 * in one go. For efficiency, only do the word-by-word thing if we're in
377 * danger of wrapping around.
378 */
379 /** @todo do popa boundary / wrap-around checks. */
380 if (RT_UNLIKELY( IEM_IS_REAL_OR_V86_MODE(pVCpu)
381 && (pVCpu->cpum.GstCtx.cs.u32Limit < GCPtrLast)) ) /* ASSUMES 64-bit RTGCPTR */
382 {
383 /* word-by-word */
384 RTUINT64U TmpRsp;
385 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
386 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edi, &TmpRsp);
387 if (rcStrict == VINF_SUCCESS)
388 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.esi, &TmpRsp);
389 if (rcStrict == VINF_SUCCESS)
390 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebp, &TmpRsp);
391 if (rcStrict == VINF_SUCCESS)
392 {
393 iemRegAddToRspEx(pVCpu, &TmpRsp, 2); /* sp */
394 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ebx, &TmpRsp);
395 }
396 if (rcStrict == VINF_SUCCESS)
397 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.edx, &TmpRsp);
398 if (rcStrict == VINF_SUCCESS)
399 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.ecx, &TmpRsp);
400 if (rcStrict == VINF_SUCCESS)
401 rcStrict = iemMemStackPopU32Ex(pVCpu, &pVCpu->cpum.GstCtx.eax, &TmpRsp);
402 if (rcStrict == VINF_SUCCESS)
403 {
404#if 1 /** @todo what actually happens with the high bits when we're in 16-bit mode? */
405 pVCpu->cpum.GstCtx.rdi &= UINT32_MAX;
406 pVCpu->cpum.GstCtx.rsi &= UINT32_MAX;
407 pVCpu->cpum.GstCtx.rbp &= UINT32_MAX;
408 pVCpu->cpum.GstCtx.rbx &= UINT32_MAX;
409 pVCpu->cpum.GstCtx.rdx &= UINT32_MAX;
410 pVCpu->cpum.GstCtx.rcx &= UINT32_MAX;
411 pVCpu->cpum.GstCtx.rax &= UINT32_MAX;
412#endif
413 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
414 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
415 }
416 }
417 else
418 {
419 uint32_t const *pa32Mem;
420 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrStart, IEM_ACCESS_STACK_R, sizeof(*pa32Mem) - 1);
421 if (rcStrict == VINF_SUCCESS)
422 {
423 pVCpu->cpum.GstCtx.rdi = pa32Mem[7 - X86_GREG_xDI];
424 pVCpu->cpum.GstCtx.rsi = pa32Mem[7 - X86_GREG_xSI];
425 pVCpu->cpum.GstCtx.rbp = pa32Mem[7 - X86_GREG_xBP];
426 /* skip esp */
427 pVCpu->cpum.GstCtx.rbx = pa32Mem[7 - X86_GREG_xBX];
428 pVCpu->cpum.GstCtx.rdx = pa32Mem[7 - X86_GREG_xDX];
429 pVCpu->cpum.GstCtx.rcx = pa32Mem[7 - X86_GREG_xCX];
430 pVCpu->cpum.GstCtx.rax = pa32Mem[7 - X86_GREG_xAX];
431 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa32Mem, IEM_ACCESS_STACK_R);
432 if (rcStrict == VINF_SUCCESS)
433 {
434 iemRegAddToRsp(pVCpu, 32);
435 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
436 }
437 }
438 }
439 return rcStrict;
440}
441
442
443/**
444 * Implements a 16-bit pusha.
445 */
446IEM_CIMPL_DEF_0(iemCImpl_pusha_16)
447{
448 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
449 RTGCPTR GCPtrBottom = GCPtrTop - 15;
450 VBOXSTRICTRC rcStrict;
451
452 /*
453 * The docs are a bit hard to comprehend here, but it looks like we wrap
454 * around in real mode as long as none of the individual "pushd" crosses the
455 * end of the stack segment. In protected mode we check the whole access
456 * in one go. For efficiency, only do the word-by-word thing if we're in
457 * danger of wrapping around.
458 */
459 /** @todo do pusha boundary / wrap-around checks. */
460 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
461 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
462 {
463 /* word-by-word */
464 RTUINT64U TmpRsp;
465 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
466 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.ax, &TmpRsp);
467 if (rcStrict == VINF_SUCCESS)
468 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.cx, &TmpRsp);
469 if (rcStrict == VINF_SUCCESS)
470 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.dx, &TmpRsp);
471 if (rcStrict == VINF_SUCCESS)
472 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bx, &TmpRsp);
473 if (rcStrict == VINF_SUCCESS)
474 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.sp, &TmpRsp);
475 if (rcStrict == VINF_SUCCESS)
476 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.bp, &TmpRsp);
477 if (rcStrict == VINF_SUCCESS)
478 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.si, &TmpRsp);
479 if (rcStrict == VINF_SUCCESS)
480 rcStrict = iemMemStackPushU16Ex(pVCpu, pVCpu->cpum.GstCtx.di, &TmpRsp);
481 if (rcStrict == VINF_SUCCESS)
482 {
483 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
484 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
485 }
486 }
487 else
488 {
489 GCPtrBottom--;
490 uint16_t *pa16Mem = NULL;
491 rcStrict = iemMemMap(pVCpu, (void **)&pa16Mem, 16, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa16Mem) - 1);
492 if (rcStrict == VINF_SUCCESS)
493 {
494 pa16Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.di;
495 pa16Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.si;
496 pa16Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.bp;
497 pa16Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.sp;
498 pa16Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.bx;
499 pa16Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.dx;
500 pa16Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.cx;
501 pa16Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.ax;
502 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pa16Mem, IEM_ACCESS_STACK_W);
503 if (rcStrict == VINF_SUCCESS)
504 {
505 iemRegSubFromRsp(pVCpu, 16);
506 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
507 }
508 }
509 }
510 return rcStrict;
511}
512
513
514/**
515 * Implements a 32-bit pusha.
516 */
517IEM_CIMPL_DEF_0(iemCImpl_pusha_32)
518{
519 RTGCPTR GCPtrTop = iemRegGetEffRsp(pVCpu);
520 RTGCPTR GCPtrBottom = GCPtrTop - 31;
521 VBOXSTRICTRC rcStrict;
522
523 /*
524 * The docs are a bit hard to comprehend here, but it looks like we wrap
525 * around in real mode as long as none of the individual "pusha" crosses the
526 * end of the stack segment. In protected mode we check the whole access
527 * in one go. For efficiency, only do the word-by-word thing if we're in
528 * danger of wrapping around.
529 */
530 /** @todo do pusha boundary / wrap-around checks. */
531 if (RT_UNLIKELY( GCPtrBottom > GCPtrTop
532 && IEM_IS_REAL_OR_V86_MODE(pVCpu) ) )
533 {
534 /* word-by-word */
535 RTUINT64U TmpRsp;
536 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
537 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.eax, &TmpRsp);
538 if (rcStrict == VINF_SUCCESS)
539 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ecx, &TmpRsp);
540 if (rcStrict == VINF_SUCCESS)
541 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edx, &TmpRsp);
542 if (rcStrict == VINF_SUCCESS)
543 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebx, &TmpRsp);
544 if (rcStrict == VINF_SUCCESS)
545 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esp, &TmpRsp);
546 if (rcStrict == VINF_SUCCESS)
547 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.ebp, &TmpRsp);
548 if (rcStrict == VINF_SUCCESS)
549 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.esi, &TmpRsp);
550 if (rcStrict == VINF_SUCCESS)
551 rcStrict = iemMemStackPushU32Ex(pVCpu, pVCpu->cpum.GstCtx.edi, &TmpRsp);
552 if (rcStrict == VINF_SUCCESS)
553 {
554 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
555 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
556 }
557 }
558 else
559 {
560 GCPtrBottom--;
561 uint32_t *pa32Mem;
562 rcStrict = iemMemMap(pVCpu, (void **)&pa32Mem, 32, X86_SREG_SS, GCPtrBottom, IEM_ACCESS_STACK_W, sizeof(*pa32Mem) - 1);
563 if (rcStrict == VINF_SUCCESS)
564 {
565 pa32Mem[7 - X86_GREG_xDI] = pVCpu->cpum.GstCtx.edi;
566 pa32Mem[7 - X86_GREG_xSI] = pVCpu->cpum.GstCtx.esi;
567 pa32Mem[7 - X86_GREG_xBP] = pVCpu->cpum.GstCtx.ebp;
568 pa32Mem[7 - X86_GREG_xSP] = pVCpu->cpum.GstCtx.esp;
569 pa32Mem[7 - X86_GREG_xBX] = pVCpu->cpum.GstCtx.ebx;
570 pa32Mem[7 - X86_GREG_xDX] = pVCpu->cpum.GstCtx.edx;
571 pa32Mem[7 - X86_GREG_xCX] = pVCpu->cpum.GstCtx.ecx;
572 pa32Mem[7 - X86_GREG_xAX] = pVCpu->cpum.GstCtx.eax;
573 rcStrict = iemMemCommitAndUnmap(pVCpu, pa32Mem, IEM_ACCESS_STACK_W);
574 if (rcStrict == VINF_SUCCESS)
575 {
576 iemRegSubFromRsp(pVCpu, 32);
577 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
578 }
579 }
580 }
581 return rcStrict;
582}
583
584
585/**
586 * Implements pushf.
587 *
588 *
589 * @param enmEffOpSize The effective operand size.
590 */
591IEM_CIMPL_DEF_1(iemCImpl_pushf, IEMMODE, enmEffOpSize)
592{
593 VBOXSTRICTRC rcStrict;
594
595 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_PUSHF))
596 {
597 Log2(("pushf: Guest intercept -> #VMEXIT\n"));
598 IEM_SVM_UPDATE_NRIP(pVCpu);
599 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_PUSHF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
600 }
601
602 /*
603 * If we're in V8086 mode some care is required (which is why we're in
604 * doing this in a C implementation).
605 */
606 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
607 if ( (fEfl & X86_EFL_VM)
608 && X86_EFL_GET_IOPL(fEfl) != 3 )
609 {
610 Assert(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE);
611 if ( enmEffOpSize != IEMMODE_16BIT
612 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
613 return iemRaiseGeneralProtectionFault0(pVCpu);
614 fEfl &= ~X86_EFL_IF; /* (RF and VM are out of range) */
615 fEfl |= (fEfl & X86_EFL_VIF) >> (19 - 9);
616 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
617 }
618 else
619 {
620
621 /*
622 * Ok, clear RF and VM, adjust for ancient CPUs, and push the flags.
623 */
624 fEfl &= ~(X86_EFL_RF | X86_EFL_VM);
625
626 switch (enmEffOpSize)
627 {
628 case IEMMODE_16BIT:
629 AssertCompile(IEMTARGETCPU_8086 <= IEMTARGETCPU_186 && IEMTARGETCPU_V20 <= IEMTARGETCPU_186 && IEMTARGETCPU_286 > IEMTARGETCPU_186);
630 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_186)
631 fEfl |= UINT16_C(0xf000);
632 rcStrict = iemMemStackPushU16(pVCpu, (uint16_t)fEfl);
633 break;
634 case IEMMODE_32BIT:
635 rcStrict = iemMemStackPushU32(pVCpu, fEfl);
636 break;
637 case IEMMODE_64BIT:
638 rcStrict = iemMemStackPushU64(pVCpu, fEfl);
639 break;
640 IEM_NOT_REACHED_DEFAULT_CASE_RET();
641 }
642 }
643 if (rcStrict != VINF_SUCCESS)
644 return rcStrict;
645
646 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
647 return VINF_SUCCESS;
648}
649
650
651/**
652 * Implements popf.
653 *
654 * @param enmEffOpSize The effective operand size.
655 */
656IEM_CIMPL_DEF_1(iemCImpl_popf, IEMMODE, enmEffOpSize)
657{
658 uint32_t const fEflOld = IEMMISC_GET_EFL(pVCpu);
659 VBOXSTRICTRC rcStrict;
660 uint32_t fEflNew;
661
662 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_POPF))
663 {
664 Log2(("popf: Guest intercept -> #VMEXIT\n"));
665 IEM_SVM_UPDATE_NRIP(pVCpu);
666 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_POPF, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
667 }
668
669 /*
670 * V8086 is special as usual.
671 */
672 if (fEflOld & X86_EFL_VM)
673 {
674 /*
675 * Almost anything goes if IOPL is 3.
676 */
677 if (X86_EFL_GET_IOPL(fEflOld) == 3)
678 {
679 switch (enmEffOpSize)
680 {
681 case IEMMODE_16BIT:
682 {
683 uint16_t u16Value;
684 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
685 if (rcStrict != VINF_SUCCESS)
686 return rcStrict;
687 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
688 break;
689 }
690 case IEMMODE_32BIT:
691 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
692 if (rcStrict != VINF_SUCCESS)
693 return rcStrict;
694 break;
695 IEM_NOT_REACHED_DEFAULT_CASE_RET();
696 }
697
698 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
699 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
700 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
701 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
702 }
703 /*
704 * Interrupt flag virtualization with CR4.VME=1.
705 */
706 else if ( enmEffOpSize == IEMMODE_16BIT
707 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
708 {
709 uint16_t u16Value;
710 RTUINT64U TmpRsp;
711 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
712 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Value, &TmpRsp);
713 if (rcStrict != VINF_SUCCESS)
714 return rcStrict;
715
716 /** @todo Is the popf VME \#GP(0) delivered after updating RSP+RIP
717 * or before? */
718 if ( ( (u16Value & X86_EFL_IF)
719 && (fEflOld & X86_EFL_VIP))
720 || (u16Value & X86_EFL_TF) )
721 return iemRaiseGeneralProtectionFault0(pVCpu);
722
723 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000) & ~X86_EFL_VIF);
724 fEflNew |= (fEflNew & X86_EFL_IF) << (19 - 9);
725 fEflNew &= X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
726 fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
727
728 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
729 }
730 else
731 return iemRaiseGeneralProtectionFault0(pVCpu);
732
733 }
734 /*
735 * Not in V8086 mode.
736 */
737 else
738 {
739 /* Pop the flags. */
740 switch (enmEffOpSize)
741 {
742 case IEMMODE_16BIT:
743 {
744 uint16_t u16Value;
745 rcStrict = iemMemStackPopU16(pVCpu, &u16Value);
746 if (rcStrict != VINF_SUCCESS)
747 return rcStrict;
748 fEflNew = u16Value | (fEflOld & UINT32_C(0xffff0000));
749
750 /*
751 * Ancient CPU adjustments:
752 * - 8086, 80186, V20/30:
753 * Fixed bits 15:12 bits are not kept correctly internally, mostly for
754 * practical reasons (masking below). We add them when pushing flags.
755 * - 80286:
756 * The NT and IOPL flags cannot be popped from real mode and are
757 * therefore always zero (since a 286 can never exit from PM and
758 * their initial value is zero). This changed on a 386 and can
759 * therefore be used to detect 286 or 386 CPU in real mode.
760 */
761 if ( IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286
762 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
763 fEflNew &= ~(X86_EFL_NT | X86_EFL_IOPL);
764 break;
765 }
766 case IEMMODE_32BIT:
767 rcStrict = iemMemStackPopU32(pVCpu, &fEflNew);
768 if (rcStrict != VINF_SUCCESS)
769 return rcStrict;
770 break;
771 case IEMMODE_64BIT:
772 {
773 uint64_t u64Value;
774 rcStrict = iemMemStackPopU64(pVCpu, &u64Value);
775 if (rcStrict != VINF_SUCCESS)
776 return rcStrict;
777 fEflNew = u64Value; /** @todo testcase: Check exactly what happens if high bits are set. */
778 break;
779 }
780 IEM_NOT_REACHED_DEFAULT_CASE_RET();
781 }
782
783 /* Merge them with the current flags. */
784 const uint32_t fPopfBits = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
785 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
786 if ( (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
787 || pVCpu->iem.s.uCpl == 0)
788 {
789 fEflNew &= fPopfBits;
790 fEflNew |= ~fPopfBits & fEflOld;
791 }
792 else if (pVCpu->iem.s.uCpl <= X86_EFL_GET_IOPL(fEflOld))
793 {
794 fEflNew &= fPopfBits & ~(X86_EFL_IOPL);
795 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
796 }
797 else
798 {
799 fEflNew &= fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
800 fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
801 }
802 }
803
804 /*
805 * Commit the flags.
806 */
807 Assert(fEflNew & RT_BIT_32(1));
808 IEMMISC_SET_EFL(pVCpu, fEflNew);
809 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
810
811 return VINF_SUCCESS;
812}
813
814
815/**
816 * Implements an indirect call.
817 *
818 * @param uNewPC The new program counter (RIP) value (loaded from the
819 * operand).
820 */
821IEM_CIMPL_DEF_1(iemCImpl_call_16, uint16_t, uNewPC)
822{
823 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
824 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
825 return iemRaiseGeneralProtectionFault0(pVCpu);
826
827 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
828 if (rcStrict != VINF_SUCCESS)
829 return rcStrict;
830
831 pVCpu->cpum.GstCtx.rip = uNewPC;
832 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
833
834#ifndef IEM_WITH_CODE_TLB
835 /* Flush the prefetch buffer. */
836 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
837#endif
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Implements a 16-bit relative call.
844 *
845 * @param offDisp The displacment offset.
846 */
847IEM_CIMPL_DEF_1(iemCImpl_call_rel_16, int16_t, offDisp)
848{
849 uint16_t uOldPC = pVCpu->cpum.GstCtx.ip + cbInstr;
850 uint16_t uNewPC = uOldPC + offDisp;
851 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
852 return iemRaiseGeneralProtectionFault0(pVCpu);
853
854 VBOXSTRICTRC rcStrict = iemMemStackPushU16(pVCpu, uOldPC);
855 if (rcStrict != VINF_SUCCESS)
856 return rcStrict;
857
858 pVCpu->cpum.GstCtx.rip = uNewPC;
859 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
860
861#ifndef IEM_WITH_CODE_TLB
862 /* Flush the prefetch buffer. */
863 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
864#endif
865 return VINF_SUCCESS;
866}
867
868
869/**
870 * Implements a 32-bit indirect call.
871 *
872 * @param uNewPC The new program counter (RIP) value (loaded from the
873 * operand).
874 */
875IEM_CIMPL_DEF_1(iemCImpl_call_32, uint32_t, uNewPC)
876{
877 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
878 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
879 return iemRaiseGeneralProtectionFault0(pVCpu);
880
881 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
882 if (rcStrict != VINF_SUCCESS)
883 return rcStrict;
884
885 pVCpu->cpum.GstCtx.rip = uNewPC;
886 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
887
888#ifndef IEM_WITH_CODE_TLB
889 /* Flush the prefetch buffer. */
890 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
891#endif
892 return VINF_SUCCESS;
893}
894
895
896/**
897 * Implements a 32-bit relative call.
898 *
899 * @param offDisp The displacment offset.
900 */
901IEM_CIMPL_DEF_1(iemCImpl_call_rel_32, int32_t, offDisp)
902{
903 uint32_t uOldPC = pVCpu->cpum.GstCtx.eip + cbInstr;
904 uint32_t uNewPC = uOldPC + offDisp;
905 if (uNewPC > pVCpu->cpum.GstCtx.cs.u32Limit)
906 return iemRaiseGeneralProtectionFault0(pVCpu);
907
908 VBOXSTRICTRC rcStrict = iemMemStackPushU32(pVCpu, uOldPC);
909 if (rcStrict != VINF_SUCCESS)
910 return rcStrict;
911
912 pVCpu->cpum.GstCtx.rip = uNewPC;
913 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
914
915#ifndef IEM_WITH_CODE_TLB
916 /* Flush the prefetch buffer. */
917 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
918#endif
919 return VINF_SUCCESS;
920}
921
922
923/**
924 * Implements a 64-bit indirect call.
925 *
926 * @param uNewPC The new program counter (RIP) value (loaded from the
927 * operand).
928 */
929IEM_CIMPL_DEF_1(iemCImpl_call_64, uint64_t, uNewPC)
930{
931 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
932 if (!IEM_IS_CANONICAL(uNewPC))
933 return iemRaiseGeneralProtectionFault0(pVCpu);
934
935 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
936 if (rcStrict != VINF_SUCCESS)
937 return rcStrict;
938
939 pVCpu->cpum.GstCtx.rip = uNewPC;
940 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
941
942#ifndef IEM_WITH_CODE_TLB
943 /* Flush the prefetch buffer. */
944 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
945#endif
946 return VINF_SUCCESS;
947}
948
949
950/**
951 * Implements a 64-bit relative call.
952 *
953 * @param offDisp The displacment offset.
954 */
955IEM_CIMPL_DEF_1(iemCImpl_call_rel_64, int64_t, offDisp)
956{
957 uint64_t uOldPC = pVCpu->cpum.GstCtx.rip + cbInstr;
958 uint64_t uNewPC = uOldPC + offDisp;
959 if (!IEM_IS_CANONICAL(uNewPC))
960 return iemRaiseNotCanonical(pVCpu);
961
962 VBOXSTRICTRC rcStrict = iemMemStackPushU64(pVCpu, uOldPC);
963 if (rcStrict != VINF_SUCCESS)
964 return rcStrict;
965
966 pVCpu->cpum.GstCtx.rip = uNewPC;
967 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
968
969#ifndef IEM_WITH_CODE_TLB
970 /* Flush the prefetch buffer. */
971 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
972#endif
973
974 return VINF_SUCCESS;
975}
976
977
978/**
979 * Implements far jumps and calls thru task segments (TSS).
980 *
981 * @param uSel The selector.
982 * @param enmBranch The kind of branching we're performing.
983 * @param enmEffOpSize The effective operand size.
984 * @param pDesc The descriptor corresponding to @a uSel. The type is
985 * task gate.
986 */
987IEM_CIMPL_DEF_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
988{
989#ifndef IEM_IMPLEMENTS_TASKSWITCH
990 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
991#else
992 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
993 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL
994 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL);
995 RT_NOREF_PV(enmEffOpSize);
996 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
997
998 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
999 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1000 {
1001 Log(("BranchTaskSegment invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1002 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1003 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1004 }
1005
1006 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1007 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1008 * checked here, need testcases. */
1009 if (!pDesc->Legacy.Gen.u1Present)
1010 {
1011 Log(("BranchTaskSegment TSS not present uSel=%04x -> #NP\n", uSel));
1012 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1013 }
1014
1015 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1016 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1017 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSel, pDesc);
1018#endif
1019}
1020
1021
1022/**
1023 * Implements far jumps and calls thru task gates.
1024 *
1025 * @param uSel The selector.
1026 * @param enmBranch The kind of branching we're performing.
1027 * @param enmEffOpSize The effective operand size.
1028 * @param pDesc The descriptor corresponding to @a uSel. The type is
1029 * task gate.
1030 */
1031IEM_CIMPL_DEF_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1032{
1033#ifndef IEM_IMPLEMENTS_TASKSWITCH
1034 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1035#else
1036 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1037 RT_NOREF_PV(enmEffOpSize);
1038 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1039
1040 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1041 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1042 {
1043 Log(("BranchTaskGate invalid priv. uSel=%04x TSS DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1044 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1045 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1046 }
1047
1048 /** @todo This is checked earlier for far jumps (see iemCImpl_FarJmp) but not
1049 * far calls (see iemCImpl_callf). Most likely in both cases it should be
1050 * checked here, need testcases. */
1051 if (!pDesc->Legacy.Gen.u1Present)
1052 {
1053 Log(("BranchTaskSegment segment not present uSel=%04x -> #NP\n", uSel));
1054 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1055 }
1056
1057 /*
1058 * Fetch the new TSS descriptor from the GDT.
1059 */
1060 RTSEL uSelTss = pDesc->Legacy.Gate.u16Sel;
1061 if (uSelTss & X86_SEL_LDT)
1062 {
1063 Log(("BranchTaskGate TSS is in LDT. uSel=%04x uSelTss=%04x -> #GP\n", uSel, uSelTss));
1064 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1065 }
1066
1067 IEMSELDESC TssDesc;
1068 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelTss, X86_XCPT_GP);
1069 if (rcStrict != VINF_SUCCESS)
1070 return rcStrict;
1071
1072 if (TssDesc.Legacy.Gate.u4Type & X86_SEL_TYPE_SYS_TSS_BUSY_MASK)
1073 {
1074 Log(("BranchTaskGate TSS is busy. uSel=%04x uSelTss=%04x DescType=%#x -> #GP\n", uSel, uSelTss,
1075 TssDesc.Legacy.Gate.u4Type));
1076 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel & X86_SEL_MASK_OFF_RPL);
1077 }
1078
1079 if (!TssDesc.Legacy.Gate.u1Present)
1080 {
1081 Log(("BranchTaskGate TSS is not present. uSel=%04x uSelTss=%04x -> #NP\n", uSel, uSelTss));
1082 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelTss & X86_SEL_MASK_OFF_RPL);
1083 }
1084
1085 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
1086 return iemTaskSwitch(pVCpu, enmBranch == IEMBRANCH_JUMP ? IEMTASKSWITCH_JUMP : IEMTASKSWITCH_CALL,
1087 uNextEip, 0 /* fFlags */, 0 /* uErr */, 0 /* uCr2 */, uSelTss, &TssDesc);
1088#endif
1089}
1090
1091
1092/**
1093 * Implements far jumps and calls thru call gates.
1094 *
1095 * @param uSel The selector.
1096 * @param enmBranch The kind of branching we're performing.
1097 * @param enmEffOpSize The effective operand size.
1098 * @param pDesc The descriptor corresponding to @a uSel. The type is
1099 * call gate.
1100 */
1101IEM_CIMPL_DEF_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1102{
1103#define IEM_IMPLEMENTS_CALLGATE
1104#ifndef IEM_IMPLEMENTS_CALLGATE
1105 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
1106#else
1107 RT_NOREF_PV(enmEffOpSize);
1108 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1109
1110 /* NB: Far jumps can only do intra-privilege transfers. Far calls support
1111 * inter-privilege calls and are much more complex.
1112 *
1113 * NB: 64-bit call gate has the same type as a 32-bit call gate! If
1114 * EFER.LMA=1, the gate must be 64-bit. Conversely if EFER.LMA=0, the gate
1115 * must be 16-bit or 32-bit.
1116 */
1117 /** @todo effective operand size is probably irrelevant here, only the
1118 * call gate bitness matters??
1119 */
1120 VBOXSTRICTRC rcStrict;
1121 RTPTRUNION uPtrRet;
1122 uint64_t uNewRsp;
1123 uint64_t uNewRip;
1124 uint64_t u64Base;
1125 uint32_t cbLimit;
1126 RTSEL uNewCS;
1127 IEMSELDESC DescCS;
1128
1129 AssertCompile(X86_SEL_TYPE_SYS_386_CALL_GATE == AMD64_SEL_TYPE_SYS_CALL_GATE);
1130 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1131 Assert( pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE
1132 || pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE);
1133
1134 /* Determine the new instruction pointer from the gate descriptor. */
1135 uNewRip = pDesc->Legacy.Gate.u16OffsetLow
1136 | ((uint32_t)pDesc->Legacy.Gate.u16OffsetHigh << 16)
1137 | ((uint64_t)pDesc->Long.Gate.u32OffsetTop << 32);
1138
1139 /* Perform DPL checks on the gate descriptor. */
1140 if ( pDesc->Legacy.Gate.u2Dpl < pVCpu->iem.s.uCpl
1141 || pDesc->Legacy.Gate.u2Dpl < (uSel & X86_SEL_RPL))
1142 {
1143 Log(("BranchCallGate invalid priv. uSel=%04x Gate DPL=%d CPL=%u Sel RPL=%u -> #GP\n", uSel, pDesc->Legacy.Gate.u2Dpl,
1144 pVCpu->iem.s.uCpl, (uSel & X86_SEL_RPL)));
1145 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1146 }
1147
1148 /** @todo does this catch NULL selectors, too? */
1149 if (!pDesc->Legacy.Gen.u1Present)
1150 {
1151 Log(("BranchCallGate Gate not present uSel=%04x -> #NP\n", uSel));
1152 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1153 }
1154
1155 /*
1156 * Fetch the target CS descriptor from the GDT or LDT.
1157 */
1158 uNewCS = pDesc->Legacy.Gate.u16Sel;
1159 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCS, X86_XCPT_GP);
1160 if (rcStrict != VINF_SUCCESS)
1161 return rcStrict;
1162
1163 /* Target CS must be a code selector. */
1164 if ( !DescCS.Legacy.Gen.u1DescType
1165 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
1166 {
1167 Log(("BranchCallGate %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
1168 uNewCS, uNewRip, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
1169 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1170 }
1171
1172 /* Privilege checks on target CS. */
1173 if (enmBranch == IEMBRANCH_JUMP)
1174 {
1175 if (DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1176 {
1177 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1178 {
1179 Log(("BranchCallGate jump (conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1180 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1181 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1182 }
1183 }
1184 else
1185 {
1186 if (DescCS.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
1187 {
1188 Log(("BranchCallGate jump (non-conforming) bad DPL uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1189 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1190 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1191 }
1192 }
1193 }
1194 else
1195 {
1196 Assert(enmBranch == IEMBRANCH_CALL);
1197 if (DescCS.Legacy.Gen.u2Dpl > pVCpu->iem.s.uCpl)
1198 {
1199 Log(("BranchCallGate call invalid priv. uNewCS=%04x Gate DPL=%d CPL=%u -> #GP\n",
1200 uNewCS, DescCS.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1201 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS & X86_SEL_MASK_OFF_RPL);
1202 }
1203 }
1204
1205 /* Additional long mode checks. */
1206 if (IEM_IS_LONG_MODE(pVCpu))
1207 {
1208 if (!DescCS.Legacy.Gen.u1Long)
1209 {
1210 Log(("BranchCallGate uNewCS %04x -> not a 64-bit code segment.\n", uNewCS));
1211 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1212 }
1213
1214 /* L vs D. */
1215 if ( DescCS.Legacy.Gen.u1Long
1216 && DescCS.Legacy.Gen.u1DefBig)
1217 {
1218 Log(("BranchCallGate uNewCS %04x -> both L and D are set.\n", uNewCS));
1219 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCS);
1220 }
1221 }
1222
1223 if (!DescCS.Legacy.Gate.u1Present)
1224 {
1225 Log(("BranchCallGate target CS is not present. uSel=%04x uNewCS=%04x -> #NP(CS)\n", uSel, uNewCS));
1226 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCS);
1227 }
1228
1229 if (enmBranch == IEMBRANCH_JUMP)
1230 {
1231 /** @todo This is very similar to regular far jumps; merge! */
1232 /* Jumps are fairly simple... */
1233
1234 /* Chop the high bits off if 16-bit gate (Intel says so). */
1235 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1236 uNewRip = (uint16_t)uNewRip;
1237
1238 /* Limit check for non-long segments. */
1239 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1240 if (DescCS.Legacy.Gen.u1Long)
1241 u64Base = 0;
1242 else
1243 {
1244 if (uNewRip > cbLimit)
1245 {
1246 Log(("BranchCallGate jump %04x:%08RX64 -> out of bounds (%#x) -> #GP(0)\n", uNewCS, uNewRip, cbLimit));
1247 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1248 }
1249 u64Base = X86DESC_BASE(&DescCS.Legacy);
1250 }
1251
1252 /* Canonical address check. */
1253 if (!IEM_IS_CANONICAL(uNewRip))
1254 {
1255 Log(("BranchCallGate jump %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1256 return iemRaiseNotCanonical(pVCpu);
1257 }
1258
1259 /*
1260 * Ok, everything checked out fine. Now set the accessed bit before
1261 * committing the result into CS, CSHID and RIP.
1262 */
1263 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1264 {
1265 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1266 if (rcStrict != VINF_SUCCESS)
1267 return rcStrict;
1268 /** @todo check what VT-x and AMD-V does. */
1269 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1270 }
1271
1272 /* commit */
1273 pVCpu->cpum.GstCtx.rip = uNewRip;
1274 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1275 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1276 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1277 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1278 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1279 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1280 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1281 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1282 }
1283 else
1284 {
1285 Assert(enmBranch == IEMBRANCH_CALL);
1286 /* Calls are much more complicated. */
1287
1288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF) && (DescCS.Legacy.Gen.u2Dpl < pVCpu->iem.s.uCpl))
1289 {
1290 uint16_t offNewStack; /* Offset of new stack in TSS. */
1291 uint16_t cbNewStack; /* Number of bytes the stack information takes up in TSS. */
1292 uint8_t uNewCSDpl;
1293 uint8_t cbWords;
1294 RTSEL uNewSS;
1295 RTSEL uOldSS;
1296 uint64_t uOldRsp;
1297 IEMSELDESC DescSS;
1298 RTPTRUNION uPtrTSS;
1299 RTGCPTR GCPtrTSS;
1300 RTPTRUNION uPtrParmWds;
1301 RTGCPTR GCPtrParmWds;
1302
1303 /* More privilege. This is the fun part. */
1304 Assert(!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)); /* Filtered out above. */
1305
1306 /*
1307 * Determine new SS:rSP from the TSS.
1308 */
1309 Assert(!pVCpu->cpum.GstCtx.tr.Attr.n.u1DescType);
1310
1311 /* Figure out where the new stack pointer is stored in the TSS. */
1312 uNewCSDpl = DescCS.Legacy.Gen.u2Dpl;
1313 if (!IEM_IS_LONG_MODE(pVCpu))
1314 {
1315 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1316 {
1317 offNewStack = RT_UOFFSETOF(X86TSS32, esp0) + uNewCSDpl * 8;
1318 cbNewStack = RT_SIZEOFMEMB(X86TSS32, esp0) + RT_SIZEOFMEMB(X86TSS32, ss0);
1319 }
1320 else
1321 {
1322 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1323 offNewStack = RT_UOFFSETOF(X86TSS16, sp0) + uNewCSDpl * 4;
1324 cbNewStack = RT_SIZEOFMEMB(X86TSS16, sp0) + RT_SIZEOFMEMB(X86TSS16, ss0);
1325 }
1326 }
1327 else
1328 {
1329 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1330 offNewStack = RT_UOFFSETOF(X86TSS64, rsp0) + uNewCSDpl * RT_SIZEOFMEMB(X86TSS64, rsp0);
1331 cbNewStack = RT_SIZEOFMEMB(X86TSS64, rsp0);
1332 }
1333
1334 /* Check against TSS limit. */
1335 if ((uint16_t)(offNewStack + cbNewStack - 1) > pVCpu->cpum.GstCtx.tr.u32Limit)
1336 {
1337 Log(("BranchCallGate inner stack past TSS limit - %u > %u -> #TS(TSS)\n", offNewStack + cbNewStack - 1, pVCpu->cpum.GstCtx.tr.u32Limit));
1338 return iemRaiseTaskSwitchFaultBySelector(pVCpu, pVCpu->cpum.GstCtx.tr.Sel);
1339 }
1340
1341 GCPtrTSS = pVCpu->cpum.GstCtx.tr.u64Base + offNewStack;
1342 rcStrict = iemMemMap(pVCpu, &uPtrTSS.pv, cbNewStack, UINT8_MAX, GCPtrTSS, IEM_ACCESS_SYS_R, 0);
1343 if (rcStrict != VINF_SUCCESS)
1344 {
1345 Log(("BranchCallGate: TSS mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1346 return rcStrict;
1347 }
1348
1349 if (!IEM_IS_LONG_MODE(pVCpu))
1350 {
1351 if (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY)
1352 {
1353 uNewRsp = uPtrTSS.pu32[0];
1354 uNewSS = uPtrTSS.pu16[2];
1355 }
1356 else
1357 {
1358 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY);
1359 uNewRsp = uPtrTSS.pu16[0];
1360 uNewSS = uPtrTSS.pu16[1];
1361 }
1362 }
1363 else
1364 {
1365 Assert(pVCpu->cpum.GstCtx.tr.Attr.n.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY);
1366 /* SS will be a NULL selector, but that's valid. */
1367 uNewRsp = uPtrTSS.pu64[0];
1368 uNewSS = uNewCSDpl;
1369 }
1370
1371 /* Done with the TSS now. */
1372 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrTSS.pv, IEM_ACCESS_SYS_R);
1373 if (rcStrict != VINF_SUCCESS)
1374 {
1375 Log(("BranchCallGate: TSS unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1376 return rcStrict;
1377 }
1378
1379 /* Only used outside of long mode. */
1380 cbWords = pDesc->Legacy.Gate.u5ParmCount;
1381
1382 /* If EFER.LMA is 0, there's extra work to do. */
1383 if (!IEM_IS_LONG_MODE(pVCpu))
1384 {
1385 if ((uNewSS & X86_SEL_MASK_OFF_RPL) == 0)
1386 {
1387 Log(("BranchCallGate new SS NULL -> #TS(NewSS)\n"));
1388 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1389 }
1390
1391 /* Grab the new SS descriptor. */
1392 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1393 if (rcStrict != VINF_SUCCESS)
1394 return rcStrict;
1395
1396 /* Ensure that CS.DPL == SS.RPL == SS.DPL. */
1397 if ( (DescCS.Legacy.Gen.u2Dpl != (uNewSS & X86_SEL_RPL))
1398 || (DescCS.Legacy.Gen.u2Dpl != DescSS.Legacy.Gen.u2Dpl))
1399 {
1400 Log(("BranchCallGate call bad RPL/DPL uNewSS=%04x SS DPL=%d CS DPL=%u -> #TS(NewSS)\n",
1401 uNewSS, DescCS.Legacy.Gen.u2Dpl, DescCS.Legacy.Gen.u2Dpl));
1402 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1403 }
1404
1405 /* Ensure new SS is a writable data segment. */
1406 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
1407 {
1408 Log(("BranchCallGate call new SS -> not a writable data selector (u4Type=%#x)\n", DescSS.Legacy.Gen.u4Type));
1409 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uNewSS);
1410 }
1411
1412 if (!DescSS.Legacy.Gen.u1Present)
1413 {
1414 Log(("BranchCallGate New stack not present uSel=%04x -> #SS(NewSS)\n", uNewSS));
1415 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
1416 }
1417 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1418 cbNewStack = (uint16_t)sizeof(uint32_t) * (4 + cbWords);
1419 else
1420 cbNewStack = (uint16_t)sizeof(uint16_t) * (4 + cbWords);
1421 }
1422 else
1423 {
1424 /* Just grab the new (NULL) SS descriptor. */
1425 /** @todo testcase: Check whether the zero GDT entry is actually loaded here
1426 * like we do... */
1427 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_SS);
1428 if (rcStrict != VINF_SUCCESS)
1429 return rcStrict;
1430
1431 cbNewStack = sizeof(uint64_t) * 4;
1432 }
1433
1434 /** @todo According to Intel, new stack is checked for enough space first,
1435 * then switched. According to AMD, the stack is switched first and
1436 * then pushes might fault!
1437 * NB: OS/2 Warp 3/4 actively relies on the fact that possible
1438 * incoming stack \#PF happens before actual stack switch. AMD is
1439 * either lying or implicitly assumes that new state is committed
1440 * only if and when an instruction doesn't fault.
1441 */
1442
1443 /** @todo According to AMD, CS is loaded first, then SS.
1444 * According to Intel, it's the other way around!?
1445 */
1446
1447 /** @todo Intel and AMD disagree on when exactly the CPL changes! */
1448
1449 /* Set the accessed bit before committing new SS. */
1450 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1451 {
1452 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
1453 if (rcStrict != VINF_SUCCESS)
1454 return rcStrict;
1455 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1456 }
1457
1458 /* Remember the old SS:rSP and their linear address. */
1459 uOldSS = pVCpu->cpum.GstCtx.ss.Sel;
1460 uOldRsp = pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig ? pVCpu->cpum.GstCtx.rsp : pVCpu->cpum.GstCtx.sp;
1461
1462 GCPtrParmWds = pVCpu->cpum.GstCtx.ss.u64Base + uOldRsp;
1463
1464 /* HACK ALERT! Probe if the write to the new stack will succeed. May #SS(NewSS)
1465 or #PF, the former is not implemented in this workaround. */
1466 /** @todo Proper fix callgate target stack exceptions. */
1467 /** @todo testcase: Cover callgates with partially or fully inaccessible
1468 * target stacks. */
1469 void *pvNewFrame;
1470 RTGCPTR GCPtrNewStack = X86DESC_BASE(&DescSS.Legacy) + uNewRsp - cbNewStack;
1471 rcStrict = iemMemMap(pVCpu, &pvNewFrame, cbNewStack, UINT8_MAX, GCPtrNewStack, IEM_ACCESS_SYS_RW, 0);
1472 if (rcStrict != VINF_SUCCESS)
1473 {
1474 Log(("BranchCallGate: Incoming stack (%04x:%08RX64) not accessible, rc=%Rrc\n", uNewSS, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
1475 return rcStrict;
1476 }
1477 rcStrict = iemMemCommitAndUnmap(pVCpu, pvNewFrame, IEM_ACCESS_SYS_RW);
1478 if (rcStrict != VINF_SUCCESS)
1479 {
1480 Log(("BranchCallGate: New stack probe unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1481 return rcStrict;
1482 }
1483
1484 /* Commit new SS:rSP. */
1485 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
1486 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
1487 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
1488 pVCpu->cpum.GstCtx.ss.u32Limit = X86DESC_LIMIT_G(&DescSS.Legacy);
1489 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
1490 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
1491 pVCpu->cpum.GstCtx.rsp = uNewRsp;
1492 pVCpu->iem.s.uCpl = uNewCSDpl; /** @todo is the parameter words accessed using the new CPL or the old CPL? */
1493 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
1494 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
1495
1496 /* At this point the stack access must not fail because new state was already committed. */
1497 /** @todo this can still fail due to SS.LIMIT not check. */
1498 rcStrict = iemMemStackPushBeginSpecial(pVCpu, cbNewStack,
1499 IEM_IS_LONG_MODE(pVCpu) ? 7
1500 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 1,
1501 &uPtrRet.pv, &uNewRsp);
1502 AssertMsgReturn(rcStrict == VINF_SUCCESS, ("BranchCallGate: New stack mapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)),
1503 VERR_INTERNAL_ERROR_5);
1504
1505 if (!IEM_IS_LONG_MODE(pVCpu))
1506 {
1507 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1508 {
1509 if (cbWords)
1510 {
1511 /* Map the relevant chunk of the old stack. */
1512 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 4, UINT8_MAX, GCPtrParmWds,
1513 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1514 if (rcStrict != VINF_SUCCESS)
1515 {
1516 Log(("BranchCallGate: Old stack mapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1517 return rcStrict;
1518 }
1519
1520 /* Copy the parameter (d)words. */
1521 for (int i = 0; i < cbWords; ++i)
1522 uPtrRet.pu32[2 + i] = uPtrParmWds.pu32[i];
1523
1524 /* Unmap the old stack. */
1525 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1526 if (rcStrict != VINF_SUCCESS)
1527 {
1528 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1529 return rcStrict;
1530 }
1531 }
1532
1533 /* Push the old CS:rIP. */
1534 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1535 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1536
1537 /* Push the old SS:rSP. */
1538 uPtrRet.pu32[2 + cbWords + 0] = uOldRsp;
1539 uPtrRet.pu32[2 + cbWords + 1] = uOldSS;
1540 }
1541 else
1542 {
1543 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1544
1545 if (cbWords)
1546 {
1547 /* Map the relevant chunk of the old stack. */
1548 rcStrict = iemMemMap(pVCpu, &uPtrParmWds.pv, cbWords * 2, UINT8_MAX, GCPtrParmWds,
1549 IEM_ACCESS_DATA_R, 0 /** @todo Can uNewCSDpl == 3? Then we need alignment mask here! */);
1550 if (rcStrict != VINF_SUCCESS)
1551 {
1552 Log(("BranchCallGate: Old stack mapping (16-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1553 return rcStrict;
1554 }
1555
1556 /* Copy the parameter words. */
1557 for (int i = 0; i < cbWords; ++i)
1558 uPtrRet.pu16[2 + i] = uPtrParmWds.pu16[i];
1559
1560 /* Unmap the old stack. */
1561 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtrParmWds.pv, IEM_ACCESS_DATA_R);
1562 if (rcStrict != VINF_SUCCESS)
1563 {
1564 Log(("BranchCallGate: Old stack unmapping (32-bit) failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1565 return rcStrict;
1566 }
1567 }
1568
1569 /* Push the old CS:rIP. */
1570 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1571 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1572
1573 /* Push the old SS:rSP. */
1574 uPtrRet.pu16[2 + cbWords + 0] = uOldRsp;
1575 uPtrRet.pu16[2 + cbWords + 1] = uOldSS;
1576 }
1577 }
1578 else
1579 {
1580 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1581
1582 /* For 64-bit gates, no parameters are copied. Just push old SS:rSP and CS:rIP. */
1583 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1584 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1585 uPtrRet.pu64[2] = uOldRsp;
1586 uPtrRet.pu64[3] = uOldSS; /** @todo Testcase: What is written to the high words when pushing SS? */
1587 }
1588
1589 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1590 if (rcStrict != VINF_SUCCESS)
1591 {
1592 Log(("BranchCallGate: New stack unmapping failed (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
1593 return rcStrict;
1594 }
1595
1596 /* Chop the high bits off if 16-bit gate (Intel says so). */
1597 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1598 uNewRip = (uint16_t)uNewRip;
1599
1600 /* Limit / canonical check. */
1601 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1602 if (!IEM_IS_LONG_MODE(pVCpu))
1603 {
1604 if (uNewRip > cbLimit)
1605 {
1606 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1607 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1608 }
1609 u64Base = X86DESC_BASE(&DescCS.Legacy);
1610 }
1611 else
1612 {
1613 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1614 if (!IEM_IS_CANONICAL(uNewRip))
1615 {
1616 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1617 return iemRaiseNotCanonical(pVCpu);
1618 }
1619 u64Base = 0;
1620 }
1621
1622 /*
1623 * Now set the accessed bit before
1624 * writing the return address to the stack and committing the result into
1625 * CS, CSHID and RIP.
1626 */
1627 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1628 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1629 {
1630 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1631 if (rcStrict != VINF_SUCCESS)
1632 return rcStrict;
1633 /** @todo check what VT-x and AMD-V does. */
1634 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1635 }
1636
1637 /* Commit new CS:rIP. */
1638 pVCpu->cpum.GstCtx.rip = uNewRip;
1639 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1640 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1641 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1642 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1643 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1644 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1645 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1646 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1647 }
1648 else
1649 {
1650 /* Same privilege. */
1651 /** @todo This is very similar to regular far calls; merge! */
1652
1653 /* Check stack first - may #SS(0). */
1654 /** @todo check how gate size affects pushing of CS! Does callf 16:32 in
1655 * 16-bit code cause a two or four byte CS to be pushed? */
1656 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
1657 IEM_IS_LONG_MODE(pVCpu) ? 8+8
1658 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 4+4 : 2+2,
1659 IEM_IS_LONG_MODE(pVCpu) ? 7
1660 : pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE ? 3 : 2,
1661 &uPtrRet.pv, &uNewRsp);
1662 if (rcStrict != VINF_SUCCESS)
1663 return rcStrict;
1664
1665 /* Chop the high bits off if 16-bit gate (Intel says so). */
1666 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE)
1667 uNewRip = (uint16_t)uNewRip;
1668
1669 /* Limit / canonical check. */
1670 cbLimit = X86DESC_LIMIT_G(&DescCS.Legacy);
1671 if (!IEM_IS_LONG_MODE(pVCpu))
1672 {
1673 if (uNewRip > cbLimit)
1674 {
1675 Log(("BranchCallGate %04x:%08RX64 -> out of bounds (%#x)\n", uNewCS, uNewRip, cbLimit));
1676 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, 0);
1677 }
1678 u64Base = X86DESC_BASE(&DescCS.Legacy);
1679 }
1680 else
1681 {
1682 if (!IEM_IS_CANONICAL(uNewRip))
1683 {
1684 Log(("BranchCallGate call %04x:%016RX64 - not canonical -> #GP\n", uNewCS, uNewRip));
1685 return iemRaiseNotCanonical(pVCpu);
1686 }
1687 u64Base = 0;
1688 }
1689
1690 /*
1691 * Now set the accessed bit before
1692 * writing the return address to the stack and committing the result into
1693 * CS, CSHID and RIP.
1694 */
1695 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
1696 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1697 {
1698 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCS);
1699 if (rcStrict != VINF_SUCCESS)
1700 return rcStrict;
1701 /** @todo check what VT-x and AMD-V does. */
1702 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1703 }
1704
1705 /* stack */
1706 if (!IEM_IS_LONG_MODE(pVCpu))
1707 {
1708 if (pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_386_CALL_GATE)
1709 {
1710 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
1711 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when pushing CS? */
1712 }
1713 else
1714 {
1715 Assert(pDesc->Legacy.Gate.u4Type == X86_SEL_TYPE_SYS_286_CALL_GATE);
1716 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
1717 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
1718 }
1719 }
1720 else
1721 {
1722 Assert(pDesc->Legacy.Gate.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE);
1723 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
1724 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when pushing CS? */
1725 }
1726
1727 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
1728 if (rcStrict != VINF_SUCCESS)
1729 return rcStrict;
1730
1731 /* commit */
1732 pVCpu->cpum.GstCtx.rip = uNewRip;
1733 pVCpu->cpum.GstCtx.cs.Sel = uNewCS & X86_SEL_MASK_OFF_RPL;
1734 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
1735 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1736 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1737 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
1738 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1739 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1740 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1741 }
1742 }
1743 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1744
1745 /* Flush the prefetch buffer. */
1746# ifdef IEM_WITH_CODE_TLB
1747 pVCpu->iem.s.pbInstrBuf = NULL;
1748# else
1749 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1750# endif
1751 return VINF_SUCCESS;
1752#endif
1753}
1754
1755
1756/**
1757 * Implements far jumps and calls thru system selectors.
1758 *
1759 * @param uSel The selector.
1760 * @param enmBranch The kind of branching we're performing.
1761 * @param enmEffOpSize The effective operand size.
1762 * @param pDesc The descriptor corresponding to @a uSel.
1763 */
1764IEM_CIMPL_DEF_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc)
1765{
1766 Assert(enmBranch == IEMBRANCH_JUMP || enmBranch == IEMBRANCH_CALL);
1767 Assert((uSel & X86_SEL_MASK_OFF_RPL));
1768 IEM_CTX_IMPORT_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
1769
1770 if (IEM_IS_LONG_MODE(pVCpu))
1771 switch (pDesc->Legacy.Gen.u4Type)
1772 {
1773 case AMD64_SEL_TYPE_SYS_CALL_GATE:
1774 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1775
1776 default:
1777 case AMD64_SEL_TYPE_SYS_LDT:
1778 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
1779 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
1780 case AMD64_SEL_TYPE_SYS_TRAP_GATE:
1781 case AMD64_SEL_TYPE_SYS_INT_GATE:
1782 Log(("branch %04x -> wrong sys selector (64-bit): %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1783 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1784 }
1785
1786 switch (pDesc->Legacy.Gen.u4Type)
1787 {
1788 case X86_SEL_TYPE_SYS_286_CALL_GATE:
1789 case X86_SEL_TYPE_SYS_386_CALL_GATE:
1790 return IEM_CIMPL_CALL_4(iemCImpl_BranchCallGate, uSel, enmBranch, enmEffOpSize, pDesc);
1791
1792 case X86_SEL_TYPE_SYS_TASK_GATE:
1793 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskGate, uSel, enmBranch, enmEffOpSize, pDesc);
1794
1795 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1796 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1797 return IEM_CIMPL_CALL_4(iemCImpl_BranchTaskSegment, uSel, enmBranch, enmEffOpSize, pDesc);
1798
1799 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1800 Log(("branch %04x -> busy 286 TSS\n", uSel));
1801 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1802
1803 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1804 Log(("branch %04x -> busy 386 TSS\n", uSel));
1805 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1806
1807 default:
1808 case X86_SEL_TYPE_SYS_LDT:
1809 case X86_SEL_TYPE_SYS_286_INT_GATE:
1810 case X86_SEL_TYPE_SYS_286_TRAP_GATE:
1811 case X86_SEL_TYPE_SYS_386_INT_GATE:
1812 case X86_SEL_TYPE_SYS_386_TRAP_GATE:
1813 Log(("branch %04x -> wrong sys selector: %d\n", uSel, pDesc->Legacy.Gen.u4Type));
1814 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1815 }
1816}
1817
1818
1819/**
1820 * Implements far jumps.
1821 *
1822 * @param uSel The selector.
1823 * @param offSeg The segment offset.
1824 * @param enmEffOpSize The effective operand size.
1825 */
1826IEM_CIMPL_DEF_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
1827{
1828 NOREF(cbInstr);
1829 Assert(offSeg <= UINT32_MAX);
1830
1831 /*
1832 * Real mode and V8086 mode are easy. The only snag seems to be that
1833 * CS.limit doesn't change and the limit check is done against the current
1834 * limit.
1835 */
1836 /** @todo Robert Collins claims (The Segment Descriptor Cache, DDJ August
1837 * 1998) that up to and including the Intel 486, far control
1838 * transfers in real mode set default CS attributes (0x93) and also
1839 * set a 64K segment limit. Starting with the Pentium, the
1840 * attributes and limit are left alone but the access rights are
1841 * ignored. We only implement the Pentium+ behavior.
1842 * */
1843 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
1844 {
1845 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
1846 if (offSeg > pVCpu->cpum.GstCtx.cs.u32Limit)
1847 {
1848 Log(("iemCImpl_FarJmp: 16-bit limit\n"));
1849 return iemRaiseGeneralProtectionFault0(pVCpu);
1850 }
1851
1852 if (enmEffOpSize == IEMMODE_16BIT) /** @todo WRONG, must pass this. */
1853 pVCpu->cpum.GstCtx.rip = offSeg;
1854 else
1855 pVCpu->cpum.GstCtx.rip = offSeg & UINT16_MAX;
1856 pVCpu->cpum.GstCtx.cs.Sel = uSel;
1857 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
1858 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1859 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
1860 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1861 return VINF_SUCCESS;
1862 }
1863
1864 /*
1865 * Protected mode. Need to parse the specified descriptor...
1866 */
1867 if (!(uSel & X86_SEL_MASK_OFF_RPL))
1868 {
1869 Log(("jmpf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
1870 return iemRaiseGeneralProtectionFault0(pVCpu);
1871 }
1872
1873 /* Fetch the descriptor. */
1874 IEMSELDESC Desc;
1875 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
1876 if (rcStrict != VINF_SUCCESS)
1877 return rcStrict;
1878
1879 /* Is it there? */
1880 if (!Desc.Legacy.Gen.u1Present) /** @todo this is probably checked too early. Testcase! */
1881 {
1882 Log(("jmpf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
1883 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
1884 }
1885
1886 /*
1887 * Deal with it according to its type. We do the standard code selectors
1888 * here and dispatch the system selectors to worker functions.
1889 */
1890 if (!Desc.Legacy.Gen.u1DescType)
1891 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_JUMP, enmEffOpSize, &Desc);
1892
1893 /* Only code segments. */
1894 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
1895 {
1896 Log(("jmpf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
1897 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1898 }
1899
1900 /* L vs D. */
1901 if ( Desc.Legacy.Gen.u1Long
1902 && Desc.Legacy.Gen.u1DefBig
1903 && IEM_IS_LONG_MODE(pVCpu))
1904 {
1905 Log(("jmpf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
1906 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1907 }
1908
1909 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
1910 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
1911 {
1912 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
1913 {
1914 Log(("jmpf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
1915 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1916 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1917 }
1918 }
1919 else
1920 {
1921 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
1922 {
1923 Log(("jmpf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
1924 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1925 }
1926 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
1927 {
1928 Log(("jmpf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
1929 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1930 }
1931 }
1932
1933 /* Chop the high bits if 16-bit (Intel says so). */
1934 if (enmEffOpSize == IEMMODE_16BIT)
1935 offSeg &= UINT16_MAX;
1936
1937 /* Limit check. (Should alternatively check for non-canonical addresses
1938 here, but that is ruled out by offSeg being 32-bit, right?) */
1939 uint64_t u64Base;
1940 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
1941 if (Desc.Legacy.Gen.u1Long)
1942 u64Base = 0;
1943 else
1944 {
1945 if (offSeg > cbLimit)
1946 {
1947 Log(("jmpf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
1948 /** @todo Intel says this is \#GP(0)! */
1949 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
1950 }
1951 u64Base = X86DESC_BASE(&Desc.Legacy);
1952 }
1953
1954 /*
1955 * Ok, everything checked out fine. Now set the accessed bit before
1956 * committing the result into CS, CSHID and RIP.
1957 */
1958 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1959 {
1960 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
1961 if (rcStrict != VINF_SUCCESS)
1962 return rcStrict;
1963 /** @todo check what VT-x and AMD-V does. */
1964 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1965 }
1966
1967 /* commit */
1968 pVCpu->cpum.GstCtx.rip = offSeg;
1969 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
1970 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl; /** @todo is this right for conforming segs? or in general? */
1971 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
1972 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
1973 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
1974 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
1975 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
1976 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
1977 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
1978 /** @todo check if the hidden bits are loaded correctly for 64-bit
1979 * mode. */
1980
1981 /* Flush the prefetch buffer. */
1982#ifdef IEM_WITH_CODE_TLB
1983 pVCpu->iem.s.pbInstrBuf = NULL;
1984#else
1985 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
1986#endif
1987
1988 return VINF_SUCCESS;
1989}
1990
1991
1992/**
1993 * Implements far calls.
1994 *
1995 * This very similar to iemCImpl_FarJmp.
1996 *
1997 * @param uSel The selector.
1998 * @param offSeg The segment offset.
1999 * @param enmEffOpSize The operand size (in case we need it).
2000 */
2001IEM_CIMPL_DEF_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize)
2002{
2003 VBOXSTRICTRC rcStrict;
2004 uint64_t uNewRsp;
2005 RTPTRUNION uPtrRet;
2006
2007 /*
2008 * Real mode and V8086 mode are easy. The only snag seems to be that
2009 * CS.limit doesn't change and the limit check is done against the current
2010 * limit.
2011 */
2012 /** @todo See comment for similar code in iemCImpl_FarJmp */
2013 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2014 {
2015 Assert(enmEffOpSize == IEMMODE_16BIT || enmEffOpSize == IEMMODE_32BIT);
2016
2017 /* Check stack first - may #SS(0). */
2018 rcStrict = iemMemStackPushBeginSpecial(pVCpu, enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2019 enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2020 &uPtrRet.pv, &uNewRsp);
2021 if (rcStrict != VINF_SUCCESS)
2022 return rcStrict;
2023
2024 /* Check the target address range. */
2025 if (offSeg > UINT32_MAX)
2026 return iemRaiseGeneralProtectionFault0(pVCpu);
2027
2028 /* Everything is fine, push the return address. */
2029 if (enmEffOpSize == IEMMODE_16BIT)
2030 {
2031 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2032 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2033 }
2034 else
2035 {
2036 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2037 uPtrRet.pu16[2] = pVCpu->cpum.GstCtx.cs.Sel;
2038 }
2039 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2040 if (rcStrict != VINF_SUCCESS)
2041 return rcStrict;
2042
2043 /* Branch. */
2044 pVCpu->cpum.GstCtx.rip = offSeg;
2045 pVCpu->cpum.GstCtx.cs.Sel = uSel;
2046 pVCpu->cpum.GstCtx.cs.ValidSel = uSel;
2047 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2048 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uSel << 4;
2049 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2050 return VINF_SUCCESS;
2051 }
2052
2053 /*
2054 * Protected mode. Need to parse the specified descriptor...
2055 */
2056 if (!(uSel & X86_SEL_MASK_OFF_RPL))
2057 {
2058 Log(("callf %04x:%08RX64 -> invalid selector, #GP(0)\n", uSel, offSeg));
2059 return iemRaiseGeneralProtectionFault0(pVCpu);
2060 }
2061
2062 /* Fetch the descriptor. */
2063 IEMSELDESC Desc;
2064 rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP);
2065 if (rcStrict != VINF_SUCCESS)
2066 return rcStrict;
2067
2068 /*
2069 * Deal with it according to its type. We do the standard code selectors
2070 * here and dispatch the system selectors to worker functions.
2071 */
2072 if (!Desc.Legacy.Gen.u1DescType)
2073 return IEM_CIMPL_CALL_4(iemCImpl_BranchSysSel, uSel, IEMBRANCH_CALL, enmEffOpSize, &Desc);
2074
2075 /* Only code segments. */
2076 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
2077 {
2078 Log(("callf %04x:%08RX64 -> not a code selector (u4Type=%#x).\n", uSel, offSeg, Desc.Legacy.Gen.u4Type));
2079 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2080 }
2081
2082 /* L vs D. */
2083 if ( Desc.Legacy.Gen.u1Long
2084 && Desc.Legacy.Gen.u1DefBig
2085 && IEM_IS_LONG_MODE(pVCpu))
2086 {
2087 Log(("callf %04x:%08RX64 -> both L and D are set.\n", uSel, offSeg));
2088 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2089 }
2090
2091 /* DPL/RPL/CPL check, where conforming segments makes a difference. */
2092 if (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2093 {
2094 if (pVCpu->iem.s.uCpl < Desc.Legacy.Gen.u2Dpl)
2095 {
2096 Log(("callf %04x:%08RX64 -> DPL violation (conforming); DPL=%d CPL=%u\n",
2097 uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2098 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2099 }
2100 }
2101 else
2102 {
2103 if (pVCpu->iem.s.uCpl != Desc.Legacy.Gen.u2Dpl)
2104 {
2105 Log(("callf %04x:%08RX64 -> CPL != DPL; DPL=%d CPL=%u\n", uSel, offSeg, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
2106 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2107 }
2108 if ((uSel & X86_SEL_RPL) > pVCpu->iem.s.uCpl)
2109 {
2110 Log(("callf %04x:%08RX64 -> RPL > DPL; RPL=%d CPL=%u\n", uSel, offSeg, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl));
2111 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2112 }
2113 }
2114
2115 /* Is it there? */
2116 if (!Desc.Legacy.Gen.u1Present)
2117 {
2118 Log(("callf %04x:%08RX64 -> segment not present\n", uSel, offSeg));
2119 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
2120 }
2121
2122 /* Check stack first - may #SS(0). */
2123 /** @todo check how operand prefix affects pushing of CS! Does callf 16:32 in
2124 * 16-bit code cause a two or four byte CS to be pushed? */
2125 rcStrict = iemMemStackPushBeginSpecial(pVCpu,
2126 enmEffOpSize == IEMMODE_64BIT ? 8+8 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 2+2,
2127 enmEffOpSize == IEMMODE_64BIT ? 7 : enmEffOpSize == IEMMODE_32BIT ? 3 : 1,
2128 &uPtrRet.pv, &uNewRsp);
2129 if (rcStrict != VINF_SUCCESS)
2130 return rcStrict;
2131
2132 /* Chop the high bits if 16-bit (Intel says so). */
2133 if (enmEffOpSize == IEMMODE_16BIT)
2134 offSeg &= UINT16_MAX;
2135
2136 /* Limit / canonical check. */
2137 uint64_t u64Base;
2138 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
2139 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2140 {
2141 if (!IEM_IS_CANONICAL(offSeg))
2142 {
2143 Log(("callf %04x:%016RX64 - not canonical -> #GP\n", uSel, offSeg));
2144 return iemRaiseNotCanonical(pVCpu);
2145 }
2146 u64Base = 0;
2147 }
2148 else
2149 {
2150 if (offSeg > cbLimit)
2151 {
2152 Log(("callf %04x:%08RX64 -> out of bounds (%#x)\n", uSel, offSeg, cbLimit));
2153 /** @todo Intel says this is \#GP(0)! */
2154 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
2155 }
2156 u64Base = X86DESC_BASE(&Desc.Legacy);
2157 }
2158
2159 /*
2160 * Now set the accessed bit before
2161 * writing the return address to the stack and committing the result into
2162 * CS, CSHID and RIP.
2163 */
2164 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2165 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2166 {
2167 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
2168 if (rcStrict != VINF_SUCCESS)
2169 return rcStrict;
2170 /** @todo check what VT-x and AMD-V does. */
2171 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2172 }
2173
2174 /* stack */
2175 if (enmEffOpSize == IEMMODE_16BIT)
2176 {
2177 uPtrRet.pu16[0] = pVCpu->cpum.GstCtx.ip + cbInstr;
2178 uPtrRet.pu16[1] = pVCpu->cpum.GstCtx.cs.Sel;
2179 }
2180 else if (enmEffOpSize == IEMMODE_32BIT)
2181 {
2182 uPtrRet.pu32[0] = pVCpu->cpum.GstCtx.eip + cbInstr;
2183 uPtrRet.pu32[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high word when callf is pushing CS? */
2184 }
2185 else
2186 {
2187 uPtrRet.pu64[0] = pVCpu->cpum.GstCtx.rip + cbInstr;
2188 uPtrRet.pu64[1] = pVCpu->cpum.GstCtx.cs.Sel; /** @todo Testcase: What is written to the high words when callf is pushing CS? */
2189 }
2190 rcStrict = iemMemStackPushCommitSpecial(pVCpu, uPtrRet.pv, uNewRsp);
2191 if (rcStrict != VINF_SUCCESS)
2192 return rcStrict;
2193
2194 /* commit */
2195 pVCpu->cpum.GstCtx.rip = offSeg;
2196 pVCpu->cpum.GstCtx.cs.Sel = uSel & X86_SEL_MASK_OFF_RPL;
2197 pVCpu->cpum.GstCtx.cs.Sel |= pVCpu->iem.s.uCpl;
2198 pVCpu->cpum.GstCtx.cs.ValidSel = pVCpu->cpum.GstCtx.cs.Sel;
2199 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2200 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
2201 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimit;
2202 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2203 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2204 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2205 /** @todo check if the hidden bits are loaded correctly for 64-bit
2206 * mode. */
2207
2208 /* Flush the prefetch buffer. */
2209#ifdef IEM_WITH_CODE_TLB
2210 pVCpu->iem.s.pbInstrBuf = NULL;
2211#else
2212 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2213#endif
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/**
2219 * Implements retf.
2220 *
2221 * @param enmEffOpSize The effective operand size.
2222 * @param cbPop The amount of arguments to pop from the stack
2223 * (bytes).
2224 */
2225IEM_CIMPL_DEF_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2226{
2227 VBOXSTRICTRC rcStrict;
2228 RTCPTRUNION uPtrFrame;
2229 uint64_t uNewRsp;
2230 uint64_t uNewRip;
2231 uint16_t uNewCs;
2232 NOREF(cbInstr);
2233
2234 /*
2235 * Read the stack values first.
2236 */
2237 uint32_t cbRetPtr = enmEffOpSize == IEMMODE_16BIT ? 2+2
2238 : enmEffOpSize == IEMMODE_32BIT ? 4+4 : 8+8;
2239 rcStrict = iemMemStackPopBeginSpecial(pVCpu, cbRetPtr,
2240 enmEffOpSize == IEMMODE_16BIT ? 1 : enmEffOpSize == IEMMODE_32BIT ? 3 : 7,
2241 &uPtrFrame.pv, &uNewRsp);
2242 if (rcStrict != VINF_SUCCESS)
2243 return rcStrict;
2244 if (enmEffOpSize == IEMMODE_16BIT)
2245 {
2246 uNewRip = uPtrFrame.pu16[0];
2247 uNewCs = uPtrFrame.pu16[1];
2248 }
2249 else if (enmEffOpSize == IEMMODE_32BIT)
2250 {
2251 uNewRip = uPtrFrame.pu32[0];
2252 uNewCs = uPtrFrame.pu16[2];
2253 }
2254 else
2255 {
2256 uNewRip = uPtrFrame.pu64[0];
2257 uNewCs = uPtrFrame.pu16[4];
2258 }
2259 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2260 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2261 { /* extremely likely */ }
2262 else
2263 return rcStrict;
2264
2265 /*
2266 * Real mode and V8086 mode are easy.
2267 */
2268 /** @todo See comment for similar code in iemCImpl_FarJmp */
2269 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2270 {
2271 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2272 /** @todo check how this is supposed to work if sp=0xfffe. */
2273
2274 /* Check the limit of the new EIP. */
2275 /** @todo Intel pseudo code only does the limit check for 16-bit
2276 * operands, AMD does not make any distinction. What is right? */
2277 if (uNewRip > pVCpu->cpum.GstCtx.cs.u32Limit)
2278 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2279
2280 /* commit the operation. */
2281 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2282 pVCpu->cpum.GstCtx.rip = uNewRip;
2283 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2284 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2285 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2286 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
2287 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2288 if (cbPop)
2289 iemRegAddToRsp(pVCpu, cbPop);
2290 return VINF_SUCCESS;
2291 }
2292
2293 /*
2294 * Protected mode is complicated, of course.
2295 */
2296 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
2297 {
2298 Log(("retf %04x:%08RX64 -> invalid selector, #GP(0)\n", uNewCs, uNewRip));
2299 return iemRaiseGeneralProtectionFault0(pVCpu);
2300 }
2301
2302 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
2303
2304 /* Fetch the descriptor. */
2305 IEMSELDESC DescCs;
2306 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCs, uNewCs, X86_XCPT_GP);
2307 if (rcStrict != VINF_SUCCESS)
2308 return rcStrict;
2309
2310 /* Can only return to a code selector. */
2311 if ( !DescCs.Legacy.Gen.u1DescType
2312 || !(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE) )
2313 {
2314 Log(("retf %04x:%08RX64 -> not a code selector (u1DescType=%u u4Type=%#x).\n",
2315 uNewCs, uNewRip, DescCs.Legacy.Gen.u1DescType, DescCs.Legacy.Gen.u4Type));
2316 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2317 }
2318
2319 /* L vs D. */
2320 if ( DescCs.Legacy.Gen.u1Long /** @todo Testcase: far return to a selector with both L and D set. */
2321 && DescCs.Legacy.Gen.u1DefBig
2322 && IEM_IS_LONG_MODE(pVCpu))
2323 {
2324 Log(("retf %04x:%08RX64 -> both L & D set.\n", uNewCs, uNewRip));
2325 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2326 }
2327
2328 /* DPL/RPL/CPL checks. */
2329 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
2330 {
2331 Log(("retf %04x:%08RX64 -> RPL < CPL(%d).\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
2332 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2333 }
2334
2335 if (DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF)
2336 {
2337 if ((uNewCs & X86_SEL_RPL) < DescCs.Legacy.Gen.u2Dpl)
2338 {
2339 Log(("retf %04x:%08RX64 -> DPL violation (conforming); DPL=%u RPL=%u\n",
2340 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2341 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2342 }
2343 }
2344 else
2345 {
2346 if ((uNewCs & X86_SEL_RPL) != DescCs.Legacy.Gen.u2Dpl)
2347 {
2348 Log(("retf %04x:%08RX64 -> RPL != DPL; DPL=%u RPL=%u\n",
2349 uNewCs, uNewRip, DescCs.Legacy.Gen.u2Dpl, (uNewCs & X86_SEL_RPL)));
2350 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2351 }
2352 }
2353
2354 /* Is it there? */
2355 if (!DescCs.Legacy.Gen.u1Present)
2356 {
2357 Log(("retf %04x:%08RX64 -> segment not present\n", uNewCs, uNewRip));
2358 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2359 }
2360
2361 /*
2362 * Return to outer privilege? (We'll typically have entered via a call gate.)
2363 */
2364 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
2365 {
2366 /* Read the outer stack pointer stored *after* the parameters. */
2367 rcStrict = iemMemStackPopContinueSpecial(pVCpu, cbPop /*off*/, cbRetPtr, &uPtrFrame.pv, uNewRsp);
2368 if (rcStrict != VINF_SUCCESS)
2369 return rcStrict;
2370
2371 uint16_t uNewOuterSs;
2372 uint64_t uNewOuterRsp;
2373 if (enmEffOpSize == IEMMODE_16BIT)
2374 {
2375 uNewOuterRsp = uPtrFrame.pu16[0];
2376 uNewOuterSs = uPtrFrame.pu16[1];
2377 }
2378 else if (enmEffOpSize == IEMMODE_32BIT)
2379 {
2380 uNewOuterRsp = uPtrFrame.pu32[0];
2381 uNewOuterSs = uPtrFrame.pu16[2];
2382 }
2383 else
2384 {
2385 uNewOuterRsp = uPtrFrame.pu64[0];
2386 uNewOuterSs = uPtrFrame.pu16[4];
2387 }
2388 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uPtrFrame.pv);
2389 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2390 { /* extremely likely */ }
2391 else
2392 return rcStrict;
2393
2394 /* Check for NULL stack selector (invalid in ring-3 and non-long mode)
2395 and read the selector. */
2396 IEMSELDESC DescSs;
2397 if (!(uNewOuterSs & X86_SEL_MASK_OFF_RPL))
2398 {
2399 if ( !DescCs.Legacy.Gen.u1Long
2400 || (uNewOuterSs & X86_SEL_RPL) == 3)
2401 {
2402 Log(("retf %04x:%08RX64 %04x:%08RX64 -> invalid stack selector, #GP\n",
2403 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2404 return iemRaiseGeneralProtectionFault0(pVCpu);
2405 }
2406 /** @todo Testcase: Return far to ring-1 or ring-2 with SS=0. */
2407 iemMemFakeStackSelDesc(&DescSs, (uNewOuterSs & X86_SEL_RPL));
2408 }
2409 else
2410 {
2411 /* Fetch the descriptor for the new stack segment. */
2412 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSs, uNewOuterSs, X86_XCPT_GP);
2413 if (rcStrict != VINF_SUCCESS)
2414 return rcStrict;
2415 }
2416
2417 /* Check that RPL of stack and code selectors match. */
2418 if ((uNewCs & X86_SEL_RPL) != (uNewOuterSs & X86_SEL_RPL))
2419 {
2420 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.RPL != CS.RPL -> #GP(SS)\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2421 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2422 }
2423
2424 /* Must be a writable data segment. */
2425 if ( !DescSs.Legacy.Gen.u1DescType
2426 || (DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
2427 || !(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
2428 {
2429 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not a writable data segment (u1DescType=%u u4Type=%#x) -> #GP(SS).\n",
2430 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u1DescType, DescSs.Legacy.Gen.u4Type));
2431 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2432 }
2433
2434 /* L vs D. (Not mentioned by intel.) */
2435 if ( DescSs.Legacy.Gen.u1Long /** @todo Testcase: far return to a stack selector with both L and D set. */
2436 && DescSs.Legacy.Gen.u1DefBig
2437 && IEM_IS_LONG_MODE(pVCpu))
2438 {
2439 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS has both L & D set -> #GP(SS).\n",
2440 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2441 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2442 }
2443
2444 /* DPL/RPL/CPL checks. */
2445 if (DescSs.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
2446 {
2447 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS.DPL(%u) != CS.RPL (%u) -> #GP(SS).\n",
2448 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, DescSs.Legacy.Gen.u2Dpl, uNewCs & X86_SEL_RPL));
2449 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewOuterSs);
2450 }
2451
2452 /* Is it there? */
2453 if (!DescSs.Legacy.Gen.u1Present)
2454 {
2455 Log(("retf %04x:%08RX64 %04x:%08RX64 - SS not present -> #NP(SS).\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2456 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
2457 }
2458
2459 /* Calc SS limit.*/
2460 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSs.Legacy);
2461
2462 /* Is RIP canonical or within CS.limit? */
2463 uint64_t u64Base;
2464 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2465
2466 /** @todo Testcase: Is this correct? */
2467 if ( DescCs.Legacy.Gen.u1Long
2468 && IEM_IS_LONG_MODE(pVCpu) )
2469 {
2470 if (!IEM_IS_CANONICAL(uNewRip))
2471 {
2472 Log(("retf %04x:%08RX64 %04x:%08RX64 - not canonical -> #GP.\n", uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp));
2473 return iemRaiseNotCanonical(pVCpu);
2474 }
2475 u64Base = 0;
2476 }
2477 else
2478 {
2479 if (uNewRip > cbLimitCs)
2480 {
2481 Log(("retf %04x:%08RX64 %04x:%08RX64 - out of bounds (%#x)-> #GP(CS).\n",
2482 uNewCs, uNewRip, uNewOuterSs, uNewOuterRsp, cbLimitCs));
2483 /** @todo Intel says this is \#GP(0)! */
2484 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2485 }
2486 u64Base = X86DESC_BASE(&DescCs.Legacy);
2487 }
2488
2489 /*
2490 * Now set the accessed bit before
2491 * writing the return address to the stack and committing the result into
2492 * CS, CSHID and RIP.
2493 */
2494 /** @todo Testcase: Need to check WHEN exactly the CS accessed bit is set. */
2495 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2496 {
2497 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2498 if (rcStrict != VINF_SUCCESS)
2499 return rcStrict;
2500 /** @todo check what VT-x and AMD-V does. */
2501 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2502 }
2503 /** @todo Testcase: Need to check WHEN exactly the SS accessed bit is set. */
2504 if (!(DescSs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2505 {
2506 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewOuterSs);
2507 if (rcStrict != VINF_SUCCESS)
2508 return rcStrict;
2509 /** @todo check what VT-x and AMD-V does. */
2510 DescSs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2511 }
2512
2513 /* commit */
2514 if (enmEffOpSize == IEMMODE_16BIT)
2515 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2516 else
2517 pVCpu->cpum.GstCtx.rip = uNewRip;
2518 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2519 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2520 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2521 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2522 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2523 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2524 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2525 pVCpu->cpum.GstCtx.ss.Sel = uNewOuterSs;
2526 pVCpu->cpum.GstCtx.ss.ValidSel = uNewOuterSs;
2527 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
2528 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSs.Legacy);
2529 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
2530 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2531 pVCpu->cpum.GstCtx.ss.u64Base = 0;
2532 else
2533 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSs.Legacy);
2534 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2535 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewOuterRsp;
2536 else
2537 pVCpu->cpum.GstCtx.rsp = uNewOuterRsp;
2538
2539 pVCpu->iem.s.uCpl = (uNewCs & X86_SEL_RPL);
2540 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
2541 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
2542 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
2543 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
2544
2545 /** @todo check if the hidden bits are loaded correctly for 64-bit
2546 * mode. */
2547
2548 if (cbPop)
2549 iemRegAddToRsp(pVCpu, cbPop);
2550 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2551
2552 /* Done! */
2553 }
2554 /*
2555 * Return to the same privilege level
2556 */
2557 else
2558 {
2559 /* Limit / canonical check. */
2560 uint64_t u64Base;
2561 uint32_t cbLimitCs = X86DESC_LIMIT_G(&DescCs.Legacy);
2562
2563 /** @todo Testcase: Is this correct? */
2564 if ( DescCs.Legacy.Gen.u1Long
2565 && IEM_IS_LONG_MODE(pVCpu) )
2566 {
2567 if (!IEM_IS_CANONICAL(uNewRip))
2568 {
2569 Log(("retf %04x:%08RX64 - not canonical -> #GP\n", uNewCs, uNewRip));
2570 return iemRaiseNotCanonical(pVCpu);
2571 }
2572 u64Base = 0;
2573 }
2574 else
2575 {
2576 if (uNewRip > cbLimitCs)
2577 {
2578 Log(("retf %04x:%08RX64 -> out of bounds (%#x)\n", uNewCs, uNewRip, cbLimitCs));
2579 /** @todo Intel says this is \#GP(0)! */
2580 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
2581 }
2582 u64Base = X86DESC_BASE(&DescCs.Legacy);
2583 }
2584
2585 /*
2586 * Now set the accessed bit before
2587 * writing the return address to the stack and committing the result into
2588 * CS, CSHID and RIP.
2589 */
2590 /** @todo Testcase: Need to check WHEN exactly the accessed bit is set. */
2591 if (!(DescCs.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
2592 {
2593 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
2594 if (rcStrict != VINF_SUCCESS)
2595 return rcStrict;
2596 /** @todo check what VT-x and AMD-V does. */
2597 DescCs.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
2598 }
2599
2600 /* commit */
2601 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2602 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
2603 else
2604 pVCpu->cpum.GstCtx.rsp = uNewRsp;
2605 if (enmEffOpSize == IEMMODE_16BIT)
2606 pVCpu->cpum.GstCtx.rip = uNewRip & UINT16_MAX; /** @todo Testcase: When exactly does this occur? With call it happens prior to the limit check according to Intel... */
2607 else
2608 pVCpu->cpum.GstCtx.rip = uNewRip;
2609 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
2610 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
2611 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
2612 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCs.Legacy);
2613 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCs;
2614 pVCpu->cpum.GstCtx.cs.u64Base = u64Base;
2615 /** @todo check if the hidden bits are loaded correctly for 64-bit
2616 * mode. */
2617 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
2618 if (cbPop)
2619 iemRegAddToRsp(pVCpu, cbPop);
2620 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2621 }
2622
2623 /* Flush the prefetch buffer. */
2624#ifdef IEM_WITH_CODE_TLB
2625 pVCpu->iem.s.pbInstrBuf = NULL;
2626#else
2627 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2628#endif
2629 return VINF_SUCCESS;
2630}
2631
2632
2633/**
2634 * Implements retn.
2635 *
2636 * We're doing this in C because of the \#GP that might be raised if the popped
2637 * program counter is out of bounds.
2638 *
2639 * @param enmEffOpSize The effective operand size.
2640 * @param cbPop The amount of arguments to pop from the stack
2641 * (bytes).
2642 */
2643IEM_CIMPL_DEF_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop)
2644{
2645 NOREF(cbInstr);
2646
2647 /* Fetch the RSP from the stack. */
2648 VBOXSTRICTRC rcStrict;
2649 RTUINT64U NewRip;
2650 RTUINT64U NewRsp;
2651 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2652
2653 switch (enmEffOpSize)
2654 {
2655 case IEMMODE_16BIT:
2656 NewRip.u = 0;
2657 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRip.Words.w0, &NewRsp);
2658 break;
2659 case IEMMODE_32BIT:
2660 NewRip.u = 0;
2661 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRip.DWords.dw0, &NewRsp);
2662 break;
2663 case IEMMODE_64BIT:
2664 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRip.u, &NewRsp);
2665 break;
2666 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2667 }
2668 if (rcStrict != VINF_SUCCESS)
2669 return rcStrict;
2670
2671 /* Check the new RSP before loading it. */
2672 /** @todo Should test this as the intel+amd pseudo code doesn't mention half
2673 * of it. The canonical test is performed here and for call. */
2674 if (enmEffOpSize != IEMMODE_64BIT)
2675 {
2676 if (NewRip.DWords.dw0 > pVCpu->cpum.GstCtx.cs.u32Limit)
2677 {
2678 Log(("retn newrip=%llx - out of bounds (%x) -> #GP\n", NewRip.u, pVCpu->cpum.GstCtx.cs.u32Limit));
2679 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2680 }
2681 }
2682 else
2683 {
2684 if (!IEM_IS_CANONICAL(NewRip.u))
2685 {
2686 Log(("retn newrip=%llx - not canonical -> #GP\n", NewRip.u));
2687 return iemRaiseNotCanonical(pVCpu);
2688 }
2689 }
2690
2691 /* Apply cbPop */
2692 if (cbPop)
2693 iemRegAddToRspEx(pVCpu, &NewRsp, cbPop);
2694
2695 /* Commit it. */
2696 pVCpu->cpum.GstCtx.rip = NewRip.u;
2697 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2698 pVCpu->cpum.GstCtx.eflags.Bits.u1RF = 0;
2699
2700 /* Flush the prefetch buffer. */
2701#ifndef IEM_WITH_CODE_TLB
2702 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
2703#endif
2704
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/**
2710 * Implements enter.
2711 *
2712 * We're doing this in C because the instruction is insane, even for the
2713 * u8NestingLevel=0 case dealing with the stack is tedious.
2714 *
2715 * @param enmEffOpSize The effective operand size.
2716 * @param cbFrame Frame size.
2717 * @param cParameters Frame parameter count.
2718 */
2719IEM_CIMPL_DEF_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters)
2720{
2721 /* Push RBP, saving the old value in TmpRbp. */
2722 RTUINT64U NewRsp; NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2723 RTUINT64U TmpRbp; TmpRbp.u = pVCpu->cpum.GstCtx.rbp;
2724 RTUINT64U NewRbp;
2725 VBOXSTRICTRC rcStrict;
2726 if (enmEffOpSize == IEMMODE_64BIT)
2727 {
2728 rcStrict = iemMemStackPushU64Ex(pVCpu, TmpRbp.u, &NewRsp);
2729 NewRbp = NewRsp;
2730 }
2731 else if (enmEffOpSize == IEMMODE_32BIT)
2732 {
2733 rcStrict = iemMemStackPushU32Ex(pVCpu, TmpRbp.DWords.dw0, &NewRsp);
2734 NewRbp = NewRsp;
2735 }
2736 else
2737 {
2738 rcStrict = iemMemStackPushU16Ex(pVCpu, TmpRbp.Words.w0, &NewRsp);
2739 NewRbp = TmpRbp;
2740 NewRbp.Words.w0 = NewRsp.Words.w0;
2741 }
2742 if (rcStrict != VINF_SUCCESS)
2743 return rcStrict;
2744
2745 /* Copy the parameters (aka nesting levels by Intel). */
2746 cParameters &= 0x1f;
2747 if (cParameters > 0)
2748 {
2749 switch (enmEffOpSize)
2750 {
2751 case IEMMODE_16BIT:
2752 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2753 TmpRbp.DWords.dw0 -= 2;
2754 else
2755 TmpRbp.Words.w0 -= 2;
2756 do
2757 {
2758 uint16_t u16Tmp;
2759 rcStrict = iemMemStackPopU16Ex(pVCpu, &u16Tmp, &TmpRbp);
2760 if (rcStrict != VINF_SUCCESS)
2761 break;
2762 rcStrict = iemMemStackPushU16Ex(pVCpu, u16Tmp, &NewRsp);
2763 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2764 break;
2765
2766 case IEMMODE_32BIT:
2767 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2768 TmpRbp.DWords.dw0 -= 4;
2769 else
2770 TmpRbp.Words.w0 -= 4;
2771 do
2772 {
2773 uint32_t u32Tmp;
2774 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Tmp, &TmpRbp);
2775 if (rcStrict != VINF_SUCCESS)
2776 break;
2777 rcStrict = iemMemStackPushU32Ex(pVCpu, u32Tmp, &NewRsp);
2778 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2779 break;
2780
2781 case IEMMODE_64BIT:
2782 TmpRbp.u -= 8;
2783 do
2784 {
2785 uint64_t u64Tmp;
2786 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Tmp, &TmpRbp);
2787 if (rcStrict != VINF_SUCCESS)
2788 break;
2789 rcStrict = iemMemStackPushU64Ex(pVCpu, u64Tmp, &NewRsp);
2790 } while (--cParameters > 0 && rcStrict == VINF_SUCCESS);
2791 break;
2792
2793 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2794 }
2795 if (rcStrict != VINF_SUCCESS)
2796 return VINF_SUCCESS;
2797
2798 /* Push the new RBP */
2799 if (enmEffOpSize == IEMMODE_64BIT)
2800 rcStrict = iemMemStackPushU64Ex(pVCpu, NewRbp.u, &NewRsp);
2801 else if (enmEffOpSize == IEMMODE_32BIT)
2802 rcStrict = iemMemStackPushU32Ex(pVCpu, NewRbp.DWords.dw0, &NewRsp);
2803 else
2804 rcStrict = iemMemStackPushU16Ex(pVCpu, NewRbp.Words.w0, &NewRsp);
2805 if (rcStrict != VINF_SUCCESS)
2806 return rcStrict;
2807
2808 }
2809
2810 /* Recalc RSP. */
2811 iemRegSubFromRspEx(pVCpu, &NewRsp, cbFrame);
2812
2813 /** @todo Should probe write access at the new RSP according to AMD. */
2814 /** @todo Should handle accesses to the VMX APIC-access page. */
2815
2816 /* Commit it. */
2817 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2818 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2819 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2820
2821 return VINF_SUCCESS;
2822}
2823
2824
2825
2826/**
2827 * Implements leave.
2828 *
2829 * We're doing this in C because messing with the stack registers is annoying
2830 * since they depends on SS attributes.
2831 *
2832 * @param enmEffOpSize The effective operand size.
2833 */
2834IEM_CIMPL_DEF_1(iemCImpl_leave, IEMMODE, enmEffOpSize)
2835{
2836 /* Calculate the intermediate RSP from RBP and the stack attributes. */
2837 RTUINT64U NewRsp;
2838 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2839 NewRsp.u = pVCpu->cpum.GstCtx.rbp;
2840 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2841 NewRsp.u = pVCpu->cpum.GstCtx.ebp;
2842 else
2843 {
2844 /** @todo Check that LEAVE actually preserve the high EBP bits. */
2845 NewRsp.u = pVCpu->cpum.GstCtx.rsp;
2846 NewRsp.Words.w0 = pVCpu->cpum.GstCtx.bp;
2847 }
2848
2849 /* Pop RBP according to the operand size. */
2850 VBOXSTRICTRC rcStrict;
2851 RTUINT64U NewRbp;
2852 switch (enmEffOpSize)
2853 {
2854 case IEMMODE_16BIT:
2855 NewRbp.u = pVCpu->cpum.GstCtx.rbp;
2856 rcStrict = iemMemStackPopU16Ex(pVCpu, &NewRbp.Words.w0, &NewRsp);
2857 break;
2858 case IEMMODE_32BIT:
2859 NewRbp.u = 0;
2860 rcStrict = iemMemStackPopU32Ex(pVCpu, &NewRbp.DWords.dw0, &NewRsp);
2861 break;
2862 case IEMMODE_64BIT:
2863 rcStrict = iemMemStackPopU64Ex(pVCpu, &NewRbp.u, &NewRsp);
2864 break;
2865 IEM_NOT_REACHED_DEFAULT_CASE_RET();
2866 }
2867 if (rcStrict != VINF_SUCCESS)
2868 return rcStrict;
2869
2870
2871 /* Commit it. */
2872 pVCpu->cpum.GstCtx.rbp = NewRbp.u;
2873 pVCpu->cpum.GstCtx.rsp = NewRsp.u;
2874 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
2875
2876 return VINF_SUCCESS;
2877}
2878
2879
2880/**
2881 * Implements int3 and int XX.
2882 *
2883 * @param u8Int The interrupt vector number.
2884 * @param enmInt The int instruction type.
2885 */
2886IEM_CIMPL_DEF_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt)
2887{
2888 Assert(pVCpu->iem.s.cXcptRecursions == 0);
2889
2890 /*
2891 * We must check if this INT3 might belong to DBGF before raising a #BP.
2892 */
2893 if (u8Int == 3)
2894 {
2895 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2896 if (pVM->dbgf.ro.cEnabledInt3Breakpoints == 0)
2897 { /* likely: No vbox debugger breakpoints */ }
2898 else
2899 {
2900 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVM, pVCpu, &pVCpu->cpum.GstCtx);
2901 Log(("iemCImpl_int: DBGFTrap03Handler -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));
2902 if (rcStrict != VINF_EM_RAW_GUEST_TRAP)
2903 return iemSetPassUpStatus(pVCpu, rcStrict);
2904 }
2905 }
2906 return iemRaiseXcptOrInt(pVCpu,
2907 cbInstr,
2908 u8Int,
2909 IEM_XCPT_FLAGS_T_SOFT_INT | enmInt,
2910 0,
2911 0);
2912}
2913
2914
2915/**
2916 * Implements iret for real mode and V8086 mode.
2917 *
2918 * @param enmEffOpSize The effective operand size.
2919 */
2920IEM_CIMPL_DEF_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize)
2921{
2922 X86EFLAGS Efl;
2923 Efl.u = IEMMISC_GET_EFL(pVCpu);
2924 NOREF(cbInstr);
2925
2926 /*
2927 * iret throws an exception if VME isn't enabled.
2928 */
2929 if ( Efl.Bits.u1VM
2930 && Efl.Bits.u2IOPL != 3
2931 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME))
2932 return iemRaiseGeneralProtectionFault0(pVCpu);
2933
2934 /*
2935 * Do the stack bits, but don't commit RSP before everything checks
2936 * out right.
2937 */
2938 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2939 VBOXSTRICTRC rcStrict;
2940 RTCPTRUNION uFrame;
2941 uint16_t uNewCs;
2942 uint32_t uNewEip;
2943 uint32_t uNewFlags;
2944 uint64_t uNewRsp;
2945 if (enmEffOpSize == IEMMODE_32BIT)
2946 {
2947 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 1, &uFrame.pv, &uNewRsp);
2948 if (rcStrict != VINF_SUCCESS)
2949 return rcStrict;
2950 uNewEip = uFrame.pu32[0];
2951 if (uNewEip > UINT16_MAX)
2952 return iemRaiseGeneralProtectionFault0(pVCpu);
2953
2954 uNewCs = (uint16_t)uFrame.pu32[1];
2955 uNewFlags = uFrame.pu32[2];
2956 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2957 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT
2958 | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
2959 | X86_EFL_ID;
2960 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
2961 uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
2962 uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
2963 }
2964 else
2965 {
2966 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
2967 if (rcStrict != VINF_SUCCESS)
2968 return rcStrict;
2969 uNewEip = uFrame.pu16[0];
2970 uNewCs = uFrame.pu16[1];
2971 uNewFlags = uFrame.pu16[2];
2972 uNewFlags &= X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
2973 | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT;
2974 uNewFlags |= Efl.u & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF);
2975 /** @todo The intel pseudo code does not indicate what happens to
2976 * reserved flags. We just ignore them. */
2977 /* Ancient CPU adjustments: See iemCImpl_popf. */
2978 if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_286)
2979 uNewFlags &= ~(X86_EFL_NT | X86_EFL_IOPL);
2980 }
2981 rcStrict = iemMemStackPopDoneSpecial(pVCpu, uFrame.pv);
2982 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2983 { /* extremely likely */ }
2984 else
2985 return rcStrict;
2986
2987 /** @todo Check how this is supposed to work if sp=0xfffe. */
2988 Log7(("iemCImpl_iret_real_v8086: uNewCs=%#06x uNewRip=%#010x uNewFlags=%#x uNewRsp=%#18llx\n",
2989 uNewCs, uNewEip, uNewFlags, uNewRsp));
2990
2991 /*
2992 * Check the limit of the new EIP.
2993 */
2994 /** @todo Only the AMD pseudo code check the limit here, what's
2995 * right? */
2996 if (uNewEip > pVCpu->cpum.GstCtx.cs.u32Limit)
2997 return iemRaiseSelectorBounds(pVCpu, X86_SREG_CS, IEM_ACCESS_INSTRUCTION);
2998
2999 /*
3000 * V8086 checks and flag adjustments
3001 */
3002 if (Efl.Bits.u1VM)
3003 {
3004 if (Efl.Bits.u2IOPL == 3)
3005 {
3006 /* Preserve IOPL and clear RF. */
3007 uNewFlags &= ~(X86_EFL_IOPL | X86_EFL_RF);
3008 uNewFlags |= Efl.u & (X86_EFL_IOPL);
3009 }
3010 else if ( enmEffOpSize == IEMMODE_16BIT
3011 && ( !(uNewFlags & X86_EFL_IF)
3012 || !Efl.Bits.u1VIP )
3013 && !(uNewFlags & X86_EFL_TF) )
3014 {
3015 /* Move IF to VIF, clear RF and preserve IF and IOPL.*/
3016 uNewFlags &= ~X86_EFL_VIF;
3017 uNewFlags |= (uNewFlags & X86_EFL_IF) << (19 - 9);
3018 uNewFlags &= ~(X86_EFL_IF | X86_EFL_IOPL | X86_EFL_RF);
3019 uNewFlags |= Efl.u & (X86_EFL_IF | X86_EFL_IOPL);
3020 }
3021 else
3022 return iemRaiseGeneralProtectionFault0(pVCpu);
3023 Log7(("iemCImpl_iret_real_v8086: u1VM=1: adjusted uNewFlags=%#x\n", uNewFlags));
3024 }
3025
3026 /*
3027 * Commit the operation.
3028 */
3029#ifdef DBGFTRACE_ENABLED
3030 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/rm %04x:%04x -> %04x:%04x %x %04llx",
3031 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewRsp);
3032#endif
3033 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3034 pVCpu->cpum.GstCtx.rip = uNewEip;
3035 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3036 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3037 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3038 pVCpu->cpum.GstCtx.cs.u64Base = (uint32_t)uNewCs << 4;
3039 /** @todo do we load attribs and limit as well? */
3040 Assert(uNewFlags & X86_EFL_1);
3041 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3042
3043 /* Flush the prefetch buffer. */
3044#ifdef IEM_WITH_CODE_TLB
3045 pVCpu->iem.s.pbInstrBuf = NULL;
3046#else
3047 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3048#endif
3049
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/**
3055 * Loads a segment register when entering V8086 mode.
3056 *
3057 * @param pSReg The segment register.
3058 * @param uSeg The segment to load.
3059 */
3060static void iemCImplCommonV8086LoadSeg(PCPUMSELREG pSReg, uint16_t uSeg)
3061{
3062 pSReg->Sel = uSeg;
3063 pSReg->ValidSel = uSeg;
3064 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
3065 pSReg->u64Base = (uint32_t)uSeg << 4;
3066 pSReg->u32Limit = 0xffff;
3067 pSReg->Attr.u = X86_SEL_TYPE_RW_ACC | RT_BIT(4) /*!sys*/ | RT_BIT(7) /*P*/ | (3 /*DPL*/ << 5); /* VT-x wants 0xf3 */
3068 /** @todo Testcase: Check if VT-x really needs this and what it does itself when
3069 * IRET'ing to V8086. */
3070}
3071
3072
3073/**
3074 * Implements iret for protected mode returning to V8086 mode.
3075 *
3076 * @param uNewEip The new EIP.
3077 * @param uNewCs The new CS.
3078 * @param uNewFlags The new EFLAGS.
3079 * @param uNewRsp The RSP after the initial IRET frame.
3080 *
3081 * @note This can only be a 32-bit iret du to the X86_EFL_VM position.
3082 */
3083IEM_CIMPL_DEF_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp)
3084{
3085 RT_NOREF_PV(cbInstr);
3086 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK);
3087
3088 /*
3089 * Pop the V8086 specific frame bits off the stack.
3090 */
3091 VBOXSTRICTRC rcStrict;
3092 RTCPTRUNION uFrame;
3093 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 24 /*cbMem*/, &uFrame.pv, uNewRsp);
3094 if (rcStrict != VINF_SUCCESS)
3095 return rcStrict;
3096 uint32_t uNewEsp = uFrame.pu32[0];
3097 uint16_t uNewSs = uFrame.pu32[1];
3098 uint16_t uNewEs = uFrame.pu32[2];
3099 uint16_t uNewDs = uFrame.pu32[3];
3100 uint16_t uNewFs = uFrame.pu32[4];
3101 uint16_t uNewGs = uFrame.pu32[5];
3102 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R); /* don't use iemMemStackPopCommitSpecial here. */
3103 if (rcStrict != VINF_SUCCESS)
3104 return rcStrict;
3105
3106 /*
3107 * Commit the operation.
3108 */
3109 uNewFlags &= X86_EFL_LIVE_MASK;
3110 uNewFlags |= X86_EFL_RA1_MASK;
3111#ifdef DBGFTRACE_ENABLED
3112 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/p/v %04x:%08x -> %04x:%04x %x %04x:%04x",
3113 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp);
3114#endif
3115 Log7(("iemCImpl_iret_prot_v8086: %04x:%08x -> %04x:%04x %x %04x:%04x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, uNewCs, uNewEip, uNewFlags, uNewSs, uNewEsp));
3116
3117 IEMMISC_SET_EFL(pVCpu, uNewFlags);
3118 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.cs, uNewCs);
3119 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ss, uNewSs);
3120 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.es, uNewEs);
3121 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.ds, uNewDs);
3122 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.fs, uNewFs);
3123 iemCImplCommonV8086LoadSeg(&pVCpu->cpum.GstCtx.gs, uNewGs);
3124 pVCpu->cpum.GstCtx.rip = (uint16_t)uNewEip;
3125 pVCpu->cpum.GstCtx.rsp = uNewEsp; /** @todo check this out! */
3126 pVCpu->iem.s.uCpl = 3;
3127
3128 /* Flush the prefetch buffer. */
3129#ifdef IEM_WITH_CODE_TLB
3130 pVCpu->iem.s.pbInstrBuf = NULL;
3131#else
3132 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3133#endif
3134
3135 return VINF_SUCCESS;
3136}
3137
3138
3139/**
3140 * Implements iret for protected mode returning via a nested task.
3141 *
3142 * @param enmEffOpSize The effective operand size.
3143 */
3144IEM_CIMPL_DEF_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize)
3145{
3146 Log7(("iemCImpl_iret_prot_NestedTask:\n"));
3147#ifndef IEM_IMPLEMENTS_TASKSWITCH
3148 IEM_RETURN_ASPECT_NOT_IMPLEMENTED();
3149#else
3150 RT_NOREF_PV(enmEffOpSize);
3151
3152 /*
3153 * Read the segment selector in the link-field of the current TSS.
3154 */
3155 RTSEL uSelRet;
3156 VBOXSTRICTRC rcStrict = iemMemFetchSysU16(pVCpu, &uSelRet, UINT8_MAX, pVCpu->cpum.GstCtx.tr.u64Base);
3157 if (rcStrict != VINF_SUCCESS)
3158 return rcStrict;
3159
3160 /*
3161 * Fetch the returning task's TSS descriptor from the GDT.
3162 */
3163 if (uSelRet & X86_SEL_LDT)
3164 {
3165 Log(("iret_prot_NestedTask TSS not in LDT. uSelRet=%04x -> #TS\n", uSelRet));
3166 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet);
3167 }
3168
3169 IEMSELDESC TssDesc;
3170 rcStrict = iemMemFetchSelDesc(pVCpu, &TssDesc, uSelRet, X86_XCPT_GP);
3171 if (rcStrict != VINF_SUCCESS)
3172 return rcStrict;
3173
3174 if (TssDesc.Legacy.Gate.u1DescType)
3175 {
3176 Log(("iret_prot_NestedTask Invalid TSS type. uSelRet=%04x -> #TS\n", uSelRet));
3177 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3178 }
3179
3180 if ( TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_286_TSS_BUSY
3181 && TssDesc.Legacy.Gate.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
3182 {
3183 Log(("iret_prot_NestedTask TSS is not busy. uSelRet=%04x DescType=%#x -> #TS\n", uSelRet, TssDesc.Legacy.Gate.u4Type));
3184 return iemRaiseTaskSwitchFaultBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3185 }
3186
3187 if (!TssDesc.Legacy.Gate.u1Present)
3188 {
3189 Log(("iret_prot_NestedTask TSS is not present. uSelRet=%04x -> #NP\n", uSelRet));
3190 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSelRet & X86_SEL_MASK_OFF_RPL);
3191 }
3192
3193 uint32_t uNextEip = pVCpu->cpum.GstCtx.eip + cbInstr;
3194 return iemTaskSwitch(pVCpu, IEMTASKSWITCH_IRET, uNextEip, 0 /* fFlags */, 0 /* uErr */,
3195 0 /* uCr2 */, uSelRet, &TssDesc);
3196#endif
3197}
3198
3199
3200/**
3201 * Implements iret for protected mode
3202 *
3203 * @param enmEffOpSize The effective operand size.
3204 */
3205IEM_CIMPL_DEF_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize)
3206{
3207 NOREF(cbInstr);
3208 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3209
3210 /*
3211 * Nested task return.
3212 */
3213 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3214 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot_NestedTask, enmEffOpSize);
3215
3216 /*
3217 * Normal return.
3218 *
3219 * Do the stack bits, but don't commit RSP before everything checks
3220 * out right.
3221 */
3222 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
3223 VBOXSTRICTRC rcStrict;
3224 RTCPTRUNION uFrame;
3225 uint16_t uNewCs;
3226 uint32_t uNewEip;
3227 uint32_t uNewFlags;
3228 uint64_t uNewRsp;
3229 if (enmEffOpSize == IEMMODE_32BIT)
3230 {
3231 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 12, 3, &uFrame.pv, &uNewRsp);
3232 if (rcStrict != VINF_SUCCESS)
3233 return rcStrict;
3234 uNewEip = uFrame.pu32[0];
3235 uNewCs = (uint16_t)uFrame.pu32[1];
3236 uNewFlags = uFrame.pu32[2];
3237 }
3238 else
3239 {
3240 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 6, 1, &uFrame.pv, &uNewRsp);
3241 if (rcStrict != VINF_SUCCESS)
3242 return rcStrict;
3243 uNewEip = uFrame.pu16[0];
3244 uNewCs = uFrame.pu16[1];
3245 uNewFlags = uFrame.pu16[2];
3246 }
3247 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3248 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3249 { /* extremely likely */ }
3250 else
3251 return rcStrict;
3252 Log7(("iemCImpl_iret_prot: uNewCs=%#06x uNewEip=%#010x uNewFlags=%#x uNewRsp=%#18llx uCpl=%u\n", uNewCs, uNewEip, uNewFlags, uNewRsp, pVCpu->iem.s.uCpl));
3253
3254 /*
3255 * We're hopefully not returning to V8086 mode...
3256 */
3257 if ( (uNewFlags & X86_EFL_VM)
3258 && pVCpu->iem.s.uCpl == 0)
3259 {
3260 Assert(enmEffOpSize == IEMMODE_32BIT);
3261 return IEM_CIMPL_CALL_4(iemCImpl_iret_prot_v8086, uNewEip, uNewCs, uNewFlags, uNewRsp);
3262 }
3263
3264 /*
3265 * Protected mode.
3266 */
3267 /* Read the CS descriptor. */
3268 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3269 {
3270 Log(("iret %04x:%08x -> invalid CS selector, #GP(0)\n", uNewCs, uNewEip));
3271 return iemRaiseGeneralProtectionFault0(pVCpu);
3272 }
3273
3274 IEMSELDESC DescCS;
3275 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3276 if (rcStrict != VINF_SUCCESS)
3277 {
3278 Log(("iret %04x:%08x - rcStrict=%Rrc when fetching CS\n", uNewCs, uNewEip, VBOXSTRICTRC_VAL(rcStrict)));
3279 return rcStrict;
3280 }
3281
3282 /* Must be a code descriptor. */
3283 if (!DescCS.Legacy.Gen.u1DescType)
3284 {
3285 Log(("iret %04x:%08x - CS is system segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3286 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3287 }
3288 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3289 {
3290 Log(("iret %04x:%08x - not code segment (%#x) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u4Type));
3291 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3292 }
3293
3294 /* Privilege checks. */
3295 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3296 {
3297 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3298 {
3299 Log(("iret %04x:%08x - RPL != DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3300 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3301 }
3302 }
3303 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3304 {
3305 Log(("iret %04x:%08x - RPL < DPL (%d) -> #GP\n", uNewCs, uNewEip, DescCS.Legacy.Gen.u2Dpl));
3306 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3307 }
3308 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3309 {
3310 Log(("iret %04x:%08x - RPL < CPL (%d) -> #GP\n", uNewCs, uNewEip, pVCpu->iem.s.uCpl));
3311 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3312 }
3313
3314 /* Present? */
3315 if (!DescCS.Legacy.Gen.u1Present)
3316 {
3317 Log(("iret %04x:%08x - CS not present -> #NP\n", uNewCs, uNewEip));
3318 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3319 }
3320
3321 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3322
3323 /*
3324 * Return to outer level?
3325 */
3326 if ((uNewCs & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
3327 {
3328 uint16_t uNewSS;
3329 uint32_t uNewESP;
3330 if (enmEffOpSize == IEMMODE_32BIT)
3331 {
3332 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0/*off*/, 8 /*cbMem*/, &uFrame.pv, uNewRsp);
3333 if (rcStrict != VINF_SUCCESS)
3334 return rcStrict;
3335/** @todo We might be popping a 32-bit ESP from the IRET frame, but whether
3336 * 16-bit or 32-bit are being loaded into SP depends on the D/B
3337 * bit of the popped SS selector it turns out. */
3338 uNewESP = uFrame.pu32[0];
3339 uNewSS = (uint16_t)uFrame.pu32[1];
3340 }
3341 else
3342 {
3343 rcStrict = iemMemStackPopContinueSpecial(pVCpu, 0 /*off*/, 4 /*cbMem*/, &uFrame.pv, uNewRsp);
3344 if (rcStrict != VINF_SUCCESS)
3345 return rcStrict;
3346 uNewESP = uFrame.pu16[0];
3347 uNewSS = uFrame.pu16[1];
3348 }
3349 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uFrame.pv, IEM_ACCESS_STACK_R);
3350 if (rcStrict != VINF_SUCCESS)
3351 return rcStrict;
3352 Log7(("iemCImpl_iret_prot: uNewSS=%#06x uNewESP=%#010x\n", uNewSS, uNewESP));
3353
3354 /* Read the SS descriptor. */
3355 if (!(uNewSS & X86_SEL_MASK_OFF_RPL))
3356 {
3357 Log(("iret %04x:%08x/%04x:%08x -> invalid SS selector, #GP(0)\n", uNewCs, uNewEip, uNewSS, uNewESP));
3358 return iemRaiseGeneralProtectionFault0(pVCpu);
3359 }
3360
3361 IEMSELDESC DescSS;
3362 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSS, X86_XCPT_GP); /** @todo Correct exception? */
3363 if (rcStrict != VINF_SUCCESS)
3364 {
3365 Log(("iret %04x:%08x/%04x:%08x - %Rrc when fetching SS\n",
3366 uNewCs, uNewEip, uNewSS, uNewESP, VBOXSTRICTRC_VAL(rcStrict)));
3367 return rcStrict;
3368 }
3369
3370 /* Privilege checks. */
3371 if ((uNewSS & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3372 {
3373 Log(("iret %04x:%08x/%04x:%08x -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewEip, uNewSS, uNewESP));
3374 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3375 }
3376 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3377 {
3378 Log(("iret %04x:%08x/%04x:%08x -> SS.DPL (%d) != CS.RPL -> #GP\n",
3379 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u2Dpl));
3380 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3381 }
3382
3383 /* Must be a writeable data segment descriptor. */
3384 if (!DescSS.Legacy.Gen.u1DescType)
3385 {
3386 Log(("iret %04x:%08x/%04x:%08x -> SS is system segment (%#x) -> #GP\n",
3387 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3388 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3389 }
3390 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3391 {
3392 Log(("iret %04x:%08x/%04x:%08x - not writable data segment (%#x) -> #GP\n",
3393 uNewCs, uNewEip, uNewSS, uNewESP, DescSS.Legacy.Gen.u4Type));
3394 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSS);
3395 }
3396
3397 /* Present? */
3398 if (!DescSS.Legacy.Gen.u1Present)
3399 {
3400 Log(("iret %04x:%08x/%04x:%08x -> SS not present -> #SS\n", uNewCs, uNewEip, uNewSS, uNewESP));
3401 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSS);
3402 }
3403
3404 uint32_t cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3405
3406 /* Check EIP. */
3407 if (uNewEip > cbLimitCS)
3408 {
3409 Log(("iret %04x:%08x/%04x:%08x -> EIP is out of bounds (%#x) -> #GP(0)\n",
3410 uNewCs, uNewEip, uNewSS, uNewESP, cbLimitCS));
3411 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3412 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3413 }
3414
3415 /*
3416 * Commit the changes, marking CS and SS accessed first since
3417 * that may fail.
3418 */
3419 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3420 {
3421 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3422 if (rcStrict != VINF_SUCCESS)
3423 return rcStrict;
3424 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3425 }
3426 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3427 {
3428 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSS);
3429 if (rcStrict != VINF_SUCCESS)
3430 return rcStrict;
3431 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3432 }
3433
3434 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3435 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3436 if (enmEffOpSize != IEMMODE_16BIT)
3437 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3438 if (pVCpu->iem.s.uCpl == 0)
3439 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3440 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3441 fEFlagsMask |= X86_EFL_IF;
3442 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3443 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3444 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3445 fEFlagsNew &= ~fEFlagsMask;
3446 fEFlagsNew |= uNewFlags & fEFlagsMask;
3447#ifdef DBGFTRACE_ENABLED
3448 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up%u %04x:%08x -> %04x:%04x %x %04x:%04x",
3449 pVCpu->iem.s.uCpl, uNewCs & X86_SEL_RPL, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3450 uNewCs, uNewEip, uNewFlags, uNewSS, uNewESP);
3451#endif
3452
3453 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3454 pVCpu->cpum.GstCtx.rip = uNewEip;
3455 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3456 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3457 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3458 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3459 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3460 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3461 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3462
3463 pVCpu->cpum.GstCtx.ss.Sel = uNewSS;
3464 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSS;
3465 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3466 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3467 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3468 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3469 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3470 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewESP;
3471 else
3472 pVCpu->cpum.GstCtx.rsp = uNewESP;
3473
3474 pVCpu->iem.s.uCpl = uNewCs & X86_SEL_RPL;
3475 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.ds);
3476 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.es);
3477 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.fs);
3478 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCs & X86_SEL_RPL, &pVCpu->cpum.GstCtx.gs);
3479
3480 /* Done! */
3481
3482 }
3483 /*
3484 * Return to the same level.
3485 */
3486 else
3487 {
3488 /* Check EIP. */
3489 if (uNewEip > cbLimitCS)
3490 {
3491 Log(("iret %04x:%08x - EIP is out of bounds (%#x) -> #GP(0)\n", uNewCs, uNewEip, cbLimitCS));
3492 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3493 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3494 }
3495
3496 /*
3497 * Commit the changes, marking CS first since it may fail.
3498 */
3499 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3500 {
3501 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3502 if (rcStrict != VINF_SUCCESS)
3503 return rcStrict;
3504 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3505 }
3506
3507 X86EFLAGS NewEfl;
3508 NewEfl.u = IEMMISC_GET_EFL(pVCpu);
3509 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3510 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3511 if (enmEffOpSize != IEMMODE_16BIT)
3512 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3513 if (pVCpu->iem.s.uCpl == 0)
3514 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is 0 */
3515 else if (pVCpu->iem.s.uCpl <= NewEfl.Bits.u2IOPL)
3516 fEFlagsMask |= X86_EFL_IF;
3517 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
3518 fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
3519 NewEfl.u &= ~fEFlagsMask;
3520 NewEfl.u |= fEFlagsMask & uNewFlags;
3521#ifdef DBGFTRACE_ENABLED
3522 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%up %04x:%08x -> %04x:%04x %x %04x:%04llx",
3523 pVCpu->iem.s.uCpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip,
3524 uNewCs, uNewEip, uNewFlags, pVCpu->cpum.GstCtx.ss.Sel, uNewRsp);
3525#endif
3526
3527 IEMMISC_SET_EFL(pVCpu, NewEfl.u);
3528 pVCpu->cpum.GstCtx.rip = uNewEip;
3529 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3530 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3531 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3532 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3533 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3534 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3535 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3536 if (!pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
3537 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3538 else
3539 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3540 /* Done! */
3541 }
3542
3543 /* Flush the prefetch buffer. */
3544#ifdef IEM_WITH_CODE_TLB
3545 pVCpu->iem.s.pbInstrBuf = NULL;
3546#else
3547 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3548#endif
3549
3550 return VINF_SUCCESS;
3551}
3552
3553
3554/**
3555 * Implements iret for long mode
3556 *
3557 * @param enmEffOpSize The effective operand size.
3558 */
3559IEM_CIMPL_DEF_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize)
3560{
3561 NOREF(cbInstr);
3562
3563 /*
3564 * Nested task return is not supported in long mode.
3565 */
3566 if (pVCpu->cpum.GstCtx.eflags.Bits.u1NT)
3567 {
3568 Log(("iretq with NT=1 (eflags=%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.eflags.u));
3569 return iemRaiseGeneralProtectionFault0(pVCpu);
3570 }
3571
3572 /*
3573 * Normal return.
3574 *
3575 * Do the stack bits, but don't commit RSP before everything checks
3576 * out right.
3577 */
3578 VBOXSTRICTRC rcStrict;
3579 RTCPTRUNION uFrame;
3580 uint64_t uNewRip;
3581 uint16_t uNewCs;
3582 uint16_t uNewSs;
3583 uint32_t uNewFlags;
3584 uint64_t uNewRsp;
3585 if (enmEffOpSize == IEMMODE_64BIT)
3586 {
3587 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*8, 7, &uFrame.pv, &uNewRsp);
3588 if (rcStrict != VINF_SUCCESS)
3589 return rcStrict;
3590 uNewRip = uFrame.pu64[0];
3591 uNewCs = (uint16_t)uFrame.pu64[1];
3592 uNewFlags = (uint32_t)uFrame.pu64[2];
3593 uNewRsp = uFrame.pu64[3];
3594 uNewSs = (uint16_t)uFrame.pu64[4];
3595 }
3596 else if (enmEffOpSize == IEMMODE_32BIT)
3597 {
3598 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*4, 3, &uFrame.pv, &uNewRsp);
3599 if (rcStrict != VINF_SUCCESS)
3600 return rcStrict;
3601 uNewRip = uFrame.pu32[0];
3602 uNewCs = (uint16_t)uFrame.pu32[1];
3603 uNewFlags = uFrame.pu32[2];
3604 uNewRsp = uFrame.pu32[3];
3605 uNewSs = (uint16_t)uFrame.pu32[4];
3606 }
3607 else
3608 {
3609 Assert(enmEffOpSize == IEMMODE_16BIT);
3610 rcStrict = iemMemStackPopBeginSpecial(pVCpu, 5*2, 1, &uFrame.pv, &uNewRsp);
3611 if (rcStrict != VINF_SUCCESS)
3612 return rcStrict;
3613 uNewRip = uFrame.pu16[0];
3614 uNewCs = uFrame.pu16[1];
3615 uNewFlags = uFrame.pu16[2];
3616 uNewRsp = uFrame.pu16[3];
3617 uNewSs = uFrame.pu16[4];
3618 }
3619 rcStrict = iemMemStackPopDoneSpecial(pVCpu, (void *)uFrame.pv); /* don't use iemMemStackPopCommitSpecial here. */
3620 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3621 { /* extremely like */ }
3622 else
3623 return rcStrict;
3624 Log7(("iretq stack: cs:rip=%04x:%016RX64 rflags=%016RX64 ss:rsp=%04x:%016RX64\n", uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp));
3625
3626 /*
3627 * Check stuff.
3628 */
3629 /* Read the CS descriptor. */
3630 if (!(uNewCs & X86_SEL_MASK_OFF_RPL))
3631 {
3632 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid CS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3633 return iemRaiseGeneralProtectionFault0(pVCpu);
3634 }
3635
3636 IEMSELDESC DescCS;
3637 rcStrict = iemMemFetchSelDesc(pVCpu, &DescCS, uNewCs, X86_XCPT_GP);
3638 if (rcStrict != VINF_SUCCESS)
3639 {
3640 Log(("iret %04x:%016RX64/%04x:%016RX64 - rcStrict=%Rrc when fetching CS\n",
3641 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3642 return rcStrict;
3643 }
3644
3645 /* Must be a code descriptor. */
3646 if ( !DescCS.Legacy.Gen.u1DescType
3647 || !(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE))
3648 {
3649 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS is not a code segment T=%u T=%#xu -> #GP\n",
3650 uNewCs, uNewRip, uNewSs, uNewRsp, DescCS.Legacy.Gen.u1DescType, DescCS.Legacy.Gen.u4Type));
3651 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3652 }
3653
3654 /* Privilege checks. */
3655 uint8_t const uNewCpl = uNewCs & X86_SEL_RPL;
3656 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_CONF))
3657 {
3658 if ((uNewCs & X86_SEL_RPL) != DescCS.Legacy.Gen.u2Dpl)
3659 {
3660 Log(("iret %04x:%016RX64 - RPL != DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3661 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3662 }
3663 }
3664 else if ((uNewCs & X86_SEL_RPL) < DescCS.Legacy.Gen.u2Dpl)
3665 {
3666 Log(("iret %04x:%016RX64 - RPL < DPL (%d) -> #GP\n", uNewCs, uNewRip, DescCS.Legacy.Gen.u2Dpl));
3667 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3668 }
3669 if ((uNewCs & X86_SEL_RPL) < pVCpu->iem.s.uCpl)
3670 {
3671 Log(("iret %04x:%016RX64 - RPL < CPL (%d) -> #GP\n", uNewCs, uNewRip, pVCpu->iem.s.uCpl));
3672 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewCs);
3673 }
3674
3675 /* Present? */
3676 if (!DescCS.Legacy.Gen.u1Present)
3677 {
3678 Log(("iret %04x:%016RX64/%04x:%016RX64 - CS not present -> #NP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3679 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewCs);
3680 }
3681
3682 uint32_t cbLimitCS = X86DESC_LIMIT_G(&DescCS.Legacy);
3683
3684 /* Read the SS descriptor. */
3685 IEMSELDESC DescSS;
3686 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3687 {
3688 if ( !DescCS.Legacy.Gen.u1Long
3689 || DescCS.Legacy.Gen.u1DefBig /** @todo exactly how does iret (and others) behave with u1Long=1 and u1DefBig=1? \#GP(sel)? */
3690 || uNewCpl > 2) /** @todo verify SS=0 impossible for ring-3. */
3691 {
3692 Log(("iret %04x:%016RX64/%04x:%016RX64 -> invalid SS selector, #GP(0)\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3693 return iemRaiseGeneralProtectionFault0(pVCpu);
3694 }
3695 DescSS.Legacy.u = 0;
3696 }
3697 else
3698 {
3699 rcStrict = iemMemFetchSelDesc(pVCpu, &DescSS, uNewSs, X86_XCPT_GP); /** @todo Correct exception? */
3700 if (rcStrict != VINF_SUCCESS)
3701 {
3702 Log(("iret %04x:%016RX64/%04x:%016RX64 - %Rrc when fetching SS\n",
3703 uNewCs, uNewRip, uNewSs, uNewRsp, VBOXSTRICTRC_VAL(rcStrict)));
3704 return rcStrict;
3705 }
3706 }
3707
3708 /* Privilege checks. */
3709 if ((uNewSs & X86_SEL_RPL) != (uNewCs & X86_SEL_RPL))
3710 {
3711 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.RPL != CS.RPL -> #GP\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3712 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3713 }
3714
3715 uint32_t cbLimitSs;
3716 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3717 cbLimitSs = UINT32_MAX;
3718 else
3719 {
3720 if (DescSS.Legacy.Gen.u2Dpl != (uNewCs & X86_SEL_RPL))
3721 {
3722 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS.DPL (%d) != CS.RPL -> #GP\n",
3723 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u2Dpl));
3724 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3725 }
3726
3727 /* Must be a writeable data segment descriptor. */
3728 if (!DescSS.Legacy.Gen.u1DescType)
3729 {
3730 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS is system segment (%#x) -> #GP\n",
3731 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3732 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3733 }
3734 if ((DescSS.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
3735 {
3736 Log(("iret %04x:%016RX64/%04x:%016RX64 - not writable data segment (%#x) -> #GP\n",
3737 uNewCs, uNewRip, uNewSs, uNewRsp, DescSS.Legacy.Gen.u4Type));
3738 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewSs);
3739 }
3740
3741 /* Present? */
3742 if (!DescSS.Legacy.Gen.u1Present)
3743 {
3744 Log(("iret %04x:%016RX64/%04x:%016RX64 -> SS not present -> #SS\n", uNewCs, uNewRip, uNewSs, uNewRsp));
3745 return iemRaiseStackSelectorNotPresentBySelector(pVCpu, uNewSs);
3746 }
3747 cbLimitSs = X86DESC_LIMIT_G(&DescSS.Legacy);
3748 }
3749
3750 /* Check EIP. */
3751 if (DescCS.Legacy.Gen.u1Long)
3752 {
3753 if (!IEM_IS_CANONICAL(uNewRip))
3754 {
3755 Log(("iret %04x:%016RX64/%04x:%016RX64 -> RIP is not canonical -> #GP(0)\n",
3756 uNewCs, uNewRip, uNewSs, uNewRsp));
3757 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3758 }
3759 }
3760 else
3761 {
3762 if (uNewRip > cbLimitCS)
3763 {
3764 Log(("iret %04x:%016RX64/%04x:%016RX64 -> EIP is out of bounds (%#x) -> #GP(0)\n",
3765 uNewCs, uNewRip, uNewSs, uNewRsp, cbLimitCS));
3766 /** @todo Which is it, \#GP(0) or \#GP(sel)? */
3767 return iemRaiseSelectorBoundsBySelector(pVCpu, uNewCs);
3768 }
3769 }
3770
3771 /*
3772 * Commit the changes, marking CS and SS accessed first since
3773 * that may fail.
3774 */
3775 /** @todo where exactly are these actually marked accessed by a real CPU? */
3776 if (!(DescCS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3777 {
3778 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewCs);
3779 if (rcStrict != VINF_SUCCESS)
3780 return rcStrict;
3781 DescCS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3782 }
3783 if (!(DescSS.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
3784 {
3785 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uNewSs);
3786 if (rcStrict != VINF_SUCCESS)
3787 return rcStrict;
3788 DescSS.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
3789 }
3790
3791 uint32_t fEFlagsMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF
3792 | X86_EFL_TF | X86_EFL_DF | X86_EFL_OF | X86_EFL_NT;
3793 if (enmEffOpSize != IEMMODE_16BIT)
3794 fEFlagsMask |= X86_EFL_RF | X86_EFL_AC | X86_EFL_ID;
3795 if (pVCpu->iem.s.uCpl == 0)
3796 fEFlagsMask |= X86_EFL_IF | X86_EFL_IOPL | X86_EFL_VIF | X86_EFL_VIP; /* VM is ignored */
3797 else if (pVCpu->iem.s.uCpl <= pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL)
3798 fEFlagsMask |= X86_EFL_IF;
3799 uint32_t fEFlagsNew = IEMMISC_GET_EFL(pVCpu);
3800 fEFlagsNew &= ~fEFlagsMask;
3801 fEFlagsNew |= uNewFlags & fEFlagsMask;
3802#ifdef DBGFTRACE_ENABLED
3803 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "iret/%ul%u %08llx -> %04x:%04llx %llx %04x:%04llx",
3804 pVCpu->iem.s.uCpl, uNewCpl, pVCpu->cpum.GstCtx.rip, uNewCs, uNewRip, uNewFlags, uNewSs, uNewRsp);
3805#endif
3806
3807 IEMMISC_SET_EFL(pVCpu, fEFlagsNew);
3808 pVCpu->cpum.GstCtx.rip = uNewRip;
3809 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
3810 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
3811 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
3812 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESC_GET_HID_ATTR(&DescCS.Legacy);
3813 pVCpu->cpum.GstCtx.cs.u32Limit = cbLimitCS;
3814 pVCpu->cpum.GstCtx.cs.u64Base = X86DESC_BASE(&DescCS.Legacy);
3815 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
3816 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
3817 pVCpu->cpum.GstCtx.rsp = uNewRsp;
3818 else
3819 pVCpu->cpum.GstCtx.sp = (uint16_t)uNewRsp;
3820 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
3821 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
3822 if (!(uNewSs & X86_SEL_MASK_OFF_RPL))
3823 {
3824 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3825 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_UNUSABLE | (uNewCpl << X86DESCATTR_DPL_SHIFT);
3826 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
3827 pVCpu->cpum.GstCtx.ss.u64Base = 0;
3828 Log2(("iretq new SS: NULL\n"));
3829 }
3830 else
3831 {
3832 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
3833 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESC_GET_HID_ATTR(&DescSS.Legacy);
3834 pVCpu->cpum.GstCtx.ss.u32Limit = cbLimitSs;
3835 pVCpu->cpum.GstCtx.ss.u64Base = X86DESC_BASE(&DescSS.Legacy);
3836 Log2(("iretq new SS: base=%#RX64 lim=%#x attr=%#x\n", pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
3837 }
3838
3839 if (pVCpu->iem.s.uCpl != uNewCpl)
3840 {
3841 pVCpu->iem.s.uCpl = uNewCpl;
3842 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.ds);
3843 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.es);
3844 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.fs);
3845 iemHlpAdjustSelectorForNewCpl(pVCpu, uNewCpl, &pVCpu->cpum.GstCtx.gs);
3846 }
3847
3848 /* Flush the prefetch buffer. */
3849#ifdef IEM_WITH_CODE_TLB
3850 pVCpu->iem.s.pbInstrBuf = NULL;
3851#else
3852 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
3853#endif
3854
3855 return VINF_SUCCESS;
3856}
3857
3858
3859/**
3860 * Implements iret.
3861 *
3862 * @param enmEffOpSize The effective operand size.
3863 */
3864IEM_CIMPL_DEF_1(iemCImpl_iret, IEMMODE, enmEffOpSize)
3865{
3866 bool fBlockingNmi = CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx);
3867
3868#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3869 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
3870 {
3871 /*
3872 * Record whether NMI (or virtual-NMI) blocking is in effect during the execution
3873 * of this IRET instruction. We need to provide this information as part of some
3874 * VM-exits.
3875 *
3876 * See Intel spec. 27.2.2 "Information for VM Exits Due to Vectored Events".
3877 */
3878 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_VIRT_NMI))
3879 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking;
3880 else
3881 pVCpu->cpum.GstCtx.hwvirt.vmx.fNmiUnblockingIret = fBlockingNmi;
3882
3883 /*
3884 * If "NMI exiting" is set, IRET does not affect blocking of NMIs.
3885 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
3886 */
3887 if (IEM_VMX_IS_PINCTLS_SET(pVCpu, VMX_PIN_CTLS_NMI_EXIT))
3888 fBlockingNmi = false;
3889
3890 /* Clear virtual-NMI blocking, if any, before causing any further exceptions. */
3891 pVCpu->cpum.GstCtx.hwvirt.vmx.fVirtNmiBlocking = false;
3892 }
3893#endif
3894
3895 /*
3896 * The SVM nested-guest intercept for IRET takes priority over all exceptions,
3897 * The NMI is still held pending (which I assume means blocking of further NMIs
3898 * is in effect).
3899 *
3900 * See AMD spec. 15.9 "Instruction Intercepts".
3901 * See AMD spec. 15.21.9 "NMI Support".
3902 */
3903 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IRET))
3904 {
3905 Log(("iret: Guest intercept -> #VMEXIT\n"));
3906 IEM_SVM_UPDATE_NRIP(pVCpu);
3907 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IRET, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
3908 }
3909
3910 /*
3911 * Clear NMI blocking, if any, before causing any further exceptions.
3912 * See Intel spec. 6.7.1 "Handling Multiple NMIs".
3913 */
3914 if (fBlockingNmi)
3915 CPUMClearInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
3916
3917 /*
3918 * Call a mode specific worker.
3919 */
3920 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
3921 return IEM_CIMPL_CALL_1(iemCImpl_iret_real_v8086, enmEffOpSize);
3922 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_LDTR);
3923 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
3924 return IEM_CIMPL_CALL_1(iemCImpl_iret_64bit, enmEffOpSize);
3925 return IEM_CIMPL_CALL_1(iemCImpl_iret_prot, enmEffOpSize);
3926}
3927
3928
3929static void iemLoadallSetSelector(PVMCPUCC pVCpu, uint8_t iSegReg, uint16_t uSel)
3930{
3931 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3932
3933 pHid->Sel = uSel;
3934 pHid->ValidSel = uSel;
3935 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
3936}
3937
3938
3939static void iemLoadall286SetDescCache(PVMCPUCC pVCpu, uint8_t iSegReg, uint8_t const *pbMem)
3940{
3941 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
3942
3943 /* The base is in the first three bytes. */
3944 pHid->u64Base = pbMem[0] + (pbMem[1] << 8) + (pbMem[2] << 16);
3945 /* The attributes are in the fourth byte. */
3946 pHid->Attr.u = pbMem[3];
3947 /* The limit is in the last two bytes. */
3948 pHid->u32Limit = pbMem[4] + (pbMem[5] << 8);
3949}
3950
3951
3952/**
3953 * Implements 286 LOADALL (286 CPUs only).
3954 */
3955IEM_CIMPL_DEF_0(iemCImpl_loadall286)
3956{
3957 NOREF(cbInstr);
3958
3959 /* Data is loaded from a buffer at 800h. No checks are done on the
3960 * validity of loaded state.
3961 *
3962 * LOADALL only loads the internal CPU state, it does not access any
3963 * GDT, LDT, or similar tables.
3964 */
3965
3966 if (pVCpu->iem.s.uCpl != 0)
3967 {
3968 Log(("loadall286: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
3969 return iemRaiseGeneralProtectionFault0(pVCpu);
3970 }
3971
3972 uint8_t const *pbMem = NULL;
3973 uint16_t const *pa16Mem;
3974 uint8_t const *pa8Mem;
3975 RTGCPHYS GCPtrStart = 0x800; /* Fixed table location. */
3976 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&pbMem, 0x66, UINT8_MAX, GCPtrStart, IEM_ACCESS_SYS_R, 0);
3977 if (rcStrict != VINF_SUCCESS)
3978 return rcStrict;
3979
3980 /* The MSW is at offset 0x06. */
3981 pa16Mem = (uint16_t const *)(pbMem + 0x06);
3982 /* Even LOADALL can't clear the MSW.PE bit, though it can set it. */
3983 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3984 uNewCr0 |= *pa16Mem & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
3985 uint64_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
3986
3987 CPUMSetGuestCR0(pVCpu, uNewCr0);
3988 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCr0);
3989
3990 /* Inform PGM if mode changed. */
3991 if ((uNewCr0 & X86_CR0_PE) != (uOldCr0 & X86_CR0_PE))
3992 {
3993 int rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
3994 AssertRCReturn(rc, rc);
3995 /* ignore informational status codes */
3996 }
3997 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
3998 false /* fForce */);
3999
4000 /* TR selector is at offset 0x16. */
4001 pa16Mem = (uint16_t const *)(pbMem + 0x16);
4002 pVCpu->cpum.GstCtx.tr.Sel = pa16Mem[0];
4003 pVCpu->cpum.GstCtx.tr.ValidSel = pa16Mem[0];
4004 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
4005
4006 /* Followed by FLAGS... */
4007 pVCpu->cpum.GstCtx.eflags.u = pa16Mem[1] | X86_EFL_1;
4008 pVCpu->cpum.GstCtx.ip = pa16Mem[2]; /* ...and IP. */
4009
4010 /* LDT is at offset 0x1C. */
4011 pa16Mem = (uint16_t const *)(pbMem + 0x1C);
4012 pVCpu->cpum.GstCtx.ldtr.Sel = pa16Mem[0];
4013 pVCpu->cpum.GstCtx.ldtr.ValidSel = pa16Mem[0];
4014 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
4015
4016 /* Segment registers are at offset 0x1E. */
4017 pa16Mem = (uint16_t const *)(pbMem + 0x1E);
4018 iemLoadallSetSelector(pVCpu, X86_SREG_DS, pa16Mem[0]);
4019 iemLoadallSetSelector(pVCpu, X86_SREG_SS, pa16Mem[1]);
4020 iemLoadallSetSelector(pVCpu, X86_SREG_CS, pa16Mem[2]);
4021 iemLoadallSetSelector(pVCpu, X86_SREG_ES, pa16Mem[3]);
4022
4023 /* GPRs are at offset 0x26. */
4024 pa16Mem = (uint16_t const *)(pbMem + 0x26);
4025 pVCpu->cpum.GstCtx.di = pa16Mem[0];
4026 pVCpu->cpum.GstCtx.si = pa16Mem[1];
4027 pVCpu->cpum.GstCtx.bp = pa16Mem[2];
4028 pVCpu->cpum.GstCtx.sp = pa16Mem[3];
4029 pVCpu->cpum.GstCtx.bx = pa16Mem[4];
4030 pVCpu->cpum.GstCtx.dx = pa16Mem[5];
4031 pVCpu->cpum.GstCtx.cx = pa16Mem[6];
4032 pVCpu->cpum.GstCtx.ax = pa16Mem[7];
4033
4034 /* Descriptor caches are at offset 0x36, 6 bytes per entry. */
4035 iemLoadall286SetDescCache(pVCpu, X86_SREG_ES, pbMem + 0x36);
4036 iemLoadall286SetDescCache(pVCpu, X86_SREG_CS, pbMem + 0x3C);
4037 iemLoadall286SetDescCache(pVCpu, X86_SREG_SS, pbMem + 0x42);
4038 iemLoadall286SetDescCache(pVCpu, X86_SREG_DS, pbMem + 0x48);
4039
4040 /* GDTR contents are at offset 0x4E, 6 bytes. */
4041 RTGCPHYS GCPtrBase;
4042 uint16_t cbLimit;
4043 pa8Mem = pbMem + 0x4E;
4044 /* NB: Fourth byte "should be zero"; we are ignoring it. */
4045 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4046 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4047 CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
4048
4049 /* IDTR contents are at offset 0x5A, 6 bytes. */
4050 pa8Mem = pbMem + 0x5A;
4051 GCPtrBase = pa8Mem[0] + (pa8Mem[1] << 8) + (pa8Mem[2] << 16);
4052 cbLimit = pa8Mem[4] + (pa8Mem[5] << 8);
4053 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
4054
4055 Log(("LOADALL: GDTR:%08RX64/%04X, IDTR:%08RX64/%04X\n", pVCpu->cpum.GstCtx.gdtr.pGdt, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.idtr.pIdt, pVCpu->cpum.GstCtx.idtr.cbIdt));
4056 Log(("LOADALL: CS:%04X, CS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.cs.u64Base, pVCpu->cpum.GstCtx.cs.u32Limit, pVCpu->cpum.GstCtx.cs.Attr.u));
4057 Log(("LOADALL: DS:%04X, DS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ds.Sel, pVCpu->cpum.GstCtx.ds.u64Base, pVCpu->cpum.GstCtx.ds.u32Limit, pVCpu->cpum.GstCtx.ds.Attr.u));
4058 Log(("LOADALL: ES:%04X, ES base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.es.Sel, pVCpu->cpum.GstCtx.es.u64Base, pVCpu->cpum.GstCtx.es.u32Limit, pVCpu->cpum.GstCtx.es.Attr.u));
4059 Log(("LOADALL: SS:%04X, SS base:%08X, limit:%04X, attrs:%02X\n", pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.ss.u64Base, pVCpu->cpum.GstCtx.ss.u32Limit, pVCpu->cpum.GstCtx.ss.Attr.u));
4060 Log(("LOADALL: SI:%04X, DI:%04X, AX:%04X, BX:%04X, CX:%04X, DX:%04X\n", pVCpu->cpum.GstCtx.si, pVCpu->cpum.GstCtx.di, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.bx, pVCpu->cpum.GstCtx.cx, pVCpu->cpum.GstCtx.dx));
4061
4062 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pbMem, IEM_ACCESS_SYS_R);
4063 if (rcStrict != VINF_SUCCESS)
4064 return rcStrict;
4065
4066 /* The CPL may change. It is taken from the "DPL fields of the SS and CS
4067 * descriptor caches" but there is no word as to what happens if those are
4068 * not identical (probably bad things).
4069 */
4070 pVCpu->iem.s.uCpl = pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl;
4071
4072 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS | CPUM_CHANGED_IDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_TR | CPUM_CHANGED_LDTR);
4073
4074 /* Flush the prefetch buffer. */
4075#ifdef IEM_WITH_CODE_TLB
4076 pVCpu->iem.s.pbInstrBuf = NULL;
4077#else
4078 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4079#endif
4080 return rcStrict;
4081}
4082
4083
4084/**
4085 * Implements SYSCALL (AMD and Intel64).
4086 */
4087IEM_CIMPL_DEF_0(iemCImpl_syscall)
4088{
4089 /** @todo hack, LOADALL should be decoded as such on a 286. */
4090 if (RT_UNLIKELY(pVCpu->iem.s.uTargetCpu == IEMTARGETCPU_286))
4091 return iemCImpl_loadall286(pVCpu, cbInstr);
4092
4093 /*
4094 * Check preconditions.
4095 *
4096 * Note that CPUs described in the documentation may load a few odd values
4097 * into CS and SS than we allow here. This has yet to be checked on real
4098 * hardware.
4099 */
4100 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4101 {
4102 Log(("syscall: Not enabled in EFER -> #UD\n"));
4103 return iemRaiseUndefinedOpcode(pVCpu);
4104 }
4105 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4106 {
4107 Log(("syscall: Protected mode is required -> #GP(0)\n"));
4108 return iemRaiseGeneralProtectionFault0(pVCpu);
4109 }
4110 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4111 {
4112 Log(("syscall: Only available in long mode on intel -> #UD\n"));
4113 return iemRaiseUndefinedOpcode(pVCpu);
4114 }
4115
4116 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4117
4118 /** @todo verify RPL ignoring and CS=0xfff8 (i.e. SS == 0). */
4119 /** @todo what about LDT selectors? Shouldn't matter, really. */
4120 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSCALL_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4121 uint16_t uNewSs = uNewCs + 8;
4122 if (uNewCs == 0 || uNewSs == 0)
4123 {
4124 /** @todo Neither Intel nor AMD document this check. */
4125 Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4126 return iemRaiseGeneralProtectionFault0(pVCpu);
4127 }
4128
4129 /* Long mode and legacy mode differs. */
4130 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4131 {
4132 uint64_t uNewRip = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.msrLSTAR : pVCpu->cpum.GstCtx. msrCSTAR;
4133
4134 /* This test isn't in the docs, but I'm not trusting the guys writing
4135 the MSRs to have validated the values as canonical like they should. */
4136 if (!IEM_IS_CANONICAL(uNewRip))
4137 {
4138 /** @todo Intel claims this can't happen because IA32_LSTAR MSR can't be written with non-canonical address. */
4139 Log(("syscall: New RIP not canonical -> #UD\n"));
4140 return iemRaiseUndefinedOpcode(pVCpu);
4141 }
4142
4143 /*
4144 * Commit it.
4145 */
4146 Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
4147 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.rip + cbInstr;
4148 pVCpu->cpum.GstCtx.rip = uNewRip;
4149
4150 pVCpu->cpum.GstCtx.rflags.u &= ~X86_EFL_RF;
4151 pVCpu->cpum.GstCtx.r11 = pVCpu->cpum.GstCtx.rflags.u;
4152 pVCpu->cpum.GstCtx.rflags.u &= ~pVCpu->cpum.GstCtx.msrSFMASK;
4153 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4154
4155 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4156 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4157 }
4158 else
4159 {
4160 /*
4161 * Commit it.
4162 */
4163 Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
4164 pVCpu->cpum.GstCtx.rcx = pVCpu->cpum.GstCtx.eip + cbInstr;
4165 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
4166 pVCpu->cpum.GstCtx.rflags.u &= ~(X86_EFL_VM | X86_EFL_IF | X86_EFL_RF);
4167
4168 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
4169 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
4170 }
4171 pVCpu->cpum.GstCtx.cs.Sel = uNewCs;
4172 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs;
4173 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4174 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4175 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4176
4177 pVCpu->cpum.GstCtx.ss.Sel = uNewSs;
4178 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs;
4179 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4180 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4181 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4182
4183 pVCpu->iem.s.uCpl = 0;
4184 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
4185
4186 /* Flush the prefetch buffer. */
4187#ifdef IEM_WITH_CODE_TLB
4188 pVCpu->iem.s.pbInstrBuf = NULL;
4189#else
4190 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4191#endif
4192
4193 return VINF_SUCCESS;
4194}
4195
4196
4197/**
4198 * Implements SYSRET (AMD and Intel64).
4199 */
4200IEM_CIMPL_DEF_0(iemCImpl_sysret)
4201
4202{
4203 RT_NOREF_PV(cbInstr);
4204
4205 /*
4206 * Check preconditions.
4207 *
4208 * Note that CPUs described in the documentation may load a few odd values
4209 * into CS and SS than we allow here. This has yet to be checked on real
4210 * hardware.
4211 */
4212 if (!(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SCE))
4213 {
4214 Log(("sysret: Not enabled in EFER -> #UD\n"));
4215 return iemRaiseUndefinedOpcode(pVCpu);
4216 }
4217 if (IEM_IS_GUEST_CPU_INTEL(pVCpu) && !CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4218 {
4219 Log(("sysret: Only available in long mode on intel -> #UD\n"));
4220 return iemRaiseUndefinedOpcode(pVCpu);
4221 }
4222 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4223 {
4224 Log(("sysret: Protected mode is required -> #GP(0)\n"));
4225 return iemRaiseGeneralProtectionFault0(pVCpu);
4226 }
4227 if (pVCpu->iem.s.uCpl != 0)
4228 {
4229 Log(("sysret: CPL must be 0 not %u -> #GP(0)\n", pVCpu->iem.s.uCpl));
4230 return iemRaiseGeneralProtectionFault0(pVCpu);
4231 }
4232
4233 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS);
4234
4235 /** @todo Does SYSRET verify CS != 0 and SS != 0? Neither is valid in ring-3. */
4236 uint16_t uNewCs = (pVCpu->cpum.GstCtx.msrSTAR >> MSR_K6_STAR_SYSRET_CS_SS_SHIFT) & X86_SEL_MASK_OFF_RPL;
4237 uint16_t uNewSs = uNewCs + 8;
4238 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4239 uNewCs += 16;
4240 if (uNewCs == 0 || uNewSs == 0)
4241 {
4242 Log(("sysret: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
4243 return iemRaiseGeneralProtectionFault0(pVCpu);
4244 }
4245
4246 /*
4247 * Commit it.
4248 */
4249 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4250 {
4251 if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
4252 {
4253 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
4254 /* Note! We disregard intel manual regarding the RCX canonical
4255 check, ask intel+xen why AMD doesn't do it. */
4256 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4257 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4258 | (3 << X86DESCATTR_DPL_SHIFT);
4259 }
4260 else
4261 {
4262 Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
4263 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.ecx;
4264 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4265 | (3 << X86DESCATTR_DPL_SHIFT);
4266 }
4267 /** @todo testcase: See what kind of flags we can make SYSRET restore and
4268 * what it really ignores. RF and VM are hinted at being zero, by AMD.
4269 * Intel says: RFLAGS := (R11 & 3C7FD7H) | 2; */
4270 pVCpu->cpum.GstCtx.rflags.u = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
4271 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_1;
4272 }
4273 else
4274 {
4275 Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
4276 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rcx;
4277 pVCpu->cpum.GstCtx.rflags.u |= X86_EFL_IF;
4278 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
4279 | (3 << X86DESCATTR_DPL_SHIFT);
4280 }
4281 pVCpu->cpum.GstCtx.cs.Sel = uNewCs | 3;
4282 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs | 3;
4283 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4284 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4285 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4286
4287 pVCpu->cpum.GstCtx.ss.Sel = uNewSs | 3;
4288 pVCpu->cpum.GstCtx.ss.ValidSel = uNewSs | 3;
4289 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4290 /* The SS hidden bits remains unchanged says AMD. To that I say "Yeah, right!". */
4291 pVCpu->cpum.GstCtx.ss.Attr.u |= (3 << X86DESCATTR_DPL_SHIFT);
4292 /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
4293 * on sysret. */
4294
4295 pVCpu->iem.s.uCpl = 3;
4296 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
4297
4298 /* Flush the prefetch buffer. */
4299#ifdef IEM_WITH_CODE_TLB
4300 pVCpu->iem.s.pbInstrBuf = NULL;
4301#else
4302 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4303#endif
4304
4305 return VINF_SUCCESS;
4306}
4307
4308
4309/**
4310 * Implements SYSENTER (Intel, 32-bit AMD).
4311 */
4312IEM_CIMPL_DEF_0(iemCImpl_sysenter)
4313{
4314 RT_NOREF(cbInstr);
4315
4316 /*
4317 * Check preconditions.
4318 *
4319 * Note that CPUs described in the documentation may load a few odd values
4320 * into CS and SS than we allow here. This has yet to be checked on real
4321 * hardware.
4322 */
4323 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4324 {
4325 Log(("sysenter: not supported -=> #UD\n"));
4326 return iemRaiseUndefinedOpcode(pVCpu);
4327 }
4328 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4329 {
4330 Log(("sysenter: Protected or long mode is required -> #GP(0)\n"));
4331 return iemRaiseGeneralProtectionFault0(pVCpu);
4332 }
4333 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4334 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4335 {
4336 Log(("sysenter: Only available in protected mode on AMD -> #UD\n"));
4337 return iemRaiseUndefinedOpcode(pVCpu);
4338 }
4339 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4340 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4341 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4342 {
4343 Log(("sysenter: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4344 return iemRaiseGeneralProtectionFault0(pVCpu);
4345 }
4346
4347 /* This test isn't in the docs, it's just a safeguard against missing
4348 canonical checks when writing the registers. */
4349 if (RT_LIKELY( !fIsLongMode
4350 || ( IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.eip)
4351 && IEM_IS_CANONICAL(pVCpu->cpum.GstCtx.SysEnter.esp))))
4352 { /* likely */ }
4353 else
4354 {
4355 Log(("sysenter: SYSENTER_EIP = %#RX64 or/and SYSENTER_ESP = %#RX64 not canonical -> #GP(0)\n",
4356 pVCpu->cpum.GstCtx.SysEnter.eip, pVCpu->cpum.GstCtx.SysEnter.esp));
4357 return iemRaiseUndefinedOpcode(pVCpu);
4358 }
4359
4360/** @todo Test: Sysenter from ring-0, ring-1 and ring-2. */
4361
4362 /*
4363 * Update registers and commit.
4364 */
4365 if (fIsLongMode)
4366 {
4367 Log(("sysenter: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4368 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, pVCpu->cpum.GstCtx.SysEnter.eip));
4369 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.SysEnter.eip;
4370 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.SysEnter.esp;
4371 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4372 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4373 }
4374 else
4375 {
4376 Log(("sysenter: %04x:%08RX32 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, (uint32_t)pVCpu->cpum.GstCtx.rip,
4377 pVCpu->cpum.GstCtx.rflags.u, uNewCs & X86_SEL_MASK_OFF_RPL, (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip));
4378 pVCpu->cpum.GstCtx.rip = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.eip;
4379 pVCpu->cpum.GstCtx.rsp = (uint32_t)pVCpu->cpum.GstCtx.SysEnter.esp;
4380 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4381 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC;
4382 }
4383 pVCpu->cpum.GstCtx.cs.Sel = uNewCs & X86_SEL_MASK_OFF_RPL;
4384 pVCpu->cpum.GstCtx.cs.ValidSel = uNewCs & X86_SEL_MASK_OFF_RPL;
4385 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4386 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4387 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4388
4389 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4390 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs & X86_SEL_MASK_OFF_RPL) + 8;
4391 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4392 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4393 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4394 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC;
4395 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4396
4397 pVCpu->cpum.GstCtx.rflags.Bits.u1IF = 0;
4398 pVCpu->cpum.GstCtx.rflags.Bits.u1VM = 0;
4399 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4400
4401 pVCpu->iem.s.uCpl = 0;
4402
4403 /* Flush the prefetch buffer. */
4404#ifdef IEM_WITH_CODE_TLB
4405 pVCpu->iem.s.pbInstrBuf = NULL;
4406#else
4407 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4408#endif
4409
4410 return VINF_SUCCESS;
4411}
4412
4413
4414/**
4415 * Implements SYSEXIT (Intel, 32-bit AMD).
4416 *
4417 * @param enmEffOpSize The effective operand size.
4418 */
4419IEM_CIMPL_DEF_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize)
4420{
4421 RT_NOREF(cbInstr);
4422
4423 /*
4424 * Check preconditions.
4425 *
4426 * Note that CPUs described in the documentation may load a few odd values
4427 * into CS and SS than we allow here. This has yet to be checked on real
4428 * hardware.
4429 */
4430 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSysEnter)
4431 {
4432 Log(("sysexit: not supported -=> #UD\n"));
4433 return iemRaiseUndefinedOpcode(pVCpu);
4434 }
4435 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
4436 {
4437 Log(("sysexit: Protected or long mode is required -> #GP(0)\n"));
4438 return iemRaiseGeneralProtectionFault0(pVCpu);
4439 }
4440 bool fIsLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
4441 if (IEM_IS_GUEST_CPU_AMD(pVCpu) && fIsLongMode)
4442 {
4443 Log(("sysexit: Only available in protected mode on AMD -> #UD\n"));
4444 return iemRaiseUndefinedOpcode(pVCpu);
4445 }
4446 if (pVCpu->iem.s.uCpl != 0)
4447 {
4448 Log(("sysexit: CPL(=%u) != 0 -> #GP(0)\n", pVCpu->iem.s.uCpl));
4449 return iemRaiseGeneralProtectionFault0(pVCpu);
4450 }
4451 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4452 uint16_t uNewCs = pVCpu->cpum.GstCtx.SysEnter.cs;
4453 if ((uNewCs & X86_SEL_MASK_OFF_RPL) == 0)
4454 {
4455 Log(("sysexit: SYSENTER_CS = %#x -> #GP(0)\n", uNewCs));
4456 return iemRaiseGeneralProtectionFault0(pVCpu);
4457 }
4458
4459 /*
4460 * Update registers and commit.
4461 */
4462 if (enmEffOpSize == IEMMODE_64BIT)
4463 {
4464 Log(("sysexit: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4465 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 32, pVCpu->cpum.GstCtx.rcx));
4466 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rdx;
4467 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.rcx;
4468 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_L | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4469 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4470 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 32;
4471 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 32;
4472 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 40;
4473 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 40;
4474 }
4475 else
4476 {
4477 Log(("sysexit: %04x:%08RX64 [efl=%#llx] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip,
4478 pVCpu->cpum.GstCtx.rflags.u, (uNewCs | 3) + 16, (uint32_t)pVCpu->cpum.GstCtx.edx));
4479 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.edx;
4480 pVCpu->cpum.GstCtx.rsp = pVCpu->cpum.GstCtx.ecx;
4481 pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4482 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_ER_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4483 pVCpu->cpum.GstCtx.cs.Sel = (uNewCs | 3) + 16;
4484 pVCpu->cpum.GstCtx.cs.ValidSel = (uNewCs | 3) + 16;
4485 pVCpu->cpum.GstCtx.ss.Sel = (uNewCs | 3) + 24;
4486 pVCpu->cpum.GstCtx.ss.ValidSel = (uNewCs | 3) + 24;
4487 }
4488 pVCpu->cpum.GstCtx.cs.u64Base = 0;
4489 pVCpu->cpum.GstCtx.cs.u32Limit = UINT32_MAX;
4490 pVCpu->cpum.GstCtx.cs.fFlags = CPUMSELREG_FLAGS_VALID;
4491
4492 pVCpu->cpum.GstCtx.ss.u64Base = 0;
4493 pVCpu->cpum.GstCtx.ss.u32Limit = UINT32_MAX;
4494 pVCpu->cpum.GstCtx.ss.Attr.u = X86DESCATTR_D | X86DESCATTR_G | X86DESCATTR_P | X86DESCATTR_DT
4495 | X86DESCATTR_LIMIT_HIGH | X86_SEL_TYPE_RW_ACC | (3 << X86DESCATTR_DPL_SHIFT);
4496 pVCpu->cpum.GstCtx.ss.fFlags = CPUMSELREG_FLAGS_VALID;
4497 pVCpu->cpum.GstCtx.rflags.Bits.u1RF = 0;
4498
4499 pVCpu->iem.s.uCpl = 3;
4500
4501 /* Flush the prefetch buffer. */
4502#ifdef IEM_WITH_CODE_TLB
4503 pVCpu->iem.s.pbInstrBuf = NULL;
4504#else
4505 pVCpu->iem.s.cbOpcode = pVCpu->iem.s.offOpcode;
4506#endif
4507
4508 return VINF_SUCCESS;
4509}
4510
4511
4512/**
4513 * Common worker for 'pop SReg', 'mov SReg, GReg' and 'lXs GReg, reg/mem'.
4514 *
4515 * @param iSegReg The segment register number (valid).
4516 * @param uSel The new selector value.
4517 */
4518IEM_CIMPL_DEF_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel)
4519{
4520 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
4521 uint16_t *pSel = iemSRegRef(pVCpu, iSegReg);
4522 PCPUMSELREGHID pHid = iemSRegGetHid(pVCpu, iSegReg);
4523
4524 Assert(iSegReg <= X86_SREG_GS && iSegReg != X86_SREG_CS);
4525
4526 /*
4527 * Real mode and V8086 mode are easy.
4528 */
4529 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
4530 {
4531 *pSel = uSel;
4532 pHid->u64Base = (uint32_t)uSel << 4;
4533 pHid->ValidSel = uSel;
4534 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4535#if 0 /* AMD Volume 2, chapter 4.1 - "real mode segmentation" - states that limit and attributes are untouched. */
4536 /** @todo Does the CPU actually load limits and attributes in the
4537 * real/V8086 mode segment load case? It doesn't for CS in far
4538 * jumps... Affects unreal mode. */
4539 pHid->u32Limit = 0xffff;
4540 pHid->Attr.u = 0;
4541 pHid->Attr.n.u1Present = 1;
4542 pHid->Attr.n.u1DescType = 1;
4543 pHid->Attr.n.u4Type = iSegReg != X86_SREG_CS
4544 ? X86_SEL_TYPE_RW
4545 : X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
4546#endif
4547 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4548 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4549 return VINF_SUCCESS;
4550 }
4551
4552 /*
4553 * Protected mode.
4554 *
4555 * Check if it's a null segment selector value first, that's OK for DS, ES,
4556 * FS and GS. If not null, then we have to load and parse the descriptor.
4557 */
4558 if (!(uSel & X86_SEL_MASK_OFF_RPL))
4559 {
4560 Assert(iSegReg != X86_SREG_CS); /** @todo testcase for \#UD on MOV CS, ax! */
4561 if (iSegReg == X86_SREG_SS)
4562 {
4563 /* In 64-bit kernel mode, the stack can be 0 because of the way
4564 interrupts are dispatched. AMD seems to have a slighly more
4565 relaxed relationship to SS.RPL than intel does. */
4566 /** @todo We cannot 'mov ss, 3' in 64-bit kernel mode, can we? There is a testcase (bs-cpu-xcpt-1), but double check this! */
4567 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
4568 || pVCpu->iem.s.uCpl > 2
4569 || ( uSel != pVCpu->iem.s.uCpl
4570 && !IEM_IS_GUEST_CPU_AMD(pVCpu)) )
4571 {
4572 Log(("load sreg %#x -> invalid stack selector, #GP(0)\n", uSel));
4573 return iemRaiseGeneralProtectionFault0(pVCpu);
4574 }
4575 }
4576
4577 *pSel = uSel; /* Not RPL, remember :-) */
4578 iemHlpLoadNullDataSelectorProt(pVCpu, pHid, uSel);
4579 if (iSegReg == X86_SREG_SS)
4580 pHid->Attr.u |= pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT;
4581
4582 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4583 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4584
4585 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4586 return VINF_SUCCESS;
4587 }
4588
4589 /* Fetch the descriptor. */
4590 IEMSELDESC Desc;
4591 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uSel, X86_XCPT_GP); /** @todo Correct exception? */
4592 if (rcStrict != VINF_SUCCESS)
4593 return rcStrict;
4594
4595 /* Check GPs first. */
4596 if (!Desc.Legacy.Gen.u1DescType)
4597 {
4598 Log(("load sreg %d (=%#x) - system selector (%#x) -> #GP\n", iSegReg, uSel, Desc.Legacy.Gen.u4Type));
4599 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4600 }
4601 if (iSegReg == X86_SREG_SS) /* SS gets different treatment */
4602 {
4603 if ( (Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_CODE)
4604 || !(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_WRITE) )
4605 {
4606 Log(("load sreg SS, %#x - code or read only (%#x) -> #GP\n", uSel, Desc.Legacy.Gen.u4Type));
4607 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4608 }
4609 if ((uSel & X86_SEL_RPL) != pVCpu->iem.s.uCpl)
4610 {
4611 Log(("load sreg SS, %#x - RPL and CPL (%d) differs -> #GP\n", uSel, pVCpu->iem.s.uCpl));
4612 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4613 }
4614 if (Desc.Legacy.Gen.u2Dpl != pVCpu->iem.s.uCpl)
4615 {
4616 Log(("load sreg SS, %#x - DPL (%d) and CPL (%d) differs -> #GP\n", uSel, Desc.Legacy.Gen.u2Dpl, pVCpu->iem.s.uCpl));
4617 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4618 }
4619 }
4620 else
4621 {
4622 if ((Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4623 {
4624 Log(("load sreg%u, %#x - execute only segment -> #GP\n", iSegReg, uSel));
4625 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4626 }
4627 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4628 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4629 {
4630#if 0 /* this is what intel says. */
4631 if ( (uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl
4632 && pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4633 {
4634 Log(("load sreg%u, %#x - both RPL (%d) and CPL (%d) are greater than DPL (%d) -> #GP\n",
4635 iSegReg, uSel, (uSel & X86_SEL_RPL), pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4636 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4637 }
4638#else /* this is what makes more sense. */
4639 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4640 {
4641 Log(("load sreg%u, %#x - RPL (%d) is greater than DPL (%d) -> #GP\n",
4642 iSegReg, uSel, (uSel & X86_SEL_RPL), Desc.Legacy.Gen.u2Dpl));
4643 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4644 }
4645 if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4646 {
4647 Log(("load sreg%u, %#x - CPL (%d) is greater than DPL (%d) -> #GP\n",
4648 iSegReg, uSel, pVCpu->iem.s.uCpl, Desc.Legacy.Gen.u2Dpl));
4649 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uSel);
4650 }
4651#endif
4652 }
4653 }
4654
4655 /* Is it there? */
4656 if (!Desc.Legacy.Gen.u1Present)
4657 {
4658 Log(("load sreg%d,%#x - segment not present -> #NP\n", iSegReg, uSel));
4659 return iemRaiseSelectorNotPresentBySelector(pVCpu, uSel);
4660 }
4661
4662 /* The base and limit. */
4663 uint32_t cbLimit = X86DESC_LIMIT_G(&Desc.Legacy);
4664 uint64_t u64Base = X86DESC_BASE(&Desc.Legacy);
4665
4666 /*
4667 * Ok, everything checked out fine. Now set the accessed bit before
4668 * committing the result into the registers.
4669 */
4670 if (!(Desc.Legacy.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
4671 {
4672 rcStrict = iemMemMarkSelDescAccessed(pVCpu, uSel);
4673 if (rcStrict != VINF_SUCCESS)
4674 return rcStrict;
4675 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
4676 }
4677
4678 /* commit */
4679 *pSel = uSel;
4680 pHid->Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
4681 pHid->u32Limit = cbLimit;
4682 pHid->u64Base = u64Base;
4683 pHid->ValidSel = uSel;
4684 pHid->fFlags = CPUMSELREG_FLAGS_VALID;
4685
4686 /** @todo check if the hidden bits are loaded correctly for 64-bit
4687 * mode. */
4688 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pHid));
4689
4690 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_HIDDEN_SEL_REGS);
4691 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4692 return VINF_SUCCESS;
4693}
4694
4695
4696/**
4697 * Implements 'mov SReg, r/m'.
4698 *
4699 * @param iSegReg The segment register number (valid).
4700 * @param uSel The new selector value.
4701 */
4702IEM_CIMPL_DEF_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel)
4703{
4704 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4705 if (iSegReg == X86_SREG_SS && rcStrict == VINF_SUCCESS)
4706 CPUMSetInInterruptShadowSs(&pVCpu->cpum.GstCtx);
4707 return rcStrict;
4708}
4709
4710
4711/**
4712 * Implements 'pop SReg'.
4713 *
4714 * @param iSegReg The segment register number (valid).
4715 * @param enmEffOpSize The efficient operand size (valid).
4716 */
4717IEM_CIMPL_DEF_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize)
4718{
4719 VBOXSTRICTRC rcStrict;
4720
4721 /*
4722 * Read the selector off the stack and join paths with mov ss, reg.
4723 */
4724 RTUINT64U TmpRsp;
4725 TmpRsp.u = pVCpu->cpum.GstCtx.rsp;
4726 switch (enmEffOpSize)
4727 {
4728 case IEMMODE_16BIT:
4729 {
4730 uint16_t uSel;
4731 rcStrict = iemMemStackPopU16Ex(pVCpu, &uSel, &TmpRsp);
4732 if (rcStrict == VINF_SUCCESS)
4733 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4734 break;
4735 }
4736
4737 case IEMMODE_32BIT:
4738 {
4739 uint32_t u32Value;
4740 rcStrict = iemMemStackPopU32Ex(pVCpu, &u32Value, &TmpRsp);
4741 if (rcStrict == VINF_SUCCESS)
4742 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u32Value);
4743 break;
4744 }
4745
4746 case IEMMODE_64BIT:
4747 {
4748 uint64_t u64Value;
4749 rcStrict = iemMemStackPopU64Ex(pVCpu, &u64Value, &TmpRsp);
4750 if (rcStrict == VINF_SUCCESS)
4751 rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, (uint16_t)u64Value);
4752 break;
4753 }
4754 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4755 }
4756
4757 /*
4758 * Commit the stack on success.
4759 */
4760 if (rcStrict == VINF_SUCCESS)
4761 {
4762 pVCpu->cpum.GstCtx.rsp = TmpRsp.u;
4763 if (iSegReg == X86_SREG_SS)
4764 CPUMSetInInterruptShadowSs(&pVCpu->cpum.GstCtx);
4765 }
4766 return rcStrict;
4767}
4768
4769
4770/**
4771 * Implements lgs, lfs, les, lds & lss.
4772 */
4773IEM_CIMPL_DEF_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize)
4774{
4775 /*
4776 * Use iemCImpl_LoadSReg to do the tricky segment register loading.
4777 */
4778 /** @todo verify and test that mov, pop and lXs works the segment
4779 * register loading in the exact same way. */
4780 VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_LoadSReg, iSegReg, uSel);
4781 if (rcStrict == VINF_SUCCESS)
4782 {
4783 switch (enmEffOpSize)
4784 {
4785 case IEMMODE_16BIT:
4786 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4787 break;
4788 case IEMMODE_32BIT:
4789 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4790 break;
4791 case IEMMODE_64BIT:
4792 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = offSeg;
4793 break;
4794 IEM_NOT_REACHED_DEFAULT_CASE_RET();
4795 }
4796 }
4797
4798 return rcStrict;
4799}
4800
4801
4802/**
4803 * Helper for VERR, VERW, LAR, and LSL and loads the descriptor into memory.
4804 *
4805 * @retval VINF_SUCCESS on success.
4806 * @retval VINF_IEM_SELECTOR_NOT_OK if the selector isn't ok.
4807 * @retval iemMemFetchSysU64 return value.
4808 *
4809 * @param pVCpu The cross context virtual CPU structure of the calling thread.
4810 * @param uSel The selector value.
4811 * @param fAllowSysDesc Whether system descriptors are OK or not.
4812 * @param pDesc Where to return the descriptor on success.
4813 */
4814static VBOXSTRICTRC iemCImpl_LoadDescHelper(PVMCPUCC pVCpu, uint16_t uSel, bool fAllowSysDesc, PIEMSELDESC pDesc)
4815{
4816 pDesc->Long.au64[0] = 0;
4817 pDesc->Long.au64[1] = 0;
4818
4819 if (!(uSel & X86_SEL_MASK_OFF_RPL)) /** @todo test this on 64-bit. */
4820 return VINF_IEM_SELECTOR_NOT_OK;
4821
4822 /* Within the table limits? */
4823 RTGCPTR GCPtrBase;
4824 if (uSel & X86_SEL_LDT)
4825 {
4826 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
4827 if ( !pVCpu->cpum.GstCtx.ldtr.Attr.n.u1Present
4828 || (uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.ldtr.u32Limit )
4829 return VINF_IEM_SELECTOR_NOT_OK;
4830 GCPtrBase = pVCpu->cpum.GstCtx.ldtr.u64Base;
4831 }
4832 else
4833 {
4834 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
4835 if ((uSel | X86_SEL_RPL_LDT) > pVCpu->cpum.GstCtx.gdtr.cbGdt)
4836 return VINF_IEM_SELECTOR_NOT_OK;
4837 GCPtrBase = pVCpu->cpum.GstCtx.gdtr.pGdt;
4838 }
4839
4840 /* Fetch the descriptor. */
4841 VBOXSTRICTRC rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Legacy.u, UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK));
4842 if (rcStrict != VINF_SUCCESS)
4843 return rcStrict;
4844 if (!pDesc->Legacy.Gen.u1DescType)
4845 {
4846 if (!fAllowSysDesc)
4847 return VINF_IEM_SELECTOR_NOT_OK;
4848 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4849 {
4850 rcStrict = iemMemFetchSysU64(pVCpu, &pDesc->Long.au64[1], UINT8_MAX, GCPtrBase + (uSel & X86_SEL_MASK) + 8);
4851 if (rcStrict != VINF_SUCCESS)
4852 return rcStrict;
4853 }
4854
4855 }
4856
4857 return VINF_SUCCESS;
4858}
4859
4860
4861/**
4862 * Implements verr (fWrite = false) and verw (fWrite = true).
4863 */
4864IEM_CIMPL_DEF_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite)
4865{
4866 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4867
4868 /** @todo figure whether the accessed bit is set or not. */
4869
4870 bool fAccessible = true;
4871 IEMSELDESC Desc;
4872 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, false /*fAllowSysDesc*/, &Desc);
4873 if (rcStrict == VINF_SUCCESS)
4874 {
4875 /* Check the descriptor, order doesn't matter much here. */
4876 if ( !Desc.Legacy.Gen.u1DescType
4877 || !Desc.Legacy.Gen.u1Present)
4878 fAccessible = false;
4879 else
4880 {
4881 if ( fWrite
4882 ? (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE
4883 : (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
4884 fAccessible = false;
4885
4886 /** @todo testcase for the conforming behavior. */
4887 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4888 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
4889 {
4890 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4891 fAccessible = false;
4892 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4893 fAccessible = false;
4894 }
4895 }
4896
4897 }
4898 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
4899 fAccessible = false;
4900 else
4901 return rcStrict;
4902
4903 /* commit */
4904 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fAccessible;
4905
4906 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
4907 return VINF_SUCCESS;
4908}
4909
4910
4911/**
4912 * Implements LAR and LSL with 64-bit operand size.
4913 *
4914 * @returns VINF_SUCCESS.
4915 * @param pu64Dst Pointer to the destination register.
4916 * @param uSel The selector to load details for.
4917 * @param fIsLar true = LAR, false = LSL.
4918 */
4919IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar)
4920{
4921 Assert(!IEM_IS_REAL_OR_V86_MODE(pVCpu));
4922
4923 /** @todo figure whether the accessed bit is set or not. */
4924
4925 bool fDescOk = true;
4926 IEMSELDESC Desc;
4927 VBOXSTRICTRC rcStrict = iemCImpl_LoadDescHelper(pVCpu, uSel, true /*fAllowSysDesc*/, &Desc);
4928 if (rcStrict == VINF_SUCCESS)
4929 {
4930 /*
4931 * Check the descriptor type.
4932 */
4933 if (!Desc.Legacy.Gen.u1DescType)
4934 {
4935 if (CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
4936 {
4937 if (Desc.Long.Gen.u5Zeros)
4938 fDescOk = false;
4939 else
4940 switch (Desc.Long.Gen.u4Type)
4941 {
4942 /** @todo Intel lists 0 as valid for LSL, verify whether that's correct */
4943 case AMD64_SEL_TYPE_SYS_TSS_AVAIL:
4944 case AMD64_SEL_TYPE_SYS_TSS_BUSY:
4945 case AMD64_SEL_TYPE_SYS_LDT: /** @todo Intel lists this as invalid for LAR, AMD and 32-bit does otherwise. */
4946 break;
4947 case AMD64_SEL_TYPE_SYS_CALL_GATE:
4948 fDescOk = fIsLar;
4949 break;
4950 default:
4951 fDescOk = false;
4952 break;
4953 }
4954 }
4955 else
4956 {
4957 switch (Desc.Long.Gen.u4Type)
4958 {
4959 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
4960 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
4961 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
4962 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
4963 case X86_SEL_TYPE_SYS_LDT:
4964 break;
4965 case X86_SEL_TYPE_SYS_286_CALL_GATE:
4966 case X86_SEL_TYPE_SYS_TASK_GATE:
4967 case X86_SEL_TYPE_SYS_386_CALL_GATE:
4968 fDescOk = fIsLar;
4969 break;
4970 default:
4971 fDescOk = false;
4972 break;
4973 }
4974 }
4975 }
4976 if (fDescOk)
4977 {
4978 /*
4979 * Check the RPL/DPL/CPL interaction..
4980 */
4981 /** @todo testcase for the conforming behavior. */
4982 if ( (Desc.Legacy.Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)) != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF)
4983 || !Desc.Legacy.Gen.u1DescType)
4984 {
4985 if ((unsigned)(uSel & X86_SEL_RPL) > Desc.Legacy.Gen.u2Dpl)
4986 fDescOk = false;
4987 else if (pVCpu->iem.s.uCpl > Desc.Legacy.Gen.u2Dpl)
4988 fDescOk = false;
4989 }
4990 }
4991
4992 if (fDescOk)
4993 {
4994 /*
4995 * All fine, start committing the result.
4996 */
4997 if (fIsLar)
4998 *pu64Dst = Desc.Legacy.au32[1] & UINT32_C(0x00ffff00);
4999 else
5000 *pu64Dst = X86DESC_LIMIT_G(&Desc.Legacy);
5001 }
5002
5003 }
5004 else if (rcStrict == VINF_IEM_SELECTOR_NOT_OK)
5005 fDescOk = false;
5006 else
5007 return rcStrict;
5008
5009 /* commit flags value and advance rip. */
5010 pVCpu->cpum.GstCtx.eflags.Bits.u1ZF = fDescOk;
5011 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5012
5013 return VINF_SUCCESS;
5014}
5015
5016
5017/**
5018 * Implements LAR and LSL with 16-bit operand size.
5019 *
5020 * @returns VINF_SUCCESS.
5021 * @param pu16Dst Pointer to the destination register.
5022 * @param uSel The selector to load details for.
5023 * @param fIsLar true = LAR, false = LSL.
5024 */
5025IEM_CIMPL_DEF_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar)
5026{
5027 uint64_t u64TmpDst = *pu16Dst;
5028 IEM_CIMPL_CALL_3(iemCImpl_LarLsl_u64, &u64TmpDst, uSel, fIsLar);
5029 *pu16Dst = u64TmpDst;
5030 return VINF_SUCCESS;
5031}
5032
5033
5034/**
5035 * Implements lgdt.
5036 *
5037 * @param iEffSeg The segment of the new gdtr contents
5038 * @param GCPtrEffSrc The address of the new gdtr contents.
5039 * @param enmEffOpSize The effective operand size.
5040 */
5041IEM_CIMPL_DEF_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5042{
5043 if (pVCpu->iem.s.uCpl != 0)
5044 return iemRaiseGeneralProtectionFault0(pVCpu);
5045 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5046
5047 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5048 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5049 {
5050 Log(("lgdt: Guest intercept -> VM-exit\n"));
5051 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_LGDT, cbInstr);
5052 }
5053
5054 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_WRITES))
5055 {
5056 Log(("lgdt: Guest intercept -> #VMEXIT\n"));
5057 IEM_SVM_UPDATE_NRIP(pVCpu);
5058 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5059 }
5060
5061 /*
5062 * Fetch the limit and base address.
5063 */
5064 uint16_t cbLimit;
5065 RTGCPTR GCPtrBase;
5066 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5067 if (rcStrict == VINF_SUCCESS)
5068 {
5069 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5070 || X86_IS_CANONICAL(GCPtrBase))
5071 {
5072 rcStrict = CPUMSetGuestGDTR(pVCpu, GCPtrBase, cbLimit);
5073 if (rcStrict == VINF_SUCCESS)
5074 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5075 }
5076 else
5077 {
5078 Log(("iemCImpl_lgdt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5079 return iemRaiseGeneralProtectionFault0(pVCpu);
5080 }
5081 }
5082 return rcStrict;
5083}
5084
5085
5086/**
5087 * Implements sgdt.
5088 *
5089 * @param iEffSeg The segment where to store the gdtr content.
5090 * @param GCPtrEffDst The address where to store the gdtr content.
5091 */
5092IEM_CIMPL_DEF_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5093{
5094 /*
5095 * Join paths with sidt.
5096 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5097 * you really must know.
5098 */
5099 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5100 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5101 {
5102 Log(("sgdt: Guest intercept -> VM-exit\n"));
5103 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_GDTR_IDTR_ACCESS, VMXINSTRID_SGDT, cbInstr);
5104 }
5105
5106 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_GDTR_READS))
5107 {
5108 Log(("sgdt: Guest intercept -> #VMEXIT\n"));
5109 IEM_SVM_UPDATE_NRIP(pVCpu);
5110 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_GDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5111 }
5112
5113 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_GDTR);
5114 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.gdtr.cbGdt, pVCpu->cpum.GstCtx.gdtr.pGdt, iEffSeg, GCPtrEffDst);
5115 if (rcStrict == VINF_SUCCESS)
5116 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5117 return rcStrict;
5118}
5119
5120
5121/**
5122 * Implements lidt.
5123 *
5124 * @param iEffSeg The segment of the new idtr contents
5125 * @param GCPtrEffSrc The address of the new idtr contents.
5126 * @param enmEffOpSize The effective operand size.
5127 */
5128IEM_CIMPL_DEF_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize)
5129{
5130 if (pVCpu->iem.s.uCpl != 0)
5131 return iemRaiseGeneralProtectionFault0(pVCpu);
5132 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5133
5134 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_WRITES))
5135 {
5136 Log(("lidt: Guest intercept -> #VMEXIT\n"));
5137 IEM_SVM_UPDATE_NRIP(pVCpu);
5138 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5139 }
5140
5141 /*
5142 * Fetch the limit and base address.
5143 */
5144 uint16_t cbLimit;
5145 RTGCPTR GCPtrBase;
5146 VBOXSTRICTRC rcStrict = iemMemFetchDataXdtr(pVCpu, &cbLimit, &GCPtrBase, iEffSeg, GCPtrEffSrc, enmEffOpSize);
5147 if (rcStrict == VINF_SUCCESS)
5148 {
5149 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
5150 || X86_IS_CANONICAL(GCPtrBase))
5151 {
5152 CPUMSetGuestIDTR(pVCpu, GCPtrBase, cbLimit);
5153 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5154 }
5155 else
5156 {
5157 Log(("iemCImpl_lidt: Non-canonical base %04x:%RGv\n", cbLimit, GCPtrBase));
5158 return iemRaiseGeneralProtectionFault0(pVCpu);
5159 }
5160 }
5161 return rcStrict;
5162}
5163
5164
5165/**
5166 * Implements sidt.
5167 *
5168 * @param iEffSeg The segment where to store the idtr content.
5169 * @param GCPtrEffDst The address where to store the idtr content.
5170 */
5171IEM_CIMPL_DEF_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5172{
5173 /*
5174 * Join paths with sgdt.
5175 * Note! No CPL or V8086 checks here, it's a really sad story, ask Intel if
5176 * you really must know.
5177 */
5178 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IDTR_READS))
5179 {
5180 Log(("sidt: Guest intercept -> #VMEXIT\n"));
5181 IEM_SVM_UPDATE_NRIP(pVCpu);
5182 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_IDTR_READ, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5183 }
5184
5185 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_IDTR);
5186 VBOXSTRICTRC rcStrict = iemMemStoreDataXdtr(pVCpu, pVCpu->cpum.GstCtx.idtr.cbIdt, pVCpu->cpum.GstCtx.idtr.pIdt, iEffSeg, GCPtrEffDst);
5187 if (rcStrict == VINF_SUCCESS)
5188 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5189 return rcStrict;
5190}
5191
5192
5193/**
5194 * Implements lldt.
5195 *
5196 * @param uNewLdt The new LDT selector value.
5197 */
5198IEM_CIMPL_DEF_1(iemCImpl_lldt, uint16_t, uNewLdt)
5199{
5200 /*
5201 * Check preconditions.
5202 */
5203 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5204 {
5205 Log(("lldt %04x - real or v8086 mode -> #GP(0)\n", uNewLdt));
5206 return iemRaiseUndefinedOpcode(pVCpu);
5207 }
5208 if (pVCpu->iem.s.uCpl != 0)
5209 {
5210 Log(("lldt %04x - CPL is %d -> #GP(0)\n", uNewLdt, pVCpu->iem.s.uCpl));
5211 return iemRaiseGeneralProtectionFault0(pVCpu);
5212 }
5213 /* Nested-guest VMX intercept. */
5214 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5215 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5216 {
5217 Log(("lldt: Guest intercept -> VM-exit\n"));
5218 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LLDT, cbInstr);
5219 }
5220 if (uNewLdt & X86_SEL_LDT)
5221 {
5222 Log(("lldt %04x - LDT selector -> #GP\n", uNewLdt));
5223 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewLdt);
5224 }
5225
5226 /*
5227 * Now, loading a NULL selector is easy.
5228 */
5229 if (!(uNewLdt & X86_SEL_MASK_OFF_RPL))
5230 {
5231 /* Nested-guest SVM intercept. */
5232 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5233 {
5234 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5235 IEM_SVM_UPDATE_NRIP(pVCpu);
5236 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5237 }
5238
5239 Log(("lldt %04x: Loading NULL selector.\n", uNewLdt));
5240 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_LDTR;
5241 CPUMSetGuestLDTR(pVCpu, uNewLdt);
5242 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt;
5243 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5244 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
5245 {
5246 /* AMD-V seems to leave the base and limit alone. */
5247 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE;
5248 }
5249 else
5250 {
5251 /* VT-x (Intel 3960x) seems to be doing the following. */
5252 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D;
5253 pVCpu->cpum.GstCtx.ldtr.u64Base = 0;
5254 pVCpu->cpum.GstCtx.ldtr.u32Limit = UINT32_MAX;
5255 }
5256
5257 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5258 return VINF_SUCCESS;
5259 }
5260
5261 /*
5262 * Read the descriptor.
5263 */
5264 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR);
5265 IEMSELDESC Desc;
5266 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewLdt, X86_XCPT_GP); /** @todo Correct exception? */
5267 if (rcStrict != VINF_SUCCESS)
5268 return rcStrict;
5269
5270 /* Check GPs first. */
5271 if (Desc.Legacy.Gen.u1DescType)
5272 {
5273 Log(("lldt %#x - not system selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5274 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5275 }
5276 if (Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
5277 {
5278 Log(("lldt %#x - not LDT selector (type %x) -> #GP\n", uNewLdt, Desc.Legacy.Gen.u4Type));
5279 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5280 }
5281 uint64_t u64Base;
5282 if (!IEM_IS_LONG_MODE(pVCpu))
5283 u64Base = X86DESC_BASE(&Desc.Legacy);
5284 else
5285 {
5286 if (Desc.Long.Gen.u5Zeros)
5287 {
5288 Log(("lldt %#x - u5Zeros=%#x -> #GP\n", uNewLdt, Desc.Long.Gen.u5Zeros));
5289 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5290 }
5291
5292 u64Base = X86DESC64_BASE(&Desc.Long);
5293 if (!IEM_IS_CANONICAL(u64Base))
5294 {
5295 Log(("lldt %#x - non-canonical base address %#llx -> #GP\n", uNewLdt, u64Base));
5296 return iemRaiseGeneralProtectionFault(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5297 }
5298 }
5299
5300 /* NP */
5301 if (!Desc.Legacy.Gen.u1Present)
5302 {
5303 Log(("lldt %#x - segment not present -> #NP\n", uNewLdt));
5304 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewLdt);
5305 }
5306
5307 /* Nested-guest SVM intercept. */
5308 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_LDTR_WRITES))
5309 {
5310 Log(("lldt: Guest intercept -> #VMEXIT\n"));
5311 IEM_SVM_UPDATE_NRIP(pVCpu);
5312 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_LDTR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5313 }
5314
5315 /*
5316 * It checks out alright, update the registers.
5317 */
5318/** @todo check if the actual value is loaded or if the RPL is dropped */
5319 CPUMSetGuestLDTR(pVCpu, uNewLdt & X86_SEL_MASK_OFF_RPL);
5320 pVCpu->cpum.GstCtx.ldtr.ValidSel = uNewLdt & X86_SEL_MASK_OFF_RPL;
5321 pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
5322 pVCpu->cpum.GstCtx.ldtr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5323 pVCpu->cpum.GstCtx.ldtr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5324 pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
5325
5326 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5327 return VINF_SUCCESS;
5328}
5329
5330
5331/**
5332 * Implements sldt GReg
5333 *
5334 * @param iGReg The general register to store the CRx value in.
5335 * @param enmEffOpSize The operand size.
5336 */
5337IEM_CIMPL_DEF_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5338{
5339 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5340 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5341 {
5342 Log(("sldt: Guest intercept -> VM-exit\n"));
5343 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_SLDT, cbInstr);
5344 }
5345
5346 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5347
5348 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5349 switch (enmEffOpSize)
5350 {
5351 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5352 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5353 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.ldtr.Sel; break;
5354 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5355 }
5356 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5357 return VINF_SUCCESS;
5358}
5359
5360
5361/**
5362 * Implements sldt mem.
5363 *
5364 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5365 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5366 */
5367IEM_CIMPL_DEF_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5368{
5369 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_LDTR_READS, SVM_EXIT_LDTR_READ, 0, 0);
5370
5371 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR);
5372 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.ldtr.Sel);
5373 if (rcStrict == VINF_SUCCESS)
5374 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5375 return rcStrict;
5376}
5377
5378
5379/**
5380 * Implements ltr.
5381 *
5382 * @param uNewTr The new TSS selector value.
5383 */
5384IEM_CIMPL_DEF_1(iemCImpl_ltr, uint16_t, uNewTr)
5385{
5386 /*
5387 * Check preconditions.
5388 */
5389 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
5390 {
5391 Log(("ltr %04x - real or v8086 mode -> #GP(0)\n", uNewTr));
5392 return iemRaiseUndefinedOpcode(pVCpu);
5393 }
5394 if (pVCpu->iem.s.uCpl != 0)
5395 {
5396 Log(("ltr %04x - CPL is %d -> #GP(0)\n", uNewTr, pVCpu->iem.s.uCpl));
5397 return iemRaiseGeneralProtectionFault0(pVCpu);
5398 }
5399 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5400 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5401 {
5402 Log(("ltr: Guest intercept -> VM-exit\n"));
5403 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_LTR, cbInstr);
5404 }
5405 if (uNewTr & X86_SEL_LDT)
5406 {
5407 Log(("ltr %04x - LDT selector -> #GP\n", uNewTr));
5408 return iemRaiseGeneralProtectionFaultBySelector(pVCpu, uNewTr);
5409 }
5410 if (!(uNewTr & X86_SEL_MASK_OFF_RPL))
5411 {
5412 Log(("ltr %04x - NULL selector -> #GP(0)\n", uNewTr));
5413 return iemRaiseGeneralProtectionFault0(pVCpu);
5414 }
5415 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_TR_WRITES))
5416 {
5417 Log(("ltr: Guest intercept -> #VMEXIT\n"));
5418 IEM_SVM_UPDATE_NRIP(pVCpu);
5419 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_TR_WRITE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5420 }
5421
5422 /*
5423 * Read the descriptor.
5424 */
5425 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_TR);
5426 IEMSELDESC Desc;
5427 VBOXSTRICTRC rcStrict = iemMemFetchSelDesc(pVCpu, &Desc, uNewTr, X86_XCPT_GP); /** @todo Correct exception? */
5428 if (rcStrict != VINF_SUCCESS)
5429 return rcStrict;
5430
5431 /* Check GPs first. */
5432 if (Desc.Legacy.Gen.u1DescType)
5433 {
5434 Log(("ltr %#x - not system selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5435 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5436 }
5437 if ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL /* same as AMD64_SEL_TYPE_SYS_TSS_AVAIL */
5438 && ( Desc.Legacy.Gen.u4Type != X86_SEL_TYPE_SYS_286_TSS_AVAIL
5439 || IEM_IS_LONG_MODE(pVCpu)) )
5440 {
5441 Log(("ltr %#x - not an available TSS selector (type %x) -> #GP\n", uNewTr, Desc.Legacy.Gen.u4Type));
5442 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5443 }
5444 uint64_t u64Base;
5445 if (!IEM_IS_LONG_MODE(pVCpu))
5446 u64Base = X86DESC_BASE(&Desc.Legacy);
5447 else
5448 {
5449 if (Desc.Long.Gen.u5Zeros)
5450 {
5451 Log(("ltr %#x - u5Zeros=%#x -> #GP\n", uNewTr, Desc.Long.Gen.u5Zeros));
5452 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5453 }
5454
5455 u64Base = X86DESC64_BASE(&Desc.Long);
5456 if (!IEM_IS_CANONICAL(u64Base))
5457 {
5458 Log(("ltr %#x - non-canonical base address %#llx -> #GP\n", uNewTr, u64Base));
5459 return iemRaiseGeneralProtectionFault(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5460 }
5461 }
5462
5463 /* NP */
5464 if (!Desc.Legacy.Gen.u1Present)
5465 {
5466 Log(("ltr %#x - segment not present -> #NP\n", uNewTr));
5467 return iemRaiseSelectorNotPresentBySelector(pVCpu, uNewTr);
5468 }
5469
5470 /*
5471 * Set it busy.
5472 * Note! Intel says this should lock down the whole descriptor, but we'll
5473 * restrict our selves to 32-bit for now due to lack of inline
5474 * assembly and such.
5475 */
5476 void *pvDesc;
5477 rcStrict = iemMemMap(pVCpu, &pvDesc, 8, UINT8_MAX, pVCpu->cpum.GstCtx.gdtr.pGdt + (uNewTr & X86_SEL_MASK_OFF_RPL),
5478 IEM_ACCESS_DATA_RW, 0);
5479 if (rcStrict != VINF_SUCCESS)
5480 return rcStrict;
5481 switch ((uintptr_t)pvDesc & 3)
5482 {
5483 case 0: ASMAtomicBitSet(pvDesc, 40 + 1); break;
5484 case 1: ASMAtomicBitSet((uint8_t *)pvDesc + 3, 40 + 1 - 24); break;
5485 case 2: ASMAtomicBitSet((uint8_t *)pvDesc + 2, 40 + 1 - 16); break;
5486 case 3: ASMAtomicBitSet((uint8_t *)pvDesc + 1, 40 + 1 - 8); break;
5487 }
5488 rcStrict = iemMemCommitAndUnmap(pVCpu, pvDesc, IEM_ACCESS_DATA_RW);
5489 if (rcStrict != VINF_SUCCESS)
5490 return rcStrict;
5491 Desc.Legacy.Gen.u4Type |= X86_SEL_TYPE_SYS_TSS_BUSY_MASK;
5492
5493 /*
5494 * It checks out alright, update the registers.
5495 */
5496/** @todo check if the actual value is loaded or if the RPL is dropped */
5497 CPUMSetGuestTR(pVCpu, uNewTr & X86_SEL_MASK_OFF_RPL);
5498 pVCpu->cpum.GstCtx.tr.ValidSel = uNewTr & X86_SEL_MASK_OFF_RPL;
5499 pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
5500 pVCpu->cpum.GstCtx.tr.Attr.u = X86DESC_GET_HID_ATTR(&Desc.Legacy);
5501 pVCpu->cpum.GstCtx.tr.u32Limit = X86DESC_LIMIT_G(&Desc.Legacy);
5502 pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
5503
5504 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5505 return VINF_SUCCESS;
5506}
5507
5508
5509/**
5510 * Implements str GReg
5511 *
5512 * @param iGReg The general register to store the CRx value in.
5513 * @param enmEffOpSize The operand size.
5514 */
5515IEM_CIMPL_DEF_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5516{
5517 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5518 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5519 {
5520 Log(("str_reg: Guest intercept -> VM-exit\n"));
5521 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5522 }
5523
5524 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5525
5526 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5527 switch (enmEffOpSize)
5528 {
5529 case IEMMODE_16BIT: *(uint16_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5530 case IEMMODE_32BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5531 case IEMMODE_64BIT: *(uint64_t *)iemGRegRef(pVCpu, iGReg) = pVCpu->cpum.GstCtx.tr.Sel; break;
5532 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5533 }
5534 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5535 return VINF_SUCCESS;
5536}
5537
5538
5539/**
5540 * Implements str mem.
5541 *
5542 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5543 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5544 */
5545IEM_CIMPL_DEF_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5546{
5547 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
5548 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_DESC_TABLE_EXIT))
5549 {
5550 Log(("str_mem: Guest intercept -> VM-exit\n"));
5551 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_LDTR_TR_ACCESS, VMXINSTRID_STR, cbInstr);
5552 }
5553
5554 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_TR_READS, SVM_EXIT_TR_READ, 0, 0);
5555
5556 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TR);
5557 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, pVCpu->cpum.GstCtx.tr.Sel);
5558 if (rcStrict == VINF_SUCCESS)
5559 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5560 return rcStrict;
5561}
5562
5563
5564/**
5565 * Implements mov GReg,CRx.
5566 *
5567 * @param iGReg The general register to store the CRx value in.
5568 * @param iCrReg The CRx register to read (valid).
5569 */
5570IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg)
5571{
5572 if (pVCpu->iem.s.uCpl != 0)
5573 return iemRaiseGeneralProtectionFault0(pVCpu);
5574 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
5575
5576 if (IEM_SVM_IS_READ_CR_INTERCEPT_SET(pVCpu, iCrReg))
5577 {
5578 Log(("iemCImpl_mov_Rd_Cd: Guest intercept CR%u -> #VMEXIT\n", iCrReg));
5579 IEM_SVM_UPDATE_NRIP(pVCpu);
5580 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_READ_CR0 + iCrReg, IEMACCESSCRX_MOV_CRX, iGReg);
5581 }
5582
5583 /* Read it. */
5584 uint64_t crX;
5585 switch (iCrReg)
5586 {
5587 case 0:
5588 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5589 crX = pVCpu->cpum.GstCtx.cr0;
5590 if (IEM_GET_TARGET_CPU(pVCpu) <= IEMTARGETCPU_386)
5591 crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
5592 break;
5593 case 2:
5594 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR2);
5595 crX = pVCpu->cpum.GstCtx.cr2;
5596 break;
5597 case 3:
5598 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5599 crX = pVCpu->cpum.GstCtx.cr3;
5600 break;
5601 case 4:
5602 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5603 crX = pVCpu->cpum.GstCtx.cr4;
5604 break;
5605 case 8:
5606 {
5607 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5608#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5609 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5610 {
5611 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr8(pVCpu, iGReg, cbInstr);
5612 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5613 return rcStrict;
5614
5615 /*
5616 * If the Mov-from-CR8 doesn't cause a VM-exit, bits 7:4 of the VTPR is copied
5617 * to bits 0:3 of the destination operand. Bits 63:4 of the destination operand
5618 * are cleared.
5619 *
5620 * See Intel Spec. 29.3 "Virtualizing CR8-based TPR Accesses"
5621 */
5622 if (IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
5623 {
5624 uint32_t const uTpr = iemVmxVirtApicReadRaw32(pVCpu, XAPIC_OFF_TPR);
5625 crX = (uTpr >> 4) & 0xf;
5626 break;
5627 }
5628 }
5629#endif
5630#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5631 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5632 {
5633 PCSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl;
5634 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
5635 {
5636 crX = pVmcbCtrl->IntCtrl.n.u8VTPR & 0xf;
5637 break;
5638 }
5639 }
5640#endif
5641 uint8_t uTpr;
5642 int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
5643 if (RT_SUCCESS(rc))
5644 crX = uTpr >> 4;
5645 else
5646 crX = 0;
5647 break;
5648 }
5649 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
5650 }
5651
5652#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5653 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5654 {
5655 switch (iCrReg)
5656 {
5657 /* CR0/CR4 reads are subject to masking when in VMX non-root mode. */
5658 case 0: crX = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u); break;
5659 case 4: crX = CPUMGetGuestVmxMaskedCr4(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr4Mask.u); break;
5660
5661 case 3:
5662 {
5663 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovFromCr3(pVCpu, iGReg, cbInstr);
5664 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
5665 return rcStrict;
5666 break;
5667 }
5668 }
5669 }
5670#endif
5671
5672 /* Store it. */
5673 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
5674 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = crX;
5675 else
5676 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)crX;
5677
5678 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5679 return VINF_SUCCESS;
5680}
5681
5682
5683/**
5684 * Implements smsw GReg.
5685 *
5686 * @param iGReg The general register to store the CRx value in.
5687 * @param enmEffOpSize The operand size.
5688 */
5689IEM_CIMPL_DEF_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize)
5690{
5691 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5692
5693#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5694 uint64_t u64MaskedCr0;
5695 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5696 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5697 else
5698 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5699 uint64_t const u64GuestCr0 = u64MaskedCr0;
5700#else
5701 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5702#endif
5703
5704 switch (enmEffOpSize)
5705 {
5706 case IEMMODE_16BIT:
5707 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5708 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0;
5709 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5710 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xffe0;
5711 else
5712 *(uint16_t *)iemGRegRef(pVCpu, iGReg) = (uint16_t)u64GuestCr0 | 0xfff0;
5713 break;
5714
5715 case IEMMODE_32BIT:
5716 *(uint32_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)u64GuestCr0;
5717 break;
5718
5719 case IEMMODE_64BIT:
5720 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = u64GuestCr0;
5721 break;
5722
5723 IEM_NOT_REACHED_DEFAULT_CASE_RET();
5724 }
5725
5726 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5727 return VINF_SUCCESS;
5728}
5729
5730
5731/**
5732 * Implements smsw mem.
5733 *
5734 * @param iEffSeg The effective segment register to use with @a GCPtrMem.
5735 * @param GCPtrEffDst Where to store the 16-bit CR0 value.
5736 */
5737IEM_CIMPL_DEF_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
5738{
5739 IEM_SVM_CHECK_READ_CR0_INTERCEPT(pVCpu, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
5740
5741#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5742 uint64_t u64MaskedCr0;
5743 if (!IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
5744 u64MaskedCr0 = pVCpu->cpum.GstCtx.cr0;
5745 else
5746 u64MaskedCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.hwvirt.vmx.Vmcs.u64Cr0Mask.u);
5747 uint64_t const u64GuestCr0 = u64MaskedCr0;
5748#else
5749 uint64_t const u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5750#endif
5751
5752 uint16_t u16Value;
5753 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
5754 u16Value = (uint16_t)u64GuestCr0;
5755 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
5756 u16Value = (uint16_t)u64GuestCr0 | 0xffe0;
5757 else
5758 u16Value = (uint16_t)u64GuestCr0 | 0xfff0;
5759
5760 VBOXSTRICTRC rcStrict = iemMemStoreDataU16(pVCpu, iEffSeg, GCPtrEffDst, u16Value);
5761 if (rcStrict == VINF_SUCCESS)
5762 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
5763 return rcStrict;
5764}
5765
5766
5767/**
5768 * Helper for mapping CR3 and PAE PDPEs for 'mov CRx,GReg'.
5769 */
5770#define IEM_MAP_PAE_PDPES_AT_CR3_RET(a_pVCpu, a_iCrReg, a_uCr3) \
5771 do \
5772 { \
5773 int const rcX = PGMGstMapPaePdpesAtCr3(a_pVCpu, a_uCr3); \
5774 if (RT_SUCCESS(rcX)) \
5775 { /* likely */ } \
5776 else \
5777 { \
5778 /* Either invalid PDPTEs or CR3 second-level translation failed. Raise #GP(0) either way. */ \
5779 Log(("iemCImpl_load_Cr%#x: Trying to load invalid PAE PDPEs\n", a_iCrReg)); \
5780 return iemRaiseGeneralProtectionFault0(a_pVCpu); \
5781 } \
5782 } while (0)
5783
5784
5785/**
5786 * Used to implemented 'mov CRx,GReg' and 'lmsw r/m16'.
5787 *
5788 * @param iCrReg The CRx register to write (valid).
5789 * @param uNewCrX The new value.
5790 * @param enmAccessCrX The instruction that caused the CrX load.
5791 * @param iGReg The general register in case of a 'mov CRx,GReg'
5792 * instruction.
5793 */
5794IEM_CIMPL_DEF_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg)
5795{
5796 VBOXSTRICTRC rcStrict;
5797 int rc;
5798#ifndef VBOX_WITH_NESTED_HWVIRT_SVM
5799 RT_NOREF2(iGReg, enmAccessCrX);
5800#endif
5801
5802 /*
5803 * Try store it.
5804 * Unfortunately, CPUM only does a tiny bit of the work.
5805 */
5806 switch (iCrReg)
5807 {
5808 case 0:
5809 {
5810 /*
5811 * Perform checks.
5812 */
5813 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5814
5815 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr0;
5816 uint32_t const fValid = CPUMGetGuestCR0ValidMask();
5817
5818 /* ET is hardcoded on 486 and later. */
5819 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_486)
5820 uNewCrX |= X86_CR0_ET;
5821 /* The 386 and 486 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable on 386. */
5822 else if (IEM_GET_TARGET_CPU(pVCpu) == IEMTARGETCPU_486)
5823 {
5824 uNewCrX &= fValid;
5825 uNewCrX |= X86_CR0_ET;
5826 }
5827 else
5828 uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
5829
5830 /* Check for reserved bits. */
5831 if (uNewCrX & ~(uint64_t)fValid)
5832 {
5833 Log(("Trying to set reserved CR0 bits: NewCR0=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
5834 return iemRaiseGeneralProtectionFault0(pVCpu);
5835 }
5836
5837 /* Check for invalid combinations. */
5838 if ( (uNewCrX & X86_CR0_PG)
5839 && !(uNewCrX & X86_CR0_PE) )
5840 {
5841 Log(("Trying to set CR0.PG without CR0.PE\n"));
5842 return iemRaiseGeneralProtectionFault0(pVCpu);
5843 }
5844
5845 if ( !(uNewCrX & X86_CR0_CD)
5846 && (uNewCrX & X86_CR0_NW) )
5847 {
5848 Log(("Trying to clear CR0.CD while leaving CR0.NW set\n"));
5849 return iemRaiseGeneralProtectionFault0(pVCpu);
5850 }
5851
5852 if ( !(uNewCrX & X86_CR0_PG)
5853 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE))
5854 {
5855 Log(("Trying to clear CR0.PG while leaving CR4.PCID set\n"));
5856 return iemRaiseGeneralProtectionFault0(pVCpu);
5857 }
5858
5859 /* Long mode consistency checks. */
5860 if ( (uNewCrX & X86_CR0_PG)
5861 && !(uOldCrX & X86_CR0_PG)
5862 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5863 {
5864 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE))
5865 {
5866 Log(("Trying to enabled long mode paging without CR4.PAE set\n"));
5867 return iemRaiseGeneralProtectionFault0(pVCpu);
5868 }
5869 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1Long)
5870 {
5871 Log(("Trying to enabled long mode paging with a long CS descriptor loaded.\n"));
5872 return iemRaiseGeneralProtectionFault0(pVCpu);
5873 }
5874 }
5875
5876 /* Check for bits that must remain set or cleared in VMX operation,
5877 see Intel spec. 23.8 "Restrictions on VMX operation". */
5878 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
5879 {
5880#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5881 uint64_t const uCr0Fixed0 = IEM_VMX_IS_NON_ROOT_MODE(pVCpu) ? iemVmxGetCr0Fixed0(pVCpu) : VMX_V_CR0_FIXED0;
5882#else
5883 uint64_t const uCr0Fixed0 = VMX_V_CR0_FIXED0;
5884#endif
5885 if ((uNewCrX & uCr0Fixed0) != uCr0Fixed0)
5886 {
5887 Log(("Trying to clear reserved CR0 bits in VMX operation: NewCr0=%#llx MB1=%#llx\n", uNewCrX, uCr0Fixed0));
5888 return iemRaiseGeneralProtectionFault0(pVCpu);
5889 }
5890
5891 uint64_t const uCr0Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr0Fixed1;
5892 if (uNewCrX & ~uCr0Fixed1)
5893 {
5894 Log(("Trying to set reserved CR0 bits in VMX operation: NewCr0=%#llx MB0=%#llx\n", uNewCrX, uCr0Fixed1));
5895 return iemRaiseGeneralProtectionFault0(pVCpu);
5896 }
5897 }
5898
5899 /*
5900 * SVM nested-guest CR0 write intercepts.
5901 */
5902 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, iCrReg))
5903 {
5904 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5905 IEM_SVM_UPDATE_NRIP(pVCpu);
5906 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR0, enmAccessCrX, iGReg);
5907 }
5908 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5909 {
5910 /* 'lmsw' intercepts regardless of whether the TS/MP bits are actually toggled. */
5911 if ( enmAccessCrX == IEMACCESSCRX_LMSW
5912 || (uNewCrX & ~(X86_CR0_TS | X86_CR0_MP)) != (uOldCrX & ~(X86_CR0_TS | X86_CR0_MP)))
5913 {
5914 Assert(enmAccessCrX != IEMACCESSCRX_CLTS);
5915 Log(("iemCImpl_load_Cr%#x: lmsw or bits other than TS/MP changed: Guest intercept -> #VMEXIT\n", iCrReg));
5916 IEM_SVM_UPDATE_NRIP(pVCpu);
5917 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_CR0_SEL_WRITE, enmAccessCrX, iGReg);
5918 }
5919 }
5920
5921 /*
5922 * Change EFER.LMA if entering or leaving long mode.
5923 */
5924 uint64_t NewEFER = pVCpu->cpum.GstCtx.msrEFER;
5925 if ( (uNewCrX & X86_CR0_PG) != (uOldCrX & X86_CR0_PG)
5926 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME) )
5927 {
5928 if (uNewCrX & X86_CR0_PG)
5929 NewEFER |= MSR_K6_EFER_LMA;
5930 else
5931 NewEFER &= ~MSR_K6_EFER_LMA;
5932
5933 CPUMSetGuestEFER(pVCpu, NewEFER);
5934 Assert(pVCpu->cpum.GstCtx.msrEFER == NewEFER);
5935 }
5936
5937 /*
5938 * Inform PGM.
5939 */
5940 if ( (uNewCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW))
5941 != (uOldCrX & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE | X86_CR0_CD | X86_CR0_NW)) )
5942 {
5943 if ( enmAccessCrX != IEMACCESSCRX_MOV_CRX
5944 || !CPUMIsPaePagingEnabled(uNewCrX, pVCpu->cpum.GstCtx.cr4, NewEFER)
5945 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
5946 { /* likely */ }
5947 else
5948 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
5949 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
5950 AssertRCReturn(rc, rc);
5951 /* ignore informational status codes */
5952 }
5953
5954 /*
5955 * Change CR0.
5956 */
5957 CPUMSetGuestCR0(pVCpu, uNewCrX);
5958 Assert(pVCpu->cpum.GstCtx.cr0 == uNewCrX);
5959
5960 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
5961 false /* fForce */);
5962 break;
5963 }
5964
5965 /*
5966 * CR2 can be changed without any restrictions.
5967 */
5968 case 2:
5969 {
5970 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 2))
5971 {
5972 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
5973 IEM_SVM_UPDATE_NRIP(pVCpu);
5974 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR2, enmAccessCrX, iGReg);
5975 }
5976 pVCpu->cpum.GstCtx.cr2 = uNewCrX;
5977 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_CR2;
5978 rcStrict = VINF_SUCCESS;
5979 break;
5980 }
5981
5982 /*
5983 * CR3 is relatively simple, although AMD and Intel have different
5984 * accounts of how setting reserved bits are handled. We take intel's
5985 * word for the lower bits and AMD's for the high bits (63:52). The
5986 * lower reserved bits are ignored and left alone; OpenBSD 5.8 relies
5987 * on this.
5988 */
5989 /** @todo Testcase: Setting reserved bits in CR3, especially before
5990 * enabling paging. */
5991 case 3:
5992 {
5993 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5994
5995 /* Bit 63 being clear in the source operand with PCIDE indicates no invalidations are required. */
5996 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
5997 && (uNewCrX & RT_BIT_64(63)))
5998 {
5999 /** @todo r=ramshankar: avoiding a TLB flush altogether here causes Windows 10
6000 * SMP(w/o nested-paging) to hang during bootup on Skylake systems, see
6001 * Intel spec. 4.10.4.1 "Operations that Invalidate TLBs and
6002 * Paging-Structure Caches". */
6003 uNewCrX &= ~RT_BIT_64(63);
6004 }
6005
6006 /* Check / mask the value. */
6007#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
6008 /* See Intel spec. 27.2.2 "EPT Translation Mechanism" footnote. */
6009 uint64_t const fInvPhysMask = !CPUMIsGuestVmxEptPagingEnabledEx(IEM_GET_CTX(pVCpu))
6010 ? (UINT64_MAX << IEM_GET_GUEST_CPU_FEATURES(pVCpu)->cMaxPhysAddrWidth)
6011 : (~X86_CR3_EPT_PAGE_MASK & X86_PAGE_4K_BASE_MASK);
6012#else
6013 uint64_t const fInvPhysMask = UINT64_C(0xfff0000000000000);
6014#endif
6015 if (uNewCrX & fInvPhysMask)
6016 {
6017 /** @todo Should we raise this only for 64-bit mode like Intel claims? AMD is
6018 * very vague in this area. As mentioned above, need testcase on real
6019 * hardware... Sigh. */
6020 Log(("Trying to load CR3 with invalid high bits set: %#llx\n", uNewCrX));
6021 return iemRaiseGeneralProtectionFault0(pVCpu);
6022 }
6023
6024 uint64_t fValid;
6025 if ( (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PAE)
6026 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME))
6027 {
6028 /** @todo Redundant? This value has already been validated above. */
6029 fValid = UINT64_C(0x000fffffffffffff);
6030 }
6031 else
6032 fValid = UINT64_C(0xffffffff);
6033 if (uNewCrX & ~fValid)
6034 {
6035 Log(("Automatically clearing reserved MBZ bits in CR3 load: NewCR3=%#llx ClearedBits=%#llx\n",
6036 uNewCrX, uNewCrX & ~fValid));
6037 uNewCrX &= fValid;
6038 }
6039
6040 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 3))
6041 {
6042 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6043 IEM_SVM_UPDATE_NRIP(pVCpu);
6044 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR3, enmAccessCrX, iGReg);
6045 }
6046
6047 /* Inform PGM. */
6048 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PG)
6049 {
6050 if ( !CPUMIsGuestInPAEModeEx(IEM_GET_CTX(pVCpu))
6051 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6052 { /* likely */ }
6053 else
6054 {
6055 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6056 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, uNewCrX);
6057 }
6058 rc = PGMFlushTLB(pVCpu, uNewCrX, !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PGE));
6059 AssertRCReturn(rc, rc);
6060 /* ignore informational status codes */
6061 }
6062
6063 /* Make the change. */
6064 rc = CPUMSetGuestCR3(pVCpu, uNewCrX);
6065 AssertRCSuccessReturn(rc, rc);
6066
6067 rcStrict = VINF_SUCCESS;
6068 break;
6069 }
6070
6071 /*
6072 * CR4 is a bit more tedious as there are bits which cannot be cleared
6073 * under some circumstances and such.
6074 */
6075 case 4:
6076 {
6077 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6078 uint64_t const uOldCrX = pVCpu->cpum.GstCtx.cr4;
6079
6080 /* Reserved bits. */
6081 uint32_t const fValid = CPUMGetGuestCR4ValidMask(pVCpu->CTX_SUFF(pVM));
6082 if (uNewCrX & ~(uint64_t)fValid)
6083 {
6084 Log(("Trying to set reserved CR4 bits: NewCR4=%#llx InvalidBits=%#llx\n", uNewCrX, uNewCrX & ~(uint64_t)fValid));
6085 return iemRaiseGeneralProtectionFault0(pVCpu);
6086 }
6087
6088 bool const fPcide = !(uOldCrX & X86_CR4_PCIDE) && (uNewCrX & X86_CR4_PCIDE);
6089 bool const fLongMode = CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu));
6090
6091 /* PCIDE check. */
6092 if ( fPcide
6093 && ( !fLongMode
6094 || (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))))
6095 {
6096 Log(("Trying to set PCIDE with invalid PCID or outside long mode. Pcid=%#x\n", (pVCpu->cpum.GstCtx.cr3 & UINT64_C(0xfff))));
6097 return iemRaiseGeneralProtectionFault0(pVCpu);
6098 }
6099
6100 /* PAE check. */
6101 if ( fLongMode
6102 && (uOldCrX & X86_CR4_PAE)
6103 && !(uNewCrX & X86_CR4_PAE))
6104 {
6105 Log(("Trying to set clear CR4.PAE while long mode is active\n"));
6106 return iemRaiseGeneralProtectionFault0(pVCpu);
6107 }
6108
6109 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 4))
6110 {
6111 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6112 IEM_SVM_UPDATE_NRIP(pVCpu);
6113 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR4, enmAccessCrX, iGReg);
6114 }
6115
6116 /* Check for bits that must remain set or cleared in VMX operation,
6117 see Intel spec. 23.8 "Restrictions on VMX operation". */
6118 if (IEM_VMX_IS_ROOT_MODE(pVCpu))
6119 {
6120 uint64_t const uCr4Fixed0 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed0;
6121 if ((uNewCrX & uCr4Fixed0) != uCr4Fixed0)
6122 {
6123 Log(("Trying to clear reserved CR4 bits in VMX operation: NewCr4=%#llx MB1=%#llx\n", uNewCrX, uCr4Fixed0));
6124 return iemRaiseGeneralProtectionFault0(pVCpu);
6125 }
6126
6127 uint64_t const uCr4Fixed1 = pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs.u64Cr4Fixed1;
6128 if (uNewCrX & ~uCr4Fixed1)
6129 {
6130 Log(("Trying to set reserved CR4 bits in VMX operation: NewCr4=%#llx MB0=%#llx\n", uNewCrX, uCr4Fixed1));
6131 return iemRaiseGeneralProtectionFault0(pVCpu);
6132 }
6133 }
6134
6135 /*
6136 * Notify PGM.
6137 */
6138 if ((uNewCrX ^ uOldCrX) & (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_PCIDE /* | X86_CR4_SMEP */))
6139 {
6140 if ( !CPUMIsPaePagingEnabled(pVCpu->cpum.GstCtx.cr0, uNewCrX, pVCpu->cpum.GstCtx.msrEFER)
6141 || CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6142 { /* likely */ }
6143 else
6144 {
6145 Assert(enmAccessCrX == IEMACCESSCRX_MOV_CRX);
6146 IEM_MAP_PAE_PDPES_AT_CR3_RET(pVCpu, iCrReg, pVCpu->cpum.GstCtx.cr3);
6147 }
6148 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true /* global */);
6149 AssertRCReturn(rc, rc);
6150 /* ignore informational status codes */
6151 }
6152
6153 /*
6154 * Change it.
6155 */
6156 rc = CPUMSetGuestCR4(pVCpu, uNewCrX);
6157 AssertRCSuccessReturn(rc, rc);
6158 Assert(pVCpu->cpum.GstCtx.cr4 == uNewCrX);
6159
6160 rcStrict = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
6161 false /* fForce */);
6162 break;
6163 }
6164
6165 /*
6166 * CR8 maps to the APIC TPR.
6167 */
6168 case 8:
6169 {
6170 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
6171 if (uNewCrX & ~(uint64_t)0xf)
6172 {
6173 Log(("Trying to set reserved CR8 bits (%#RX64)\n", uNewCrX));
6174 return iemRaiseGeneralProtectionFault0(pVCpu);
6175 }
6176
6177#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6178 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6179 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_USE_TPR_SHADOW))
6180 {
6181 /*
6182 * If the Mov-to-CR8 doesn't cause a VM-exit, bits 0:3 of the source operand
6183 * is copied to bits 7:4 of the VTPR. Bits 0:3 and bits 31:8 of the VTPR are
6184 * cleared. Following this the processor performs TPR virtualization.
6185 *
6186 * However, we should not perform TPR virtualization immediately here but
6187 * after this instruction has completed.
6188 *
6189 * See Intel spec. 29.3 "Virtualizing CR8-based TPR Accesses"
6190 * See Intel spec. 27.1 "Architectural State Before A VM-exit"
6191 */
6192 uint32_t const uTpr = (uNewCrX & 0xf) << 4;
6193 Log(("iemCImpl_load_Cr%#x: Virtualizing TPR (%#x) write\n", iCrReg, uTpr));
6194 iemVmxVirtApicWriteRaw32(pVCpu, XAPIC_OFF_TPR, uTpr);
6195 iemVmxVirtApicSetPendingWrite(pVCpu, XAPIC_OFF_TPR);
6196 rcStrict = VINF_SUCCESS;
6197 break;
6198 }
6199#endif
6200
6201#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6202 if (CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)))
6203 {
6204 if (IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(pVCpu, /*cr*/ 8))
6205 {
6206 Log(("iemCImpl_load_Cr%#x: Guest intercept -> #VMEXIT\n", iCrReg));
6207 IEM_SVM_UPDATE_NRIP(pVCpu);
6208 IEM_SVM_CRX_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_CR8, enmAccessCrX, iGReg);
6209 }
6210
6211 pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.IntCtrl.n.u8VTPR = uNewCrX;
6212 if (CPUMIsGuestSvmVirtIntrMasking(pVCpu, IEM_GET_CTX(pVCpu)))
6213 {
6214 rcStrict = VINF_SUCCESS;
6215 break;
6216 }
6217 }
6218#endif
6219 uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
6220 APICSetTpr(pVCpu, u8Tpr);
6221 rcStrict = VINF_SUCCESS;
6222 break;
6223 }
6224
6225 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6226 }
6227
6228 /*
6229 * Advance the RIP on success.
6230 */
6231 if (RT_SUCCESS(rcStrict))
6232 {
6233 if (rcStrict != VINF_SUCCESS)
6234 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
6235 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6236 }
6237
6238 return rcStrict;
6239}
6240
6241
6242/**
6243 * Implements mov CRx,GReg.
6244 *
6245 * @param iCrReg The CRx register to write (valid).
6246 * @param iGReg The general register to load the CRx value from.
6247 */
6248IEM_CIMPL_DEF_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg)
6249{
6250 if (pVCpu->iem.s.uCpl != 0)
6251 return iemRaiseGeneralProtectionFault0(pVCpu);
6252 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6253
6254 /*
6255 * Read the new value from the source register and call common worker.
6256 */
6257 uint64_t uNewCrX;
6258 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6259 uNewCrX = iemGRegFetchU64(pVCpu, iGReg);
6260 else
6261 uNewCrX = iemGRegFetchU32(pVCpu, iGReg);
6262
6263#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6264 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6265 {
6266 VBOXSTRICTRC rcStrict = VINF_VMX_INTERCEPT_NOT_ACTIVE;
6267 switch (iCrReg)
6268 {
6269 case 0:
6270 case 4: rcStrict = iemVmxVmexitInstrMovToCr0Cr4(pVCpu, iCrReg, &uNewCrX, iGReg, cbInstr); break;
6271 case 3: rcStrict = iemVmxVmexitInstrMovToCr3(pVCpu, uNewCrX, iGReg, cbInstr); break;
6272 case 8: rcStrict = iemVmxVmexitInstrMovToCr8(pVCpu, iGReg, cbInstr); break;
6273 }
6274 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6275 return rcStrict;
6276 }
6277#endif
6278
6279 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, iCrReg, uNewCrX, IEMACCESSCRX_MOV_CRX, iGReg);
6280}
6281
6282
6283/**
6284 * Implements 'LMSW r/m16'
6285 *
6286 * @param u16NewMsw The new value.
6287 * @param GCPtrEffDst The guest-linear address of the source operand in case
6288 * of a memory operand. For register operand, pass
6289 * NIL_RTGCPTR.
6290 */
6291IEM_CIMPL_DEF_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst)
6292{
6293 if (pVCpu->iem.s.uCpl != 0)
6294 return iemRaiseGeneralProtectionFault0(pVCpu);
6295 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6296 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6297
6298#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6299 /* Check nested-guest VMX intercept and get updated MSW if there's no VM-exit. */
6300 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6301 {
6302 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrLmsw(pVCpu, pVCpu->cpum.GstCtx.cr0, &u16NewMsw, GCPtrEffDst, cbInstr);
6303 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6304 return rcStrict;
6305 }
6306#else
6307 RT_NOREF_PV(GCPtrEffDst);
6308#endif
6309
6310 /*
6311 * Compose the new CR0 value and call common worker.
6312 */
6313 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0 & ~(X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6314 uNewCr0 |= u16NewMsw & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS);
6315 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_LMSW, UINT8_MAX /* iGReg */);
6316}
6317
6318
6319/**
6320 * Implements 'CLTS'.
6321 */
6322IEM_CIMPL_DEF_0(iemCImpl_clts)
6323{
6324 if (pVCpu->iem.s.uCpl != 0)
6325 return iemRaiseGeneralProtectionFault0(pVCpu);
6326
6327 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
6328 uint64_t uNewCr0 = pVCpu->cpum.GstCtx.cr0;
6329 uNewCr0 &= ~X86_CR0_TS;
6330
6331#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6332 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6333 {
6334 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrClts(pVCpu, cbInstr);
6335 if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
6336 uNewCr0 |= (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS);
6337 else if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6338 return rcStrict;
6339 }
6340#endif
6341
6342 return IEM_CIMPL_CALL_4(iemCImpl_load_CrX, /*cr*/ 0, uNewCr0, IEMACCESSCRX_CLTS, UINT8_MAX /* iGReg */);
6343}
6344
6345
6346/**
6347 * Implements mov GReg,DRx.
6348 *
6349 * @param iGReg The general register to store the DRx value in.
6350 * @param iDrReg The DRx register to read (0-7).
6351 */
6352IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg)
6353{
6354#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6355 /*
6356 * Check nested-guest VMX intercept.
6357 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6358 * over CPL and CR4.DE and even DR4/DR5 checks.
6359 *
6360 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6361 */
6362 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6363 {
6364 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_FROM_DRX, iDrReg, iGReg, cbInstr);
6365 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6366 return rcStrict;
6367 }
6368#endif
6369
6370 /*
6371 * Check preconditions.
6372 */
6373 /* Raise GPs. */
6374 if (pVCpu->iem.s.uCpl != 0)
6375 return iemRaiseGeneralProtectionFault0(pVCpu);
6376 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6377 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
6378
6379 if ( (iDrReg == 4 || iDrReg == 5)
6380 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
6381 {
6382 Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
6383 return iemRaiseGeneralProtectionFault0(pVCpu);
6384 }
6385
6386 /* Raise #DB if general access detect is enabled. */
6387 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6388 {
6389 Log(("mov r%u,dr%u: DR7.GD=1 -> #DB\n", iGReg, iDrReg));
6390 return iemRaiseDebugException(pVCpu);
6391 }
6392
6393 /*
6394 * Read the debug register and store it in the specified general register.
6395 */
6396 uint64_t drX;
6397 switch (iDrReg)
6398 {
6399 case 0:
6400 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6401 drX = pVCpu->cpum.GstCtx.dr[0];
6402 break;
6403 case 1:
6404 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6405 drX = pVCpu->cpum.GstCtx.dr[1];
6406 break;
6407 case 2:
6408 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6409 drX = pVCpu->cpum.GstCtx.dr[2];
6410 break;
6411 case 3:
6412 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6413 drX = pVCpu->cpum.GstCtx.dr[3];
6414 break;
6415 case 6:
6416 case 4:
6417 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6418 drX = pVCpu->cpum.GstCtx.dr[6];
6419 drX |= X86_DR6_RA1_MASK;
6420 drX &= ~X86_DR6_RAZ_MASK;
6421 break;
6422 case 7:
6423 case 5:
6424 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
6425 drX = pVCpu->cpum.GstCtx.dr[7];
6426 drX |=X86_DR7_RA1_MASK;
6427 drX &= ~X86_DR7_RAZ_MASK;
6428 break;
6429 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* caller checks */
6430 }
6431
6432 /** @todo SVM nested-guest intercept for DR8-DR15? */
6433 /*
6434 * Check for any SVM nested-guest intercepts for the DRx read.
6435 */
6436 if (IEM_SVM_IS_READ_DR_INTERCEPT_SET(pVCpu, iDrReg))
6437 {
6438 Log(("mov r%u,dr%u: Guest intercept -> #VMEXIT\n", iGReg, iDrReg));
6439 IEM_SVM_UPDATE_NRIP(pVCpu);
6440 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
6441 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6442 }
6443
6444 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6445 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = drX;
6446 else
6447 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)drX;
6448
6449 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6450 return VINF_SUCCESS;
6451}
6452
6453
6454/**
6455 * Implements mov DRx,GReg.
6456 *
6457 * @param iDrReg The DRx register to write (valid).
6458 * @param iGReg The general register to load the DRx value from.
6459 */
6460IEM_CIMPL_DEF_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg)
6461{
6462#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6463 /*
6464 * Check nested-guest VMX intercept.
6465 * Unlike most other intercepts, the Mov DRx intercept takes preceedence
6466 * over CPL and CR4.DE and even DR4/DR5 checks.
6467 *
6468 * See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
6469 */
6470 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6471 {
6472 VBOXSTRICTRC rcStrict = iemVmxVmexitInstrMovDrX(pVCpu, VMXINSTRID_MOV_TO_DRX, iDrReg, iGReg, cbInstr);
6473 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
6474 return rcStrict;
6475 }
6476#endif
6477
6478 /*
6479 * Check preconditions.
6480 */
6481 if (pVCpu->iem.s.uCpl != 0)
6482 return iemRaiseGeneralProtectionFault0(pVCpu);
6483 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6484 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
6485
6486 if (iDrReg == 4 || iDrReg == 5)
6487 {
6488 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
6489 {
6490 Log(("mov dr%u,r%u: CR4.DE=1 -> #GP(0)\n", iDrReg, iGReg));
6491 return iemRaiseGeneralProtectionFault0(pVCpu);
6492 }
6493 iDrReg += 2;
6494 }
6495
6496 /* Raise #DB if general access detect is enabled. */
6497 /** @todo is \#DB/DR7.GD raised before any reserved high bits in DR7/DR6
6498 * \#GP? */
6499 if (pVCpu->cpum.GstCtx.dr[7] & X86_DR7_GD)
6500 {
6501 Log(("mov dr%u,r%u: DR7.GD=1 -> #DB\n", iDrReg, iGReg));
6502 return iemRaiseDebugException(pVCpu);
6503 }
6504
6505 /*
6506 * Read the new value from the source register.
6507 */
6508 uint64_t uNewDrX;
6509 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6510 uNewDrX = iemGRegFetchU64(pVCpu, iGReg);
6511 else
6512 uNewDrX = iemGRegFetchU32(pVCpu, iGReg);
6513
6514 /*
6515 * Adjust it.
6516 */
6517 switch (iDrReg)
6518 {
6519 case 0:
6520 case 1:
6521 case 2:
6522 case 3:
6523 /* nothing to adjust */
6524 break;
6525
6526 case 6:
6527 if (uNewDrX & X86_DR6_MBZ_MASK)
6528 {
6529 Log(("mov dr%u,%#llx: DR6 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6530 return iemRaiseGeneralProtectionFault0(pVCpu);
6531 }
6532 uNewDrX |= X86_DR6_RA1_MASK;
6533 uNewDrX &= ~X86_DR6_RAZ_MASK;
6534 break;
6535
6536 case 7:
6537 if (uNewDrX & X86_DR7_MBZ_MASK)
6538 {
6539 Log(("mov dr%u,%#llx: DR7 high bits are not zero -> #GP(0)\n", iDrReg, uNewDrX));
6540 return iemRaiseGeneralProtectionFault0(pVCpu);
6541 }
6542 uNewDrX |= X86_DR7_RA1_MASK;
6543 uNewDrX &= ~X86_DR7_RAZ_MASK;
6544 break;
6545
6546 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6547 }
6548
6549 /** @todo SVM nested-guest intercept for DR8-DR15? */
6550 /*
6551 * Check for any SVM nested-guest intercepts for the DRx write.
6552 */
6553 if (IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(pVCpu, iDrReg))
6554 {
6555 Log2(("mov dr%u,r%u: Guest intercept -> #VMEXIT\n", iDrReg, iGReg));
6556 IEM_SVM_UPDATE_NRIP(pVCpu);
6557 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_WRITE_DR0 + (iDrReg & 0xf),
6558 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
6559 }
6560
6561 /*
6562 * Do the actual setting.
6563 */
6564 if (iDrReg < 4)
6565 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3);
6566 else if (iDrReg == 6)
6567 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
6568
6569 int rc = CPUMSetGuestDRx(pVCpu, iDrReg, uNewDrX);
6570 AssertRCSuccessReturn(rc, RT_SUCCESS_NP(rc) ? VERR_IEM_IPE_1 : rc);
6571
6572 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6573 return VINF_SUCCESS;
6574}
6575
6576
6577/**
6578 * Implements mov GReg,TRx.
6579 *
6580 * @param iGReg The general register to store the
6581 * TRx value in.
6582 * @param iTrReg The TRx register to read (6/7).
6583 */
6584IEM_CIMPL_DEF_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg)
6585{
6586 /*
6587 * Check preconditions. NB: This instruction is 386/486 only.
6588 */
6589
6590 /* Raise GPs. */
6591 if (pVCpu->iem.s.uCpl != 0)
6592 return iemRaiseGeneralProtectionFault0(pVCpu);
6593 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6594
6595 if (iTrReg < 6 || iTrReg > 7)
6596 {
6597 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6598 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6599 return iemRaiseGeneralProtectionFault0(pVCpu);
6600 }
6601
6602 /*
6603 * Read the test register and store it in the specified general register.
6604 * This is currently a dummy implementation that only exists to satisfy
6605 * old debuggers like WDEB386 or OS/2 KDB which unconditionally read the
6606 * TR6/TR7 registers. Software which actually depends on the TR values
6607 * (different on 386/486) is exceedingly rare.
6608 */
6609 uint64_t trX;
6610 switch (iTrReg)
6611 {
6612 case 6:
6613 trX = 0; /* Currently a dummy. */
6614 break;
6615 case 7:
6616 trX = 0; /* Currently a dummy. */
6617 break;
6618 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
6619 }
6620
6621 *(uint64_t *)iemGRegRef(pVCpu, iGReg) = (uint32_t)trX;
6622
6623 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6624 return VINF_SUCCESS;
6625}
6626
6627
6628/**
6629 * Implements mov TRx,GReg.
6630 *
6631 * @param iTrReg The TRx register to write (valid).
6632 * @param iGReg The general register to load the TRx
6633 * value from.
6634 */
6635IEM_CIMPL_DEF_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg)
6636{
6637 /*
6638 * Check preconditions. NB: This instruction is 386/486 only.
6639 */
6640
6641 /* Raise GPs. */
6642 if (pVCpu->iem.s.uCpl != 0)
6643 return iemRaiseGeneralProtectionFault0(pVCpu);
6644 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6645
6646 if (iTrReg < 6 || iTrReg > 7)
6647 {
6648 /** @todo Do Intel CPUs reject this or are the TRs aliased? */
6649 Log(("mov r%u,tr%u: invalid register -> #GP(0)\n", iGReg, iTrReg));
6650 return iemRaiseGeneralProtectionFault0(pVCpu);
6651 }
6652
6653 /*
6654 * Read the new value from the source register.
6655 */
6656 uint64_t uNewTrX;
6657 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
6658 uNewTrX = iemGRegFetchU64(pVCpu, iGReg);
6659 else
6660 uNewTrX = iemGRegFetchU32(pVCpu, iGReg);
6661
6662 /*
6663 * Here we would do the actual setting if this weren't a dummy implementation.
6664 * This is currently a dummy implementation that only exists to prevent
6665 * old debuggers like WDEB386 or OS/2 KDB from crashing.
6666 */
6667 RT_NOREF(uNewTrX);
6668
6669 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6670 return VINF_SUCCESS;
6671}
6672
6673
6674/**
6675 * Implements 'INVLPG m'.
6676 *
6677 * @param GCPtrPage The effective address of the page to invalidate.
6678 * @remarks Updates the RIP.
6679 */
6680IEM_CIMPL_DEF_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage)
6681{
6682 /* ring-0 only. */
6683 if (pVCpu->iem.s.uCpl != 0)
6684 return iemRaiseGeneralProtectionFault0(pVCpu);
6685 Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
6686 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6687
6688#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6689 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6690 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6691 {
6692 Log(("invlpg: Guest intercept (%RGp) -> VM-exit\n", GCPtrPage));
6693 return iemVmxVmexitInstrInvlpg(pVCpu, GCPtrPage, cbInstr);
6694 }
6695#endif
6696
6697 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
6698 {
6699 Log(("invlpg: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
6700 IEM_SVM_UPDATE_NRIP(pVCpu);
6701 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_INVLPG,
6702 IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? GCPtrPage : 0, 0 /* uExitInfo2 */);
6703 }
6704
6705 int rc = PGMInvalidatePage(pVCpu, GCPtrPage);
6706 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6707
6708 if (rc == VINF_SUCCESS)
6709 return VINF_SUCCESS;
6710 if (rc == VINF_PGM_SYNC_CR3)
6711 return iemSetPassUpStatus(pVCpu, rc);
6712
6713 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
6714 Log(("PGMInvalidatePage(%RGv) -> %Rrc\n", GCPtrPage, rc));
6715 return rc;
6716}
6717
6718
6719/**
6720 * Implements INVPCID.
6721 *
6722 * @param iEffSeg The segment of the invpcid descriptor.
6723 * @param GCPtrInvpcidDesc The address of invpcid descriptor.
6724 * @param uInvpcidType The invalidation type.
6725 * @remarks Updates the RIP.
6726 */
6727IEM_CIMPL_DEF_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType)
6728{
6729 /*
6730 * Check preconditions.
6731 */
6732 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fInvpcid)
6733 return iemRaiseUndefinedOpcode(pVCpu);
6734
6735 /* When in VMX non-root mode and INVPCID is not enabled, it results in #UD. */
6736 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6737 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_INVPCID))
6738 {
6739 Log(("invpcid: Not enabled for nested-guest execution -> #UD\n"));
6740 return iemRaiseUndefinedOpcode(pVCpu);
6741 }
6742
6743 if (pVCpu->iem.s.uCpl != 0)
6744 {
6745 Log(("invpcid: CPL != 0 -> #GP(0)\n"));
6746 return iemRaiseGeneralProtectionFault0(pVCpu);
6747 }
6748
6749 if (IEM_IS_V86_MODE(pVCpu))
6750 {
6751 Log(("invpcid: v8086 mode -> #GP(0)\n"));
6752 return iemRaiseGeneralProtectionFault0(pVCpu);
6753 }
6754
6755 /*
6756 * Check nested-guest intercept.
6757 *
6758 * INVPCID causes a VM-exit if "enable INVPCID" and "INVLPG exiting" are
6759 * both set. We have already checked the former earlier in this function.
6760 *
6761 * CPL and virtual-8086 mode checks take priority over this VM-exit.
6762 * See Intel spec. "25.1.1 Relative Priority of Faults and VM Exits".
6763 */
6764 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6765 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INVLPG_EXIT))
6766 {
6767 Log(("invpcid: Guest intercept -> #VM-exit\n"));
6768 IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(pVCpu, VMX_EXIT_INVPCID, VMXINSTRID_NONE, cbInstr);
6769 }
6770
6771 if (uInvpcidType > X86_INVPCID_TYPE_MAX_VALID)
6772 {
6773 Log(("invpcid: invalid/unrecognized invpcid type %#RX64 -> #GP(0)\n", uInvpcidType));
6774 return iemRaiseGeneralProtectionFault0(pVCpu);
6775 }
6776 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
6777
6778 /*
6779 * Fetch the invpcid descriptor from guest memory.
6780 */
6781 RTUINT128U uDesc;
6782 VBOXSTRICTRC rcStrict = iemMemFetchDataU128(pVCpu, &uDesc, iEffSeg, GCPtrInvpcidDesc);
6783 if (rcStrict == VINF_SUCCESS)
6784 {
6785 /*
6786 * Validate the descriptor.
6787 */
6788 if (uDesc.s.Lo > 0xfff)
6789 {
6790 Log(("invpcid: reserved bits set in invpcid descriptor %#RX64 -> #GP(0)\n", uDesc.s.Lo));
6791 return iemRaiseGeneralProtectionFault0(pVCpu);
6792 }
6793
6794 RTGCUINTPTR64 const GCPtrInvAddr = uDesc.s.Hi;
6795 uint8_t const uPcid = uDesc.s.Lo & UINT64_C(0xfff);
6796 uint32_t const uCr4 = pVCpu->cpum.GstCtx.cr4;
6797 uint64_t const uCr3 = pVCpu->cpum.GstCtx.cr3;
6798 switch (uInvpcidType)
6799 {
6800 case X86_INVPCID_TYPE_INDV_ADDR:
6801 {
6802 if (!IEM_IS_CANONICAL(GCPtrInvAddr))
6803 {
6804 Log(("invpcid: invalidation address %#RGP is not canonical -> #GP(0)\n", GCPtrInvAddr));
6805 return iemRaiseGeneralProtectionFault0(pVCpu);
6806 }
6807 if ( !(uCr4 & X86_CR4_PCIDE)
6808 && uPcid != 0)
6809 {
6810 Log(("invpcid: invalid pcid %#x\n", uPcid));
6811 return iemRaiseGeneralProtectionFault0(pVCpu);
6812 }
6813
6814 /* Invalidate mappings for the linear address tagged with PCID except global translations. */
6815 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6816 break;
6817 }
6818
6819 case X86_INVPCID_TYPE_SINGLE_CONTEXT:
6820 {
6821 if ( !(uCr4 & X86_CR4_PCIDE)
6822 && uPcid != 0)
6823 {
6824 Log(("invpcid: invalid pcid %#x\n", uPcid));
6825 return iemRaiseGeneralProtectionFault0(pVCpu);
6826 }
6827 /* Invalidate all mappings associated with PCID except global translations. */
6828 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6829 break;
6830 }
6831
6832 case X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL:
6833 {
6834 PGMFlushTLB(pVCpu, uCr3, true /* fGlobal */);
6835 break;
6836 }
6837
6838 case X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL:
6839 {
6840 PGMFlushTLB(pVCpu, uCr3, false /* fGlobal */);
6841 break;
6842 }
6843 IEM_NOT_REACHED_DEFAULT_CASE_RET();
6844 }
6845 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6846 }
6847 return rcStrict;
6848}
6849
6850
6851/**
6852 * Implements INVD.
6853 */
6854IEM_CIMPL_DEF_0(iemCImpl_invd)
6855{
6856 if (pVCpu->iem.s.uCpl != 0)
6857 {
6858 Log(("invd: CPL != 0 -> #GP(0)\n"));
6859 return iemRaiseGeneralProtectionFault0(pVCpu);
6860 }
6861
6862 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6863 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_INVD, cbInstr);
6864
6865 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_INVD, SVM_EXIT_INVD, 0, 0);
6866
6867 /* We currently take no action here. */
6868 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6869 return VINF_SUCCESS;
6870}
6871
6872
6873/**
6874 * Implements WBINVD.
6875 */
6876IEM_CIMPL_DEF_0(iemCImpl_wbinvd)
6877{
6878 if (pVCpu->iem.s.uCpl != 0)
6879 {
6880 Log(("wbinvd: CPL != 0 -> #GP(0)\n"));
6881 return iemRaiseGeneralProtectionFault0(pVCpu);
6882 }
6883
6884 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
6885 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WBINVD, cbInstr);
6886
6887 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_WBINVD, SVM_EXIT_WBINVD, 0, 0);
6888
6889 /* We currently take no action here. */
6890 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6891 return VINF_SUCCESS;
6892}
6893
6894
6895/** Opcode 0x0f 0xaa. */
6896IEM_CIMPL_DEF_0(iemCImpl_rsm)
6897{
6898 IEM_SVM_CHECK_INSTR_INTERCEPT(pVCpu, SVM_CTRL_INTERCEPT_RSM, SVM_EXIT_RSM, 0, 0);
6899 NOREF(cbInstr);
6900 return iemRaiseUndefinedOpcode(pVCpu);
6901}
6902
6903
6904/**
6905 * Implements RDTSC.
6906 */
6907IEM_CIMPL_DEF_0(iemCImpl_rdtsc)
6908{
6909 /*
6910 * Check preconditions.
6911 */
6912 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fTsc)
6913 return iemRaiseUndefinedOpcode(pVCpu);
6914
6915 if (pVCpu->iem.s.uCpl != 0)
6916 {
6917 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6918 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6919 {
6920 Log(("rdtsc: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6921 return iemRaiseGeneralProtectionFault0(pVCpu);
6922 }
6923 }
6924
6925 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6926 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6927 {
6928 Log(("rdtsc: Guest intercept -> VM-exit\n"));
6929 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSC, cbInstr);
6930 }
6931
6932 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
6933 {
6934 Log(("rdtsc: Guest intercept -> #VMEXIT\n"));
6935 IEM_SVM_UPDATE_NRIP(pVCpu);
6936 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6937 }
6938
6939 /*
6940 * Do the job.
6941 */
6942 uint64_t uTicks = TMCpuTickGet(pVCpu);
6943#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
6944 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
6945#endif
6946 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
6947 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
6948 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX); /* For IEMExecDecodedRdtsc. */
6949 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
6950 return VINF_SUCCESS;
6951}
6952
6953
6954/**
6955 * Implements RDTSC.
6956 */
6957IEM_CIMPL_DEF_0(iemCImpl_rdtscp)
6958{
6959 /*
6960 * Check preconditions.
6961 */
6962 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fRdTscP)
6963 return iemRaiseUndefinedOpcode(pVCpu);
6964
6965 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6966 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_RDTSCP))
6967 {
6968 Log(("rdtscp: Not enabled for VMX non-root mode -> #UD\n"));
6969 return iemRaiseUndefinedOpcode(pVCpu);
6970 }
6971
6972 if (pVCpu->iem.s.uCpl != 0)
6973 {
6974 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6975 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_TSD)
6976 {
6977 Log(("rdtscp: CR4.TSD and CPL=%u -> #GP(0)\n", pVCpu->iem.s.uCpl));
6978 return iemRaiseGeneralProtectionFault0(pVCpu);
6979 }
6980 }
6981
6982 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
6983 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDTSC_EXIT))
6984 {
6985 Log(("rdtscp: Guest intercept -> VM-exit\n"));
6986 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDTSCP, cbInstr);
6987 }
6988 else if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
6989 {
6990 Log(("rdtscp: Guest intercept -> #VMEXIT\n"));
6991 IEM_SVM_UPDATE_NRIP(pVCpu);
6992 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDTSCP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
6993 }
6994
6995 /*
6996 * Do the job.
6997 * Query the MSR first in case of trips to ring-3.
6998 */
6999 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
7000 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pVCpu->cpum.GstCtx.rcx);
7001 if (rcStrict == VINF_SUCCESS)
7002 {
7003 /* Low dword of the TSC_AUX msr only. */
7004 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7005
7006 uint64_t uTicks = TMCpuTickGet(pVCpu);
7007#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
7008 uTicks = CPUMApplyNestedGuestTscOffset(pVCpu, uTicks);
7009#endif
7010 pVCpu->cpum.GstCtx.rax = RT_LO_U32(uTicks);
7011 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(uTicks);
7012 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX); /* For IEMExecDecodedRdtscp. */
7013 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7014 }
7015 return rcStrict;
7016}
7017
7018
7019/**
7020 * Implements RDPMC.
7021 */
7022IEM_CIMPL_DEF_0(iemCImpl_rdpmc)
7023{
7024 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
7025
7026 if ( pVCpu->iem.s.uCpl != 0
7027 && !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCE))
7028 return iemRaiseGeneralProtectionFault0(pVCpu);
7029
7030 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7031 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_RDPMC_EXIT))
7032 {
7033 Log(("rdpmc: Guest intercept -> VM-exit\n"));
7034 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDPMC, cbInstr);
7035 }
7036
7037 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
7038 {
7039 Log(("rdpmc: Guest intercept -> #VMEXIT\n"));
7040 IEM_SVM_UPDATE_NRIP(pVCpu);
7041 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_RDPMC, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7042 }
7043
7044 /** @todo Emulate performance counters, for now just return 0. */
7045 pVCpu->cpum.GstCtx.rax = 0;
7046 pVCpu->cpum.GstCtx.rdx = 0;
7047 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7048 /** @todo We should trigger a \#GP here if the CPU doesn't support the index in
7049 * ecx but see @bugref{3472}! */
7050
7051 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7052 return VINF_SUCCESS;
7053}
7054
7055
7056/**
7057 * Implements RDMSR.
7058 */
7059IEM_CIMPL_DEF_0(iemCImpl_rdmsr)
7060{
7061 /*
7062 * Check preconditions.
7063 */
7064 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7065 return iemRaiseUndefinedOpcode(pVCpu);
7066 if (pVCpu->iem.s.uCpl != 0)
7067 return iemRaiseGeneralProtectionFault0(pVCpu);
7068
7069 /*
7070 * Check nested-guest intercepts.
7071 */
7072#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7073 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7074 {
7075 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_RDMSR, pVCpu->cpum.GstCtx.ecx))
7076 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_RDMSR, cbInstr);
7077 }
7078#endif
7079
7080#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7081 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7082 {
7083 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, pVCpu->cpum.GstCtx.ecx, false /* fWrite */);
7084 if (rcStrict == VINF_SVM_VMEXIT)
7085 return VINF_SUCCESS;
7086 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7087 {
7088 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.ecx, VBOXSTRICTRC_VAL(rcStrict)));
7089 return rcStrict;
7090 }
7091 }
7092#endif
7093
7094 /*
7095 * Do the job.
7096 */
7097 RTUINT64U uValue;
7098 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7099 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7100
7101 VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pVCpu->cpum.GstCtx.ecx, &uValue.u);
7102 if (rcStrict == VINF_SUCCESS)
7103 {
7104 pVCpu->cpum.GstCtx.rax = uValue.s.Lo;
7105 pVCpu->cpum.GstCtx.rdx = uValue.s.Hi;
7106 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
7107
7108 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7109 return VINF_SUCCESS;
7110 }
7111
7112#ifndef IN_RING3
7113 /* Deferred to ring-3. */
7114 if (rcStrict == VINF_CPUM_R3_MSR_READ)
7115 {
7116 Log(("IEM: rdmsr(%#x) -> ring-3\n", pVCpu->cpum.GstCtx.ecx));
7117 return rcStrict;
7118 }
7119#endif
7120
7121 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7122 if (pVCpu->iem.s.cLogRelRdMsr < 32)
7123 {
7124 pVCpu->iem.s.cLogRelRdMsr++;
7125 LogRel(("IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7126 }
7127 else
7128 Log(( "IEM: rdmsr(%#x) -> #GP(0)\n", pVCpu->cpum.GstCtx.ecx));
7129 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7130 return iemRaiseGeneralProtectionFault0(pVCpu);
7131}
7132
7133
7134/**
7135 * Implements WRMSR.
7136 */
7137IEM_CIMPL_DEF_0(iemCImpl_wrmsr)
7138{
7139 /*
7140 * Check preconditions.
7141 */
7142 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMsr)
7143 return iemRaiseUndefinedOpcode(pVCpu);
7144 if (pVCpu->iem.s.uCpl != 0)
7145 return iemRaiseGeneralProtectionFault0(pVCpu);
7146
7147 RTUINT64U uValue;
7148 uValue.s.Lo = pVCpu->cpum.GstCtx.eax;
7149 uValue.s.Hi = pVCpu->cpum.GstCtx.edx;
7150
7151 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
7152
7153 /** @todo make CPUMAllMsrs.cpp import the necessary MSR state. */
7154 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_ALL_MSRS);
7155
7156 /*
7157 * Check nested-guest intercepts.
7158 */
7159#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7160 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7161 {
7162 if (iemVmxIsRdmsrWrmsrInterceptSet(pVCpu, VMX_EXIT_WRMSR, idMsr))
7163 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_WRMSR, cbInstr);
7164 }
7165#endif
7166
7167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7168 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
7169 {
7170 VBOXSTRICTRC rcStrict = iemSvmHandleMsrIntercept(pVCpu, idMsr, true /* fWrite */);
7171 if (rcStrict == VINF_SVM_VMEXIT)
7172 return VINF_SUCCESS;
7173 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7174 {
7175 Log(("IEM: SVM intercepted rdmsr(%#x) failed. rc=%Rrc\n", idMsr, VBOXSTRICTRC_VAL(rcStrict)));
7176 return rcStrict;
7177 }
7178 }
7179#endif
7180
7181 /*
7182 * Do the job.
7183 */
7184 VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, idMsr, uValue.u);
7185 if (rcStrict == VINF_SUCCESS)
7186 {
7187 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7188 return VINF_SUCCESS;
7189 }
7190
7191#ifndef IN_RING3
7192 /* Deferred to ring-3. */
7193 if (rcStrict == VINF_CPUM_R3_MSR_WRITE)
7194 {
7195 Log(("IEM: wrmsr(%#x) -> ring-3\n", idMsr));
7196 return rcStrict;
7197 }
7198#endif
7199
7200 /* Often a unimplemented MSR or MSR bit, so worth logging. */
7201 if (pVCpu->iem.s.cLogRelWrMsr < 32)
7202 {
7203 pVCpu->iem.s.cLogRelWrMsr++;
7204 LogRel(("IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7205 }
7206 else
7207 Log(( "IEM: wrmsr(%#x,%#x`%08x) -> #GP(0)\n", idMsr, uValue.s.Hi, uValue.s.Lo));
7208 AssertMsgReturn(rcStrict == VERR_CPUM_RAISE_GP_0, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IPE_UNEXPECTED_STATUS);
7209 return iemRaiseGeneralProtectionFault0(pVCpu);
7210}
7211
7212
7213/**
7214 * Implements 'IN eAX, port'.
7215 *
7216 * @param u16Port The source port.
7217 * @param fImm Whether the port was specified through an immediate operand
7218 * or the implicit DX register.
7219 * @param cbReg The register size.
7220 */
7221IEM_CIMPL_DEF_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7222{
7223 /*
7224 * CPL check
7225 */
7226 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7227 if (rcStrict != VINF_SUCCESS)
7228 return rcStrict;
7229
7230 /*
7231 * Check VMX nested-guest IO intercept.
7232 */
7233#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7234 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7235 {
7236 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_IN, u16Port, fImm, cbReg, cbInstr);
7237 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7238 return rcStrict;
7239 }
7240#else
7241 RT_NOREF(fImm);
7242#endif
7243
7244 /*
7245 * Check SVM nested-guest IO intercept.
7246 */
7247#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7248 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7249 {
7250 uint8_t cAddrSizeBits;
7251 switch (pVCpu->iem.s.enmEffAddrMode)
7252 {
7253 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7254 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7255 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7256 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7257 }
7258 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_IN, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7259 false /* fRep */, false /* fStrIo */, cbInstr);
7260 if (rcStrict == VINF_SVM_VMEXIT)
7261 return VINF_SUCCESS;
7262 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7263 {
7264 Log(("iemCImpl_in: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7265 VBOXSTRICTRC_VAL(rcStrict)));
7266 return rcStrict;
7267 }
7268 }
7269#endif
7270
7271 /*
7272 * Perform the I/O.
7273 */
7274 uint32_t u32Value = 0;
7275 rcStrict = IOMIOPortRead(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, &u32Value, cbReg);
7276 if (IOM_SUCCESS(rcStrict))
7277 {
7278 switch (cbReg)
7279 {
7280 case 1: pVCpu->cpum.GstCtx.al = (uint8_t)u32Value; break;
7281 case 2: pVCpu->cpum.GstCtx.ax = (uint16_t)u32Value; break;
7282 case 4: pVCpu->cpum.GstCtx.rax = u32Value; break;
7283 default: AssertFailedReturn(VERR_IEM_IPE_3);
7284 }
7285 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7286 pVCpu->iem.s.cPotentialExits++;
7287 if (rcStrict != VINF_SUCCESS)
7288 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7289 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7290
7291 /*
7292 * Check for I/O breakpoints.
7293 */
7294 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7295 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7296 && X86_DR7_ANY_RW_IO(uDr7)
7297 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7298 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7299 {
7300 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7301 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7302 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7303 rcStrict = iemRaiseDebugException(pVCpu);
7304 }
7305 }
7306
7307 return rcStrict;
7308}
7309
7310
7311/**
7312 * Implements 'IN eAX, DX'.
7313 *
7314 * @param cbReg The register size.
7315 */
7316IEM_CIMPL_DEF_1(iemCImpl_in_eAX_DX, uint8_t, cbReg)
7317{
7318 return IEM_CIMPL_CALL_3(iemCImpl_in, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7319}
7320
7321
7322/**
7323 * Implements 'OUT port, eAX'.
7324 *
7325 * @param u16Port The destination port.
7326 * @param fImm Whether the port was specified through an immediate operand
7327 * or the implicit DX register.
7328 * @param cbReg The register size.
7329 */
7330IEM_CIMPL_DEF_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg)
7331{
7332 /*
7333 * CPL check
7334 */
7335 VBOXSTRICTRC rcStrict = iemHlpCheckPortIOPermission(pVCpu, u16Port, cbReg);
7336 if (rcStrict != VINF_SUCCESS)
7337 return rcStrict;
7338
7339 /*
7340 * Check VMX nested-guest I/O intercept.
7341 */
7342#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7343 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7344 {
7345 rcStrict = iemVmxVmexitInstrIo(pVCpu, VMXINSTRID_IO_OUT, u16Port, fImm, cbReg, cbInstr);
7346 if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
7347 return rcStrict;
7348 }
7349#else
7350 RT_NOREF(fImm);
7351#endif
7352
7353 /*
7354 * Check SVM nested-guest I/O intercept.
7355 */
7356#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7357 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
7358 {
7359 uint8_t cAddrSizeBits;
7360 switch (pVCpu->iem.s.enmEffAddrMode)
7361 {
7362 case IEMMODE_16BIT: cAddrSizeBits = 16; break;
7363 case IEMMODE_32BIT: cAddrSizeBits = 32; break;
7364 case IEMMODE_64BIT: cAddrSizeBits = 64; break;
7365 IEM_NOT_REACHED_DEFAULT_CASE_RET();
7366 }
7367 rcStrict = iemSvmHandleIOIntercept(pVCpu, u16Port, SVMIOIOTYPE_OUT, cbReg, cAddrSizeBits, 0 /* N/A - iEffSeg */,
7368 false /* fRep */, false /* fStrIo */, cbInstr);
7369 if (rcStrict == VINF_SVM_VMEXIT)
7370 return VINF_SUCCESS;
7371 if (rcStrict != VINF_SVM_INTERCEPT_NOT_ACTIVE)
7372 {
7373 Log(("iemCImpl_out: iemSvmHandleIOIntercept failed (u16Port=%#x, cbReg=%u) rc=%Rrc\n", u16Port, cbReg,
7374 VBOXSTRICTRC_VAL(rcStrict)));
7375 return rcStrict;
7376 }
7377 }
7378#endif
7379
7380 /*
7381 * Perform the I/O.
7382 */
7383 uint32_t u32Value;
7384 switch (cbReg)
7385 {
7386 case 1: u32Value = pVCpu->cpum.GstCtx.al; break;
7387 case 2: u32Value = pVCpu->cpum.GstCtx.ax; break;
7388 case 4: u32Value = pVCpu->cpum.GstCtx.eax; break;
7389 default: AssertFailedReturn(VERR_IEM_IPE_4);
7390 }
7391 rcStrict = IOMIOPortWrite(pVCpu->CTX_SUFF(pVM), pVCpu, u16Port, u32Value, cbReg);
7392 if (IOM_SUCCESS(rcStrict))
7393 {
7394 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7395 pVCpu->iem.s.cPotentialExits++;
7396 if (rcStrict != VINF_SUCCESS)
7397 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
7398 Assert(rcStrict == VINF_SUCCESS); /* assumed below */
7399
7400 /*
7401 * Check for I/O breakpoints.
7402 */
7403 uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
7404 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7405 && X86_DR7_ANY_RW_IO(uDr7)
7406 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
7407 || DBGFBpIsHwIoArmed(pVCpu->CTX_SUFF(pVM))))
7408 {
7409 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
7410 rcStrict = DBGFBpCheckIo(pVCpu->CTX_SUFF(pVM), pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
7411 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
7412 rcStrict = iemRaiseDebugException(pVCpu);
7413 }
7414 }
7415 return rcStrict;
7416}
7417
7418
7419/**
7420 * Implements 'OUT DX, eAX'.
7421 *
7422 * @param cbReg The register size.
7423 */
7424IEM_CIMPL_DEF_1(iemCImpl_out_DX_eAX, uint8_t, cbReg)
7425{
7426 return IEM_CIMPL_CALL_3(iemCImpl_out, pVCpu->cpum.GstCtx.dx, false /* fImm */, cbReg);
7427}
7428
7429
7430/**
7431 * Implements 'CLI'.
7432 */
7433IEM_CIMPL_DEF_0(iemCImpl_cli)
7434{
7435 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7436 uint32_t const fEflOld = fEfl;
7437
7438 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7439 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7440 {
7441 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7442 if (!(fEfl & X86_EFL_VM))
7443 {
7444 if (pVCpu->iem.s.uCpl <= uIopl)
7445 fEfl &= ~X86_EFL_IF;
7446 else if ( pVCpu->iem.s.uCpl == 3
7447 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI) )
7448 fEfl &= ~X86_EFL_VIF;
7449 else
7450 return iemRaiseGeneralProtectionFault0(pVCpu);
7451 }
7452 /* V8086 */
7453 else if (uIopl == 3)
7454 fEfl &= ~X86_EFL_IF;
7455 else if ( uIopl < 3
7456 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME) )
7457 fEfl &= ~X86_EFL_VIF;
7458 else
7459 return iemRaiseGeneralProtectionFault0(pVCpu);
7460 }
7461 /* real mode */
7462 else
7463 fEfl &= ~X86_EFL_IF;
7464
7465 /* Commit. */
7466 IEMMISC_SET_EFL(pVCpu, fEfl);
7467 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7468 Log2(("CLI: %#x -> %#x\n", fEflOld, fEfl)); NOREF(fEflOld);
7469 return VINF_SUCCESS;
7470}
7471
7472
7473/**
7474 * Implements 'STI'.
7475 */
7476IEM_CIMPL_DEF_0(iemCImpl_sti)
7477{
7478 uint32_t fEfl = IEMMISC_GET_EFL(pVCpu);
7479 uint32_t const fEflOld = fEfl;
7480
7481 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4);
7482 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
7483 {
7484 uint8_t const uIopl = X86_EFL_GET_IOPL(fEfl);
7485 if (!(fEfl & X86_EFL_VM))
7486 {
7487 if (pVCpu->iem.s.uCpl <= uIopl)
7488 fEfl |= X86_EFL_IF;
7489 else if ( pVCpu->iem.s.uCpl == 3
7490 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PVI)
7491 && !(fEfl & X86_EFL_VIP) )
7492 fEfl |= X86_EFL_VIF;
7493 else
7494 return iemRaiseGeneralProtectionFault0(pVCpu);
7495 }
7496 /* V8086 */
7497 else if (uIopl == 3)
7498 fEfl |= X86_EFL_IF;
7499 else if ( uIopl < 3
7500 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VME)
7501 && !(fEfl & X86_EFL_VIP) )
7502 fEfl |= X86_EFL_VIF;
7503 else
7504 return iemRaiseGeneralProtectionFault0(pVCpu);
7505 }
7506 /* real mode */
7507 else
7508 fEfl |= X86_EFL_IF;
7509
7510 /* Commit. */
7511 IEMMISC_SET_EFL(pVCpu, fEfl);
7512 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7513 if (!(fEflOld & X86_EFL_IF) && (fEfl & X86_EFL_IF))
7514 CPUMSetInInterruptShadowSti(&pVCpu->cpum.GstCtx);
7515 Log2(("STI: %#x -> %#x\n", fEflOld, fEfl));
7516 return VINF_SUCCESS;
7517}
7518
7519
7520/**
7521 * Implements 'HLT'.
7522 */
7523IEM_CIMPL_DEF_0(iemCImpl_hlt)
7524{
7525 if (pVCpu->iem.s.uCpl != 0)
7526 return iemRaiseGeneralProtectionFault0(pVCpu);
7527
7528 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7529 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_HLT_EXIT))
7530 {
7531 Log2(("hlt: Guest intercept -> VM-exit\n"));
7532 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_HLT, cbInstr);
7533 }
7534
7535 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_HLT))
7536 {
7537 Log2(("hlt: Guest intercept -> #VMEXIT\n"));
7538 IEM_SVM_UPDATE_NRIP(pVCpu);
7539 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_HLT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7540 }
7541
7542 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7543 return VINF_EM_HALT;
7544}
7545
7546
7547/**
7548 * Implements 'MONITOR'.
7549 */
7550IEM_CIMPL_DEF_1(iemCImpl_monitor, uint8_t, iEffSeg)
7551{
7552 /*
7553 * Permission checks.
7554 */
7555 if (pVCpu->iem.s.uCpl != 0)
7556 {
7557 Log2(("monitor: CPL != 0\n"));
7558 return iemRaiseUndefinedOpcode(pVCpu); /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. */
7559 }
7560 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7561 {
7562 Log2(("monitor: Not in CPUID\n"));
7563 return iemRaiseUndefinedOpcode(pVCpu);
7564 }
7565
7566 /*
7567 * Check VMX guest-intercept.
7568 * This should be considered a fault-like VM-exit.
7569 * See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
7570 */
7571 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7572 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MONITOR_EXIT))
7573 {
7574 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7575 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_MONITOR, cbInstr);
7576 }
7577
7578 /*
7579 * Gather the operands and validate them.
7580 */
7581 RTGCPTR GCPtrMem = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
7582 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
7583 uint32_t uEdx = pVCpu->cpum.GstCtx.edx;
7584/** @todo Test whether EAX or ECX is processed first, i.e. do we get \#PF or
7585 * \#GP first. */
7586 if (uEcx != 0)
7587 {
7588 Log2(("monitor rax=%RX64, ecx=%RX32, edx=%RX32; ECX != 0 -> #GP(0)\n", GCPtrMem, uEcx, uEdx)); NOREF(uEdx);
7589 return iemRaiseGeneralProtectionFault0(pVCpu);
7590 }
7591
7592 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrMem);
7593 if (rcStrict != VINF_SUCCESS)
7594 return rcStrict;
7595
7596 RTGCPHYS GCPhysMem;
7597 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrMem, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
7598 if (rcStrict != VINF_SUCCESS)
7599 return rcStrict;
7600
7601#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7602 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7603 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
7604 {
7605 /*
7606 * MONITOR does not access the memory, just monitors the address. However,
7607 * if the address falls in the APIC-access page, the address monitored must
7608 * instead be the corresponding address in the virtual-APIC page.
7609 *
7610 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
7611 */
7612 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
7613 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
7614 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
7615 return rcStrict;
7616 }
7617#endif
7618
7619 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
7620 {
7621 Log2(("monitor: Guest intercept -> #VMEXIT\n"));
7622 IEM_SVM_UPDATE_NRIP(pVCpu);
7623 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MONITOR, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7624 }
7625
7626 /*
7627 * Call EM to prepare the monitor/wait.
7628 */
7629 rcStrict = EMMonitorWaitPrepare(pVCpu, pVCpu->cpum.GstCtx.rax, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.rdx, GCPhysMem);
7630 Assert(rcStrict == VINF_SUCCESS);
7631
7632 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7633 return rcStrict;
7634}
7635
7636
7637/**
7638 * Implements 'MWAIT'.
7639 */
7640IEM_CIMPL_DEF_0(iemCImpl_mwait)
7641{
7642 /*
7643 * Permission checks.
7644 */
7645 if (pVCpu->iem.s.uCpl != 0)
7646 {
7647 Log2(("mwait: CPL != 0\n"));
7648 /** @todo MSR[0xC0010015].MonMwaitUserEn if we care. (Remember to check
7649 * EFLAGS.VM then.) */
7650 return iemRaiseUndefinedOpcode(pVCpu);
7651 }
7652 if (!IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMonitorMWait)
7653 {
7654 Log2(("mwait: Not in CPUID\n"));
7655 return iemRaiseUndefinedOpcode(pVCpu);
7656 }
7657
7658 /* Check VMX nested-guest intercept. */
7659 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7660 && IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_MWAIT_EXIT))
7661 IEM_VMX_VMEXIT_MWAIT_RET(pVCpu, EMMonitorIsArmed(pVCpu), cbInstr);
7662
7663 /*
7664 * Gather the operands and validate them.
7665 */
7666 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7667 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7668 if (uEcx != 0)
7669 {
7670 /* Only supported extension is break on IRQ when IF=0. */
7671 if (uEcx > 1)
7672 {
7673 Log2(("mwait eax=%RX32, ecx=%RX32; ECX > 1 -> #GP(0)\n", uEax, uEcx));
7674 return iemRaiseGeneralProtectionFault0(pVCpu);
7675 }
7676 uint32_t fMWaitFeatures = 0;
7677 uint32_t uIgnore = 0;
7678 CPUMGetGuestCpuId(pVCpu, 5, 0, -1 /*f64BitMode*/, &uIgnore, &uIgnore, &fMWaitFeatures, &uIgnore);
7679 if ( (fMWaitFeatures & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7680 != (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
7681 {
7682 Log2(("mwait eax=%RX32, ecx=%RX32; break-on-IRQ-IF=0 extension not enabled -> #GP(0)\n", uEax, uEcx));
7683 return iemRaiseGeneralProtectionFault0(pVCpu);
7684 }
7685
7686#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7687 /*
7688 * If the interrupt-window exiting control is set or a virtual-interrupt is pending
7689 * for delivery; and interrupts are disabled the processor does not enter its
7690 * mwait state but rather passes control to the next instruction.
7691 *
7692 * See Intel spec. 25.3 "Changes to Instruction Behavior In VMX Non-root Operation".
7693 */
7694 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
7695 && !pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
7696 {
7697 if ( IEM_VMX_IS_PROCCTLS_SET(pVCpu, VMX_PROC_CTLS_INT_WINDOW_EXIT)
7698 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
7699 {
7700 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7701 return VINF_SUCCESS;
7702 }
7703 }
7704#endif
7705 }
7706
7707 /*
7708 * Check SVM nested-guest mwait intercepts.
7709 */
7710 if ( IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT_ARMED)
7711 && EMMonitorIsArmed(pVCpu))
7712 {
7713 Log2(("mwait: Guest intercept (monitor hardware armed) -> #VMEXIT\n"));
7714 IEM_SVM_UPDATE_NRIP(pVCpu);
7715 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT_ARMED, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7716 }
7717 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
7718 {
7719 Log2(("mwait: Guest intercept -> #VMEXIT\n"));
7720 IEM_SVM_UPDATE_NRIP(pVCpu);
7721 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_MWAIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7722 }
7723
7724 /*
7725 * Call EM to prepare the monitor/wait.
7726 */
7727 VBOXSTRICTRC rcStrict = EMMonitorWaitPerform(pVCpu, uEax, uEcx);
7728
7729 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7730 return rcStrict;
7731}
7732
7733
7734/**
7735 * Implements 'SWAPGS'.
7736 */
7737IEM_CIMPL_DEF_0(iemCImpl_swapgs)
7738{
7739 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT); /* Caller checks this. */
7740
7741 /*
7742 * Permission checks.
7743 */
7744 if (pVCpu->iem.s.uCpl != 0)
7745 {
7746 Log2(("swapgs: CPL != 0\n"));
7747 return iemRaiseUndefinedOpcode(pVCpu);
7748 }
7749
7750 /*
7751 * Do the job.
7752 */
7753 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_GS);
7754 uint64_t uOtherGsBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
7755 pVCpu->cpum.GstCtx.msrKERNELGSBASE = pVCpu->cpum.GstCtx.gs.u64Base;
7756 pVCpu->cpum.GstCtx.gs.u64Base = uOtherGsBase;
7757
7758 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7759 return VINF_SUCCESS;
7760}
7761
7762
7763#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7764/**
7765 * Handles a CPUID call.
7766 */
7767static VBOXSTRICTRC iemCpuIdVBoxCall(PVMCPUCC pVCpu, uint32_t iFunction,
7768 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
7769{
7770 switch (iFunction)
7771 {
7772 case VBOX_CPUID_FN_ID:
7773 LogFlow(("iemCpuIdVBoxCall: VBOX_CPUID_FN_ID\n"));
7774 *pEax = VBOX_CPUID_RESP_ID_EAX;
7775 *pEbx = VBOX_CPUID_RESP_ID_EBX;
7776 *pEcx = VBOX_CPUID_RESP_ID_ECX;
7777 *pEdx = VBOX_CPUID_RESP_ID_EDX;
7778 break;
7779
7780 case VBOX_CPUID_FN_LOG:
7781 {
7782 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX | CPUMCTX_EXTRN_RSI
7783 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
7784
7785 /* Validate input. */
7786 uint32_t cchToLog = *pEdx;
7787 if (cchToLog <= _2M)
7788 {
7789 uint32_t const uLogPicker = *pEbx;
7790 if (uLogPicker <= 1)
7791 {
7792 /* Resolve the logger. */
7793 PRTLOGGER const pLogger = !uLogPicker
7794 ? RTLogDefaultInstanceEx(UINT32_MAX) : RTLogRelGetDefaultInstanceEx(UINT32_MAX);
7795 if (pLogger)
7796 {
7797 /* Copy over the data: */
7798 RTGCPTR GCPtrSrc = pVCpu->cpum.GstCtx.rsi;
7799 while (cchToLog > 0)
7800 {
7801 uint32_t cbToMap = GUEST_PAGE_SIZE - (GCPtrSrc & GUEST_PAGE_OFFSET_MASK);
7802 if (cbToMap > cchToLog)
7803 cbToMap = cchToLog;
7804 /** @todo Extend iemMemMap to allowing page size accessing and avoid 7
7805 * unnecessary calls & iterations per pages. */
7806 if (cbToMap > 512)
7807 cbToMap = 512;
7808 void *pvSrc = NULL;
7809 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvSrc, cbToMap, UINT8_MAX, GCPtrSrc, IEM_ACCESS_DATA_R, 0);
7810 if (rcStrict == VINF_SUCCESS)
7811 {
7812 RTLogBulkNestedWrite(pLogger, (const char *)pvSrc, cbToMap, "Gst:");
7813 rcStrict = iemMemCommitAndUnmap(pVCpu, pvSrc, IEM_ACCESS_DATA_R);
7814 AssertRCSuccessReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7815 }
7816 else
7817 {
7818 Log(("iemCpuIdVBoxCall: %Rrc at %RGp LB %#x\n", VBOXSTRICTRC_VAL(rcStrict), GCPtrSrc, cbToMap));
7819 return rcStrict;
7820 }
7821
7822 /* Advance. */
7823 pVCpu->cpum.GstCtx.rsi = GCPtrSrc += cbToMap;
7824 *pEdx = cchToLog -= cbToMap;
7825 }
7826 *pEax = VINF_SUCCESS;
7827 }
7828 else
7829 *pEax = (uint32_t)VERR_NOT_FOUND;
7830 }
7831 else
7832 *pEax = (uint32_t)VERR_NOT_FOUND;
7833 }
7834 else
7835 *pEax = (uint32_t)VERR_TOO_MUCH_DATA;
7836 *pEdx = VBOX_CPUID_RESP_GEN_EDX;
7837 *pEcx = VBOX_CPUID_RESP_GEN_ECX;
7838 *pEbx = VBOX_CPUID_RESP_GEN_EBX;
7839 break;
7840 }
7841
7842 default:
7843 LogFlow(("iemCpuIdVBoxCall: Invalid function %#x (%#x, %#x)\n", iFunction, *pEbx, *pEdx));
7844 *pEax = (uint32_t)VERR_INVALID_FUNCTION;
7845 *pEbx = (uint32_t)VERR_INVALID_FUNCTION;
7846 *pEcx = (uint32_t)VERR_INVALID_FUNCTION;
7847 *pEdx = (uint32_t)VERR_INVALID_FUNCTION;
7848 break;
7849 }
7850 return VINF_SUCCESS;
7851}
7852#endif /* VBOX_WITHOUT_CPUID_HOST_CALL */
7853
7854/**
7855 * Implements 'CPUID'.
7856 */
7857IEM_CIMPL_DEF_0(iemCImpl_cpuid)
7858{
7859 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
7860 {
7861 Log2(("cpuid: Guest intercept -> VM-exit\n"));
7862 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_CPUID, cbInstr);
7863 }
7864
7865 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
7866 {
7867 Log2(("cpuid: Guest intercept -> #VMEXIT\n"));
7868 IEM_SVM_UPDATE_NRIP(pVCpu);
7869 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_CPUID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
7870 }
7871
7872
7873 uint32_t const uEax = pVCpu->cpum.GstCtx.eax;
7874 uint32_t const uEcx = pVCpu->cpum.GstCtx.ecx;
7875
7876#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
7877 /*
7878 * CPUID host call backdoor.
7879 */
7880 if ( uEax == VBOX_CPUID_REQ_EAX_FIXED
7881 && (uEcx & VBOX_CPUID_REQ_ECX_FIXED_MASK) == VBOX_CPUID_REQ_ECX_FIXED
7882 && pVCpu->CTX_SUFF(pVM)->iem.s.fCpuIdHostCall)
7883 {
7884 VBOXSTRICTRC rcStrict = iemCpuIdVBoxCall(pVCpu, uEcx & VBOX_CPUID_REQ_ECX_FN_MASK,
7885 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx,
7886 &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7887 if (rcStrict != VINF_SUCCESS)
7888 return rcStrict;
7889 }
7890 /*
7891 * Regular CPUID.
7892 */
7893 else
7894#endif
7895 CPUMGetGuestCpuId(pVCpu, uEax, uEcx, pVCpu->cpum.GstCtx.cs.Attr.n.u1Long,
7896 &pVCpu->cpum.GstCtx.eax, &pVCpu->cpum.GstCtx.ebx, &pVCpu->cpum.GstCtx.ecx, &pVCpu->cpum.GstCtx.edx);
7897
7898 pVCpu->cpum.GstCtx.rax &= UINT32_C(0xffffffff);
7899 pVCpu->cpum.GstCtx.rbx &= UINT32_C(0xffffffff);
7900 pVCpu->cpum.GstCtx.rcx &= UINT32_C(0xffffffff);
7901 pVCpu->cpum.GstCtx.rdx &= UINT32_C(0xffffffff);
7902 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RBX);
7903
7904 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7905 pVCpu->iem.s.cPotentialExits++;
7906 return VINF_SUCCESS;
7907}
7908
7909
7910/**
7911 * Implements 'AAD'.
7912 *
7913 * @param bImm The immediate operand.
7914 */
7915IEM_CIMPL_DEF_1(iemCImpl_aad, uint8_t, bImm)
7916{
7917 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7918 uint8_t const al = (uint8_t)ax + (uint8_t)(ax >> 8) * bImm;
7919 pVCpu->cpum.GstCtx.ax = al;
7920 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7921 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7922 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7923
7924 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7925 return VINF_SUCCESS;
7926}
7927
7928
7929/**
7930 * Implements 'AAM'.
7931 *
7932 * @param bImm The immediate operand. Cannot be 0.
7933 */
7934IEM_CIMPL_DEF_1(iemCImpl_aam, uint8_t, bImm)
7935{
7936 Assert(bImm != 0); /* #DE on 0 is handled in the decoder. */
7937
7938 uint16_t const ax = pVCpu->cpum.GstCtx.ax;
7939 uint8_t const al = (uint8_t)ax % bImm;
7940 uint8_t const ah = (uint8_t)ax / bImm;
7941 pVCpu->cpum.GstCtx.ax = (ah << 8) + al;
7942 iemHlpUpdateArithEFlagsU8(pVCpu, al,
7943 X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF,
7944 X86_EFL_OF | X86_EFL_AF | X86_EFL_CF);
7945
7946 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7947 return VINF_SUCCESS;
7948}
7949
7950
7951/**
7952 * Implements 'DAA'.
7953 */
7954IEM_CIMPL_DEF_0(iemCImpl_daa)
7955{
7956 uint8_t const al = pVCpu->cpum.GstCtx.al;
7957 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7958
7959 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7960 || (al & 0xf) >= 10)
7961 {
7962 pVCpu->cpum.GstCtx.al = al + 6;
7963 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7964 }
7965 else
7966 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
7967
7968 if (al >= 0x9a || fCarry)
7969 {
7970 pVCpu->cpum.GstCtx.al += 0x60;
7971 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7972 }
7973 else
7974 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
7975
7976 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
7977 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
7978 return VINF_SUCCESS;
7979}
7980
7981
7982/**
7983 * Implements 'DAS'.
7984 */
7985IEM_CIMPL_DEF_0(iemCImpl_das)
7986{
7987 uint8_t const uInputAL = pVCpu->cpum.GstCtx.al;
7988 bool const fCarry = pVCpu->cpum.GstCtx.eflags.Bits.u1CF;
7989
7990 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
7991 || (uInputAL & 0xf) >= 10)
7992 {
7993 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
7994 if (uInputAL < 6)
7995 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
7996 pVCpu->cpum.GstCtx.al = uInputAL - 6;
7997 }
7998 else
7999 {
8000 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8001 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8002 }
8003
8004 if (uInputAL >= 0x9a || fCarry)
8005 {
8006 pVCpu->cpum.GstCtx.al -= 0x60;
8007 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8008 }
8009
8010 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8011 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8012 return VINF_SUCCESS;
8013}
8014
8015
8016/**
8017 * Implements 'AAA'.
8018 */
8019IEM_CIMPL_DEF_0(iemCImpl_aaa)
8020{
8021 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8022 {
8023 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8024 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8025 {
8026 iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth);
8027 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8028 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8029 }
8030 else
8031 {
8032 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8033 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8034 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8035 }
8036 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8037 }
8038 else
8039 {
8040 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8041 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8042 {
8043 pVCpu->cpum.GstCtx.ax += UINT16_C(0x106);
8044 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8045 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8046 }
8047 else
8048 {
8049 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8050 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8051 }
8052 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8053 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8054 }
8055
8056 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8057 return VINF_SUCCESS;
8058}
8059
8060
8061/**
8062 * Implements 'AAS'.
8063 */
8064IEM_CIMPL_DEF_0(iemCImpl_aas)
8065{
8066 if (IEM_IS_GUEST_CPU_AMD(pVCpu))
8067 {
8068 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8069 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8070 {
8071 iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth);
8072 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8073 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8074 }
8075 else
8076 {
8077 iemHlpUpdateArithEFlagsU16(pVCpu, pVCpu->cpum.GstCtx.ax, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8078 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8079 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8080 }
8081 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8082 }
8083 else
8084 {
8085 if ( pVCpu->cpum.GstCtx.eflags.Bits.u1AF
8086 || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
8087 {
8088 pVCpu->cpum.GstCtx.ax -= UINT16_C(0x106);
8089 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
8090 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
8091 }
8092 else
8093 {
8094 pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 0;
8095 pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 0;
8096 }
8097 pVCpu->cpum.GstCtx.ax &= UINT16_C(0xff0f);
8098 iemHlpUpdateArithEFlagsU8(pVCpu, pVCpu->cpum.GstCtx.al, X86_EFL_SF | X86_EFL_ZF | X86_EFL_PF, X86_EFL_OF);
8099 }
8100
8101 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8102 return VINF_SUCCESS;
8103}
8104
8105
8106/**
8107 * Implements the 16-bit version of 'BOUND'.
8108 *
8109 * @note We have separate 16-bit and 32-bit variants of this function due to
8110 * the decoder using unsigned parameters, whereas we want signed one to
8111 * do the job. This is significant for a recompiler.
8112 */
8113IEM_CIMPL_DEF_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound)
8114{
8115 /*
8116 * Check if the index is inside the bounds, otherwise raise #BR.
8117 */
8118 if ( idxArray >= idxLowerBound
8119 && idxArray <= idxUpperBound)
8120 {
8121 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8122 return VINF_SUCCESS;
8123 }
8124
8125 return iemRaiseBoundRangeExceeded(pVCpu);
8126}
8127
8128
8129/**
8130 * Implements the 32-bit version of 'BOUND'.
8131 */
8132IEM_CIMPL_DEF_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound)
8133{
8134 /*
8135 * Check if the index is inside the bounds, otherwise raise #BR.
8136 */
8137 if ( idxArray >= idxLowerBound
8138 && idxArray <= idxUpperBound)
8139 {
8140 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8141 return VINF_SUCCESS;
8142 }
8143
8144 return iemRaiseBoundRangeExceeded(pVCpu);
8145}
8146
8147
8148
8149/*
8150 * Instantiate the various string operation combinations.
8151 */
8152#define OP_SIZE 8
8153#define ADDR_SIZE 16
8154#include "IEMAllCImplStrInstr.cpp.h"
8155#define OP_SIZE 8
8156#define ADDR_SIZE 32
8157#include "IEMAllCImplStrInstr.cpp.h"
8158#define OP_SIZE 8
8159#define ADDR_SIZE 64
8160#include "IEMAllCImplStrInstr.cpp.h"
8161
8162#define OP_SIZE 16
8163#define ADDR_SIZE 16
8164#include "IEMAllCImplStrInstr.cpp.h"
8165#define OP_SIZE 16
8166#define ADDR_SIZE 32
8167#include "IEMAllCImplStrInstr.cpp.h"
8168#define OP_SIZE 16
8169#define ADDR_SIZE 64
8170#include "IEMAllCImplStrInstr.cpp.h"
8171
8172#define OP_SIZE 32
8173#define ADDR_SIZE 16
8174#include "IEMAllCImplStrInstr.cpp.h"
8175#define OP_SIZE 32
8176#define ADDR_SIZE 32
8177#include "IEMAllCImplStrInstr.cpp.h"
8178#define OP_SIZE 32
8179#define ADDR_SIZE 64
8180#include "IEMAllCImplStrInstr.cpp.h"
8181
8182#define OP_SIZE 64
8183#define ADDR_SIZE 32
8184#include "IEMAllCImplStrInstr.cpp.h"
8185#define OP_SIZE 64
8186#define ADDR_SIZE 64
8187#include "IEMAllCImplStrInstr.cpp.h"
8188
8189
8190/**
8191 * Implements 'XGETBV'.
8192 */
8193IEM_CIMPL_DEF_0(iemCImpl_xgetbv)
8194{
8195 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
8196 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8197 {
8198 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8199 switch (uEcx)
8200 {
8201 case 0:
8202 break;
8203
8204 case 1: /** @todo Implement XCR1 support. */
8205 default:
8206 Log(("xgetbv ecx=%RX32 -> #GP(0)\n", uEcx));
8207 return iemRaiseGeneralProtectionFault0(pVCpu);
8208
8209 }
8210 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8211 pVCpu->cpum.GstCtx.rax = RT_LO_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8212 pVCpu->cpum.GstCtx.rdx = RT_HI_U32(pVCpu->cpum.GstCtx.aXcr[uEcx]);
8213
8214 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8215 return VINF_SUCCESS;
8216 }
8217 Log(("xgetbv CR4.OSXSAVE=0 -> UD\n"));
8218 return iemRaiseUndefinedOpcode(pVCpu);
8219}
8220
8221
8222/**
8223 * Implements 'XSETBV'.
8224 */
8225IEM_CIMPL_DEF_0(iemCImpl_xsetbv)
8226{
8227 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)
8228 {
8229 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
8230 {
8231 Log2(("xsetbv: Guest intercept -> #VMEXIT\n"));
8232 IEM_SVM_UPDATE_NRIP(pVCpu);
8233 IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_XSETBV, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
8234 }
8235
8236 if (pVCpu->iem.s.uCpl == 0)
8237 {
8238 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_XCRx);
8239
8240 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
8241 IEM_VMX_VMEXIT_INSTR_RET(pVCpu, VMX_EXIT_XSETBV, cbInstr);
8242
8243 uint32_t uEcx = pVCpu->cpum.GstCtx.ecx;
8244 uint64_t uNewValue = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx);
8245 switch (uEcx)
8246 {
8247 case 0:
8248 {
8249 int rc = CPUMSetGuestXcr0(pVCpu, uNewValue);
8250 if (rc == VINF_SUCCESS)
8251 break;
8252 Assert(rc == VERR_CPUM_RAISE_GP_0);
8253 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8254 return iemRaiseGeneralProtectionFault0(pVCpu);
8255 }
8256
8257 case 1: /** @todo Implement XCR1 support. */
8258 default:
8259 Log(("xsetbv ecx=%RX32 (newvalue=%RX64) -> #GP(0)\n", uEcx, uNewValue));
8260 return iemRaiseGeneralProtectionFault0(pVCpu);
8261
8262 }
8263
8264 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8265 return VINF_SUCCESS;
8266 }
8267
8268 Log(("xsetbv cpl=%u -> GP(0)\n", pVCpu->iem.s.uCpl));
8269 return iemRaiseGeneralProtectionFault0(pVCpu);
8270 }
8271 Log(("xsetbv CR4.OSXSAVE=0 -> UD\n"));
8272 return iemRaiseUndefinedOpcode(pVCpu);
8273}
8274
8275#ifndef RT_ARCH_ARM64
8276# ifdef IN_RING3
8277
8278/** Argument package for iemCImpl_cmpxchg16b_fallback_rendezvous_callback. */
8279struct IEMCIMPLCX16ARGS
8280{
8281 PRTUINT128U pu128Dst;
8282 PRTUINT128U pu128RaxRdx;
8283 PRTUINT128U pu128RbxRcx;
8284 uint32_t *pEFlags;
8285# ifdef VBOX_STRICT
8286 uint32_t cCalls;
8287# endif
8288};
8289
8290/**
8291 * @callback_method_impl{FNVMMEMTRENDEZVOUS,
8292 * Worker for iemCImpl_cmpxchg16b_fallback_rendezvous}
8293 */
8294static DECLCALLBACK(VBOXSTRICTRC) iemCImpl_cmpxchg16b_fallback_rendezvous_callback(PVM pVM, PVMCPUCC pVCpu, void *pvUser)
8295{
8296 RT_NOREF(pVM, pVCpu);
8297 struct IEMCIMPLCX16ARGS *pArgs = (struct IEMCIMPLCX16ARGS *)pvUser;
8298# ifdef VBOX_STRICT
8299 Assert(pArgs->cCalls == 0);
8300 pArgs->cCalls++;
8301# endif
8302
8303 iemAImpl_cmpxchg16b_fallback(pArgs->pu128Dst, pArgs->pu128RaxRdx, pArgs->pu128RbxRcx, pArgs->pEFlags);
8304 return VINF_SUCCESS;
8305}
8306
8307# endif /* IN_RING3 */
8308
8309/**
8310 * Implements 'CMPXCHG16B' fallback using rendezvous.
8311 */
8312IEM_CIMPL_DEF_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
8313 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags)
8314{
8315# ifdef IN_RING3
8316 struct IEMCIMPLCX16ARGS Args;
8317 Args.pu128Dst = pu128Dst;
8318 Args.pu128RaxRdx = pu128RaxRdx;
8319 Args.pu128RbxRcx = pu128RbxRcx;
8320 Args.pEFlags = pEFlags;
8321# ifdef VBOX_STRICT
8322 Args.cCalls = 0;
8323# endif
8324 VBOXSTRICTRC rcStrict = VMMR3EmtRendezvous(pVCpu->CTX_SUFF(pVM), VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE,
8325 iemCImpl_cmpxchg16b_fallback_rendezvous_callback, &Args);
8326 Assert(Args.cCalls == 1);
8327 if (rcStrict == VINF_SUCCESS)
8328 {
8329 /* Duplicated tail code. */
8330 rcStrict = iemMemCommitAndUnmap(pVCpu, pu128Dst, IEM_ACCESS_DATA_RW);
8331 if (rcStrict == VINF_SUCCESS)
8332 {
8333 pVCpu->cpum.GstCtx.eflags.u = *pEFlags; /* IEM_MC_COMMIT_EFLAGS */
8334 if (!(*pEFlags & X86_EFL_ZF))
8335 {
8336 pVCpu->cpum.GstCtx.rax = pu128RaxRdx->s.Lo;
8337 pVCpu->cpum.GstCtx.rdx = pu128RaxRdx->s.Hi;
8338 }
8339 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8340 }
8341 }
8342 return rcStrict;
8343# else
8344 RT_NOREF(pVCpu, cbInstr, pu128Dst, pu128RaxRdx, pu128RbxRcx, pEFlags);
8345 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; /* This should get us to ring-3 for now. Should perhaps be replaced later. */
8346# endif
8347}
8348
8349#endif /* RT_ARCH_ARM64 */
8350
8351/**
8352 * Implements 'CLFLUSH' and 'CLFLUSHOPT'.
8353 *
8354 * This is implemented in C because it triggers a load like behaviour without
8355 * actually reading anything. Since that's not so common, it's implemented
8356 * here.
8357 *
8358 * @param iEffSeg The effective segment.
8359 * @param GCPtrEff The address of the image.
8360 */
8361IEM_CIMPL_DEF_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
8362{
8363 /*
8364 * Pretend to do a load w/o reading (see also iemCImpl_monitor and iemMemMap).
8365 */
8366 VBOXSTRICTRC rcStrict = iemMemApplySegment(pVCpu, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, iEffSeg, 1, &GCPtrEff);
8367 if (rcStrict == VINF_SUCCESS)
8368 {
8369 RTGCPHYS GCPhysMem;
8370 rcStrict = iemMemPageTranslateAndCheckAccess(pVCpu, GCPtrEff, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA, &GCPhysMem);
8371 if (rcStrict == VINF_SUCCESS)
8372 {
8373#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8374 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8375 && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
8376 {
8377 /*
8378 * CLFLUSH/CLFLUSHOPT does not access the memory, but flushes the cache-line
8379 * that contains the address. However, if the address falls in the APIC-access
8380 * page, the address flushed must instead be the corresponding address in the
8381 * virtual-APIC page.
8382 *
8383 * See Intel spec. 29.4.4 "Instruction-Specific Considerations".
8384 */
8385 rcStrict = iemVmxVirtApicAccessUnused(pVCpu, &GCPhysMem, 1, IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA);
8386 if ( rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE
8387 && rcStrict != VINF_VMX_MODIFIES_BEHAVIOR)
8388 return rcStrict;
8389 }
8390#endif
8391 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8392 return VINF_SUCCESS;
8393 }
8394 }
8395
8396 return rcStrict;
8397}
8398
8399
8400/**
8401 * Implements 'FINIT' and 'FNINIT'.
8402 *
8403 * @param fCheckXcpts Whether to check for umasked pending exceptions or
8404 * not.
8405 */
8406IEM_CIMPL_DEF_1(iemCImpl_finit, bool, fCheckXcpts)
8407{
8408 /*
8409 * Exceptions.
8410 */
8411 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
8412 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
8413 return iemRaiseDeviceNotAvailable(pVCpu);
8414
8415 iemFpuActualizeStateForChange(pVCpu);
8416 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_X87);
8417
8418 /* FINIT: Raise #MF on pending exception(s): */
8419 if (fCheckXcpts && (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))
8420 return iemRaiseMathFault(pVCpu);
8421
8422 /*
8423 * Reset the state.
8424 */
8425 PX86XSAVEAREA pXState = &pVCpu->cpum.GstCtx.XState;
8426
8427 /* Rotate the stack to account for changed TOS. */
8428 iemFpuRotateStackSetTop(&pXState->x87, 0);
8429
8430 pXState->x87.FCW = 0x37f;
8431 pXState->x87.FSW = 0;
8432 pXState->x87.FTW = 0x00; /* 0 - empty. */
8433 /** @todo Intel says the instruction and data pointers are not cleared on
8434 * 387, presume that 8087 and 287 doesn't do so either. */
8435 /** @todo test this stuff. */
8436 if (IEM_GET_TARGET_CPU(pVCpu) > IEMTARGETCPU_386)
8437 {
8438 pXState->x87.FPUDP = 0;
8439 pXState->x87.DS = 0; //??
8440 pXState->x87.Rsrvd2 = 0;
8441 pXState->x87.FPUIP = 0;
8442 pXState->x87.CS = 0; //??
8443 pXState->x87.Rsrvd1 = 0;
8444 }
8445 pXState->x87.FOP = 0;
8446
8447 iemHlpUsedFpu(pVCpu);
8448 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8449 return VINF_SUCCESS;
8450}
8451
8452
8453/**
8454 * Implements 'FXSAVE'.
8455 *
8456 * @param iEffSeg The effective segment.
8457 * @param GCPtrEff The address of the image.
8458 * @param enmEffOpSize The operand size (only REX.W really matters).
8459 */
8460IEM_CIMPL_DEF_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8461{
8462 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8463
8464 /*
8465 * Raise exceptions.
8466 */
8467 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8468 return iemRaiseDeviceNotAvailable(pVCpu);
8469
8470 /*
8471 * Access the memory.
8472 */
8473 void *pvMem512;
8474 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8475 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8476 if (rcStrict != VINF_SUCCESS)
8477 return rcStrict;
8478 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8479 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8480
8481 /*
8482 * Store the registers.
8483 */
8484 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8485 * implementation specific whether MXCSR and XMM0-XMM7 are saved. */
8486
8487 /* common for all formats */
8488 pDst->FCW = pSrc->FCW;
8489 pDst->FSW = pSrc->FSW;
8490 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8491 pDst->FOP = pSrc->FOP;
8492 pDst->MXCSR = pSrc->MXCSR;
8493 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8494 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8495 {
8496 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8497 * them for now... */
8498 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8499 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8500 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8501 pDst->aRegs[i].au32[3] = 0;
8502 }
8503
8504 /* FPU IP, CS, DP and DS. */
8505 pDst->FPUIP = pSrc->FPUIP;
8506 pDst->CS = pSrc->CS;
8507 pDst->FPUDP = pSrc->FPUDP;
8508 pDst->DS = pSrc->DS;
8509 if (enmEffOpSize == IEMMODE_64BIT)
8510 {
8511 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8512 pDst->Rsrvd1 = pSrc->Rsrvd1;
8513 pDst->Rsrvd2 = pSrc->Rsrvd2;
8514 }
8515 else
8516 {
8517 pDst->Rsrvd1 = 0;
8518 pDst->Rsrvd2 = 0;
8519 }
8520
8521 /* XMM registers. */
8522 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8523 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8524 || pVCpu->iem.s.uCpl != 0)
8525 {
8526 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8527 for (uint32_t i = 0; i < cXmmRegs; i++)
8528 pDst->aXMM[i] = pSrc->aXMM[i];
8529 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8530 * right? */
8531 }
8532
8533 /*
8534 * Commit the memory.
8535 */
8536 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8537 if (rcStrict != VINF_SUCCESS)
8538 return rcStrict;
8539
8540 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8541 return VINF_SUCCESS;
8542}
8543
8544
8545/**
8546 * Implements 'FXRSTOR'.
8547 *
8548 * @param iEffSeg The effective segment register for @a GCPtrEff.
8549 * @param GCPtrEff The address of the image.
8550 * @param enmEffOpSize The operand size (only REX.W really matters).
8551 */
8552IEM_CIMPL_DEF_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8553{
8554 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
8555
8556 /*
8557 * Raise exceptions.
8558 */
8559 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_TS | X86_CR0_EM))
8560 return iemRaiseDeviceNotAvailable(pVCpu);
8561
8562 /*
8563 * Access the memory.
8564 */
8565 void *pvMem512;
8566 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8567 15 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8568 if (rcStrict != VINF_SUCCESS)
8569 return rcStrict;
8570 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8571 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8572
8573 /*
8574 * Check the state for stuff which will #GP(0).
8575 */
8576 uint32_t const fMXCSR = pSrc->MXCSR;
8577 uint32_t const fMXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8578 if (fMXCSR & ~fMXCSR_MASK)
8579 {
8580 Log(("fxrstor: MXCSR=%#x (MXCSR_MASK=%#x) -> #GP(0)\n", fMXCSR, fMXCSR_MASK));
8581 return iemRaiseGeneralProtectionFault0(pVCpu);
8582 }
8583
8584 /*
8585 * Load the registers.
8586 */
8587 /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
8588 * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
8589
8590 /* common for all formats */
8591 pDst->FCW = pSrc->FCW;
8592 pDst->FSW = pSrc->FSW;
8593 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8594 pDst->FOP = pSrc->FOP;
8595 pDst->MXCSR = fMXCSR;
8596 /* (MXCSR_MASK is read-only) */
8597 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8598 {
8599 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8600 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8601 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8602 pDst->aRegs[i].au32[3] = 0;
8603 }
8604
8605 /* FPU IP, CS, DP and DS. */
8606 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
8607 {
8608 pDst->FPUIP = pSrc->FPUIP;
8609 pDst->CS = pSrc->CS;
8610 pDst->Rsrvd1 = pSrc->Rsrvd1;
8611 pDst->FPUDP = pSrc->FPUDP;
8612 pDst->DS = pSrc->DS;
8613 pDst->Rsrvd2 = pSrc->Rsrvd2;
8614 }
8615 else
8616 {
8617 pDst->FPUIP = pSrc->FPUIP;
8618 pDst->CS = pSrc->CS;
8619 pDst->Rsrvd1 = 0;
8620 pDst->FPUDP = pSrc->FPUDP;
8621 pDst->DS = pSrc->DS;
8622 pDst->Rsrvd2 = 0;
8623 }
8624
8625 /* XMM registers. */
8626 if ( !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
8627 || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
8628 || pVCpu->iem.s.uCpl != 0)
8629 {
8630 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8631 for (uint32_t i = 0; i < cXmmRegs; i++)
8632 pDst->aXMM[i] = pSrc->aXMM[i];
8633 }
8634
8635 if (pDst->FSW & X86_FSW_ES)
8636 Log11(("fxrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8637 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8638
8639 /*
8640 * Commit the memory.
8641 */
8642 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8643 if (rcStrict != VINF_SUCCESS)
8644 return rcStrict;
8645
8646 iemHlpUsedFpu(pVCpu);
8647 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8648 return VINF_SUCCESS;
8649}
8650
8651
8652/**
8653 * Implements 'XSAVE'.
8654 *
8655 * @param iEffSeg The effective segment.
8656 * @param GCPtrEff The address of the image.
8657 * @param enmEffOpSize The operand size (only REX.W really matters).
8658 */
8659IEM_CIMPL_DEF_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8660{
8661 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8662
8663 /*
8664 * Raise exceptions.
8665 */
8666 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8667 return iemRaiseUndefinedOpcode(pVCpu);
8668 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8669 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8670 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8671 {
8672 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8673 return iemRaiseUndefinedOpcode(pVCpu);
8674 }
8675 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8676 return iemRaiseDeviceNotAvailable(pVCpu);
8677
8678 /*
8679 * Calc the requested mask.
8680 */
8681 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8682 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8683 uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8684
8685/** @todo figure out the exact protocol for the memory access. Currently we
8686 * just need this crap to work halfways to make it possible to test
8687 * AVX instructions. */
8688/** @todo figure out the XINUSE and XMODIFIED */
8689
8690 /*
8691 * Access the x87 memory state.
8692 */
8693 /* The x87+SSE state. */
8694 void *pvMem512;
8695 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
8696 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8697 if (rcStrict != VINF_SUCCESS)
8698 return rcStrict;
8699 PX86FXSTATE pDst = (PX86FXSTATE)pvMem512;
8700 PCX86FXSTATE pSrc = &pVCpu->cpum.GstCtx.XState.x87;
8701
8702 /* The header. */
8703 PX86XSAVEHDR pHdr;
8704 rcStrict = iemMemMap(pVCpu, (void **)&pHdr, sizeof(&pHdr), iEffSeg, GCPtrEff + 512, IEM_ACCESS_DATA_RW, 0 /* checked above */);
8705 if (rcStrict != VINF_SUCCESS)
8706 return rcStrict;
8707
8708 /*
8709 * Store the X87 state.
8710 */
8711 if (fReqComponents & XSAVE_C_X87)
8712 {
8713 /* common for all formats */
8714 pDst->FCW = pSrc->FCW;
8715 pDst->FSW = pSrc->FSW;
8716 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8717 pDst->FOP = pSrc->FOP;
8718 pDst->FPUIP = pSrc->FPUIP;
8719 pDst->CS = pSrc->CS;
8720 pDst->FPUDP = pSrc->FPUDP;
8721 pDst->DS = pSrc->DS;
8722 if (enmEffOpSize == IEMMODE_64BIT)
8723 {
8724 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8725 pDst->Rsrvd1 = pSrc->Rsrvd1;
8726 pDst->Rsrvd2 = pSrc->Rsrvd2;
8727 }
8728 else
8729 {
8730 pDst->Rsrvd1 = 0;
8731 pDst->Rsrvd2 = 0;
8732 }
8733 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8734 {
8735 /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
8736 * them for now... */
8737 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8738 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8739 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8740 pDst->aRegs[i].au32[3] = 0;
8741 }
8742
8743 }
8744
8745 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8746 {
8747 pDst->MXCSR = pSrc->MXCSR;
8748 pDst->MXCSR_MASK = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
8749 }
8750
8751 if (fReqComponents & XSAVE_C_SSE)
8752 {
8753 /* XMM registers. */
8754 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8755 for (uint32_t i = 0; i < cXmmRegs; i++)
8756 pDst->aXMM[i] = pSrc->aXMM[i];
8757 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8758 * right? */
8759 }
8760
8761 /* Commit the x87 state bits. (probably wrong) */
8762 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8763 if (rcStrict != VINF_SUCCESS)
8764 return rcStrict;
8765
8766 /*
8767 * Store AVX state.
8768 */
8769 if (fReqComponents & XSAVE_C_YMM)
8770 {
8771 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8772 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8773 PCX86XSAVEYMMHI pCompSrc = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
8774 PX86XSAVEYMMHI pCompDst;
8775 rcStrict = iemMemMap(pVCpu, (void **)&pCompDst, sizeof(*pCompDst), iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8776 IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 0 /* checked above */);
8777 if (rcStrict != VINF_SUCCESS)
8778 return rcStrict;
8779
8780 uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8781 for (uint32_t i = 0; i < cXmmRegs; i++)
8782 pCompDst->aYmmHi[i] = pCompSrc->aYmmHi[i];
8783
8784 rcStrict = iemMemCommitAndUnmap(pVCpu, pCompDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
8785 if (rcStrict != VINF_SUCCESS)
8786 return rcStrict;
8787 }
8788
8789 /*
8790 * Update the header.
8791 */
8792 pHdr->bmXState = (pHdr->bmXState & ~fReqComponents)
8793 | (fReqComponents & fXInUse);
8794
8795 rcStrict = iemMemCommitAndUnmap(pVCpu, pHdr, IEM_ACCESS_DATA_RW);
8796 if (rcStrict != VINF_SUCCESS)
8797 return rcStrict;
8798
8799 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
8800 return VINF_SUCCESS;
8801}
8802
8803
8804/**
8805 * Implements 'XRSTOR'.
8806 *
8807 * @param iEffSeg The effective segment.
8808 * @param GCPtrEff The address of the image.
8809 * @param enmEffOpSize The operand size (only REX.W really matters).
8810 */
8811IEM_CIMPL_DEF_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize)
8812{
8813 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
8814
8815 /*
8816 * Raise exceptions.
8817 */
8818 if (!(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
8819 return iemRaiseUndefinedOpcode(pVCpu);
8820 /* When in VMX non-root mode and XSAVE/XRSTOR is not enabled, it results in #UD. */
8821 if ( IEM_VMX_IS_NON_ROOT_MODE(pVCpu)
8822 && !IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_XSAVES_XRSTORS))
8823 {
8824 Log(("xrstor: Not enabled for nested-guest execution -> #UD\n"));
8825 return iemRaiseUndefinedOpcode(pVCpu);
8826 }
8827 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)
8828 return iemRaiseDeviceNotAvailable(pVCpu);
8829 if (GCPtrEff & 63)
8830 {
8831 /** @todo CPU/VM detection possible! \#AC might not be signal for
8832 * all/any misalignment sizes, intel says its an implementation detail. */
8833 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
8834 && pVCpu->cpum.GstCtx.eflags.Bits.u1AC
8835 && pVCpu->iem.s.uCpl == 3)
8836 return iemRaiseAlignmentCheckException(pVCpu);
8837 return iemRaiseGeneralProtectionFault0(pVCpu);
8838 }
8839
8840/** @todo figure out the exact protocol for the memory access. Currently we
8841 * just need this crap to work halfways to make it possible to test
8842 * AVX instructions. */
8843/** @todo figure out the XINUSE and XMODIFIED */
8844
8845 /*
8846 * Access the x87 memory state.
8847 */
8848 /* The x87+SSE state. */
8849 void *pvMem512;
8850 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &pvMem512, 512, iEffSeg, GCPtrEff, IEM_ACCESS_DATA_R,
8851 63 | IEM_MEMMAP_F_ALIGN_GP | IEM_MEMMAP_F_ALIGN_GP_OR_AC);
8852 if (rcStrict != VINF_SUCCESS)
8853 return rcStrict;
8854 PCX86FXSTATE pSrc = (PCX86FXSTATE)pvMem512;
8855 PX86FXSTATE pDst = &pVCpu->cpum.GstCtx.XState.x87;
8856
8857 /*
8858 * Calc the requested mask
8859 */
8860 PX86XSAVEHDR pHdrDst = &pVCpu->cpum.GstCtx.XState.Hdr;
8861 PCX86XSAVEHDR pHdrSrc;
8862 rcStrict = iemMemMap(pVCpu, (void **)&pHdrSrc, sizeof(&pHdrSrc), iEffSeg, GCPtrEff + 512,
8863 IEM_ACCESS_DATA_R, 0 /* checked above */);
8864 if (rcStrict != VINF_SUCCESS)
8865 return rcStrict;
8866
8867 uint64_t const fReqComponents = RT_MAKE_U64(pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.edx) & pVCpu->cpum.GstCtx.aXcr[0];
8868 AssertLogRelReturn(!(fReqComponents & ~(XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM)), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8869 //uint64_t const fXInUse = pVCpu->cpum.GstCtx.aXcr[0];
8870 uint64_t const fRstorMask = pHdrSrc->bmXState;
8871 uint64_t const fCompMask = pHdrSrc->bmXComp;
8872
8873 AssertLogRelReturn(!(fCompMask & XSAVE_C_X), VERR_IEM_ASPECT_NOT_IMPLEMENTED);
8874
8875 uint32_t const cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
8876
8877 /* We won't need this any longer. */
8878 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pHdrSrc, IEM_ACCESS_DATA_R);
8879 if (rcStrict != VINF_SUCCESS)
8880 return rcStrict;
8881
8882 /*
8883 * Store the X87 state.
8884 */
8885 if (fReqComponents & XSAVE_C_X87)
8886 {
8887 if (fRstorMask & XSAVE_C_X87)
8888 {
8889 pDst->FCW = pSrc->FCW;
8890 pDst->FSW = pSrc->FSW;
8891 pDst->FTW = pSrc->FTW & UINT16_C(0xff);
8892 pDst->FOP = pSrc->FOP;
8893 pDst->FPUIP = pSrc->FPUIP;
8894 pDst->CS = pSrc->CS;
8895 pDst->FPUDP = pSrc->FPUDP;
8896 pDst->DS = pSrc->DS;
8897 if (enmEffOpSize == IEMMODE_64BIT)
8898 {
8899 /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
8900 pDst->Rsrvd1 = pSrc->Rsrvd1;
8901 pDst->Rsrvd2 = pSrc->Rsrvd2;
8902 }
8903 else
8904 {
8905 pDst->Rsrvd1 = 0;
8906 pDst->Rsrvd2 = 0;
8907 }
8908 for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
8909 {
8910 pDst->aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
8911 pDst->aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
8912 pDst->aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
8913 pDst->aRegs[i].au32[3] = 0;
8914 }
8915 if (pDst->FSW & X86_FSW_ES)
8916 Log11(("xrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",
8917 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pSrc->FSW));
8918 }
8919 else
8920 {
8921 pDst->FCW = 0x37f;
8922 pDst->FSW = 0;
8923 pDst->FTW = 0x00; /* 0 - empty. */
8924 pDst->FPUDP = 0;
8925 pDst->DS = 0; //??
8926 pDst->Rsrvd2= 0;
8927 pDst->FPUIP = 0;
8928 pDst->CS = 0; //??
8929 pDst->Rsrvd1= 0;
8930 pDst->FOP = 0;
8931 for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
8932 {
8933 pDst->aRegs[i].au32[0] = 0;
8934 pDst->aRegs[i].au32[1] = 0;
8935 pDst->aRegs[i].au32[2] = 0;
8936 pDst->aRegs[i].au32[3] = 0;
8937 }
8938 }
8939 pHdrDst->bmXState |= XSAVE_C_X87; /* playing safe for now */
8940 }
8941
8942 /* MXCSR */
8943 if (fReqComponents & (XSAVE_C_SSE | XSAVE_C_YMM))
8944 {
8945 if (fRstorMask & (XSAVE_C_SSE | XSAVE_C_YMM))
8946 pDst->MXCSR = pSrc->MXCSR;
8947 else
8948 pDst->MXCSR = 0x1f80;
8949 }
8950
8951 /* XMM registers. */
8952 if (fReqComponents & XSAVE_C_SSE)
8953 {
8954 if (fRstorMask & XSAVE_C_SSE)
8955 {
8956 for (uint32_t i = 0; i < cXmmRegs; i++)
8957 pDst->aXMM[i] = pSrc->aXMM[i];
8958 /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
8959 * right? */
8960 }
8961 else
8962 {
8963 for (uint32_t i = 0; i < cXmmRegs; i++)
8964 {
8965 pDst->aXMM[i].au64[0] = 0;
8966 pDst->aXMM[i].au64[1] = 0;
8967 }
8968 }
8969 pHdrDst->bmXState |= XSAVE_C_SSE; /* playing safe for now */
8970 }
8971
8972 /* Unmap the x87 state bits (so we've don't run out of mapping). */
8973 rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
8974 if (rcStrict != VINF_SUCCESS)
8975 return rcStrict;
8976
8977 /*
8978 * Restore AVX state.
8979 */
8980 if (fReqComponents & XSAVE_C_YMM)
8981 {
8982 AssertLogRelReturn(pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT] != UINT16_MAX, VERR_IEM_IPE_9);
8983 PX86XSAVEYMMHI pCompDst = CPUMCTX_XSAVE_C_PTR(IEM_GET_CTX(pVCpu), XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
8984
8985 if (fRstorMask & XSAVE_C_YMM)
8986 {
8987 /** @todo testcase: xsave64 vs xsave32 wrt XSAVE_C_YMM. */
8988 PCX86XSAVEYMMHI pCompSrc;
8989 rcStrict = iemMemMap(pVCpu, (void **)&pCompSrc, sizeof(*pCompDst),
8990 iEffSeg, GCPtrEff + pVCpu->cpum.GstCtx.aoffXState[XSAVE_C_YMM_BIT],
8991 IEM_ACCESS_DATA_R, 0 /* checked above */);
8992 if (rcStrict != VINF_SUCCESS)
8993 return rcStrict;
8994
8995 for (uint32_t i = 0; i < cXmmRegs; i++)
8996 {
8997 pCompDst->aYmmHi[i].au64[0] = pCompSrc->aYmmHi[i].au64[0];
8998 pCompDst->aYmmHi[i].au64[1] = pCompSrc->aYmmHi[i].au64[1];
8999 }
9000
9001 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)pCompSrc, IEM_ACCESS_DATA_R);
9002 if (rcStrict != VINF_SUCCESS)
9003 return rcStrict;
9004 }
9005 else
9006 {
9007 for (uint32_t i = 0; i < cXmmRegs; i++)
9008 {
9009 pCompDst->aYmmHi[i].au64[0] = 0;
9010 pCompDst->aYmmHi[i].au64[1] = 0;
9011 }
9012 }
9013 pHdrDst->bmXState |= XSAVE_C_YMM; /* playing safe for now */
9014 }
9015
9016 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9017 return VINF_SUCCESS;
9018}
9019
9020
9021
9022
9023/**
9024 * Implements 'STMXCSR'.
9025 *
9026 * @param iEffSeg The effective segment register for @a GCPtrEff.
9027 * @param GCPtrEff The address of the image.
9028 */
9029IEM_CIMPL_DEF_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9030{
9031 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9032
9033 /*
9034 * Raise exceptions.
9035 */
9036 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9037 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9038 {
9039 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9040 {
9041 /*
9042 * Do the job.
9043 */
9044 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9045 if (rcStrict == VINF_SUCCESS)
9046 {
9047 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9048 return VINF_SUCCESS;
9049 }
9050 return rcStrict;
9051 }
9052 return iemRaiseDeviceNotAvailable(pVCpu);
9053 }
9054 return iemRaiseUndefinedOpcode(pVCpu);
9055}
9056
9057
9058/**
9059 * Implements 'VSTMXCSR'.
9060 *
9061 * @param iEffSeg The effective segment register for @a GCPtrEff.
9062 * @param GCPtrEff The address of the image.
9063 */
9064IEM_CIMPL_DEF_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9065{
9066 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_XCRx);
9067
9068 /*
9069 * Raise exceptions.
9070 */
9071 if ( ( !IEM_IS_GUEST_CPU_AMD(pVCpu)
9072 ? (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) == (XSAVE_C_SSE | XSAVE_C_YMM)
9073 : !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)) /* AMD Jaguar CPU (f0x16,m0,s1) behaviour */
9074 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE))
9075 {
9076 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9077 {
9078 /*
9079 * Do the job.
9080 */
9081 VBOXSTRICTRC rcStrict = iemMemStoreDataU32(pVCpu, iEffSeg, GCPtrEff, pVCpu->cpum.GstCtx.XState.x87.MXCSR);
9082 if (rcStrict == VINF_SUCCESS)
9083 {
9084 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9085 return VINF_SUCCESS;
9086 }
9087 return rcStrict;
9088 }
9089 return iemRaiseDeviceNotAvailable(pVCpu);
9090 }
9091 return iemRaiseUndefinedOpcode(pVCpu);
9092}
9093
9094
9095/**
9096 * Implements 'LDMXCSR'.
9097 *
9098 * @param iEffSeg The effective segment register for @a GCPtrEff.
9099 * @param GCPtrEff The address of the image.
9100 */
9101IEM_CIMPL_DEF_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff)
9102{
9103 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX);
9104
9105 /*
9106 * Raise exceptions.
9107 */
9108 /** @todo testcase - order of LDMXCSR faults. Does \#PF, \#GP and \#SS
9109 * happen after or before \#UD and \#EM? */
9110 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM)
9111 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR))
9112 {
9113 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS))
9114 {
9115 /*
9116 * Do the job.
9117 */
9118 uint32_t fNewMxCsr;
9119 VBOXSTRICTRC rcStrict = iemMemFetchDataU32(pVCpu, &fNewMxCsr, iEffSeg, GCPtrEff);
9120 if (rcStrict == VINF_SUCCESS)
9121 {
9122 uint32_t const fMxCsrMask = CPUMGetGuestMxCsrMask(pVCpu->CTX_SUFF(pVM));
9123 if (!(fNewMxCsr & ~fMxCsrMask))
9124 {
9125 pVCpu->cpum.GstCtx.XState.x87.MXCSR = fNewMxCsr;
9126 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9127 return VINF_SUCCESS;
9128 }
9129 Log(("ldmxcsr: New MXCSR=%#RX32 & ~MASK=%#RX32 = %#RX32 -> #GP(0)\n",
9130 fNewMxCsr, fMxCsrMask, fNewMxCsr & ~fMxCsrMask));
9131 return iemRaiseGeneralProtectionFault0(pVCpu);
9132 }
9133 return rcStrict;
9134 }
9135 return iemRaiseDeviceNotAvailable(pVCpu);
9136 }
9137 return iemRaiseUndefinedOpcode(pVCpu);
9138}
9139
9140
9141/**
9142 * Commmon routine for fnstenv and fnsave.
9143 *
9144 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9145 * @param enmEffOpSize The effective operand size.
9146 * @param uPtr Where to store the state.
9147 */
9148static void iemCImplCommonFpuStoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTPTRUNION uPtr)
9149{
9150 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9151 PCX86FXSTATE pSrcX87 = &pVCpu->cpum.GstCtx.XState.x87;
9152 if (enmEffOpSize == IEMMODE_16BIT)
9153 {
9154 uPtr.pu16[0] = pSrcX87->FCW;
9155 uPtr.pu16[1] = pSrcX87->FSW;
9156 uPtr.pu16[2] = iemFpuCalcFullFtw(pSrcX87);
9157 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9158 {
9159 /** @todo Testcase: How does this work when the FPUIP/CS was saved in
9160 * protected mode or long mode and we save it in real mode? And vice
9161 * versa? And with 32-bit operand size? I think CPU is storing the
9162 * effective address ((CS << 4) + IP) in the offset register and not
9163 * doing any address calculations here. */
9164 uPtr.pu16[3] = (uint16_t)pSrcX87->FPUIP;
9165 uPtr.pu16[4] = ((pSrcX87->FPUIP >> 4) & UINT16_C(0xf000)) | pSrcX87->FOP;
9166 uPtr.pu16[5] = (uint16_t)pSrcX87->FPUDP;
9167 uPtr.pu16[6] = (pSrcX87->FPUDP >> 4) & UINT16_C(0xf000);
9168 }
9169 else
9170 {
9171 uPtr.pu16[3] = pSrcX87->FPUIP;
9172 uPtr.pu16[4] = pSrcX87->CS;
9173 uPtr.pu16[5] = pSrcX87->FPUDP;
9174 uPtr.pu16[6] = pSrcX87->DS;
9175 }
9176 }
9177 else
9178 {
9179 /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
9180 uPtr.pu16[0*2] = pSrcX87->FCW;
9181 uPtr.pu16[0*2+1] = 0xffff; /* (0xffff observed on intel skylake.) */
9182 uPtr.pu16[1*2] = pSrcX87->FSW;
9183 uPtr.pu16[1*2+1] = 0xffff;
9184 uPtr.pu16[2*2] = iemFpuCalcFullFtw(pSrcX87);
9185 uPtr.pu16[2*2+1] = 0xffff;
9186 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9187 {
9188 uPtr.pu16[3*2] = (uint16_t)pSrcX87->FPUIP;
9189 uPtr.pu32[4] = ((pSrcX87->FPUIP & UINT32_C(0xffff0000)) >> 4) | pSrcX87->FOP;
9190 uPtr.pu16[5*2] = (uint16_t)pSrcX87->FPUDP;
9191 uPtr.pu32[6] = (pSrcX87->FPUDP & UINT32_C(0xffff0000)) >> 4;
9192 }
9193 else
9194 {
9195 uPtr.pu32[3] = pSrcX87->FPUIP;
9196 uPtr.pu16[4*2] = pSrcX87->CS;
9197 uPtr.pu16[4*2+1] = pSrcX87->FOP;
9198 uPtr.pu32[5] = pSrcX87->FPUDP;
9199 uPtr.pu16[6*2] = pSrcX87->DS;
9200 uPtr.pu16[6*2+1] = 0xffff;
9201 }
9202 }
9203}
9204
9205
9206/**
9207 * Commmon routine for fldenv and frstor
9208 *
9209 * @param pVCpu The cross context virtual CPU structure of the calling thread.
9210 * @param enmEffOpSize The effective operand size.
9211 * @param uPtr Where to store the state.
9212 */
9213static void iemCImplCommonFpuRestoreEnv(PVMCPUCC pVCpu, IEMMODE enmEffOpSize, RTCPTRUNION uPtr)
9214{
9215 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9216 PX86FXSTATE pDstX87 = &pVCpu->cpum.GstCtx.XState.x87;
9217 if (enmEffOpSize == IEMMODE_16BIT)
9218 {
9219 pDstX87->FCW = uPtr.pu16[0];
9220 pDstX87->FSW = uPtr.pu16[1];
9221 pDstX87->FTW = uPtr.pu16[2];
9222 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9223 {
9224 pDstX87->FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
9225 pDstX87->FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
9226 pDstX87->FOP = uPtr.pu16[4] & UINT16_C(0x07ff);
9227 pDstX87->CS = 0;
9228 pDstX87->Rsrvd1= 0;
9229 pDstX87->DS = 0;
9230 pDstX87->Rsrvd2= 0;
9231 }
9232 else
9233 {
9234 pDstX87->FPUIP = uPtr.pu16[3];
9235 pDstX87->CS = uPtr.pu16[4];
9236 pDstX87->Rsrvd1= 0;
9237 pDstX87->FPUDP = uPtr.pu16[5];
9238 pDstX87->DS = uPtr.pu16[6];
9239 pDstX87->Rsrvd2= 0;
9240 /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
9241 }
9242 }
9243 else
9244 {
9245 pDstX87->FCW = uPtr.pu16[0*2];
9246 pDstX87->FSW = uPtr.pu16[1*2];
9247 pDstX87->FTW = uPtr.pu16[2*2];
9248 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
9249 {
9250 pDstX87->FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
9251 pDstX87->FOP = uPtr.pu32[4] & UINT16_C(0x07ff);
9252 pDstX87->FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
9253 pDstX87->CS = 0;
9254 pDstX87->Rsrvd1= 0;
9255 pDstX87->DS = 0;
9256 pDstX87->Rsrvd2= 0;
9257 }
9258 else
9259 {
9260 pDstX87->FPUIP = uPtr.pu32[3];
9261 pDstX87->CS = uPtr.pu16[4*2];
9262 pDstX87->Rsrvd1= 0;
9263 pDstX87->FOP = uPtr.pu16[4*2+1];
9264 pDstX87->FPUDP = uPtr.pu32[5];
9265 pDstX87->DS = uPtr.pu16[6*2];
9266 pDstX87->Rsrvd2= 0;
9267 }
9268 }
9269
9270 /* Make adjustments. */
9271 pDstX87->FTW = iemFpuCompressFtw(pDstX87->FTW);
9272#ifdef LOG_ENABLED
9273 uint16_t const fOldFsw = pDstX87->FSW;
9274#endif
9275 pDstX87->FCW &= ~X86_FCW_ZERO_MASK;
9276 iemFpuRecalcExceptionStatus(pDstX87);
9277#ifdef LOG_ENABLED
9278 if ((pDstX87->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9279 Log11(("iemCImplCommonFpuRestoreEnv: %04x:%08RX64: %s FPU exception (FCW=%#x FSW=%#x -> %#x)\n",
9280 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, fOldFsw & X86_FSW_ES ? "Supressed" : "Raised",
9281 pDstX87->FCW, fOldFsw, pDstX87->FSW));
9282#endif
9283
9284 /** @todo Testcase: Check if ES and/or B are automatically cleared if no
9285 * exceptions are pending after loading the saved state? */
9286}
9287
9288
9289/**
9290 * Implements 'FNSTENV'.
9291 *
9292 * @param enmEffOpSize The operand size (only REX.W really matters).
9293 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9294 * @param GCPtrEffDst The address of the image.
9295 */
9296IEM_CIMPL_DEF_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9297{
9298 RTPTRUNION uPtr;
9299 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9300 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE,
9301 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ? */);
9302 if (rcStrict != VINF_SUCCESS)
9303 return rcStrict;
9304
9305 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9306
9307 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9308 if (rcStrict != VINF_SUCCESS)
9309 return rcStrict;
9310
9311 /* Mask all math exceptions. Any possibly pending exceptions will be cleared. */
9312 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9313 pFpuCtx->FCW |= X86_FCW_XCPT_MASK;
9314#ifdef LOG_ENABLED
9315 uint16_t fOldFsw = pFpuCtx->FSW;
9316#endif
9317 iemFpuRecalcExceptionStatus(pFpuCtx);
9318#ifdef LOG_ENABLED
9319 if ((pFpuCtx->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9320 Log11(("fnstenv: %04x:%08RX64: %s FPU exception (FCW=%#x, FSW %#x -> %#x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
9321 fOldFsw & X86_FSW_ES ? "Supressed" : "Raised", pFpuCtx->FCW, fOldFsw, pFpuCtx->FSW));
9322#endif
9323
9324 iemHlpUsedFpu(pVCpu);
9325
9326 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9327 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9328 return VINF_SUCCESS;
9329}
9330
9331
9332/**
9333 * Implements 'FNSAVE'.
9334 *
9335 * @param enmEffOpSize The operand size.
9336 * @param iEffSeg The effective segment register for @a GCPtrEffDst.
9337 * @param GCPtrEffDst The address of the image.
9338 */
9339IEM_CIMPL_DEF_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst)
9340{
9341 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9342
9343 RTPTRUNION uPtr;
9344 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, &uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9345 iEffSeg, GCPtrEffDst, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE, 3 /** @todo ? */);
9346 if (rcStrict != VINF_SUCCESS)
9347 return rcStrict;
9348
9349 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9350 iemCImplCommonFpuStoreEnv(pVCpu, enmEffOpSize, uPtr);
9351 PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9352 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9353 {
9354 paRegs[i].au32[0] = pFpuCtx->aRegs[i].au32[0];
9355 paRegs[i].au32[1] = pFpuCtx->aRegs[i].au32[1];
9356 paRegs[i].au16[4] = pFpuCtx->aRegs[i].au16[4];
9357 }
9358
9359 rcStrict = iemMemCommitAndUnmap(pVCpu, uPtr.pv, IEM_ACCESS_DATA_W | IEM_ACCESS_PARTIAL_WRITE);
9360 if (rcStrict != VINF_SUCCESS)
9361 return rcStrict;
9362
9363 /* Rotate the stack to account for changed TOS. */
9364 iemFpuRotateStackSetTop(pFpuCtx, 0);
9365
9366 /*
9367 * Re-initialize the FPU context.
9368 */
9369 pFpuCtx->FCW = 0x37f;
9370 pFpuCtx->FSW = 0;
9371 pFpuCtx->FTW = 0x00; /* 0 - empty */
9372 pFpuCtx->FPUDP = 0;
9373 pFpuCtx->DS = 0;
9374 pFpuCtx->Rsrvd2= 0;
9375 pFpuCtx->FPUIP = 0;
9376 pFpuCtx->CS = 0;
9377 pFpuCtx->Rsrvd1= 0;
9378 pFpuCtx->FOP = 0;
9379
9380 iemHlpUsedFpu(pVCpu);
9381 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9382 return VINF_SUCCESS;
9383}
9384
9385
9386
9387/**
9388 * Implements 'FLDENV'.
9389 *
9390 * @param enmEffOpSize The operand size (only REX.W really matters).
9391 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9392 * @param GCPtrEffSrc The address of the image.
9393 */
9394IEM_CIMPL_DEF_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9395{
9396 RTCPTRUNION uPtr;
9397 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 14 : 28,
9398 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R,
9399 enmEffOpSize == IEMMODE_16BIT ? 1 : 3 /** @todo ?*/);
9400 if (rcStrict != VINF_SUCCESS)
9401 return rcStrict;
9402
9403 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9404
9405 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9406 if (rcStrict != VINF_SUCCESS)
9407 return rcStrict;
9408
9409 iemHlpUsedFpu(pVCpu);
9410 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9411 return VINF_SUCCESS;
9412}
9413
9414
9415/**
9416 * Implements 'FRSTOR'.
9417 *
9418 * @param enmEffOpSize The operand size.
9419 * @param iEffSeg The effective segment register for @a GCPtrEffSrc.
9420 * @param GCPtrEffSrc The address of the image.
9421 */
9422IEM_CIMPL_DEF_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc)
9423{
9424 RTCPTRUNION uPtr;
9425 VBOXSTRICTRC rcStrict = iemMemMap(pVCpu, (void **)&uPtr.pv, enmEffOpSize == IEMMODE_16BIT ? 94 : 108,
9426 iEffSeg, GCPtrEffSrc, IEM_ACCESS_DATA_R, 3 /** @todo ?*/ );
9427 if (rcStrict != VINF_SUCCESS)
9428 return rcStrict;
9429
9430 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9431 iemCImplCommonFpuRestoreEnv(pVCpu, enmEffOpSize, uPtr);
9432 PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
9433 for (uint32_t i = 0; i < RT_ELEMENTS(pFpuCtx->aRegs); i++)
9434 {
9435 pFpuCtx->aRegs[i].au32[0] = paRegs[i].au32[0];
9436 pFpuCtx->aRegs[i].au32[1] = paRegs[i].au32[1];
9437 pFpuCtx->aRegs[i].au32[2] = paRegs[i].au16[4];
9438 pFpuCtx->aRegs[i].au32[3] = 0;
9439 }
9440
9441 rcStrict = iemMemCommitAndUnmap(pVCpu, (void *)uPtr.pv, IEM_ACCESS_DATA_R);
9442 if (rcStrict != VINF_SUCCESS)
9443 return rcStrict;
9444
9445 iemHlpUsedFpu(pVCpu);
9446 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9447 return VINF_SUCCESS;
9448}
9449
9450
9451/**
9452 * Implements 'FLDCW'.
9453 *
9454 * @param u16Fcw The new FCW.
9455 */
9456IEM_CIMPL_DEF_1(iemCImpl_fldcw, uint16_t, u16Fcw)
9457{
9458 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9459
9460 /** @todo Testcase: Check what happens when trying to load X86_FCW_PC_RSVD. */
9461 /** @todo Testcase: Try see what happens when trying to set undefined bits
9462 * (other than 6 and 7). Currently ignoring them. */
9463 /** @todo Testcase: Test that it raises and loweres the FPU exception bits
9464 * according to FSW. (This is what is currently implemented.) */
9465 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9466 pFpuCtx->FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
9467#ifdef LOG_ENABLED
9468 uint16_t fOldFsw = pFpuCtx->FSW;
9469#endif
9470 iemFpuRecalcExceptionStatus(pFpuCtx);
9471#ifdef LOG_ENABLED
9472 if ((pFpuCtx->FSW & X86_FSW_ES) ^ (fOldFsw & X86_FSW_ES))
9473 Log11(("fldcw: %04x:%08RX64: %s FPU exception (FCW=%#x, FSW %#x -> %#x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
9474 fOldFsw & X86_FSW_ES ? "Supressed" : "Raised", pFpuCtx->FCW, fOldFsw, pFpuCtx->FSW));
9475#endif
9476
9477 /* Note: C0, C1, C2 and C3 are documented as undefined, we leave them untouched! */
9478 iemHlpUsedFpu(pVCpu);
9479 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9480 return VINF_SUCCESS;
9481}
9482
9483
9484
9485/**
9486 * Implements the underflow case of fxch.
9487 *
9488 * @param iStReg The other stack register.
9489 */
9490IEM_CIMPL_DEF_1(iemCImpl_fxch_underflow, uint8_t, iStReg)
9491{
9492 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9493
9494 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9495 unsigned const iReg1 = X86_FSW_TOP_GET(pFpuCtx->FSW);
9496 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9497 Assert(!(RT_BIT(iReg1) & pFpuCtx->FTW) || !(RT_BIT(iReg2) & pFpuCtx->FTW));
9498
9499 /** @todo Testcase: fxch underflow. Making assumptions that underflowed
9500 * registers are read as QNaN and then exchanged. This could be
9501 * wrong... */
9502 if (pFpuCtx->FCW & X86_FCW_IM)
9503 {
9504 if (RT_BIT(iReg1) & pFpuCtx->FTW)
9505 {
9506 if (RT_BIT(iReg2) & pFpuCtx->FTW)
9507 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9508 else
9509 pFpuCtx->aRegs[0].r80 = pFpuCtx->aRegs[iStReg].r80;
9510 iemFpuStoreQNan(&pFpuCtx->aRegs[iStReg].r80);
9511 }
9512 else
9513 {
9514 pFpuCtx->aRegs[iStReg].r80 = pFpuCtx->aRegs[0].r80;
9515 iemFpuStoreQNan(&pFpuCtx->aRegs[0].r80);
9516 }
9517 pFpuCtx->FSW &= ~X86_FSW_C_MASK;
9518 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
9519 }
9520 else
9521 {
9522 /* raise underflow exception, don't change anything. */
9523 pFpuCtx->FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
9524 pFpuCtx->FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9525 Log11(("fxch: %04x:%08RX64: Underflow exception (FSW=%#x)\n",
9526 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9527 }
9528
9529 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9530 iemHlpUsedFpu(pVCpu);
9531 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9532 return VINF_SUCCESS;
9533}
9534
9535
9536/**
9537 * Implements 'FCOMI', 'FCOMIP', 'FUCOMI', and 'FUCOMIP'.
9538 *
9539 * @param iStReg The other stack register.
9540 * @param pfnAImpl The assembly comparison implementation.
9541 * @param fPop Whether we should pop the stack when done or not.
9542 */
9543IEM_CIMPL_DEF_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop)
9544{
9545 Assert(iStReg < 8);
9546 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_X87);
9547
9548 /*
9549 * Raise exceptions.
9550 */
9551 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))
9552 return iemRaiseDeviceNotAvailable(pVCpu);
9553
9554 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
9555 uint16_t u16Fsw = pFpuCtx->FSW;
9556 if (u16Fsw & X86_FSW_ES)
9557 return iemRaiseMathFault(pVCpu);
9558
9559 /*
9560 * Check if any of the register accesses causes #SF + #IA.
9561 */
9562 unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
9563 unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
9564 if ((pFpuCtx->FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
9565 {
9566 uint32_t u32Eflags = pfnAImpl(pFpuCtx, &u16Fsw, &pFpuCtx->aRegs[0].r80, &pFpuCtx->aRegs[iStReg].r80);
9567
9568 pFpuCtx->FSW &= ~X86_FSW_C1;
9569 pFpuCtx->FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
9570 if ( !(u16Fsw & X86_FSW_IE)
9571 || (pFpuCtx->FCW & X86_FCW_IM) )
9572 {
9573 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9574 pVCpu->cpum.GstCtx.eflags.u |= u32Eflags & (X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9575 }
9576 }
9577 else if (pFpuCtx->FCW & X86_FCW_IM)
9578 {
9579 /* Masked underflow. */
9580 pFpuCtx->FSW &= ~X86_FSW_C1;
9581 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF;
9582 pVCpu->cpum.GstCtx.eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
9583 pVCpu->cpum.GstCtx.eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
9584 }
9585 else
9586 {
9587 /* Raise underflow - don't touch EFLAGS or TOP. */
9588 pFpuCtx->FSW &= ~X86_FSW_C1;
9589 pFpuCtx->FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
9590 Log11(("fxch: %04x:%08RX64: Raising IE+SF exception (FSW=%#x)\n",
9591 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pFpuCtx->FSW));
9592 fPop = false;
9593 }
9594
9595 /*
9596 * Pop if necessary.
9597 */
9598 if (fPop)
9599 {
9600 pFpuCtx->FTW &= ~RT_BIT(iReg1);
9601 iemFpuStackIncTop(pVCpu);
9602 }
9603
9604 iemFpuUpdateOpcodeAndIpWorker(pVCpu, pFpuCtx);
9605 iemHlpUsedFpu(pVCpu);
9606 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
9607 return VINF_SUCCESS;
9608}
9609
9610/** @} */
9611
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