IEMAllCImplSvmInstr.cpp.h@ 70263

Last change on this file since 70263 was 70263, checked in by vboxsync, 7 years ago
VMM/IEM: SVM VMCB struct logical adjustments for new SVM features (Virtualized VMSAVE/VMLOAD).
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1	/* $Id: IEMAllCImplSvmInstr.cpp.h 70263 2017-12-21 08:32:55Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/**
20	* Converts an IEM exception event type to an SVM event type.
21	*
22	* @returns The SVM event type.
23	* @retval UINT8_MAX if the specified type of event isn't among the set
24	* of recognized IEM event types.
25	*
26	* @param uVector The vector of the event.
27	* @param fIemXcptFlags The IEM exception / interrupt flags.
28	*/
29	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
30	{
31	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
32	{
33	if (uVector != X86_XCPT_NMI)
34	return SVM_EVENT_EXCEPTION;
35	return SVM_EVENT_NMI;
36	}
37
38	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
39	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
40	return SVM_EVENT_EXCEPTION;
41
42	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
43	return SVM_EVENT_EXTERNAL_IRQ;
44
45	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
46	return SVM_EVENT_SOFTWARE_INT;
47
48	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
49	return UINT8_MAX;
50	}
51
52
53	/**
54	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
55	*
56	* @returns Strict VBox status code.
57	* @param pVCpu The cross context virtual CPU structure.
58	* @param pCtx The guest-CPU context.
59	*/
60	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPU pVCpu, PCPUMCTX pCtx)
61	{
62	/*
63	* Flush the TLB with new CR3. This is required in case the PGM mode change
64	* below doesn't actually change anything.
65	*/
66	PGMFlushTLB(pVCpu, pCtx->cr3, true);
67
68	/*
69	* Inform PGM about paging mode changes.
70	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
71	* see comment in iemMemPageTranslateAndCheckAccess().
72	*/
73	int rc = PGMChangeMode(pVCpu, pCtx->cr0 \| X86_CR0_PE, pCtx->cr4, pCtx->msrEFER);
74	#ifdef IN_RING3
75	Assert(rc != VINF_PGM_CHANGE_MODE);
76	#endif
77	AssertRCReturn(rc, rc);
78
79	/* Inform CPUM (recompiler), can later be removed. */
80	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
81
82	/* Re-initialize IEM cache/state after the drastic mode switch. */
83	iemReInitExec(pVCpu);
84	return rc;
85	}
86
87
88	/**
89	* SVM \#VMEXIT handler.
90	*
91	* @returns Strict VBox status code.
92	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
93	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
94	* "host state" and a shutdown is required.
95	*
96	* @param pVCpu The cross context virtual CPU structure.
97	* @param pCtx The guest-CPU context.
98	* @param uExitCode The exit code.
99	* @param uExitInfo1 The exit info. 1 field.
100	* @param uExitInfo2 The exit info. 2 field.
101	*/
102	IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
103	{
104	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
105	\|\| uExitCode == SVM_EXIT_INVALID)
106	{
107	LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pCtx->cs.Sel,
108	pCtx->rip, uExitCode, uExitInfo1, uExitInfo2));
109
110	/*
111	* Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
112	*/
113	pCtx->hwvirt.svm.fGif = false;
114
115	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
116	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
117	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
118	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
119
120	/*
121	* Save the nested-guest state into the VMCB state-save area.
122	*/
123	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
124	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
125	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
126
127	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, ES, es);
128	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, CS, cs);
129	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, SS, ss);
130	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, DS, ds);
131	pVmcbNstGstState->GDTR.u32Limit = pCtx->gdtr.cbGdt;
132	pVmcbNstGstState->GDTR.u64Base = pCtx->gdtr.pGdt;
133	pVmcbNstGstState->IDTR.u32Limit = pCtx->idtr.cbIdt;
134	pVmcbNstGstState->IDTR.u64Base = pCtx->idtr.pIdt;
135	pVmcbNstGstState->u64EFER = pCtx->msrEFER;
136	pVmcbNstGstState->u64CR4 = pCtx->cr4;
137	pVmcbNstGstState->u64CR3 = pCtx->cr3;
138	pVmcbNstGstState->u64CR2 = pCtx->cr2;
139	pVmcbNstGstState->u64CR0 = pCtx->cr0;
140	/** @todo Nested paging. */
141	pVmcbNstGstState->u64RFlags = pCtx->rflags.u64;
142	pVmcbNstGstState->u64RIP = pCtx->rip;
143	pVmcbNstGstState->u64RSP = pCtx->rsp;
144	pVmcbNstGstState->u64RAX = pCtx->rax;
145	pVmcbNstGstState->u64DR7 = pCtx->dr[7];
146	pVmcbNstGstState->u64DR6 = pCtx->dr[6];
147	pVmcbNstGstState->u8CPL = pCtx->ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
148	Assert(CPUMGetGuestCPL(pVCpu) == pCtx->ss.Attr.n.u2Dpl);
149
150	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
151	/* Save interrupt shadow of the nested-guest instruction if any. */
152	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
153	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
154	{
155	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pCtx->rip));
156	pVmcbCtrl->u64IntShadow \|= SVM_INTERRUPT_SHADOW_ACTIVE;
157	}
158
159	/*
160	* Save additional state and intercept information.
161	*/
162	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
163	{
164	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
165	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
166	}
167	else
168	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
169
170	/** @todo Save V_TPR, V_IRQ. */
171	/** @todo NRIP. */
172
173	/* Save exit information. */
174	pVmcbCtrl->u64ExitCode = uExitCode;
175	pVmcbCtrl->u64ExitInfo1 = uExitInfo1;
176	pVmcbCtrl->u64ExitInfo2 = uExitInfo2;
177
178	/*
179	* Update the exit interrupt information field if this #VMEXIT happened as a result
180	* of delivering an event.
181	*/
182	{
183	uint8_t uExitIntVector;
184	uint32_t uExitIntErr;
185	uint32_t fExitIntFlags;
186	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
187	NULL /* uExitIntCr2 */);
188	pVmcbCtrl->ExitIntInfo.n.u1Valid = fRaisingEvent;
189	if (fRaisingEvent)
190	{
191	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
192	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
193	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
194	{
195	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
196	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
197	}
198	}
199	}
200
201	/*
202	* Clear event injection in the VMCB.
203	*/
204	pVmcbCtrl->EventInject.n.u1Valid = 0;
205
206	/*
207	* Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
208	* would have modified some VMCB state) that need to be restored on #VMEXIT before
209	* writing the VMCB back to guest memory.
210	*/
211	HMSvmNstGstVmExitNotify(pVCpu, pCtx);
212
213	/*
214	* Write back the nested-guest's VMCB to its guest physical memory location.
215	*/
216	VBOXSTRICTRC rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, pVmcbNstGst,
217	sizeof(*pVmcbNstGst));
218	/*
219	* Prepare for guest's "host mode" by clearing internal processor state bits.
220	*
221	* We don't need to zero out the state-save area, just the controls should be
222	* sufficient because it has the critical bit of indicating whether we're inside
223	* the nested-guest or not.
224	*/
225	memset(pVmcbNstGstCtrl, 0, sizeof(*pVmcbNstGstCtrl));
226	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
227
228	/*
229	* Restore the subset of force-flags that were preserved.
230	*/
231	if (pCtx->hwvirt.fLocalForcedActions)
232	{
233	VMCPU_FF_SET(pVCpu, pCtx->hwvirt.fLocalForcedActions);
234	pCtx->hwvirt.fLocalForcedActions = 0;
235	}
236
237	if (RT_SUCCESS(rcStrict))
238	{
239	/** @todo Nested paging. */
240	/** @todo ASID. */
241
242	/*
243	* Reload the guest's "host state".
244	*/
245	CPUMSvmVmExitRestoreHostState(pVCpu, pCtx);
246
247	/*
248	* Update PGM, IEM and others of a world-switch.
249	*/
250	rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
251	if (rcStrict == VINF_SUCCESS)
252	return VINF_SVM_VMEXIT;
253
254	if (RT_SUCCESS(rcStrict))
255	{
256	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", rcStrict));
257	iemSetPassUpStatus(pVCpu, rcStrict);
258	return VINF_SVM_VMEXIT;
259	}
260
261	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
262	}
263	else
264	LogFlow(("iemSvmVmexit: Writing VMCB at %#RGp failed. rc=%Rrc\n", pCtx->hwvirt.svm.GCPhysVmcb,
265	VBOXSTRICTRC_VAL(rcStrict)));
266
267	return VERR_SVM_VMEXIT_FAILED;
268	}
269
270	Log(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode,
271	uExitInfo1, uExitInfo2));
272	AssertMsgFailed(("iemSvmVmexit: Unexpected SVM-exit failure uExitCode=%#RX64\n", uExitCode));
273	return VERR_SVM_IPE_5;
274	}
275
276
277	/**
278	* Performs the operations necessary that are part of the vmrun instruction
279	* execution in the guest.
280	*
281	* @returns Strict VBox status code (i.e. informational status codes too).
282	* @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
283	* code execution.
284	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
285	* (SVM_EXIT_INVALID most likely).
286	*
287	* @param pVCpu The cross context virtual CPU structure.
288	* @param pCtx Pointer to the guest-CPU context.
289	* @param cbInstr The length of the VMRUN instruction.
290	* @param GCPhysVmcb Guest physical address of the VMCB to run.
291	*/
292	IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
293	{
294	LogFlow(("iemSvmVmrun\n"));
295
296	#ifdef IN_RING0
297	/*
298	* Until PGM can handle switching the guest paging mode in ring-0,
299	* there's no point in trying to emulate VMRUN in ring-0 as we have
300	* to go back to ring-3 anyway, see @bugref{7243#c48}.
301	*/
302	RT_NOREF(pVCpu, pCtx, cbInstr, GCPhysVmcb);
303	return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
304	#else
305
306	/*
307	* Cache the physical address of the VMCB for #VMEXIT exceptions.
308	*/
309	pCtx->hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
310
311	/*
312	* Save the host state.
313	*/
314	CPUMSvmVmRunSaveHostState(pCtx, cbInstr);
315
316	/*
317	* Read the guest VMCB state.
318	*/
319	PVM pVM = pVCpu->CTX_SUFF(pVM);
320	int rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pVmcb), GCPhysVmcb, sizeof(SVMVMCB));
321	if (RT_SUCCESS(rc))
322	{
323	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
324	PSVMVMCBSTATESAVE pVmcbNstGst = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->guest;
325
326	/*
327	* Validate guest-state and controls.
328	*/
329	/* VMRUN must always be intercepted. */
330	if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
331	{
332	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
333	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
334	}
335
336	/* Nested paging. */
337	if ( pVmcbCtrl->u1NestedPaging
338	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
339	{
340	Log(("iemSvmVmrun: Nested paging not supported -> #VMEXIT\n"));
341	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
342	}
343
344	/* AVIC. */
345	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
346	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
347	{
348	Log(("iemSvmVmrun: AVIC not supported -> #VMEXIT\n"));
349	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
350	}
351
352	/* Last branch record (LBR) virtualization. */
353	if ( pVmcbCtrl->u1LbrVirt
354	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
355	{
356	Log(("iemSvmVmrun: LBR virtualization not supported -> #VMEXIT\n"));
357	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
358	}
359
360	/* Guest ASID. */
361	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
362	{
363	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
364	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
365	}
366
367	/* IO permission bitmap. */
368	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
369	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
370	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
371	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
372	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
373	{
374	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
375	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
376	}
377
378	/* MSR permission bitmap. */
379	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
380	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
381	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
382	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
383	{
384	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
385	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
386	}
387
388	/* CR0. */
389	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
390	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
391	{
392	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
393	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
394	}
395	if (pVmcbNstGst->u64CR0 >> 32)
396	{
397	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
398	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
399	}
400	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
401
402	/* DR6 and DR7. */
403	if ( pVmcbNstGst->u64DR6 >> 32
404	\|\| pVmcbNstGst->u64DR7 >> 32)
405	{
406	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
407	pVmcbNstGst->u64DR6));
408	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
409	}
410
411	/** @todo gPAT MSR validation? */
412
413	/*
414	* Copy the IO permission bitmap into the cache.
415	*/
416	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap));
417	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap), GCPhysIOBitmap,
418	SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
419	if (RT_FAILURE(rc))
420	{
421	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
422	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
423	}
424
425	/*
426	* Copy the MSR permission bitmap into the cache.
427	*/
428	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap));
429	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap), GCPhysMsrBitmap,
430	SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
431	if (RT_FAILURE(rc))
432	{
433	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
434	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
435	}
436
437	/*
438	* Copy segments from nested-guest VMCB state to the guest-CPU state.
439	*
440	* We do this here as we need to use the CS attributes and it's easier this way
441	* then using the VMCB format selectors. It doesn't really matter where we copy
442	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
443	*/
444	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, ES, es);
445	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, CS, cs);
446	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, SS, ss);
447	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, DS, ds);
448
449	/** @todo Segment attribute overrides by VMRUN. */
450
451	/*
452	* CPL adjustments and overrides.
453	*
454	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
455	* We shall thus adjust both CS.DPL and SS.DPL here.
456	*/
457	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
458	if (CPUMIsGuestInV86ModeEx(pCtx))
459	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 3;
460	if (CPUMIsGuestInRealModeEx(pCtx))
461	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 0;
462
463	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
464
465	/*
466	* Continue validating guest-state and controls.
467	*
468	* We pass CR0 as 0 to CPUMQueryValidatedGuestEfer below to skip the illegal
469	* EFER.LME bit transition check. We pass the nested-guest's EFER as both the
470	* old and new EFER value to not have any guest EFER bits influence the new
471	* nested-guest EFER.
472	*/
473	uint64_t uValidEfer;
474	rc = CPUMQueryValidatedGuestEfer(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
475	if (RT_FAILURE(rc))
476	{
477	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
478	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
479	}
480
481	/* Validate paging and CPU mode bits. */
482	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
483	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
484	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
485	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
486	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
487	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
488	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
489	bool const fLongModeConformCS = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
490	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
491	if (fLongModeWithPaging)
492	uValidEfer \|= MSR_K6_EFER_LMA;
493	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
494	if ( !fSvm
495	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
496	\|\| (fLongModeWithPaging && !fPae)
497	\|\| (fLongModeWithPaging && !fProtMode)
498	\|\| ( fLongModeEnabled
499	&& fPaging
500	&& fPae
501	&& fLongModeConformCS))
502	{
503	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
504	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
505	}
506
507	/*
508	* Preserve the required force-flags.
509	*
510	* We only preserve the force-flags that would affect the execution of the
511	* nested-guest (or the guest).
512	*
513	* - VMCPU_FF_INHIBIT_INTERRUPTS need -not- be preserved as it's for a single
514	* instruction which is this VMRUN instruction itself.
515	*
516	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
517	* execution of a subsequent IRET instruction in the guest.
518	*
519	* - The remaining FFs (e.g. timers) can stay in place so that we will be
520	* able to generate interrupts that should cause #VMEXITs for the
521	* nested-guest.
522	*/
523	pCtx->hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
524	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
525
526	/*
527	* Interrupt shadow.
528	*/
529	if (pVmcbCtrl->u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
530	{
531	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
532	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
533	EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
534	}
535
536	/*
537	* TLB flush control.
538	* Currently disabled since it's redundant as we unconditionally flush the TLB
539	* in iemSvmWorldSwitch() below.
540	*/
541	#if 0
542	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
543	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
544	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
545	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
546	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
547	#endif
548
549	/*
550	* Copy the remaining guest state from the VMCB to the guest-CPU context.
551	*/
552	pCtx->gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
553	pCtx->gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
554	pCtx->idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
555	pCtx->idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
556	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
557	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
558	pCtx->cr3 = pVmcbNstGst->u64CR3;
559	pCtx->cr2 = pVmcbNstGst->u64CR2;
560	pCtx->dr[6] = pVmcbNstGst->u64DR6;
561	pCtx->dr[7] = pVmcbNstGst->u64DR7;
562	pCtx->rflags.u64 = pVmcbNstGst->u64RFlags;
563	pCtx->rax = pVmcbNstGst->u64RAX;
564	pCtx->rsp = pVmcbNstGst->u64RSP;
565	pCtx->rip = pVmcbNstGst->u64RIP;
566	CPUMSetGuestMsrEferNoCheck(pVCpu, pCtx->msrEFER, uValidEfer);
567
568	/* Mask DR6, DR7 bits mandatory set/clear bits. */
569	pCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
570	pCtx->dr[6] \|= X86_DR6_RA1_MASK;
571	pCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
572	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
573
574	/*
575	* Check for pending virtual interrupts.
576	*/
577	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
578	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
579	else
580	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
581
582	/*
583	* Update PGM, IEM and others of a world-switch.
584	*/
585	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
586	if (rcStrict == VINF_SUCCESS)
587	{ /* likely */ }
588	else if (RT_SUCCESS(rcStrict))
589	{
590	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
591	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
592	}
593	else
594	{
595	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
596	return rcStrict;
597	}
598
599	/*
600	* Clear global interrupt flags to allow interrupts in the guest.
601	*/
602	pCtx->hwvirt.svm.fGif = true;
603
604	/*
605	* Event injection.
606	*/
607	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
608	pCtx->hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
609	if (pEventInject->n.u1Valid)
610	{
611	uint8_t const uVector = pEventInject->n.u8Vector;
612	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject);
613	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
614
615	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
616	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
617	{
618	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
619	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
620	}
621	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
622	{
623	if ( uVector == X86_XCPT_NMI
624	\|\| uVector > X86_XCPT_LAST)
625	{
626	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
627	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
628	}
629	if ( uVector == X86_XCPT_BR
630	&& CPUMIsGuestInLongModeEx(pCtx))
631	{
632	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
633	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
634	}
635	/** @todo any others? */
636	}
637
638	/*
639	* Update the exit interruption info field so that if an exception occurs
640	* while delivering the event causing a #VMEXIT, we only need to update
641	* the valid bit while the rest is already in place.
642	*/
643	pVmcbCtrl->ExitIntInfo.u = pVmcbCtrl->EventInject.u;
644	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
645
646	/** @todo NRIP: Software interrupts can only be pushed properly if we support
647	* NRIP for the nested-guest to calculate the instruction length
648	* below. */
649	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 uVector=%#x enmType=%d uErrorCode=%u cr2=%#RX64 efer=%#RX64\n",
650	pCtx->cs.Sel, pCtx->rip, uVector, enmType, uErrorCode, pCtx->cr2, pCtx->msrEFER));
651	rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
652	}
653	else
654	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
655	pCtx->cs.Sel, pCtx->rip, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->msrEFER, pCtx->rflags.u64));
656
657	LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
658	return rcStrict;
659	}
660
661	/* Shouldn't really happen as the caller should've validated the physical address already. */
662	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
663	return rc;
664	#endif
665	}
666
667
668	#if 0
669	/**
670	* Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
671	* intercept is active.
672	*
673	* @returns Strict VBox status code.
674	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
675	* we're not executing a nested-guest.
676	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
677	* successfully.
678	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
679	* failed and a shutdown needs to be initiated for the geust.
680	*
681	* @param pVCpu The cross context virtual CPU structure.
682	* @param pCtx The guest-CPU context.
683	* @param uExitCode The SVM exit code (see SVM_EXIT_XXX).
684	* @param uExitInfo1 The exit info. 1 field.
685	* @param uExitInfo2 The exit info. 2 field.
686	*/
687	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
688	uint64_t uExitInfo2)
689	{
690	#define HMSVM_CTRL_INTERCEPT_VMEXIT(a_Intercept) \
691	do { \
692	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \
693	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \
694	break; \
695	} while (0)
696
697	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
698	return VINF_HM_INTERCEPT_NOT_ACTIVE;
699
700	switch (uExitCode)
701	{
702	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
703	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
704	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
705	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15:
706	case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
707	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
708	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27:
709	case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
710	{
711	if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0)))
712	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
713	break;
714	}
715
716	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
717	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
718	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
719	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
720	{
721	if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0))
722	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
723	break;
724	}
725
726	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
727	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
728	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
729	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
730	{
731	if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0))
732	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
733	break;
734	}
735
736	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
737	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
738	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
739	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
740	{
741	if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0))
742	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
743	break;
744	}
745
746	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
747	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
748	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
749	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
750	{
751	if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0))
752	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
753	break;
754	}
755
756	case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTR);
757	case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_NMI);
758	case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SMI);
759	case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INIT);
760	case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VINTR);
761	case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES);
762	case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_READS);
763	case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_READS);
764	case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_READS);
765	case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_READS);
766	case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_WRITES);
767	case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_WRITES);
768	case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_WRITES);
769	case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_WRITES);
770	case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSC);
771	case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDPMC);
772	case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PUSHF);
773	case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_POPF);
774	case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CPUID);
775	case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RSM);
776	case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IRET);
777	case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTN);
778	case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVD);
779	case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PAUSE);
780	case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_HLT);
781	case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPG);
782	case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPGA);
783	case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TASK_SWITCH);
784	case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_FERR_FREEZE);
785	case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SHUTDOWN);
786	case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMRUN);
787	case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMMCALL);
788	case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMLOAD);
789	case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMSAVE);
790	case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_STGI);
791	case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CLGI);
792	case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SKINIT);
793	case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSCP);
794	case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_ICEBP);
795	case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_WBINVD);
796	case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MONITOR);
797	case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT);
798	case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT_ARMED);
799	case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_XSETBV);
800
801	case SVM_EXIT_IOIO:
802	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
803	return VERR_SVM_IPE_1;
804
805	case SVM_EXIT_MSR:
806	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
807	return VERR_SVM_IPE_1;
808
809	case SVM_EXIT_NPF:
810	case SVM_EXIT_AVIC_INCOMPLETE_IPI:
811	case SVM_EXIT_AVIC_NOACCEL:
812	AssertMsgFailed(("Todo Implement.\n"));
813	return VERR_SVM_IPE_1;
814
815	default:
816	AssertMsgFailed(("Unsupported SVM exit code %#RX64\n", uExitCode));
817	return VERR_SVM_IPE_1;
818	}
819
820	return VINF_HM_INTERCEPT_NOT_ACTIVE;
821
822	#undef HMSVM_CTRL_INTERCEPT_VMEXIT
823	}
824	#endif
825
826
827	/**
828	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
829	* intercept is active.
830	*
831	* @returns Strict VBox status code.
832	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
833	* we're not executing a nested-guest.
834	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
835	* successfully.
836	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
837	* failed and a shutdown needs to be initiated for the geust.
838	*
839	* @returns VBox strict status code.
840	* @param pVCpu The cross context virtual CPU structure of the calling thread.
841	* @param u16Port The IO port being accessed.
842	* @param enmIoType The type of IO access.
843	* @param cbReg The IO operand size in bytes.
844	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
845	* @param iEffSeg The effective segment number.
846	* @param fRep Whether this is a repeating IO instruction (REP prefix).
847	* @param fStrIo Whether this is a string IO instruction.
848	* @param cbInstr The length of the IO instruction in bytes.
849	*/
850	IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr,
851	uint64_t uCr2)
852	{
853	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
854
855	/*
856	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
857	*
858	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_EXCEPTION_2 #VMEXITs.
859	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
860	* even when they use a vector in the range 0 to 31.
861	* - ICEBP should not trigger #DB intercept, but its own intercept.
862	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
863	*/
864	/* Check NMI intercept */
865	if ( u8Vector == X86_XCPT_NMI
866	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
867	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
868	{
869	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
870	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
871	}
872
873	/* Check ICEBP intercept. */
874	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
875	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
876	{
877	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
878	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
879	}
880
881	/* Check CPU exception intercepts. */
882	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
883	&& IEM_IS_SVM_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
884	{
885	Assert(u8Vector <= X86_XCPT_LAST);
886	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
887	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
888	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
889	&& u8Vector == X86_XCPT_PF
890	&& !(uErr & X86_TRAP_PF_ID))
891	{
892	/** @todo Nested-guest SVM - figure out fetching op-code bytes from IEM. */
893	#ifdef IEM_WITH_CODE_TLB
894	AssertReleaseFailedReturn(VERR_IEM_IPE_5);
895	#else
896	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
897	uint8_t const offOpCode = pVCpu->iem.s.offOpcode;
898	uint8_t const cbCurrent = pVCpu->iem.s.cbOpcode - pVCpu->iem.s.offOpcode;
899	if ( cbCurrent > 0
900	&& cbCurrent < sizeof(pVmcbCtrl->abInstr))
901	{
902	Assert(cbCurrent <= sizeof(pVCpu->iem.s.abOpcode));
903	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[offOpCode], cbCurrent);
904	}
905	#endif
906	}
907	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
908	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u32InterceptXcpt,
909	u8Vector, uExitInfo1, uExitInfo2));
910	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_EXCEPTION_0 + u8Vector, uExitInfo1, uExitInfo2);
911	}
912
913	/* Check software interrupt (INTn) intercepts. */
914	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
915	\| IEM_XCPT_FLAGS_BP_INSTR
916	\| IEM_XCPT_FLAGS_ICEBP_INSTR
917	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
918	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
919	{
920	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
921	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
922	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
923	}
924
925	return VINF_HM_INTERCEPT_NOT_ACTIVE;
926	}
927
928
929	/**
930	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
931	* corresponding intercept is active.
932	*
933	* @returns Strict VBox status code.
934	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
935	* we're not executing a nested-guest.
936	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
937	* successfully.
938	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
939	* failed and a shutdown needs to be initiated for the geust.
940	*
941	* @returns VBox strict status code.
942	* @param pVCpu The cross context virtual CPU structure of the calling thread.
943	* @param u16Port The IO port being accessed.
944	* @param enmIoType The type of IO access.
945	* @param cbReg The IO operand size in bytes.
946	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
947	* @param iEffSeg The effective segment number.
948	* @param fRep Whether this is a repeating IO instruction (REP prefix).
949	* @param fStrIo Whether this is a string IO instruction.
950	* @param cbInstr The length of the IO instruction in bytes.
951	*/
952	IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPU pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
953	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
954	{
955	Assert(IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
956	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
957	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
958
959	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
960
961	SVMIOIOEXITINFO IoExitInfo;
962	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
963	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
964	bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
965	&IoExitInfo);
966	if (fIntercept)
967	{
968	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
969	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_IOIO, IoExitInfo.u, pCtx->rip + cbInstr);
970	}
971
972	/** @todo remove later (for debugging as VirtualBox always traps all IO
973	* intercepts). */
974	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
975	return VINF_HM_INTERCEPT_NOT_ACTIVE;
976	}
977
978
979	/**
980	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
981	* corresponding intercept is active.
982	*
983	* @returns Strict VBox status code.
984	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
985	* specify interception of the accessed MSR @a idMsr.
986	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
987	* successfully.
988	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
989	* failed and a shutdown needs to be initiated for the geust.
990	*
991	* @param pVCpu The cross context virtual CPU structure.
992	* @param pCtx The guest-CPU context.
993	* @param idMsr The MSR being accessed in the nested-guest.
994	* @param fWrite Whether this is an MSR write access, @c false implies an
995	* MSR read.
996	*/
997	IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
998	{
999	/*
1000	* Check if any MSRs are being intercepted.
1001	*/
1002	Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT));
1003	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1004
1005	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1006
1007	/*
1008	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1009	*/
1010	uint16_t offMsrpm;
1011	uint32_t uMsrpmBit;
1012	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1013	if (RT_SUCCESS(rc))
1014	{
1015	Assert(uMsrpmBit < 0x3fff);
1016	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1017	if (fWrite)
1018	++uMsrpmBit;
1019
1020	/*
1021	* Check if the bit is set, if so, trigger a #VMEXIT.
1022	*/
1023	uint8_t pbMsrpm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1024	pbMsrpm += offMsrpm;
1025	if (ASMBitTest(pbMsrpm, uMsrpmBit))
1026	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1027	}
1028	else
1029	{
1030	/*
1031	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1032	*/
1033	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1034	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1035	}
1036	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1037	}
1038
1039
1040
1041	/**
1042	* Implements 'VMRUN'.
1043	*/
1044	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1045	{
1046	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1047	RT_NOREF2(pVCpu, cbInstr);
1048	return VINF_EM_RAW_EMULATE_INSTR;
1049	#else
1050	LogFlow(("iemCImpl_vmrun\n"));
1051	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1052	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1053
1054	/** @todo Check effective address size using address size prefix. */
1055	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1056	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1057	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1058	{
1059	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1060	return iemRaiseGeneralProtectionFault0(pVCpu);
1061	}
1062
1063	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1064	{
1065	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1066	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1067	}
1068
1069	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, pCtx, cbInstr, GCPhysVmcb);
1070	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1071	{
1072	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1073	rcStrict = VINF_EM_TRIPLE_FAULT;
1074	}
1075	return rcStrict;
1076	#endif
1077	}
1078
1079
1080	/**
1081	* Implements 'VMMCALL'.
1082	*/
1083	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1084	{
1085	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1086	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1087	{
1088	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1089	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1090	}
1091
1092	bool fUpdatedRipAndRF;
1093	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fUpdatedRipAndRF);
1094	if (RT_SUCCESS(rcStrict))
1095	{
1096	if (!fUpdatedRipAndRF)
1097	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1098	return rcStrict;
1099	}
1100
1101	return iemRaiseUndefinedOpcode(pVCpu);
1102	}
1103
1104
1105	/**
1106	* Implements 'VMLOAD'.
1107	*/
1108	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1109	{
1110	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1111	RT_NOREF2(pVCpu, cbInstr);
1112	return VINF_EM_RAW_EMULATE_INSTR;
1113	#else
1114	LogFlow(("iemCImpl_vmload\n"));
1115	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1116	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1117
1118	/** @todo Check effective address size using address size prefix. */
1119	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1120	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1121	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1122	{
1123	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1124	return iemRaiseGeneralProtectionFault0(pVCpu);
1125	}
1126
1127	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1128	{
1129	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1130	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1131	}
1132
1133	SVMVMCBSTATESAVE VmcbNstGst;
1134	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1135	sizeof(SVMVMCBSTATESAVE));
1136	if (rcStrict == VINF_SUCCESS)
1137	{
1138	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1139	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, FS, fs);
1140	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, GS, gs);
1141	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, TR, tr);
1142	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1143
1144	pCtx->msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1145	pCtx->msrSTAR = VmcbNstGst.u64STAR;
1146	pCtx->msrLSTAR = VmcbNstGst.u64LSTAR;
1147	pCtx->msrCSTAR = VmcbNstGst.u64CSTAR;
1148	pCtx->msrSFMASK = VmcbNstGst.u64SFMASK;
1149
1150	pCtx->SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1151	pCtx->SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1152	pCtx->SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1153
1154	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1155	}
1156	return rcStrict;
1157	#endif
1158	}
1159
1160
1161	/**
1162	* Implements 'VMSAVE'.
1163	*/
1164	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1165	{
1166	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1167	RT_NOREF2(pVCpu, cbInstr);
1168	return VINF_EM_RAW_EMULATE_INSTR;
1169	#else
1170	LogFlow(("iemCImpl_vmsave\n"));
1171	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1172	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1173
1174	/** @todo Check effective address size using address size prefix. */
1175	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1176	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1177	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1178	{
1179	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1180	return iemRaiseGeneralProtectionFault0(pVCpu);
1181	}
1182
1183	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1184	{
1185	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1186	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1187	}
1188
1189	SVMVMCBSTATESAVE VmcbNstGst;
1190	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1191	sizeof(SVMVMCBSTATESAVE));
1192	if (rcStrict == VINF_SUCCESS)
1193	{
1194	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1195	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, FS, fs);
1196	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, GS, gs);
1197	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, TR, tr);
1198	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1199
1200	VmcbNstGst.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1201	VmcbNstGst.u64STAR = pCtx->msrSTAR;
1202	VmcbNstGst.u64LSTAR = pCtx->msrLSTAR;
1203	VmcbNstGst.u64CSTAR = pCtx->msrCSTAR;
1204	VmcbNstGst.u64SFMASK = pCtx->msrSFMASK;
1205
1206	VmcbNstGst.u64SysEnterCS = pCtx->SysEnter.cs;
1207	VmcbNstGst.u64SysEnterESP = pCtx->SysEnter.esp;
1208	VmcbNstGst.u64SysEnterEIP = pCtx->SysEnter.eip;
1209
1210	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1211	sizeof(SVMVMCBSTATESAVE));
1212	if (rcStrict == VINF_SUCCESS)
1213	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1214	}
1215	return rcStrict;
1216	#endif
1217	}
1218
1219
1220	/**
1221	* Implements 'CLGI'.
1222	*/
1223	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1224	{
1225	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1226	RT_NOREF2(pVCpu, cbInstr);
1227	return VINF_EM_RAW_EMULATE_INSTR;
1228	#else
1229	LogFlow(("iemCImpl_clgi\n"));
1230	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1231	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1232	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1233	{
1234	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1235	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1236	}
1237
1238	pCtx->hwvirt.svm.fGif = false;
1239	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1240
1241	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1242	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1243	# else
1244	return VINF_SUCCESS;
1245	# endif
1246	#endif
1247	}
1248
1249
1250	/**
1251	* Implements 'STGI'.
1252	*/
1253	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1254	{
1255	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1256	RT_NOREF2(pVCpu, cbInstr);
1257	return VINF_EM_RAW_EMULATE_INSTR;
1258	#else
1259	LogFlow(("iemCImpl_stgi\n"));
1260	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1261	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1262	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1263	{
1264	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1265	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1266	}
1267
1268	pCtx->hwvirt.svm.fGif = true;
1269	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1270
1271	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1272	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1273	# else
1274	return VINF_SUCCESS;
1275	# endif
1276	#endif
1277	}
1278
1279
1280	/**
1281	* Implements 'INVLPGA'.
1282	*/
1283	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1284	{
1285	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1286	/** @todo Check effective address size using address size prefix. */
1287	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1288	/** @todo PGM needs virtual ASID support. */
1289	#if 0
1290	uint32_t const uAsid = pCtx->ecx;
1291	#endif
1292
1293	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1294	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1295	{
1296	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1297	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1298	}
1299
1300	PGMInvalidatePage(pVCpu, GCPtrPage);
1301	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1302	return VINF_SUCCESS;
1303	}
1304
1305
1306	/**
1307	* Implements 'SKINIT'.
1308	*/
1309	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1310	{
1311	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1312
1313	uint32_t uIgnore;
1314	uint32_t fFeaturesECX;
1315	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1316	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1317	return iemRaiseUndefinedOpcode(pVCpu);
1318
1319	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1320	{
1321	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1322	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1323	}
1324
1325	RT_NOREF(cbInstr);
1326	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1327	}
1328

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 70263

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