IEMAllCImplSvmInstr.cpp.h@ 70416

Last change on this file since 70416 was 70416, checked in by vboxsync, 7 years ago
VMM/IEM: SVM Virtual GIF check on VMRUN emulation.
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1	/* $Id: IEMAllCImplSvmInstr.cpp.h 70416 2018-01-02 08:37:13Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/**
20	* Converts an IEM exception event type to an SVM event type.
21	*
22	* @returns The SVM event type.
23	* @retval UINT8_MAX if the specified type of event isn't among the set
24	* of recognized IEM event types.
25	*
26	* @param uVector The vector of the event.
27	* @param fIemXcptFlags The IEM exception / interrupt flags.
28	*/
29	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
30	{
31	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
32	{
33	if (uVector != X86_XCPT_NMI)
34	return SVM_EVENT_EXCEPTION;
35	return SVM_EVENT_NMI;
36	}
37
38	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
39	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
40	return SVM_EVENT_EXCEPTION;
41
42	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
43	return SVM_EVENT_EXTERNAL_IRQ;
44
45	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
46	return SVM_EVENT_SOFTWARE_INT;
47
48	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
49	return UINT8_MAX;
50	}
51
52
53	/**
54	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
55	*
56	* @returns Strict VBox status code.
57	* @param pVCpu The cross context virtual CPU structure.
58	* @param pCtx The guest-CPU context.
59	*/
60	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPU pVCpu, PCPUMCTX pCtx)
61	{
62	/*
63	* Flush the TLB with new CR3. This is required in case the PGM mode change
64	* below doesn't actually change anything.
65	*/
66	PGMFlushTLB(pVCpu, pCtx->cr3, true);
67
68	/*
69	* Inform PGM about paging mode changes.
70	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
71	* see comment in iemMemPageTranslateAndCheckAccess().
72	*/
73	int rc = PGMChangeMode(pVCpu, pCtx->cr0 \| X86_CR0_PE, pCtx->cr4, pCtx->msrEFER);
74	#ifdef IN_RING3
75	Assert(rc != VINF_PGM_CHANGE_MODE);
76	#endif
77	AssertRCReturn(rc, rc);
78
79	/* Inform CPUM (recompiler), can later be removed. */
80	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
81
82	/* Re-initialize IEM cache/state after the drastic mode switch. */
83	iemReInitExec(pVCpu);
84	return rc;
85	}
86
87
88	/**
89	* SVM \#VMEXIT handler.
90	*
91	* @returns Strict VBox status code.
92	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
93	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
94	* "host state" and a shutdown is required.
95	*
96	* @param pVCpu The cross context virtual CPU structure.
97	* @param pCtx The guest-CPU context.
98	* @param uExitCode The exit code.
99	* @param uExitInfo1 The exit info. 1 field.
100	* @param uExitInfo2 The exit info. 2 field.
101	*/
102	IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
103	{
104	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
105	\|\| uExitCode == SVM_EXIT_INVALID)
106	{
107	LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pCtx->cs.Sel,
108	pCtx->rip, uExitCode, uExitInfo1, uExitInfo2));
109
110	/*
111	* Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
112	*/
113	pCtx->hwvirt.svm.fGif = false;
114
115	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
116	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
117	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
118	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
119
120	/*
121	* Save the nested-guest state into the VMCB state-save area.
122	*/
123	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
124	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
125	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
126
127	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, ES, es);
128	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, CS, cs);
129	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, SS, ss);
130	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, DS, ds);
131	pVmcbNstGstState->GDTR.u32Limit = pCtx->gdtr.cbGdt;
132	pVmcbNstGstState->GDTR.u64Base = pCtx->gdtr.pGdt;
133	pVmcbNstGstState->IDTR.u32Limit = pCtx->idtr.cbIdt;
134	pVmcbNstGstState->IDTR.u64Base = pCtx->idtr.pIdt;
135	pVmcbNstGstState->u64EFER = pCtx->msrEFER;
136	pVmcbNstGstState->u64CR4 = pCtx->cr4;
137	pVmcbNstGstState->u64CR3 = pCtx->cr3;
138	pVmcbNstGstState->u64CR2 = pCtx->cr2;
139	pVmcbNstGstState->u64CR0 = pCtx->cr0;
140	/** @todo Nested paging. */
141	pVmcbNstGstState->u64RFlags = pCtx->rflags.u64;
142	pVmcbNstGstState->u64RIP = pCtx->rip;
143	pVmcbNstGstState->u64RSP = pCtx->rsp;
144	pVmcbNstGstState->u64RAX = pCtx->rax;
145	pVmcbNstGstState->u64DR7 = pCtx->dr[7];
146	pVmcbNstGstState->u64DR6 = pCtx->dr[6];
147	pVmcbNstGstState->u8CPL = pCtx->ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
148	Assert(CPUMGetGuestCPL(pVCpu) == pCtx->ss.Attr.n.u2Dpl);
149
150	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
151	/* Record any interrupt shadow of the nested-guest instruction into the nested-guest VMCB. */
152	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
153	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
154	{
155	pVmcbCtrl->IntShadow.n.u1IntShadow = 1;
156
157	/* Clear the inhibit-interrupt force-flag so as to not affect the outer guest. */
158	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
159	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pCtx->rip));
160	}
161
162	/*
163	* Save additional state and intercept information.
164	*/
165	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
166	{
167	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
168	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
169	}
170	else
171	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
172
173	/** @todo Save V_TPR, V_IRQ. */
174	/** @todo NRIP. */
175
176	/* Save exit information. */
177	pVmcbCtrl->u64ExitCode = uExitCode;
178	pVmcbCtrl->u64ExitInfo1 = uExitInfo1;
179	pVmcbCtrl->u64ExitInfo2 = uExitInfo2;
180
181	/*
182	* Update the exit interrupt information field if this #VMEXIT happened as a result
183	* of delivering an event.
184	*/
185	{
186	uint8_t uExitIntVector;
187	uint32_t uExitIntErr;
188	uint32_t fExitIntFlags;
189	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
190	NULL /* uExitIntCr2 */);
191	pVmcbCtrl->ExitIntInfo.n.u1Valid = fRaisingEvent;
192	if (fRaisingEvent)
193	{
194	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
195	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
196	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
197	{
198	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
199	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
200	}
201	}
202	}
203
204	/*
205	* Clear event injection in the VMCB.
206	*/
207	pVmcbCtrl->EventInject.n.u1Valid = 0;
208
209	/*
210	* Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
211	* would have modified some VMCB state) that need to be restored on #VMEXIT before
212	* writing the VMCB back to guest memory.
213	*/
214	HMSvmNstGstVmExitNotify(pVCpu, pCtx);
215
216	/*
217	* Write back the nested-guest's VMCB to its guest physical memory location.
218	*/
219	VBOXSTRICTRC rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, pVmcbNstGst,
220	sizeof(*pVmcbNstGst));
221	/*
222	* Prepare for guest's "host mode" by clearing internal processor state bits.
223	*
224	* We don't need to zero out the state-save area, just the controls should be
225	* sufficient because it has the critical bit of indicating whether we're inside
226	* the nested-guest or not.
227	*/
228	memset(pVmcbNstGstCtrl, 0, sizeof(*pVmcbNstGstCtrl));
229	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
230
231	/*
232	* Restore the subset of force-flags that were preserved.
233	*/
234	if (pCtx->hwvirt.fLocalForcedActions)
235	{
236	VMCPU_FF_SET(pVCpu, pCtx->hwvirt.fLocalForcedActions);
237	pCtx->hwvirt.fLocalForcedActions = 0;
238	}
239
240	if (RT_SUCCESS(rcStrict))
241	{
242	/** @todo Nested paging. */
243	/** @todo ASID. */
244
245	/*
246	* Reload the guest's "host state".
247	*/
248	CPUMSvmVmExitRestoreHostState(pVCpu, pCtx);
249
250	/*
251	* Update PGM, IEM and others of a world-switch.
252	*/
253	rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
254	if (rcStrict == VINF_SUCCESS)
255	return VINF_SVM_VMEXIT;
256
257	if (RT_SUCCESS(rcStrict))
258	{
259	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", rcStrict));
260	iemSetPassUpStatus(pVCpu, rcStrict);
261	return VINF_SVM_VMEXIT;
262	}
263
264	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
265	}
266	else
267	LogFlow(("iemSvmVmexit: Writing VMCB at %#RGp failed. rc=%Rrc\n", pCtx->hwvirt.svm.GCPhysVmcb,
268	VBOXSTRICTRC_VAL(rcStrict)));
269
270	return VERR_SVM_VMEXIT_FAILED;
271	}
272
273	Log(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode,
274	uExitInfo1, uExitInfo2));
275	AssertMsgFailed(("iemSvmVmexit: Unexpected SVM-exit failure uExitCode=%#RX64\n", uExitCode));
276	return VERR_SVM_IPE_5;
277	}
278
279
280	/**
281	* Performs the operations necessary that are part of the vmrun instruction
282	* execution in the guest.
283	*
284	* @returns Strict VBox status code (i.e. informational status codes too).
285	* @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
286	* code execution.
287	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
288	* (SVM_EXIT_INVALID most likely).
289	*
290	* @param pVCpu The cross context virtual CPU structure.
291	* @param pCtx Pointer to the guest-CPU context.
292	* @param cbInstr The length of the VMRUN instruction.
293	* @param GCPhysVmcb Guest physical address of the VMCB to run.
294	*/
295	IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
296	{
297	LogFlow(("iemSvmVmrun\n"));
298
299	#ifdef IN_RING0
300	/*
301	* Until PGM can handle switching the guest paging mode in ring-0,
302	* there's no point in trying to emulate VMRUN in ring-0 as we have
303	* to go back to ring-3 anyway, see @bugref{7243#c48}.
304	*/
305	RT_NOREF(pVCpu, pCtx, cbInstr, GCPhysVmcb);
306	return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
307	#else
308
309	/*
310	* Cache the physical address of the VMCB for #VMEXIT exceptions.
311	*/
312	pCtx->hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
313
314	/*
315	* Save the host state.
316	*/
317	CPUMSvmVmRunSaveHostState(pCtx, cbInstr);
318
319	/*
320	* Read the guest VMCB state.
321	*/
322	PVM pVM = pVCpu->CTX_SUFF(pVM);
323	int rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pVmcb), GCPhysVmcb, sizeof(SVMVMCB));
324	if (RT_SUCCESS(rc))
325	{
326	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
327	PSVMVMCBSTATESAVE pVmcbNstGst = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->guest;
328
329	/*
330	* Validate guest-state and controls.
331	*/
332	/* VMRUN must always be intercepted. */
333	if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
334	{
335	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
336	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
337	}
338
339	/* Nested paging. */
340	if ( pVmcbCtrl->NestedPaging.n.u1NestedPaging
341	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
342	{
343	Log(("iemSvmVmrun: Nested paging not supported -> #VMEXIT\n"));
344	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
345	}
346
347	/* AVIC. */
348	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
349	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
350	{
351	Log(("iemSvmVmrun: AVIC not supported -> #VMEXIT\n"));
352	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
353	}
354
355	/* Last branch record (LBR) virtualization. */
356	if ( pVmcbCtrl->LbrVirt.n.u1LbrVirt
357	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
358	{
359	Log(("iemSvmVmrun: LBR virtualization not supported -> #VMEXIT\n"));
360	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
361	}
362
363	/* Virtualized VMSAVE/VMLOAD. */
364	if ( pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload
365	&& !pVM->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
366	{
367	Log(("iemSvmVmrun: Virtualized VMSAVE/VMLOAD not supported -> #VMEXIT\n"));
368	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
369	}
370
371	/* Virtual GIF. */
372	if ( pVmcbCtrl->IntCtrl.n.u1VGifEnable
373	&& !pVM->cpum.ro.GuestFeatures.fSvmVGif)
374	{
375	Log(("iemSvmVmrun: Virtual GIF not supported -> #VMEXIT\n"));
376	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
377	}
378
379	/* Guest ASID. */
380	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
381	{
382	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
383	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
384	}
385
386	/* IO permission bitmap. */
387	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
388	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
389	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
390	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
391	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
392	{
393	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
394	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
395	}
396
397	/* MSR permission bitmap. */
398	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
399	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
400	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
401	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
402	{
403	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
404	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
405	}
406
407	/* CR0. */
408	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
409	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
410	{
411	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
412	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
413	}
414	if (pVmcbNstGst->u64CR0 >> 32)
415	{
416	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
417	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
418	}
419	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
420
421	/* DR6 and DR7. */
422	if ( pVmcbNstGst->u64DR6 >> 32
423	\|\| pVmcbNstGst->u64DR7 >> 32)
424	{
425	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
426	pVmcbNstGst->u64DR6));
427	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
428	}
429
430	/** @todo gPAT MSR validation? */
431
432	/*
433	* Copy the IO permission bitmap into the cache.
434	*/
435	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap));
436	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap), GCPhysIOBitmap,
437	SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
438	if (RT_FAILURE(rc))
439	{
440	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
441	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
442	}
443
444	/*
445	* Copy the MSR permission bitmap into the cache.
446	*/
447	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap));
448	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap), GCPhysMsrBitmap,
449	SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
450	if (RT_FAILURE(rc))
451	{
452	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
453	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
454	}
455
456	/*
457	* Copy segments from nested-guest VMCB state to the guest-CPU state.
458	*
459	* We do this here as we need to use the CS attributes and it's easier this way
460	* then using the VMCB format selectors. It doesn't really matter where we copy
461	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
462	*/
463	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, ES, es);
464	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, CS, cs);
465	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, SS, ss);
466	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, DS, ds);
467
468	/** @todo Segment attribute overrides by VMRUN. */
469
470	/*
471	* CPL adjustments and overrides.
472	*
473	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
474	* We shall thus adjust both CS.DPL and SS.DPL here.
475	*/
476	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
477	if (CPUMIsGuestInV86ModeEx(pCtx))
478	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 3;
479	if (CPUMIsGuestInRealModeEx(pCtx))
480	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 0;
481	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
482
483	/*
484	* Continue validating guest-state and controls.
485	*
486	* We pass CR0 as 0 to CPUMQueryValidatedGuestEfer below to skip the illegal
487	* EFER.LME bit transition check. We pass the nested-guest's EFER as both the
488	* old and new EFER value to not have any guest EFER bits influence the new
489	* nested-guest EFER.
490	*/
491	uint64_t uValidEfer;
492	rc = CPUMQueryValidatedGuestEfer(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
493	if (RT_FAILURE(rc))
494	{
495	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
496	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
497	}
498
499	/* Validate paging and CPU mode bits. */
500	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
501	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
502	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
503	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
504	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
505	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
506	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
507	bool const fLongModeConformCS = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
508	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
509	if (fLongModeWithPaging)
510	uValidEfer \|= MSR_K6_EFER_LMA;
511	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
512	if ( !fSvm
513	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
514	\|\| (fLongModeWithPaging && !fPae)
515	\|\| (fLongModeWithPaging && !fProtMode)
516	\|\| ( fLongModeEnabled
517	&& fPaging
518	&& fPae
519	&& fLongModeConformCS))
520	{
521	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
522	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
523	}
524
525	/*
526	* Preserve the required force-flags.
527	*
528	* We only preserve the force-flags that would affect the execution of the
529	* nested-guest (or the guest).
530	*
531	* - VMCPU_FF_INHIBIT_INTERRUPTS need -not- be preserved as it's for a single
532	* instruction which is this VMRUN instruction itself.
533	*
534	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
535	* execution of a subsequent IRET instruction in the guest.
536	*
537	* - The remaining FFs (e.g. timers) can stay in place so that we will be
538	* able to generate interrupts that should cause #VMEXITs for the
539	* nested-guest.
540	*/
541	pCtx->hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
542	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
543
544	/*
545	* Interrupt shadow.
546	*/
547	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
548	{
549	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
550	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
551	EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
552	}
553
554	/*
555	* TLB flush control.
556	* Currently disabled since it's redundant as we unconditionally flush the TLB
557	* in iemSvmWorldSwitch() below.
558	*/
559	#if 0
560	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
561	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
562	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
563	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
564	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
565	#endif
566
567	/*
568	* Copy the remaining guest state from the VMCB to the guest-CPU context.
569	*/
570	pCtx->gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
571	pCtx->gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
572	pCtx->idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
573	pCtx->idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
574	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
575	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
576	pCtx->cr3 = pVmcbNstGst->u64CR3;
577	pCtx->cr2 = pVmcbNstGst->u64CR2;
578	pCtx->dr[6] = pVmcbNstGst->u64DR6;
579	pCtx->dr[7] = pVmcbNstGst->u64DR7;
580	pCtx->rflags.u64 = pVmcbNstGst->u64RFlags;
581	pCtx->rax = pVmcbNstGst->u64RAX;
582	pCtx->rsp = pVmcbNstGst->u64RSP;
583	pCtx->rip = pVmcbNstGst->u64RIP;
584	CPUMSetGuestMsrEferNoCheck(pVCpu, pCtx->msrEFER, uValidEfer);
585
586	/* Mask DR6, DR7 bits mandatory set/clear bits. */
587	pCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
588	pCtx->dr[6] \|= X86_DR6_RA1_MASK;
589	pCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
590	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
591
592	/*
593	* Check for pending virtual interrupts.
594	*/
595	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
596	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
597	else
598	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
599
600	/*
601	* Update PGM, IEM and others of a world-switch.
602	*/
603	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
604	if (rcStrict == VINF_SUCCESS)
605	{ /* likely */ }
606	else if (RT_SUCCESS(rcStrict))
607	{
608	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
609	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
610	}
611	else
612	{
613	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
614	return rcStrict;
615	}
616
617	/*
618	* Clear global interrupt flags to allow interrupts in the guest.
619	*/
620	pCtx->hwvirt.svm.fGif = true;
621
622	/*
623	* Event injection.
624	*/
625	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
626	pCtx->hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
627	if (pEventInject->n.u1Valid)
628	{
629	uint8_t const uVector = pEventInject->n.u8Vector;
630	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject);
631	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
632
633	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
634	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
635	{
636	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
637	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
638	}
639	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
640	{
641	if ( uVector == X86_XCPT_NMI
642	\|\| uVector > X86_XCPT_LAST)
643	{
644	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
645	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
646	}
647	if ( uVector == X86_XCPT_BR
648	&& CPUMIsGuestInLongModeEx(pCtx))
649	{
650	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
651	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
652	}
653	/** @todo any others? */
654	}
655
656	/*
657	* Update the exit interruption info field so that if an exception occurs
658	* while delivering the event causing a #VMEXIT, we only need to update
659	* the valid bit while the rest is already in place.
660	*/
661	pVmcbCtrl->ExitIntInfo.u = pVmcbCtrl->EventInject.u;
662	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
663
664	/** @todo NRIP: Software interrupts can only be pushed properly if we support
665	* NRIP for the nested-guest to calculate the instruction length
666	* below. */
667	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 uVector=%#x enmType=%d uErrorCode=%u cr2=%#RX64 efer=%#RX64\n",
668	pCtx->cs.Sel, pCtx->rip, uVector, enmType, uErrorCode, pCtx->cr2, pCtx->msrEFER));
669	rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
670	}
671	else
672	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
673	pCtx->cs.Sel, pCtx->rip, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->msrEFER, pCtx->rflags.u64));
674
675	LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
676	return rcStrict;
677	}
678
679	/* Shouldn't really happen as the caller should've validated the physical address already. */
680	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
681	return rc;
682	#endif
683	}
684
685
686	#if 0
687	/**
688	* Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
689	* intercept is active.
690	*
691	* @returns Strict VBox status code.
692	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
693	* we're not executing a nested-guest.
694	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
695	* successfully.
696	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
697	* failed and a shutdown needs to be initiated for the geust.
698	*
699	* @param pVCpu The cross context virtual CPU structure.
700	* @param pCtx The guest-CPU context.
701	* @param uExitCode The SVM exit code (see SVM_EXIT_XXX).
702	* @param uExitInfo1 The exit info. 1 field.
703	* @param uExitInfo2 The exit info. 2 field.
704	*/
705	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
706	uint64_t uExitInfo2)
707	{
708	#define HMSVM_CTRL_INTERCEPT_VMEXIT(a_Intercept) \
709	do { \
710	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \
711	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \
712	break; \
713	} while (0)
714
715	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
716	return VINF_HM_INTERCEPT_NOT_ACTIVE;
717
718	switch (uExitCode)
719	{
720	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
721	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
722	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
723	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15:
724	case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
725	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
726	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27:
727	case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
728	{
729	if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0)))
730	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
731	break;
732	}
733
734	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
735	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
736	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
737	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
738	{
739	if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0))
740	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
741	break;
742	}
743
744	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
745	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
746	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
747	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
748	{
749	if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0))
750	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
751	break;
752	}
753
754	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
755	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
756	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
757	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
758	{
759	if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0))
760	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
761	break;
762	}
763
764	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
765	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
766	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
767	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
768	{
769	if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0))
770	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
771	break;
772	}
773
774	case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTR);
775	case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_NMI);
776	case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SMI);
777	case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INIT);
778	case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VINTR);
779	case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES);
780	case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_READS);
781	case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_READS);
782	case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_READS);
783	case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_READS);
784	case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_WRITES);
785	case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_WRITES);
786	case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_WRITES);
787	case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_WRITES);
788	case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSC);
789	case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDPMC);
790	case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PUSHF);
791	case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_POPF);
792	case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CPUID);
793	case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RSM);
794	case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IRET);
795	case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTN);
796	case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVD);
797	case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PAUSE);
798	case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_HLT);
799	case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPG);
800	case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPGA);
801	case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TASK_SWITCH);
802	case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_FERR_FREEZE);
803	case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SHUTDOWN);
804	case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMRUN);
805	case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMMCALL);
806	case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMLOAD);
807	case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMSAVE);
808	case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_STGI);
809	case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CLGI);
810	case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SKINIT);
811	case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSCP);
812	case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_ICEBP);
813	case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_WBINVD);
814	case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MONITOR);
815	case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT);
816	case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT_ARMED);
817	case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_XSETBV);
818
819	case SVM_EXIT_IOIO:
820	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
821	return VERR_SVM_IPE_1;
822
823	case SVM_EXIT_MSR:
824	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
825	return VERR_SVM_IPE_1;
826
827	case SVM_EXIT_NPF:
828	case SVM_EXIT_AVIC_INCOMPLETE_IPI:
829	case SVM_EXIT_AVIC_NOACCEL:
830	AssertMsgFailed(("Todo Implement.\n"));
831	return VERR_SVM_IPE_1;
832
833	default:
834	AssertMsgFailed(("Unsupported SVM exit code %#RX64\n", uExitCode));
835	return VERR_SVM_IPE_1;
836	}
837
838	return VINF_HM_INTERCEPT_NOT_ACTIVE;
839
840	#undef HMSVM_CTRL_INTERCEPT_VMEXIT
841	}
842	#endif
843
844
845	/**
846	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
847	* intercept is active.
848	*
849	* @returns Strict VBox status code.
850	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
851	* we're not executing a nested-guest.
852	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
853	* successfully.
854	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
855	* failed and a shutdown needs to be initiated for the geust.
856	*
857	* @returns VBox strict status code.
858	* @param pVCpu The cross context virtual CPU structure of the calling thread.
859	* @param u16Port The IO port being accessed.
860	* @param enmIoType The type of IO access.
861	* @param cbReg The IO operand size in bytes.
862	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
863	* @param iEffSeg The effective segment number.
864	* @param fRep Whether this is a repeating IO instruction (REP prefix).
865	* @param fStrIo Whether this is a string IO instruction.
866	* @param cbInstr The length of the IO instruction in bytes.
867	*/
868	IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr,
869	uint64_t uCr2)
870	{
871	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
872
873	/*
874	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
875	*
876	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_EXCEPTION_2 #VMEXITs.
877	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
878	* even when they use a vector in the range 0 to 31.
879	* - ICEBP should not trigger #DB intercept, but its own intercept.
880	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
881	*/
882	/* Check NMI intercept */
883	if ( u8Vector == X86_XCPT_NMI
884	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
885	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
886	{
887	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
888	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
889	}
890
891	/* Check ICEBP intercept. */
892	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
893	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
894	{
895	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
896	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
897	}
898
899	/* Check CPU exception intercepts. */
900	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
901	&& IEM_IS_SVM_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
902	{
903	Assert(u8Vector <= X86_XCPT_LAST);
904	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
905	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
906	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
907	&& u8Vector == X86_XCPT_PF
908	&& !(uErr & X86_TRAP_PF_ID))
909	{
910	/** @todo Nested-guest SVM - figure out fetching op-code bytes from IEM. */
911	#ifdef IEM_WITH_CODE_TLB
912	AssertReleaseFailedReturn(VERR_IEM_IPE_5);
913	#else
914	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
915	uint8_t const offOpCode = pVCpu->iem.s.offOpcode;
916	uint8_t const cbCurrent = pVCpu->iem.s.cbOpcode - pVCpu->iem.s.offOpcode;
917	if ( cbCurrent > 0
918	&& cbCurrent < sizeof(pVmcbCtrl->abInstr))
919	{
920	Assert(cbCurrent <= sizeof(pVCpu->iem.s.abOpcode));
921	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[offOpCode], cbCurrent);
922	}
923	#endif
924	}
925	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
926	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u32InterceptXcpt,
927	u8Vector, uExitInfo1, uExitInfo2));
928	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_EXCEPTION_0 + u8Vector, uExitInfo1, uExitInfo2);
929	}
930
931	/* Check software interrupt (INTn) intercepts. */
932	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
933	\| IEM_XCPT_FLAGS_BP_INSTR
934	\| IEM_XCPT_FLAGS_ICEBP_INSTR
935	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
936	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
937	{
938	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
939	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
940	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
941	}
942
943	return VINF_HM_INTERCEPT_NOT_ACTIVE;
944	}
945
946
947	/**
948	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
949	* corresponding intercept is active.
950	*
951	* @returns Strict VBox status code.
952	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
953	* we're not executing a nested-guest.
954	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
955	* successfully.
956	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
957	* failed and a shutdown needs to be initiated for the geust.
958	*
959	* @returns VBox strict status code.
960	* @param pVCpu The cross context virtual CPU structure of the calling thread.
961	* @param u16Port The IO port being accessed.
962	* @param enmIoType The type of IO access.
963	* @param cbReg The IO operand size in bytes.
964	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
965	* @param iEffSeg The effective segment number.
966	* @param fRep Whether this is a repeating IO instruction (REP prefix).
967	* @param fStrIo Whether this is a string IO instruction.
968	* @param cbInstr The length of the IO instruction in bytes.
969	*/
970	IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPU pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
971	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
972	{
973	Assert(IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
974	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
975	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
976
977	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
978
979	SVMIOIOEXITINFO IoExitInfo;
980	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
981	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
982	bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
983	&IoExitInfo);
984	if (fIntercept)
985	{
986	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
987	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_IOIO, IoExitInfo.u, pCtx->rip + cbInstr);
988	}
989
990	/** @todo remove later (for debugging as VirtualBox always traps all IO
991	* intercepts). */
992	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
993	return VINF_HM_INTERCEPT_NOT_ACTIVE;
994	}
995
996
997	/**
998	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
999	* corresponding intercept is active.
1000	*
1001	* @returns Strict VBox status code.
1002	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1003	* specify interception of the accessed MSR @a idMsr.
1004	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1005	* successfully.
1006	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1007	* failed and a shutdown needs to be initiated for the geust.
1008	*
1009	* @param pVCpu The cross context virtual CPU structure.
1010	* @param pCtx The guest-CPU context.
1011	* @param idMsr The MSR being accessed in the nested-guest.
1012	* @param fWrite Whether this is an MSR write access, @c false implies an
1013	* MSR read.
1014	*/
1015	IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
1016	{
1017	/*
1018	* Check if any MSRs are being intercepted.
1019	*/
1020	Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT));
1021	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1022
1023	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1024
1025	/*
1026	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1027	*/
1028	uint16_t offMsrpm;
1029	uint32_t uMsrpmBit;
1030	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1031	if (RT_SUCCESS(rc))
1032	{
1033	Assert(uMsrpmBit < 0x3fff);
1034	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1035	if (fWrite)
1036	++uMsrpmBit;
1037
1038	/*
1039	* Check if the bit is set, if so, trigger a #VMEXIT.
1040	*/
1041	uint8_t pbMsrpm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1042	pbMsrpm += offMsrpm;
1043	if (ASMBitTest(pbMsrpm, uMsrpmBit))
1044	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1045	}
1046	else
1047	{
1048	/*
1049	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1050	*/
1051	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1052	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1053	}
1054	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1055	}
1056
1057
1058
1059	/**
1060	* Implements 'VMRUN'.
1061	*/
1062	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1063	{
1064	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1065	RT_NOREF2(pVCpu, cbInstr);
1066	return VINF_EM_RAW_EMULATE_INSTR;
1067	#else
1068	LogFlow(("iemCImpl_vmrun\n"));
1069	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1070	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1071
1072	/** @todo Check effective address size using address size prefix. */
1073	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1074	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1075	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1076	{
1077	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1078	return iemRaiseGeneralProtectionFault0(pVCpu);
1079	}
1080
1081	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1082	{
1083	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1084	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1085	}
1086
1087	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, pCtx, cbInstr, GCPhysVmcb);
1088	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1089	{
1090	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1091	rcStrict = VINF_EM_TRIPLE_FAULT;
1092	}
1093	return rcStrict;
1094	#endif
1095	}
1096
1097
1098	/**
1099	* Implements 'VMMCALL'.
1100	*/
1101	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1102	{
1103	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1104	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1105	{
1106	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1107	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1108	}
1109
1110	bool fUpdatedRipAndRF;
1111	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fUpdatedRipAndRF);
1112	if (RT_SUCCESS(rcStrict))
1113	{
1114	if (!fUpdatedRipAndRF)
1115	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1116	return rcStrict;
1117	}
1118
1119	return iemRaiseUndefinedOpcode(pVCpu);
1120	}
1121
1122
1123	/**
1124	* Implements 'VMLOAD'.
1125	*/
1126	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1127	{
1128	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1129	RT_NOREF2(pVCpu, cbInstr);
1130	return VINF_EM_RAW_EMULATE_INSTR;
1131	#else
1132	LogFlow(("iemCImpl_vmload\n"));
1133	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1134	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1135
1136	/** @todo Check effective address size using address size prefix. */
1137	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1138	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1139	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1140	{
1141	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1142	return iemRaiseGeneralProtectionFault0(pVCpu);
1143	}
1144
1145	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1146	{
1147	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1148	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1149	}
1150
1151	SVMVMCBSTATESAVE VmcbNstGst;
1152	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1153	sizeof(SVMVMCBSTATESAVE));
1154	if (rcStrict == VINF_SUCCESS)
1155	{
1156	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1157	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, FS, fs);
1158	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, GS, gs);
1159	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, TR, tr);
1160	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1161
1162	pCtx->msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1163	pCtx->msrSTAR = VmcbNstGst.u64STAR;
1164	pCtx->msrLSTAR = VmcbNstGst.u64LSTAR;
1165	pCtx->msrCSTAR = VmcbNstGst.u64CSTAR;
1166	pCtx->msrSFMASK = VmcbNstGst.u64SFMASK;
1167
1168	pCtx->SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1169	pCtx->SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1170	pCtx->SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1171
1172	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1173	}
1174	return rcStrict;
1175	#endif
1176	}
1177
1178
1179	/**
1180	* Implements 'VMSAVE'.
1181	*/
1182	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1183	{
1184	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1185	RT_NOREF2(pVCpu, cbInstr);
1186	return VINF_EM_RAW_EMULATE_INSTR;
1187	#else
1188	LogFlow(("iemCImpl_vmsave\n"));
1189	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1190	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1191
1192	/** @todo Check effective address size using address size prefix. */
1193	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1194	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1195	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1196	{
1197	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1198	return iemRaiseGeneralProtectionFault0(pVCpu);
1199	}
1200
1201	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1202	{
1203	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1204	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1205	}
1206
1207	SVMVMCBSTATESAVE VmcbNstGst;
1208	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1209	sizeof(SVMVMCBSTATESAVE));
1210	if (rcStrict == VINF_SUCCESS)
1211	{
1212	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1213	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, FS, fs);
1214	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, GS, gs);
1215	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, TR, tr);
1216	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1217
1218	VmcbNstGst.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1219	VmcbNstGst.u64STAR = pCtx->msrSTAR;
1220	VmcbNstGst.u64LSTAR = pCtx->msrLSTAR;
1221	VmcbNstGst.u64CSTAR = pCtx->msrCSTAR;
1222	VmcbNstGst.u64SFMASK = pCtx->msrSFMASK;
1223
1224	VmcbNstGst.u64SysEnterCS = pCtx->SysEnter.cs;
1225	VmcbNstGst.u64SysEnterESP = pCtx->SysEnter.esp;
1226	VmcbNstGst.u64SysEnterEIP = pCtx->SysEnter.eip;
1227
1228	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1229	sizeof(SVMVMCBSTATESAVE));
1230	if (rcStrict == VINF_SUCCESS)
1231	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1232	}
1233	return rcStrict;
1234	#endif
1235	}
1236
1237
1238	/**
1239	* Implements 'CLGI'.
1240	*/
1241	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1242	{
1243	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1244	RT_NOREF2(pVCpu, cbInstr);
1245	return VINF_EM_RAW_EMULATE_INSTR;
1246	#else
1247	LogFlow(("iemCImpl_clgi\n"));
1248	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1249	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1250	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1251	{
1252	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1253	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1254	}
1255
1256	pCtx->hwvirt.svm.fGif = false;
1257	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1258
1259	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1260	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1261	# else
1262	return VINF_SUCCESS;
1263	# endif
1264	#endif
1265	}
1266
1267
1268	/**
1269	* Implements 'STGI'.
1270	*/
1271	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1272	{
1273	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1274	RT_NOREF2(pVCpu, cbInstr);
1275	return VINF_EM_RAW_EMULATE_INSTR;
1276	#else
1277	LogFlow(("iemCImpl_stgi\n"));
1278	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1279	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1280	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1281	{
1282	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1283	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1284	}
1285
1286	pCtx->hwvirt.svm.fGif = true;
1287	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1288
1289	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1290	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1291	# else
1292	return VINF_SUCCESS;
1293	# endif
1294	#endif
1295	}
1296
1297
1298	/**
1299	* Implements 'INVLPGA'.
1300	*/
1301	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1302	{
1303	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1304	/** @todo Check effective address size using address size prefix. */
1305	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1306	/** @todo PGM needs virtual ASID support. */
1307	#if 0
1308	uint32_t const uAsid = pCtx->ecx;
1309	#endif
1310
1311	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1312	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1313	{
1314	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1315	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1316	}
1317
1318	PGMInvalidatePage(pVCpu, GCPtrPage);
1319	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1320	return VINF_SUCCESS;
1321	}
1322
1323
1324	/**
1325	* Implements 'SKINIT'.
1326	*/
1327	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1328	{
1329	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1330
1331	uint32_t uIgnore;
1332	uint32_t fFeaturesECX;
1333	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1334	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1335	return iemRaiseUndefinedOpcode(pVCpu);
1336
1337	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1338	{
1339	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1340	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1341	}
1342
1343	RT_NOREF(cbInstr);
1344	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1345	}
1346

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 70416

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