IEMAllCImplSvmInstr.cpp.h@ 71078

Last change on this file since 71078 was 71069, checked in by vboxsync, 7 years ago
VMM/IEM: Nested Hw.virt: Update number of bytes fetched for SVM decode assist on intercepted #PFs. Still todo/WIP when fewer than 15 bytes are present in the opcode cache.
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1	/* $Id: IEMAllCImplSvmInstr.cpp.h 71069 2018-02-20 10:53:58Z vboxsync $ */
2	/** @file
3	* IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/**
20	* Converts an IEM exception event type to an SVM event type.
21	*
22	* @returns The SVM event type.
23	* @retval UINT8_MAX if the specified type of event isn't among the set
24	* of recognized IEM event types.
25	*
26	* @param uVector The vector of the event.
27	* @param fIemXcptFlags The IEM exception / interrupt flags.
28	*/
29	IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
30	{
31	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
32	{
33	if (uVector != X86_XCPT_NMI)
34	return SVM_EVENT_EXCEPTION;
35	return SVM_EVENT_NMI;
36	}
37
38	/* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
39	if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR \| IEM_XCPT_FLAGS_ICEBP_INSTR \| IEM_XCPT_FLAGS_OF_INSTR))
40	return SVM_EVENT_EXCEPTION;
41
42	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
43	return SVM_EVENT_EXTERNAL_IRQ;
44
45	if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
46	return SVM_EVENT_SOFTWARE_INT;
47
48	AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
49	return UINT8_MAX;
50	}
51
52
53	/**
54	* Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
55	*
56	* @returns Strict VBox status code.
57	* @param pVCpu The cross context virtual CPU structure.
58	* @param pCtx The guest-CPU context.
59	*/
60	DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPU pVCpu, PCPUMCTX pCtx)
61	{
62	/*
63	* Inform PGM about paging mode changes.
64	* We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
65	* see comment in iemMemPageTranslateAndCheckAccess().
66	*/
67	int rc = PGMChangeMode(pVCpu, pCtx->cr0 \| X86_CR0_PE, pCtx->cr4, pCtx->msrEFER);
68	#ifdef IN_RING3
69	Assert(rc != VINF_PGM_CHANGE_MODE);
70	#endif
71	AssertRCReturn(rc, rc);
72
73	/* Inform CPUM (recompiler), can later be removed. */
74	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
75
76	/*
77	* Flush the TLB with new CR3. This is required in case the PGM mode change
78	* above doesn't actually change anything.
79	*/
80	if (rc == VINF_SUCCESS)
81	{
82	rc = PGMFlushTLB(pVCpu, pCtx->cr3, true);
83	AssertRCReturn(rc, rc);
84	}
85
86	/* Re-initialize IEM cache/state after the drastic mode switch. */
87	iemReInitExec(pVCpu);
88	return rc;
89	}
90
91
92	/**
93	* SVM \#VMEXIT handler.
94	*
95	* @returns Strict VBox status code.
96	* @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
97	* @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
98	* "host state" and a shutdown is required.
99	*
100	* @param pVCpu The cross context virtual CPU structure.
101	* @param pCtx The guest-CPU context.
102	* @param uExitCode The exit code.
103	* @param uExitInfo1 The exit info. 1 field.
104	* @param uExitInfo2 The exit info. 2 field.
105	*/
106	IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
107	{
108	VBOXSTRICTRC rcStrict;
109	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
110	\|\| uExitCode == SVM_EXIT_INVALID)
111	{
112	LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pCtx->cs.Sel,
113	pCtx->rip, uExitCode, uExitInfo1, uExitInfo2));
114
115	/*
116	* Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
117	*/
118	pCtx->hwvirt.fGif = false;
119
120	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->es));
121	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
122	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
123	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ds));
124
125	/*
126	* Save the nested-guest state into the VMCB state-save area.
127	*/
128	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
129	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
130	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
131
132	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, ES, es);
133	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, CS, cs);
134	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, SS, ss);
135	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, pVmcbNstGstState, DS, ds);
136	pVmcbNstGstState->GDTR.u32Limit = pCtx->gdtr.cbGdt;
137	pVmcbNstGstState->GDTR.u64Base = pCtx->gdtr.pGdt;
138	pVmcbNstGstState->IDTR.u32Limit = pCtx->idtr.cbIdt;
139	pVmcbNstGstState->IDTR.u64Base = pCtx->idtr.pIdt;
140	pVmcbNstGstState->u64EFER = pCtx->msrEFER;
141	pVmcbNstGstState->u64CR4 = pCtx->cr4;
142	pVmcbNstGstState->u64CR3 = pCtx->cr3;
143	pVmcbNstGstState->u64CR2 = pCtx->cr2;
144	pVmcbNstGstState->u64CR0 = pCtx->cr0;
145	/** @todo Nested paging. */
146	pVmcbNstGstState->u64RFlags = pCtx->rflags.u64;
147	pVmcbNstGstState->u64RIP = pCtx->rip;
148	pVmcbNstGstState->u64RSP = pCtx->rsp;
149	pVmcbNstGstState->u64RAX = pCtx->rax;
150	pVmcbNstGstState->u64DR7 = pCtx->dr[7];
151	pVmcbNstGstState->u64DR6 = pCtx->dr[6];
152	pVmcbNstGstState->u8CPL = pCtx->ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
153	Assert(CPUMGetGuestCPL(pVCpu) == pCtx->ss.Attr.n.u2Dpl);
154
155	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
156
157	/*
158	* Save additional state and intercept information.
159	*
160	* - Interrupt shadow: Tracked using VMCPU_FF_INHIBIT_INTERRUPTS and RIP.
161	* - V_TPR: Already updated by iemCImpl_load_CrX or by the physical CPU for
162	* hardware-assisted SVM execution.
163	* - V_IRQ: Tracked using VMCPU_FF_INTERRUPT_NESTED_GUEST force-flag and updated below.
164	*/
165	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
166	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
167	{
168	pVmcbCtrl->IntShadow.n.u1IntShadow = 1;
169
170	/* Clear the inhibit-interrupt force-flag so as to not affect the outer guest. */
171	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
172	LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pCtx->rip));
173	}
174
175	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
176	{
177	Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
178	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
179	}
180	else
181	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
182
183	/** @todo NRIP. */
184
185	/* Save exit information. */
186	pVmcbCtrl->u64ExitCode = uExitCode;
187	pVmcbCtrl->u64ExitInfo1 = uExitInfo1;
188	pVmcbCtrl->u64ExitInfo2 = uExitInfo2;
189
190	/*
191	* Update the exit interrupt-information field if this #VMEXIT happened as a result
192	* of delivering an event through IEM.
193	*
194	* Don't update the exit interrupt-information field if the event wasn't being injected
195	* through IEM, as it may have been updated by real hardware if the nested-guest was
196	* executed using hardware-assisted SVM.
197	*/
198	{
199	uint8_t uExitIntVector;
200	uint32_t uExitIntErr;
201	uint32_t fExitIntFlags;
202	bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
203	NULL /* uExitIntCr2 */);
204	if (fRaisingEvent)
205	{
206	pVmcbCtrl->ExitIntInfo.n.u1Valid = 1;
207	pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
208	pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
209	if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
210	{
211	pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
212	pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
213	}
214	}
215	}
216
217	/*
218	* Clear event injection in the VMCB.
219	*/
220	pVmcbCtrl->EventInject.n.u1Valid = 0;
221
222	/*
223	* Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
224	* would have modified some VMCB state) that need to be restored on #VMEXIT before
225	* writing the VMCB back to guest memory.
226	*/
227	HMSvmNstGstVmExitNotify(pVCpu, pCtx);
228
229	/*
230	* Write back the nested-guest's VMCB to its guest physical memory location.
231	*/
232	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->hwvirt.svm.GCPhysVmcb, pVmcbNstGst, sizeof(*pVmcbNstGst));
233
234	/*
235	* Prepare for guest's "host mode" by clearing internal processor state bits.
236	*
237	* We don't need to zero out the state-save area, just the controls should be
238	* sufficient because it has the critical bit of indicating whether we're inside
239	* the nested-guest or not.
240	*/
241	memset(pVmcbNstGstCtrl, 0, sizeof(*pVmcbNstGstCtrl));
242	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
243
244	/*
245	* Restore the subset of force-flags that were preserved.
246	*/
247	if (pCtx->hwvirt.fLocalForcedActions)
248	{
249	VMCPU_FF_SET(pVCpu, pCtx->hwvirt.fLocalForcedActions);
250	pCtx->hwvirt.fLocalForcedActions = 0;
251	}
252
253	if (RT_SUCCESS(rcStrict))
254	{
255	/** @todo Nested paging. */
256	/** @todo ASID. */
257
258	/*
259	* Reload the guest's "host state".
260	*/
261	CPUMSvmVmExitRestoreHostState(pVCpu, pCtx);
262
263	/*
264	* Update PGM, IEM and others of a world-switch.
265	*/
266	rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
267	if (rcStrict == VINF_SUCCESS)
268	rcStrict = VINF_SVM_VMEXIT;
269	else if (RT_SUCCESS(rcStrict))
270	{
271	LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
272	iemSetPassUpStatus(pVCpu, rcStrict);
273	rcStrict = VINF_SVM_VMEXIT;
274	}
275	else
276	LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
277	}
278	else
279	{
280	LogFlow(("iemSvmVmexit: Writing VMCB at %#RGp failed. rc=%Rrc\n", pCtx->hwvirt.svm.GCPhysVmcb,
281	VBOXSTRICTRC_VAL(rcStrict)));
282	rcStrict = VERR_SVM_VMEXIT_FAILED;
283	}
284	}
285	else
286	{
287	Log(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode,
288	uExitInfo1, uExitInfo2));
289	AssertMsgFailed(("iemSvmVmexit: Unexpected SVM-exit failure uExitCode=%#RX64\n", uExitCode));
290	rcStrict = VERR_SVM_IPE_5;
291	}
292
293	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
294	/* CLGI/STGI may not have been intercepted and thus not executed in IEM. */
295	if (HMSvmIsVGifActive(pVCpu->CTX_SUFF(pVM)))
296	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
297	# endif
298	return rcStrict;
299	}
300
301
302	/**
303	* Performs the operations necessary that are part of the vmrun instruction
304	* execution in the guest.
305	*
306	* @returns Strict VBox status code (i.e. informational status codes too).
307	* @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
308	* code execution.
309	* @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
310	* (SVM_EXIT_INVALID most likely).
311	*
312	* @param pVCpu The cross context virtual CPU structure.
313	* @param pCtx Pointer to the guest-CPU context.
314	* @param cbInstr The length of the VMRUN instruction.
315	* @param GCPhysVmcb Guest physical address of the VMCB to run.
316	*/
317	IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
318	{
319	LogFlow(("iemSvmVmrun\n"));
320
321	#ifdef IN_RING0
322	/*
323	* Until PGM can handle switching the guest paging mode in ring-0,
324	* there's no point in trying to emulate VMRUN in ring-0 as we have
325	* to go back to ring-3 anyway, see @bugref{7243#c48}.
326	*/
327	RT_NOREF(pVCpu, pCtx, cbInstr, GCPhysVmcb);
328	return VERR_IEM_ASPECT_NOT_IMPLEMENTED;
329	#else
330
331	/*
332	* Cache the physical address of the VMCB for #VMEXIT exceptions.
333	*/
334	pCtx->hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
335
336	/*
337	* Save the host state.
338	*/
339	CPUMSvmVmRunSaveHostState(pCtx, cbInstr);
340
341	/*
342	* Read the guest VMCB state.
343	*/
344	PVM pVM = pVCpu->CTX_SUFF(pVM);
345	int rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pVmcb), GCPhysVmcb, sizeof(SVMVMCB));
346	if (RT_SUCCESS(rc))
347	{
348	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
349	PSVMVMCBSTATESAVE pVmcbNstGst = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->guest;
350
351	/*
352	* Validate guest-state and controls.
353	*/
354	/* VMRUN must always be intercepted. */
355	if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
356	{
357	Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
358	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
359	}
360
361	/* Nested paging. */
362	if ( pVmcbCtrl->NestedPaging.n.u1NestedPaging
363	&& !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
364	{
365	Log(("iemSvmVmrun: Nested paging not supported -> #VMEXIT\n"));
366	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
367	}
368
369	/* AVIC. */
370	if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
371	&& !pVM->cpum.ro.GuestFeatures.fSvmAvic)
372	{
373	Log(("iemSvmVmrun: AVIC not supported -> #VMEXIT\n"));
374	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
375	}
376
377	/* Last branch record (LBR) virtualization. */
378	if ( pVmcbCtrl->LbrVirt.n.u1LbrVirt
379	&& !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
380	{
381	Log(("iemSvmVmrun: LBR virtualization not supported -> #VMEXIT\n"));
382	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
383	}
384
385	/* Virtualized VMSAVE/VMLOAD. */
386	if ( pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload
387	&& !pVM->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
388	{
389	Log(("iemSvmVmrun: Virtualized VMSAVE/VMLOAD not supported -> #VMEXIT\n"));
390	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
391	}
392
393	/* Virtual GIF. */
394	if ( pVmcbCtrl->IntCtrl.n.u1VGifEnable
395	&& !pVM->cpum.ro.GuestFeatures.fSvmVGif)
396	{
397	Log(("iemSvmVmrun: Virtual GIF not supported -> #VMEXIT\n"));
398	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
399	}
400
401	/* Guest ASID. */
402	if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
403	{
404	Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
405	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
406	}
407
408	/* IO permission bitmap. */
409	RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
410	if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
411	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
412	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
413	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
414	{
415	Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
416	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
417	}
418
419	/* MSR permission bitmap. */
420	RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
421	if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
422	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
423	\|\| !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
424	{
425	Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
426	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
427	}
428
429	/* CR0. */
430	if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
431	&& (pVmcbNstGst->u64CR0 & X86_CR0_NW))
432	{
433	Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
434	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
435	}
436	if (pVmcbNstGst->u64CR0 >> 32)
437	{
438	Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
439	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
440	}
441	/** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
442
443	/* DR6 and DR7. */
444	if ( pVmcbNstGst->u64DR6 >> 32
445	\|\| pVmcbNstGst->u64DR7 >> 32)
446	{
447	Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
448	pVmcbNstGst->u64DR6));
449	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
450	}
451
452	/** @todo gPAT MSR validation? */
453
454	/*
455	* Copy the IO permission bitmap into the cache.
456	*/
457	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap));
458	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap), GCPhysIOBitmap,
459	SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
460	if (RT_FAILURE(rc))
461	{
462	Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
463	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
464	}
465
466	/*
467	* Copy the MSR permission bitmap into the cache.
468	*/
469	Assert(pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap));
470	rc = PGMPhysSimpleReadGCPhys(pVM, pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap), GCPhysMsrBitmap,
471	SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
472	if (RT_FAILURE(rc))
473	{
474	Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
475	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
476	}
477
478	/*
479	* Copy segments from nested-guest VMCB state to the guest-CPU state.
480	*
481	* We do this here as we need to use the CS attributes and it's easier this way
482	* then using the VMCB format selectors. It doesn't really matter where we copy
483	* the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
484	*/
485	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, ES, es);
486	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, CS, cs);
487	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, SS, ss);
488	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbNstGst, DS, ds);
489
490	/** @todo Segment attribute overrides by VMRUN. */
491
492	/*
493	* CPL adjustments and overrides.
494	*
495	* SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
496	* We shall thus adjust both CS.DPL and SS.DPL here.
497	*/
498	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
499	if (CPUMIsGuestInV86ModeEx(pCtx))
500	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 3;
501	if (CPUMIsGuestInRealModeEx(pCtx))
502	pCtx->cs.Attr.n.u2Dpl = pCtx->ss.Attr.n.u2Dpl = 0;
503	Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->ss));
504
505	/*
506	* Continue validating guest-state and controls.
507	*
508	* We pass CR0 as 0 to CPUMQueryValidatedGuestEfer below to skip the illegal
509	* EFER.LME bit transition check. We pass the nested-guest's EFER as both the
510	* old and new EFER value to not have any guest EFER bits influence the new
511	* nested-guest EFER.
512	*/
513	uint64_t uValidEfer;
514	rc = CPUMQueryValidatedGuestEfer(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
515	if (RT_FAILURE(rc))
516	{
517	Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
518	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
519	}
520
521	/* Validate paging and CPU mode bits. */
522	bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
523	bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
524	bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
525	bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
526	bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
527	bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
528	bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
529	bool const fLongModeConformCS = pCtx->cs.Attr.n.u1Long && pCtx->cs.Attr.n.u1DefBig;
530	/* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
531	if (fLongModeWithPaging)
532	uValidEfer \|= MSR_K6_EFER_LMA;
533	bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME \| MSR_K6_EFER_LMA));
534	if ( !fSvm
535	\|\| (!fLongModeSupported && fLongModeActiveOrEnabled)
536	\|\| (fLongModeWithPaging && !fPae)
537	\|\| (fLongModeWithPaging && !fProtMode)
538	\|\| ( fLongModeEnabled
539	&& fPaging
540	&& fPae
541	&& fLongModeConformCS))
542	{
543	Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
544	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
545	}
546
547	/*
548	* Preserve the required force-flags.
549	*
550	* We only preserve the force-flags that would affect the execution of the
551	* nested-guest (or the guest).
552	*
553	* - VMCPU_FF_INHIBIT_INTERRUPTS need -not- be preserved as it's for a single
554	* instruction which is this VMRUN instruction itself.
555	*
556	* - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
557	* execution of a subsequent IRET instruction in the guest.
558	*
559	* - The remaining FFs (e.g. timers) can stay in place so that we will be
560	* able to generate interrupts that should cause #VMEXITs for the
561	* nested-guest.
562	*/
563	pCtx->hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
564	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
565
566	/*
567	* Interrupt shadow.
568	*/
569	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
570	{
571	LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
572	/** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
573	EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
574	}
575
576	/*
577	* TLB flush control.
578	* Currently disabled since it's redundant as we unconditionally flush the TLB
579	* in iemSvmWorldSwitch() below.
580	*/
581	#if 0
582	/** @todo @bugref{7243}: ASID based PGM TLB flushes. */
583	if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
584	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
585	\|\| pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
586	PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
587	#endif
588
589	/*
590	* Copy the remaining guest state from the VMCB to the guest-CPU context.
591	*/
592	pCtx->gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
593	pCtx->gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
594	pCtx->idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
595	pCtx->idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
596	CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
597	CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
598	pCtx->cr3 = pVmcbNstGst->u64CR3;
599	pCtx->cr2 = pVmcbNstGst->u64CR2;
600	pCtx->dr[6] = pVmcbNstGst->u64DR6;
601	pCtx->dr[7] = pVmcbNstGst->u64DR7;
602	pCtx->rflags.u64 = pVmcbNstGst->u64RFlags;
603	pCtx->rax = pVmcbNstGst->u64RAX;
604	pCtx->rsp = pVmcbNstGst->u64RSP;
605	pCtx->rip = pVmcbNstGst->u64RIP;
606	CPUMSetGuestMsrEferNoCheck(pVCpu, pCtx->msrEFER, uValidEfer);
607
608	/* Mask DR6, DR7 bits mandatory set/clear bits. */
609	pCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
610	pCtx->dr[6] \|= X86_DR6_RA1_MASK;
611	pCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
612	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
613
614	/*
615	* Check for pending virtual interrupts.
616	*/
617	if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
618	VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
619	else
620	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
621
622	/*
623	* Update PGM, IEM and others of a world-switch.
624	*/
625	VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu, pCtx);
626	if (rcStrict == VINF_SUCCESS)
627	{ /* likely */ }
628	else if (RT_SUCCESS(rcStrict))
629	{
630	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
631	rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
632	}
633	else
634	{
635	LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
636	return rcStrict;
637	}
638
639	/*
640	* Clear global interrupt flags to allow interrupts in the guest.
641	*/
642	pCtx->hwvirt.fGif = true;
643
644	/*
645	* Event injection.
646	*/
647	PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
648	pCtx->hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
649	if (pEventInject->n.u1Valid)
650	{
651	uint8_t const uVector = pEventInject->n.u8Vector;
652	TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject);
653	uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
654
655	/* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
656	if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
657	{
658	Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
659	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
660	}
661	if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
662	{
663	if ( uVector == X86_XCPT_NMI
664	\|\| uVector > X86_XCPT_LAST)
665	{
666	Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
667	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
668	}
669	if ( uVector == X86_XCPT_BR
670	&& CPUMIsGuestInLongModeEx(pCtx))
671	{
672	Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
673	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_INVALID, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
674	}
675	/** @todo any others? */
676	}
677
678	/*
679	* Invalidate the exit interrupt-information field here. This field is fully updated
680	* on #VMEXIT as events other than the one below can also cause intercepts during
681	* their injection (e.g. exceptions).
682	*/
683	pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
684
685	/*
686	* Clear the event injection valid bit here. While the AMD spec. mentions that the CPU
687	* clears this bit from the VMCB unconditionally on #VMEXIT, internally the CPU could be
688	* clearing it at any time, most likely before/after injecting the event. Since VirtualBox
689	* doesn't have any virtual-CPU internal representation of this bit, we clear/update the
690	* VMCB here. This also has the added benefit that we avoid the risk of injecting the event
691	* twice if we fallback to executing the nested-guest using hardware-assisted SVM after
692	* injecting the event through IEM here.
693	*/
694	pVmcbCtrl->EventInject.n.u1Valid = 0;
695
696	/** @todo NRIP: Software interrupts can only be pushed properly if we support
697	* NRIP for the nested-guest to calculate the instruction length
698	* below. */
699	LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 vec=%#x type=%d uErr=%u cr2=%#RX64 cr3=%#RX64 efer=%#RX64\n",
700	pCtx->cs.Sel, pCtx->rip, uVector, enmType, uErrorCode, pCtx->cr2, pCtx->cr3, pCtx->msrEFER));
701	#if 0
702	rcStrict = IEMInjectTrap(pVCpu, uVector, enmType, uErrorCode, pCtx->cr2, 0 /* cbInstr */);
703	#else
704	TRPMAssertTrap(pVCpu, uVector, enmType);
705	if (pEventInject->n.u1ErrorCodeValid)
706	TRPMSetErrorCode(pVCpu, uErrorCode);
707	if ( enmType == TRPM_TRAP
708	&& uVector == X86_XCPT_PF)
709	TRPMSetFaultAddress(pVCpu, pCtx->cr2);
710	#endif
711	}
712	else
713	LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
714	pCtx->cs.Sel, pCtx->rip, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->msrEFER, pCtx->rflags.u64));
715
716	LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
717
718	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
719	/* If CLGI/STGI isn't intercepted we force IEM-only nested-guest execution here. */
720	if (HMSvmIsVGifActive(pVM))
721	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
722	# endif
723
724	return rcStrict;
725	}
726
727	/* Shouldn't really happen as the caller should've validated the physical address already. */
728	Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
729	return rc;
730	#endif
731	}
732
733
734	#if 0
735	/**
736	* Handles nested-guest SVM control intercepts and performs the \#VMEXIT if the
737	* intercept is active.
738	*
739	* @returns Strict VBox status code.
740	* @retval VINF_SVM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
741	* we're not executing a nested-guest.
742	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
743	* successfully.
744	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
745	* failed and a shutdown needs to be initiated for the geust.
746	*
747	* @param pVCpu The cross context virtual CPU structure.
748	* @param pCtx The guest-CPU context.
749	* @param uExitCode The SVM exit code (see SVM_EXIT_XXX).
750	* @param uExitInfo1 The exit info. 1 field.
751	* @param uExitInfo2 The exit info. 2 field.
752	*/
753	VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,
754	uint64_t uExitInfo2)
755	{
756	#define HMSVM_CTRL_INTERCEPT_VMEXIT(a_Intercept) \
757	do { \
758	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, (a_Intercept))) \
759	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2); \
760	break; \
761	} while (0)
762
763	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
764	return VINF_HM_INTERCEPT_NOT_ACTIVE;
765
766	switch (uExitCode)
767	{
768	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
769	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
770	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
771	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15:
772	case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
773	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
774	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27:
775	case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
776	{
777	if (CPUMIsGuestSvmXcptInterceptSet(pCtx, (X86XCPT)(uExitCode - SVM_EXIT_EXCEPTION_0)))
778	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
779	break;
780	}
781
782	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
783	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
784	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
785	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
786	{
787	if (CPUMIsGuestSvmWriteCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_CR0))
788	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
789	break;
790	}
791
792	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
793	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
794	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
795	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
796	{
797	if (CPUMIsGuestSvmReadCRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_CR0))
798	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
799	break;
800	}
801
802	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
803	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
804	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
805	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
806	{
807	if (CPUMIsGuestSvmReadDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_READ_DR0))
808	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
809	break;
810	}
811
812	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
813	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
814	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
815	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
816	{
817	if (CPUMIsGuestSvmWriteDRxInterceptSet(pCtx, uExitCode - SVM_EXIT_WRITE_DR0))
818	return iemSvmVmexit(pVCpu, pCtx, uExitCode, uExitInfo1, uExitInfo2);
819	break;
820	}
821
822	case SVM_EXIT_INTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTR);
823	case SVM_EXIT_NMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_NMI);
824	case SVM_EXIT_SMI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SMI);
825	case SVM_EXIT_INIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INIT);
826	case SVM_EXIT_VINTR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VINTR);
827	case SVM_EXIT_CR0_SEL_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CR0_SEL_WRITES);
828	case SVM_EXIT_IDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_READS);
829	case SVM_EXIT_GDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_READS);
830	case SVM_EXIT_LDTR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_READS);
831	case SVM_EXIT_TR_READ: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_READS);
832	case SVM_EXIT_IDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IDTR_WRITES);
833	case SVM_EXIT_GDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_GDTR_WRITES);
834	case SVM_EXIT_LDTR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_LDTR_WRITES);
835	case SVM_EXIT_TR_WRITE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TR_WRITES);
836	case SVM_EXIT_RDTSC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSC);
837	case SVM_EXIT_RDPMC: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDPMC);
838	case SVM_EXIT_PUSHF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PUSHF);
839	case SVM_EXIT_POPF: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_POPF);
840	case SVM_EXIT_CPUID: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CPUID);
841	case SVM_EXIT_RSM: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RSM);
842	case SVM_EXIT_IRET: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_IRET);
843	case SVM_EXIT_SWINT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INTN);
844	case SVM_EXIT_INVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVD);
845	case SVM_EXIT_PAUSE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_PAUSE);
846	case SVM_EXIT_HLT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_HLT);
847	case SVM_EXIT_INVLPG: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPG);
848	case SVM_EXIT_INVLPGA: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_INVLPGA);
849	case SVM_EXIT_TASK_SWITCH: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_TASK_SWITCH);
850	case SVM_EXIT_FERR_FREEZE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_FERR_FREEZE);
851	case SVM_EXIT_SHUTDOWN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SHUTDOWN);
852	case SVM_EXIT_VMRUN: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMRUN);
853	case SVM_EXIT_VMMCALL: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMMCALL);
854	case SVM_EXIT_VMLOAD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMLOAD);
855	case SVM_EXIT_VMSAVE: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_VMSAVE);
856	case SVM_EXIT_STGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_STGI);
857	case SVM_EXIT_CLGI: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_CLGI);
858	case SVM_EXIT_SKINIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_SKINIT);
859	case SVM_EXIT_RDTSCP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_RDTSCP);
860	case SVM_EXIT_ICEBP: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_ICEBP);
861	case SVM_EXIT_WBINVD: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_WBINVD);
862	case SVM_EXIT_MONITOR: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MONITOR);
863	case SVM_EXIT_MWAIT: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT);
864	case SVM_EXIT_MWAIT_ARMED: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_MWAIT_ARMED);
865	case SVM_EXIT_XSETBV: HMSVM_CTRL_INTERCEPT_VMEXIT(SVM_CTRL_INTERCEPT_XSETBV);
866
867	case SVM_EXIT_IOIO:
868	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
869	return VERR_SVM_IPE_1;
870
871	case SVM_EXIT_MSR:
872	AssertMsgFailed(("Use HMSvmNstGstHandleMsrIntercept!\n"));
873	return VERR_SVM_IPE_1;
874
875	case SVM_EXIT_NPF:
876	case SVM_EXIT_AVIC_INCOMPLETE_IPI:
877	case SVM_EXIT_AVIC_NOACCEL:
878	AssertMsgFailed(("Todo Implement.\n"));
879	return VERR_SVM_IPE_1;
880
881	default:
882	AssertMsgFailed(("Unsupported SVM exit code %#RX64\n", uExitCode));
883	return VERR_SVM_IPE_1;
884	}
885
886	return VINF_HM_INTERCEPT_NOT_ACTIVE;
887
888	#undef HMSVM_CTRL_INTERCEPT_VMEXIT
889	}
890	#endif
891
892
893	/**
894	* Checks if the event intercepts and performs the \#VMEXIT if the corresponding
895	* intercept is active.
896	*
897	* @returns Strict VBox status code.
898	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
899	* we're not executing a nested-guest.
900	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
901	* successfully.
902	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
903	* failed and a shutdown needs to be initiated for the geust.
904	*
905	* @returns VBox strict status code.
906	* @param pVCpu The cross context virtual CPU structure of the calling thread.
907	* @param u16Port The IO port being accessed.
908	* @param enmIoType The type of IO access.
909	* @param cbReg The IO operand size in bytes.
910	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
911	* @param iEffSeg The effective segment number.
912	* @param fRep Whether this is a repeating IO instruction (REP prefix).
913	* @param fStrIo Whether this is a string IO instruction.
914	* @param cbInstr The length of the IO instruction in bytes.
915	*/
916	IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr,
917	uint64_t uCr2)
918	{
919	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
920
921	/*
922	* Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
923	*
924	* - NMI intercepts have their own exit code and do not cause SVM_EXIT_EXCEPTION_2 #VMEXITs.
925	* - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
926	* even when they use a vector in the range 0 to 31.
927	* - ICEBP should not trigger #DB intercept, but its own intercept.
928	* - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
929	*/
930	/* Check NMI intercept */
931	if ( u8Vector == X86_XCPT_NMI
932	&& (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
933	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
934	{
935	Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
936	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
937	}
938
939	/* Check ICEBP intercept. */
940	if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
941	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
942	{
943	Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
944	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
945	}
946
947	/* Check CPU exception intercepts. */
948	if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
949	&& IEM_IS_SVM_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
950	{
951	Assert(u8Vector <= X86_XCPT_LAST);
952	uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
953	uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
954	if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
955	&& u8Vector == X86_XCPT_PF
956	&& !(uErr & X86_TRAP_PF_ID))
957	{
958	/** @todo Nested-guest SVM - figure out fetching op-code bytes from IEM. */
959	PSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
960	#ifdef IEM_WITH_CODE_TLB
961	uint8_t const cbCurrent = pVCpu->iem.s.cbInstrBuf;
962	uint8_t const *pbInstrBuf = pVCpu->iem.s.pbInstrBuf;
963	if ( pbInstrBuf
964	&& cbCurrent >= SVM_CTRL_GUEST_INSTR_BYTES_MAX)
965	{
966	pVmcbCtrl->cbInstrFetched = SVM_CTRL_GUEST_INSTR_BYTES_MAX;
967	memcpy(&pVmcbCtrl->abInstr[0], pbInstrBuf, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
968	}
969	else
970	{ AssertReleaseFailedReturn(VERR_IEM_IPE_5); /** @todo */ }
971	#else
972	uint8_t const offOpCode = pVCpu->iem.s.offOpcode;
973	uint8_t const cbCurrent = pVCpu->iem.s.cbOpcode - offOpCode;
974	if (cbCurrent >= SVM_CTRL_GUEST_INSTR_BYTES_MAX)
975	{
976	pVmcbCtrl->cbInstrFetched = SVM_CTRL_GUEST_INSTR_BYTES_MAX;
977	memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[offOpCode], SVM_CTRL_GUEST_INSTR_BYTES_MAX);
978	}
979	else
980	{ AssertReleaseFailedReturn(VERR_IEM_IPE_5); /** @todo */ }
981	#endif
982	}
983	Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
984	"uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pCtx->hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u32InterceptXcpt,
985	u8Vector, uExitInfo1, uExitInfo2));
986	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_EXCEPTION_0 + u8Vector, uExitInfo1, uExitInfo2);
987	}
988
989	/* Check software interrupt (INTn) intercepts. */
990	if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
991	\| IEM_XCPT_FLAGS_BP_INSTR
992	\| IEM_XCPT_FLAGS_ICEBP_INSTR
993	\| IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
994	&& IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
995	{
996	uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
997	Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
998	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
999	}
1000
1001	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1002	}
1003
1004
1005	/**
1006	* Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
1007	* corresponding intercept is active.
1008	*
1009	* @returns Strict VBox status code.
1010	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
1011	* we're not executing a nested-guest.
1012	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1013	* successfully.
1014	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1015	* failed and a shutdown needs to be initiated for the geust.
1016	*
1017	* @returns VBox strict status code.
1018	* @param pVCpu The cross context virtual CPU structure of the calling thread.
1019	* @param u16Port The IO port being accessed.
1020	* @param enmIoType The type of IO access.
1021	* @param cbReg The IO operand size in bytes.
1022	* @param cAddrSizeBits The address size bits (for 16, 32 or 64).
1023	* @param iEffSeg The effective segment number.
1024	* @param fRep Whether this is a repeating IO instruction (REP prefix).
1025	* @param fStrIo Whether this is a string IO instruction.
1026	* @param cbInstr The length of the IO instruction in bytes.
1027	*/
1028	IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPU pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
1029	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
1030	{
1031	Assert(IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
1032	Assert(cAddrSizeBits == 16 \|\| cAddrSizeBits == 32 \|\| cAddrSizeBits == 64);
1033	Assert(cbReg == 1 \|\| cbReg == 2 \|\| cbReg == 4 \|\| cbReg == 8);
1034
1035	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
1036
1037	SVMIOIOEXITINFO IoExitInfo;
1038	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1039	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
1040	bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
1041	&IoExitInfo);
1042	if (fIntercept)
1043	{
1044	Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
1045	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_IOIO, IoExitInfo.u, pCtx->rip + cbInstr);
1046	}
1047
1048	/** @todo remove later (for debugging as VirtualBox always traps all IO
1049	* intercepts). */
1050	AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
1051	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1052	}
1053
1054
1055	/**
1056	* Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
1057	* corresponding intercept is active.
1058	*
1059	* @returns Strict VBox status code.
1060	* @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1061	* specify interception of the accessed MSR @a idMsr.
1062	* @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1063	* successfully.
1064	* @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1065	* failed and a shutdown needs to be initiated for the geust.
1066	*
1067	* @param pVCpu The cross context virtual CPU structure.
1068	* @param pCtx The guest-CPU context.
1069	* @param idMsr The MSR being accessed in the nested-guest.
1070	* @param fWrite Whether this is an MSR write access, @c false implies an
1071	* MSR read.
1072	*/
1073	IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite)
1074	{
1075	/*
1076	* Check if any MSRs are being intercepted.
1077	*/
1078	Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT));
1079	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1080
1081	uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1082
1083	/*
1084	* Get the byte and bit offset of the permission bits corresponding to the MSR.
1085	*/
1086	uint16_t offMsrpm;
1087	uint32_t uMsrpmBit;
1088	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1089	if (RT_SUCCESS(rc))
1090	{
1091	Assert(uMsrpmBit < 0x3fff);
1092	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1093	if (fWrite)
1094	++uMsrpmBit;
1095
1096	/*
1097	* Check if the bit is set, if so, trigger a #VMEXIT.
1098	*/
1099	uint8_t pbMsrpm = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1100	pbMsrpm += offMsrpm;
1101	if (ASMBitTest(pbMsrpm, uMsrpmBit))
1102	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1103	}
1104	else
1105	{
1106	/*
1107	* This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1108	*/
1109	Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1110	return iemSvmVmexit(pVCpu, pCtx, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1111	}
1112	return VINF_HM_INTERCEPT_NOT_ACTIVE;
1113	}
1114
1115
1116
1117	/**
1118	* Implements 'VMRUN'.
1119	*/
1120	IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1121	{
1122	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1123	RT_NOREF2(pVCpu, cbInstr);
1124	return VINF_EM_RAW_EMULATE_INSTR;
1125	#else
1126	LogFlow(("iemCImpl_vmrun\n"));
1127	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1128	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1129
1130	/** @todo Check effective address size using address size prefix. */
1131	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1132	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1133	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1134	{
1135	Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1136	return iemRaiseGeneralProtectionFault0(pVCpu);
1137	}
1138
1139	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1140	{
1141	Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1142	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1143	}
1144
1145	VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, pCtx, cbInstr, GCPhysVmcb);
1146	if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1147	{
1148	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
1149	rcStrict = VINF_EM_TRIPLE_FAULT;
1150	}
1151	return rcStrict;
1152	#endif
1153	}
1154
1155
1156	/**
1157	* Implements 'VMMCALL'.
1158	*/
1159	IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1160	{
1161	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1162	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1163	{
1164	Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1165	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1166	}
1167
1168	bool fUpdatedRipAndRF;
1169	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fUpdatedRipAndRF);
1170	if (RT_SUCCESS(rcStrict))
1171	{
1172	if (!fUpdatedRipAndRF)
1173	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1174	return rcStrict;
1175	}
1176
1177	return iemRaiseUndefinedOpcode(pVCpu);
1178	}
1179
1180
1181	/**
1182	* Implements 'VMLOAD'.
1183	*/
1184	IEM_CIMPL_DEF_0(iemCImpl_vmload)
1185	{
1186	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1187	RT_NOREF2(pVCpu, cbInstr);
1188	return VINF_EM_RAW_EMULATE_INSTR;
1189	#else
1190	LogFlow(("iemCImpl_vmload\n"));
1191	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1192	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1193
1194	/** @todo Check effective address size using address size prefix. */
1195	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1196	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1197	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1198	{
1199	Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1200	return iemRaiseGeneralProtectionFault0(pVCpu);
1201	}
1202
1203	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1204	{
1205	Log(("vmload: Guest intercept -> #VMEXIT\n"));
1206	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1207	}
1208
1209	SVMVMCBSTATESAVE VmcbNstGst;
1210	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1211	sizeof(SVMVMCBSTATESAVE));
1212	if (rcStrict == VINF_SUCCESS)
1213	{
1214	LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1215	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, FS, fs);
1216	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, GS, gs);
1217	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, TR, tr);
1218	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1219
1220	pCtx->msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1221	pCtx->msrSTAR = VmcbNstGst.u64STAR;
1222	pCtx->msrLSTAR = VmcbNstGst.u64LSTAR;
1223	pCtx->msrCSTAR = VmcbNstGst.u64CSTAR;
1224	pCtx->msrSFMASK = VmcbNstGst.u64SFMASK;
1225
1226	pCtx->SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1227	pCtx->SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1228	pCtx->SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1229
1230	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1231	}
1232	return rcStrict;
1233	#endif
1234	}
1235
1236
1237	/**
1238	* Implements 'VMSAVE'.
1239	*/
1240	IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1241	{
1242	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1243	RT_NOREF2(pVCpu, cbInstr);
1244	return VINF_EM_RAW_EMULATE_INSTR;
1245	#else
1246	LogFlow(("iemCImpl_vmsave\n"));
1247	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1248	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1249
1250	/** @todo Check effective address size using address size prefix. */
1251	RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1252	if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1253	\|\| !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1254	{
1255	Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1256	return iemRaiseGeneralProtectionFault0(pVCpu);
1257	}
1258
1259	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1260	{
1261	Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1262	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1263	}
1264
1265	SVMVMCBSTATESAVE VmcbNstGst;
1266	VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1267	sizeof(SVMVMCBSTATESAVE));
1268	if (rcStrict == VINF_SUCCESS)
1269	{
1270	LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1271	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, FS, fs);
1272	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, GS, gs);
1273	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, TR, tr);
1274	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &VmcbNstGst, LDTR, ldtr);
1275
1276	VmcbNstGst.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1277	VmcbNstGst.u64STAR = pCtx->msrSTAR;
1278	VmcbNstGst.u64LSTAR = pCtx->msrLSTAR;
1279	VmcbNstGst.u64CSTAR = pCtx->msrCSTAR;
1280	VmcbNstGst.u64SFMASK = pCtx->msrSFMASK;
1281
1282	VmcbNstGst.u64SysEnterCS = pCtx->SysEnter.cs;
1283	VmcbNstGst.u64SysEnterESP = pCtx->SysEnter.esp;
1284	VmcbNstGst.u64SysEnterEIP = pCtx->SysEnter.eip;
1285
1286	rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1287	sizeof(SVMVMCBSTATESAVE));
1288	if (rcStrict == VINF_SUCCESS)
1289	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1290	}
1291	return rcStrict;
1292	#endif
1293	}
1294
1295
1296	/**
1297	* Implements 'CLGI'.
1298	*/
1299	IEM_CIMPL_DEF_0(iemCImpl_clgi)
1300	{
1301	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1302	RT_NOREF2(pVCpu, cbInstr);
1303	return VINF_EM_RAW_EMULATE_INSTR;
1304	#else
1305	LogFlow(("iemCImpl_clgi\n"));
1306	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1307	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1308	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1309	{
1310	Log(("clgi: Guest intercept -> #VMEXIT\n"));
1311	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1312	}
1313
1314	pCtx->hwvirt.fGif = false;
1315	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1316
1317	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1318	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1319	# else
1320	return VINF_SUCCESS;
1321	# endif
1322	#endif
1323	}
1324
1325
1326	/**
1327	* Implements 'STGI'.
1328	*/
1329	IEM_CIMPL_DEF_0(iemCImpl_stgi)
1330	{
1331	#if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1332	RT_NOREF2(pVCpu, cbInstr);
1333	return VINF_EM_RAW_EMULATE_INSTR;
1334	#else
1335	LogFlow(("iemCImpl_stgi\n"));
1336	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1337	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1338	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1339	{
1340	Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1341	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1342	}
1343
1344	pCtx->hwvirt.fGif = true;
1345	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1346
1347	# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1348	return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1349	# else
1350	return VINF_SUCCESS;
1351	# endif
1352	#endif
1353	}
1354
1355
1356	/**
1357	* Implements 'INVLPGA'.
1358	*/
1359	IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1360	{
1361	PCPUMCTX pCtx = IEM_GET_CTX(pVCpu);
1362	/** @todo Check effective address size using address size prefix. */
1363	RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pCtx->rax : pCtx->eax;
1364	/** @todo PGM needs virtual ASID support. */
1365	#if 0
1366	uint32_t const uAsid = pCtx->ecx;
1367	#endif
1368
1369	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1370	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1371	{
1372	Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1373	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1374	}
1375
1376	PGMInvalidatePage(pVCpu, GCPtrPage);
1377	iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1378	return VINF_SUCCESS;
1379	}
1380
1381
1382	/**
1383	* Implements 'SKINIT'.
1384	*/
1385	IEM_CIMPL_DEF_0(iemCImpl_skinit)
1386	{
1387	IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1388
1389	uint32_t uIgnore;
1390	uint32_t fFeaturesECX;
1391	CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1392	if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1393	return iemRaiseUndefinedOpcode(pVCpu);
1394
1395	if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1396	{
1397	Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1398	IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 /, 0 / uExitInfo2 */);
1399	}
1400
1401	RT_NOREF(cbInstr);
1402	return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1403	}
1404

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source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 71078

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