VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp.h@ 72514

Last change on this file since 72514 was 72506, checked in by vboxsync, 7 years ago

IEM: Made smsw use CImpl so to better facilitate SVM intercepts.
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1/* $Id: IEMAllCImplSvmInstr.cpp.h 72506 2018-06-11 12:08:11Z vboxsync $ */
2/** @file
3 * IEM - AMD-V (Secure Virtual Machine) instruction implementation.
4 */
5
6/*
7 * Copyright (C) 2011-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
20/** Check and handles SVM nested-guest instruction intercept and updates
21 * NRIP if needed.
22 * @todo r=bird: This macro is conceptually wrong.
23 */
24# define IEMOP_HLP_SVM_INSTR_INTERCEPT_AND_NRIP(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
25 do \
26 { \
27 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
28 { \
29 IEM_SVM_UPDATE_NRIP(a_pVCpu); \
30 IEM_RETURN_SVM_VMEXIT(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
31 } \
32 } while (0)
33
34/** Checks and handles SVM nested-guest CR0 read intercept. */
35# define IEMCIMPL_HLP_SVM_READ_CR_INTERCEPT(a_pVCpu, a_uCr, a_uExitInfo1, a_uExitInfo2) \
36 do \
37 { \
38 if (!IEM_IS_SVM_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr)) \
39 { /* probably likely */ } \
40 else \
41 { \
42 IEM_SVM_UPDATE_NRIP(a_pVCpu); \
43 IEM_RETURN_SVM_VMEXIT(a_pVCpu, SVM_EXIT_READ_CR0 + (a_uCr), a_uExitInfo1, a_uExitInfo2); \
44 } \
45 } while (0)
46
47#else /* !VBOX_WITH_NESTED_HWVIRT_SVM */
48# define IEMOP_HLP_SVM_INSTR_INTERCEPT_AND_NRIP(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
49# define IEMCIMPL_HLP_SVM_READ_CR_INTERCEPT(a_pVCpu, a_uCr, a_uExitInfo1, a_uExitInfo2) do { } while (0)
50#endif /* !VBOX_WITH_NESTED_HWVIRT_SVM */
51
52
53#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
54
55/**
56 * Converts an IEM exception event type to an SVM event type.
57 *
58 * @returns The SVM event type.
59 * @retval UINT8_MAX if the specified type of event isn't among the set
60 * of recognized IEM event types.
61 *
62 * @param uVector The vector of the event.
63 * @param fIemXcptFlags The IEM exception / interrupt flags.
64 */
65IEM_STATIC uint8_t iemGetSvmEventType(uint32_t uVector, uint32_t fIemXcptFlags)
66{
67 if (fIemXcptFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
68 {
69 if (uVector != X86_XCPT_NMI)
70 return SVM_EVENT_EXCEPTION;
71 return SVM_EVENT_NMI;
72 }
73
74 /* See AMD spec. Table 15-1. "Guest Exception or Interrupt Types". */
75 if (fIemXcptFlags & (IEM_XCPT_FLAGS_BP_INSTR | IEM_XCPT_FLAGS_ICEBP_INSTR | IEM_XCPT_FLAGS_OF_INSTR))
76 return SVM_EVENT_EXCEPTION;
77
78 if (fIemXcptFlags & IEM_XCPT_FLAGS_T_EXT_INT)
79 return SVM_EVENT_EXTERNAL_IRQ;
80
81 if (fIemXcptFlags & IEM_XCPT_FLAGS_T_SOFT_INT)
82 return SVM_EVENT_SOFTWARE_INT;
83
84 AssertMsgFailed(("iemGetSvmEventType: Invalid IEM xcpt/int. type %#x, uVector=%#x\n", fIemXcptFlags, uVector));
85 return UINT8_MAX;
86}
87
88
89/**
90 * Performs an SVM world-switch (VMRUN, \#VMEXIT) updating PGM and IEM internals.
91 *
92 * @returns Strict VBox status code.
93 * @param pVCpu The cross context virtual CPU structure.
94 */
95DECLINLINE(VBOXSTRICTRC) iemSvmWorldSwitch(PVMCPU pVCpu)
96{
97 /*
98 * Inform PGM about paging mode changes.
99 * We include X86_CR0_PE because PGM doesn't handle paged-real mode yet,
100 * see comment in iemMemPageTranslateAndCheckAccess().
101 */
102 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0 | X86_CR0_PE, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
103# ifdef IN_RING3
104 Assert(rc != VINF_PGM_CHANGE_MODE);
105# endif
106 AssertRCReturn(rc, rc);
107
108 /* Inform CPUM (recompiler), can later be removed. */
109 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
110
111 /*
112 * Flush the TLB with new CR3. This is required in case the PGM mode change
113 * above doesn't actually change anything.
114 */
115 if (rc == VINF_SUCCESS)
116 {
117 rc = PGMFlushTLB(pVCpu, pVCpu->cpum.GstCtx.cr3, true);
118 AssertRCReturn(rc, rc);
119 }
120
121 /* Re-initialize IEM cache/state after the drastic mode switch. */
122 iemReInitExec(pVCpu);
123 return rc;
124}
125
126
127/**
128 * SVM \#VMEXIT handler.
129 *
130 * @returns Strict VBox status code.
131 * @retval VINF_SVM_VMEXIT when the \#VMEXIT is successful.
132 * @retval VERR_SVM_VMEXIT_FAILED when the \#VMEXIT failed restoring the guest's
133 * "host state" and a shutdown is required.
134 *
135 * @param pVCpu The cross context virtual CPU structure.
136 * @param uExitCode The exit code.
137 * @param uExitInfo1 The exit info. 1 field.
138 * @param uExitInfo2 The exit info. 2 field.
139 */
140IEM_STATIC VBOXSTRICTRC iemSvmVmexit(PVMCPU pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2)
141{
142 VBOXSTRICTRC rcStrict;
143 if ( CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu))
144 || uExitCode == SVM_EXIT_INVALID)
145 {
146 LogFlow(("iemSvmVmexit: CS:RIP=%04x:%08RX64 uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pVCpu->cpum.GstCtx.cs.Sel,
147 pVCpu->cpum.GstCtx.rip, uExitCode, uExitInfo1, uExitInfo2));
148
149 /*
150 * Disable the global interrupt flag to prevent interrupts during the 'atomic' world switch.
151 */
152 pVCpu->cpum.GstCtx.hwvirt.fGif = false;
153
154 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.es));
155 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.cs));
156 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
157 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ds));
158
159 /*
160 * Map the nested-guest VMCB from its location in guest memory.
161 * Write exactly what the CPU does on #VMEXIT thereby preserving most other bits in the
162 * guest's VMCB in memory, see @bugref{7243#c113} and related comment on iemSvmVmrun().
163 */
164 PSVMVMCB pVmcbMem;
165 PGMPAGEMAPLOCK PgLockMem;
166 PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
167 rcStrict = iemMemPageMap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, (void **)&pVmcbMem, &PgLockMem);
168 if (rcStrict == VINF_SUCCESS)
169 {
170 /*
171 * Notify HM in case the nested-guest was executed using hardware-assisted SVM (which
172 * would have modified some VMCB state) that might need to be restored on #VMEXIT before
173 * writing the VMCB back to guest memory.
174 */
175 HMSvmNstGstVmExitNotify(pVCpu, IEM_GET_CTX(pVCpu));
176
177 /*
178 * Save the nested-guest state into the VMCB state-save area.
179 */
180 PSVMVMCBSTATESAVE pVmcbMemState = &pVmcbMem->guest;
181 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, ES, es);
182 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, CS, cs);
183 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, SS, ss);
184 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), pVmcbMemState, DS, ds);
185 pVmcbMemState->GDTR.u32Limit = pVCpu->cpum.GstCtx.gdtr.cbGdt;
186 pVmcbMemState->GDTR.u64Base = pVCpu->cpum.GstCtx.gdtr.pGdt;
187 pVmcbMemState->IDTR.u32Limit = pVCpu->cpum.GstCtx.idtr.cbIdt;
188 pVmcbMemState->IDTR.u64Base = pVCpu->cpum.GstCtx.idtr.pIdt;
189 pVmcbMemState->u64EFER = pVCpu->cpum.GstCtx.msrEFER;
190 pVmcbMemState->u64CR4 = pVCpu->cpum.GstCtx.cr4;
191 pVmcbMemState->u64CR3 = pVCpu->cpum.GstCtx.cr3;
192 pVmcbMemState->u64CR2 = pVCpu->cpum.GstCtx.cr2;
193 pVmcbMemState->u64CR0 = pVCpu->cpum.GstCtx.cr0;
194 /** @todo Nested paging. */
195 pVmcbMemState->u64RFlags = pVCpu->cpum.GstCtx.rflags.u64;
196 pVmcbMemState->u64RIP = pVCpu->cpum.GstCtx.rip;
197 pVmcbMemState->u64RSP = pVCpu->cpum.GstCtx.rsp;
198 pVmcbMemState->u64RAX = pVCpu->cpum.GstCtx.rax;
199 pVmcbMemState->u64DR7 = pVCpu->cpum.GstCtx.dr[7];
200 pVmcbMemState->u64DR6 = pVCpu->cpum.GstCtx.dr[6];
201 pVmcbMemState->u8CPL = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl; /* See comment in CPUMGetGuestCPL(). */
202 Assert(CPUMGetGuestCPL(pVCpu) == pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl);
203 if (CPUMIsGuestSvmNestedPagingEnabled(pVCpu, IEM_GET_CTX(pVCpu)))
204 pVmcbMemState->u64PAT = pVCpu->cpum.GstCtx.msrPAT;
205
206 /*
207 * Save additional state and intercept information.
208 *
209 * - V_IRQ: Tracked using VMCPU_FF_INTERRUPT_NESTED_GUEST force-flag and updated below.
210 * - V_TPR: Updated by iemCImpl_load_CrX or by the physical CPU for hardware-assisted
211 * SVM execution.
212 * - Interrupt shadow: Tracked using VMCPU_FF_INHIBIT_INTERRUPTS and RIP.
213 */
214 PSVMVMCBCTRL pVmcbMemCtrl = &pVmcbMem->ctrl;
215 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)) /* V_IRQ. */
216 pVmcbMemCtrl->IntCtrl.n.u1VIrqPending = 0;
217 else
218 {
219 Assert(pVmcbCtrl->IntCtrl.n.u1VIrqPending);
220 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
221 }
222
223 pVmcbMemCtrl->IntCtrl.n.u8VTPR = pVmcbCtrl->IntCtrl.n.u8VTPR; /* V_TPR. */
224
225 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) /* Interrupt shadow. */
226 && EMGetInhibitInterruptsPC(pVCpu) == pVCpu->cpum.GstCtx.rip)
227 {
228 pVmcbMemCtrl->IntShadow.n.u1IntShadow = 1;
229 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
230 LogFlow(("iemSvmVmexit: Interrupt shadow till %#RX64\n", pVCpu->cpum.GstCtx.rip));
231 }
232 else
233 pVmcbMemCtrl->IntShadow.n.u1IntShadow = 0;
234
235 /*
236 * Save nRIP, instruction length and byte fields.
237 */
238 pVmcbMemCtrl->u64NextRIP = pVmcbCtrl->u64NextRIP;
239 pVmcbMemCtrl->cbInstrFetched = pVmcbCtrl->cbInstrFetched;
240 memcpy(&pVmcbMemCtrl->abInstr[0], &pVmcbCtrl->abInstr[0], sizeof(pVmcbMemCtrl->abInstr));
241
242 /*
243 * Save exit information.
244 */
245 pVmcbMemCtrl->u64ExitCode = uExitCode;
246 pVmcbMemCtrl->u64ExitInfo1 = uExitInfo1;
247 pVmcbMemCtrl->u64ExitInfo2 = uExitInfo2;
248
249 /*
250 * Update the exit interrupt-information field if this #VMEXIT happened as a result
251 * of delivering an event through IEM.
252 *
253 * Don't update the exit interrupt-information field if the event wasn't being injected
254 * through IEM, as it would have been updated by real hardware if the nested-guest was
255 * executed using hardware-assisted SVM.
256 */
257 {
258 uint8_t uExitIntVector;
259 uint32_t uExitIntErr;
260 uint32_t fExitIntFlags;
261 bool const fRaisingEvent = IEMGetCurrentXcpt(pVCpu, &uExitIntVector, &fExitIntFlags, &uExitIntErr,
262 NULL /* uExitIntCr2 */);
263 if (fRaisingEvent)
264 {
265 pVmcbCtrl->ExitIntInfo.n.u1Valid = 1;
266 pVmcbCtrl->ExitIntInfo.n.u8Vector = uExitIntVector;
267 pVmcbCtrl->ExitIntInfo.n.u3Type = iemGetSvmEventType(uExitIntVector, fExitIntFlags);
268 if (fExitIntFlags & IEM_XCPT_FLAGS_ERR)
269 {
270 pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid = true;
271 pVmcbCtrl->ExitIntInfo.n.u32ErrorCode = uExitIntErr;
272 }
273 }
274 }
275
276 /*
277 * Save the exit interrupt-information field.
278 *
279 * We write the whole field including overwriting reserved bits as it was observed on an
280 * AMD Ryzen 5 Pro 1500 that the CPU does not preserve reserved bits in EXITINTINFO.
281 */
282 pVmcbMemCtrl->ExitIntInfo = pVmcbCtrl->ExitIntInfo;
283
284 /*
285 * Clear event injection.
286 */
287 pVmcbMemCtrl->EventInject.n.u1Valid = 0;
288
289 iemMemPageUnmap(pVCpu, pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, IEM_ACCESS_DATA_RW, pVmcbMem, &PgLockMem);
290 }
291
292 /*
293 * Prepare for guest's "host mode" by clearing internal processor state bits.
294 *
295 * We don't need to zero out the state-save area, just the controls should be
296 * sufficient because it has the critical bit of indicating whether we're inside
297 * the nested-guest or not.
298 */
299 memset(pVmcbCtrl, 0, sizeof(*pVmcbCtrl));
300 Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
301
302 /*
303 * Restore the subset of force-flags that were preserved.
304 */
305 if (pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions)
306 {
307 VMCPU_FF_SET(pVCpu, pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions);
308 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = 0;
309 }
310
311 if (rcStrict == VINF_SUCCESS)
312 {
313 /** @todo Nested paging. */
314 /** @todo ASID. */
315
316 /*
317 * Reload the guest's "host state".
318 */
319 CPUMSvmVmExitRestoreHostState(pVCpu, IEM_GET_CTX(pVCpu));
320
321 /*
322 * Update PGM, IEM and others of a world-switch.
323 */
324 rcStrict = iemSvmWorldSwitch(pVCpu);
325 if (rcStrict == VINF_SUCCESS)
326 rcStrict = VINF_SVM_VMEXIT;
327 else if (RT_SUCCESS(rcStrict))
328 {
329 LogFlow(("iemSvmVmexit: Setting passup status from iemSvmWorldSwitch %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
330 iemSetPassUpStatus(pVCpu, rcStrict);
331 rcStrict = VINF_SVM_VMEXIT;
332 }
333 else
334 LogFlow(("iemSvmVmexit: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
335 }
336 else
337 {
338 AssertMsgFailed(("iemSvmVmexit: Mapping VMCB at %#RGp failed. rc=%Rrc\n", pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb, VBOXSTRICTRC_VAL(rcStrict)));
339 rcStrict = VERR_SVM_VMEXIT_FAILED;
340 }
341 }
342 else
343 {
344 AssertMsgFailed(("iemSvmVmexit: Not in SVM guest mode! uExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uExitCode, uExitInfo1, uExitInfo2));
345 rcStrict = VERR_SVM_IPE_3;
346 }
347
348# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
349 /* CLGI/STGI may not have been intercepted and thus not executed in IEM. */
350 if (HMSvmIsVGifActive(pVCpu->CTX_SUFF(pVM)))
351 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
352# endif
353 return rcStrict;
354}
355
356
357/**
358 * Performs the operations necessary that are part of the vmrun instruction
359 * execution in the guest.
360 *
361 * @returns Strict VBox status code (i.e. informational status codes too).
362 * @retval VINF_SUCCESS successully executed VMRUN and entered nested-guest
363 * code execution.
364 * @retval VINF_SVM_VMEXIT when executing VMRUN causes a \#VMEXIT
365 * (SVM_EXIT_INVALID most likely).
366 *
367 * @param pVCpu The cross context virtual CPU structure.
368 * @param cbInstr The length of the VMRUN instruction.
369 * @param GCPhysVmcb Guest physical address of the VMCB to run.
370 */
371IEM_STATIC VBOXSTRICTRC iemSvmVmrun(PVMCPU pVCpu, uint8_t cbInstr, RTGCPHYS GCPhysVmcb)
372{
373 LogFlow(("iemSvmVmrun\n"));
374
375 /*
376 * Cache the physical address of the VMCB for #VMEXIT exceptions.
377 */
378 pVCpu->cpum.GstCtx.hwvirt.svm.GCPhysVmcb = GCPhysVmcb;
379
380 /*
381 * Save the host state.
382 */
383 CPUMSvmVmRunSaveHostState(IEM_GET_CTX(pVCpu), cbInstr);
384
385 /*
386 * Read the guest VMCB.
387 */
388 PVM pVM = pVCpu->CTX_SUFF(pVM);
389 int rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb), GCPhysVmcb, sizeof(SVMVMCB));
390 if (RT_SUCCESS(rc))
391 {
392 /*
393 * AMD-V seems to preserve reserved fields and only writes back selected, recognized
394 * fields on #VMEXIT. However, not all reserved bits are preserved (e.g, EXITINTINFO)
395 * but in our implementation we try to preserve as much as we possibly can.
396 *
397 * We could read the entire page here and only write back the relevant fields on
398 * #VMEXIT but since our internal VMCB is also being used by HM during hardware-assisted
399 * SVM execution, it creates a potential for a nested-hypervisor to set bits that are
400 * currently reserved but may be recognized as features bits in future CPUs causing
401 * unexpected & undesired results. Hence, we zero out unrecognized fields here as we
402 * typically enter hardware-assisted SVM soon anyway, see @bugref{7243#c113}.
403 */
404 PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
405 PSVMVMCBSTATESAVE pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->guest;
406
407 RT_ZERO(pVmcbCtrl->u8Reserved0);
408 RT_ZERO(pVmcbCtrl->u8Reserved1);
409 RT_ZERO(pVmcbCtrl->u8Reserved2);
410 RT_ZERO(pVmcbNstGst->u8Reserved0);
411 RT_ZERO(pVmcbNstGst->u8Reserved1);
412 RT_ZERO(pVmcbNstGst->u8Reserved2);
413 RT_ZERO(pVmcbNstGst->u8Reserved3);
414 RT_ZERO(pVmcbNstGst->u8Reserved4);
415 RT_ZERO(pVmcbNstGst->u8Reserved5);
416 pVmcbCtrl->u32Reserved0 = 0;
417 pVmcbCtrl->TLBCtrl.n.u24Reserved = 0;
418 pVmcbCtrl->IntCtrl.n.u6Reserved = 0;
419 pVmcbCtrl->IntCtrl.n.u3Reserved = 0;
420 pVmcbCtrl->IntCtrl.n.u5Reserved = 0;
421 pVmcbCtrl->IntCtrl.n.u24Reserved = 0;
422 pVmcbCtrl->IntShadow.n.u30Reserved = 0;
423 pVmcbCtrl->ExitIntInfo.n.u19Reserved = 0;
424 pVmcbCtrl->NestedPagingCtrl.n.u29Reserved = 0;
425 pVmcbCtrl->EventInject.n.u19Reserved = 0;
426 pVmcbCtrl->LbrVirt.n.u30Reserved = 0;
427
428 /*
429 * Validate guest-state and controls.
430 */
431 /* VMRUN must always be intercepted. */
432 if (!CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_VMRUN))
433 {
434 Log(("iemSvmVmrun: VMRUN instruction not intercepted -> #VMEXIT\n"));
435 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
436 }
437
438 /* Nested paging. */
439 if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
440 && !pVM->cpum.ro.GuestFeatures.fSvmNestedPaging)
441 {
442 Log(("iemSvmVmrun: Nested paging not supported -> Disabling\n"));
443 pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = 0;
444 }
445
446 /* AVIC. */
447 if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
448 && !pVM->cpum.ro.GuestFeatures.fSvmAvic)
449 {
450 Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
451 pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
452 }
453
454 /* Last branch record (LBR) virtualization. */
455 if ( pVmcbCtrl->LbrVirt.n.u1LbrVirt
456 && !pVM->cpum.ro.GuestFeatures.fSvmLbrVirt)
457 {
458 Log(("iemSvmVmrun: LBR virtualization not supported -> Disabling\n"));
459 pVmcbCtrl->LbrVirt.n.u1LbrVirt = 0;
460 }
461
462 /* Virtualized VMSAVE/VMLOAD. */
463 if ( pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload
464 && !pVM->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
465 {
466 Log(("iemSvmVmrun: Virtualized VMSAVE/VMLOAD not supported -> Disabling\n"));
467 pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = 0;
468 }
469
470 /* Virtual GIF. */
471 if ( pVmcbCtrl->IntCtrl.n.u1VGifEnable
472 && !pVM->cpum.ro.GuestFeatures.fSvmVGif)
473 {
474 Log(("iemSvmVmrun: Virtual GIF not supported -> Disabling\n"));
475 pVmcbCtrl->IntCtrl.n.u1VGifEnable = 0;
476 }
477
478 /* Guest ASID. */
479 if (!pVmcbCtrl->TLBCtrl.n.u32ASID)
480 {
481 Log(("iemSvmVmrun: Guest ASID is invalid -> #VMEXIT\n"));
482 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
483 }
484
485 /* Guest AVIC. */
486 if ( pVmcbCtrl->IntCtrl.n.u1AvicEnable
487 && !pVM->cpum.ro.GuestFeatures.fSvmAvic)
488 {
489 Log(("iemSvmVmrun: AVIC not supported -> Disabling\n"));
490 pVmcbCtrl->IntCtrl.n.u1AvicEnable = 0;
491 }
492
493 /* Guest Secure Encrypted Virtualization. */
494 if ( ( pVmcbCtrl->NestedPagingCtrl.n.u1Sev
495 || pVmcbCtrl->NestedPagingCtrl.n.u1SevEs)
496 && !pVM->cpum.ro.GuestFeatures.fSvmAvic)
497 {
498 Log(("iemSvmVmrun: SEV not supported -> Disabling\n"));
499 pVmcbCtrl->NestedPagingCtrl.n.u1Sev = 0;
500 pVmcbCtrl->NestedPagingCtrl.n.u1SevEs = 0;
501 }
502
503 /* Flush by ASID. */
504 if ( !pVM->cpum.ro.GuestFeatures.fSvmFlusbByAsid
505 && pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_NOTHING
506 && pVmcbCtrl->TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_ENTIRE)
507 {
508 Log(("iemSvmVmrun: Flush-by-ASID not supported -> #VMEXIT\n"));
509 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
510 }
511
512 /* IO permission bitmap. */
513 RTGCPHYS const GCPhysIOBitmap = pVmcbCtrl->u64IOPMPhysAddr;
514 if ( (GCPhysIOBitmap & X86_PAGE_4K_OFFSET_MASK)
515 || !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap)
516 || !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + X86_PAGE_4K_SIZE)
517 || !PGMPhysIsGCPhysNormal(pVM, GCPhysIOBitmap + (X86_PAGE_4K_SIZE << 1)))
518 {
519 Log(("iemSvmVmrun: IO bitmap physaddr invalid. GCPhysIOBitmap=%#RX64 -> #VMEXIT\n", GCPhysIOBitmap));
520 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
521 }
522
523 /* MSR permission bitmap. */
524 RTGCPHYS const GCPhysMsrBitmap = pVmcbCtrl->u64MSRPMPhysAddr;
525 if ( (GCPhysMsrBitmap & X86_PAGE_4K_OFFSET_MASK)
526 || !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap)
527 || !PGMPhysIsGCPhysNormal(pVM, GCPhysMsrBitmap + X86_PAGE_4K_SIZE))
528 {
529 Log(("iemSvmVmrun: MSR bitmap physaddr invalid. GCPhysMsrBitmap=%#RX64 -> #VMEXIT\n", GCPhysMsrBitmap));
530 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
531 }
532
533 /* CR0. */
534 if ( !(pVmcbNstGst->u64CR0 & X86_CR0_CD)
535 && (pVmcbNstGst->u64CR0 & X86_CR0_NW))
536 {
537 Log(("iemSvmVmrun: CR0 no-write through with cache disabled. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
538 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
539 }
540 if (pVmcbNstGst->u64CR0 >> 32)
541 {
542 Log(("iemSvmVmrun: CR0 reserved bits set. CR0=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64CR0));
543 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
544 }
545 /** @todo Implement all reserved bits/illegal combinations for CR3, CR4. */
546
547 /* DR6 and DR7. */
548 if ( pVmcbNstGst->u64DR6 >> 32
549 || pVmcbNstGst->u64DR7 >> 32)
550 {
551 Log(("iemSvmVmrun: DR6 and/or DR7 reserved bits set. DR6=%#RX64 DR7=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64DR6,
552 pVmcbNstGst->u64DR6));
553 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
554 }
555
556 /*
557 * PAT (Page Attribute Table) MSR.
558 *
559 * The CPU only validates and loads it when nested-paging is enabled.
560 * See AMD spec. "15.25.4 Nested Paging and VMRUN/#VMEXIT".
561 */
562 if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
563 && !CPUMIsPatMsrValid(pVmcbNstGst->u64PAT))
564 {
565 Log(("iemSvmVmrun: PAT invalid. u64PAT=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64PAT));
566 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
567 }
568
569 /*
570 * Copy the IO permission bitmap into the cache.
571 */
572 Assert(pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap));
573 rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap), GCPhysIOBitmap,
574 SVM_IOPM_PAGES * X86_PAGE_4K_SIZE);
575 if (RT_FAILURE(rc))
576 {
577 Log(("iemSvmVmrun: Failed reading the IO permission bitmap at %#RGp. rc=%Rrc\n", GCPhysIOBitmap, rc));
578 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
579 }
580
581 /*
582 * Copy the MSR permission bitmap into the cache.
583 */
584 Assert(pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap));
585 rc = PGMPhysSimpleReadGCPhys(pVM, pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap), GCPhysMsrBitmap,
586 SVM_MSRPM_PAGES * X86_PAGE_4K_SIZE);
587 if (RT_FAILURE(rc))
588 {
589 Log(("iemSvmVmrun: Failed reading the MSR permission bitmap at %#RGp. rc=%Rrc\n", GCPhysMsrBitmap, rc));
590 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
591 }
592
593 /*
594 * Copy segments from nested-guest VMCB state to the guest-CPU state.
595 *
596 * We do this here as we need to use the CS attributes and it's easier this way
597 * then using the VMCB format selectors. It doesn't really matter where we copy
598 * the state, we restore the guest-CPU context state on the \#VMEXIT anyway.
599 */
600 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, ES, es);
601 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, CS, cs);
602 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, SS, ss);
603 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), pVmcbNstGst, DS, ds);
604
605 /** @todo Segment attribute overrides by VMRUN. */
606
607 /*
608 * CPL adjustments and overrides.
609 *
610 * SS.DPL is apparently the CPU's CPL, see comment in CPUMGetGuestCPL().
611 * We shall thus adjust both CS.DPL and SS.DPL here.
612 */
613 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = pVmcbNstGst->u8CPL;
614 if (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(pVCpu)))
615 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 3;
616 if (CPUMIsGuestInRealModeEx(IEM_GET_CTX(pVCpu)))
617 pVCpu->cpum.GstCtx.cs.Attr.n.u2Dpl = pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl = 0;
618 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
619
620 /*
621 * Continue validating guest-state and controls.
622 *
623 * We pass CR0 as 0 to CPUMQueryValidatedGuestEfer below to skip the illegal
624 * EFER.LME bit transition check. We pass the nested-guest's EFER as both the
625 * old and new EFER value to not have any guest EFER bits influence the new
626 * nested-guest EFER.
627 */
628 uint64_t uValidEfer;
629 rc = CPUMQueryValidatedGuestEfer(pVM, 0 /* CR0 */, pVmcbNstGst->u64EFER, pVmcbNstGst->u64EFER, &uValidEfer);
630 if (RT_FAILURE(rc))
631 {
632 Log(("iemSvmVmrun: EFER invalid uOldEfer=%#RX64 -> #VMEXIT\n", pVmcbNstGst->u64EFER));
633 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
634 }
635
636 /* Validate paging and CPU mode bits. */
637 bool const fSvm = RT_BOOL(uValidEfer & MSR_K6_EFER_SVME);
638 bool const fLongModeSupported = RT_BOOL(pVM->cpum.ro.GuestFeatures.fLongMode);
639 bool const fLongModeEnabled = RT_BOOL(uValidEfer & MSR_K6_EFER_LME);
640 bool const fPaging = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PG);
641 bool const fPae = RT_BOOL(pVmcbNstGst->u64CR4 & X86_CR4_PAE);
642 bool const fProtMode = RT_BOOL(pVmcbNstGst->u64CR0 & X86_CR0_PE);
643 bool const fLongModeWithPaging = fLongModeEnabled && fPaging;
644 bool const fLongModeConformCS = pVCpu->cpum.GstCtx.cs.Attr.n.u1Long && pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig;
645 /* Adjust EFER.LMA (this is normally done by the CPU when system software writes CR0). */
646 if (fLongModeWithPaging)
647 uValidEfer |= MSR_K6_EFER_LMA;
648 bool const fLongModeActiveOrEnabled = RT_BOOL(uValidEfer & (MSR_K6_EFER_LME | MSR_K6_EFER_LMA));
649 if ( !fSvm
650 || (!fLongModeSupported && fLongModeActiveOrEnabled)
651 || (fLongModeWithPaging && !fPae)
652 || (fLongModeWithPaging && !fProtMode)
653 || ( fLongModeEnabled
654 && fPaging
655 && fPae
656 && fLongModeConformCS))
657 {
658 Log(("iemSvmVmrun: EFER invalid. uValidEfer=%#RX64 -> #VMEXIT\n", uValidEfer));
659 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
660 }
661
662 /*
663 * Preserve the required force-flags.
664 *
665 * We only preserve the force-flags that would affect the execution of the
666 * nested-guest (or the guest).
667 *
668 * - VMCPU_FF_INHIBIT_INTERRUPTS need -not- be preserved as it's for a single
669 * instruction which is this VMRUN instruction itself.
670 *
671 * - VMCPU_FF_BLOCK_NMIS needs to be preserved as it blocks NMI until the
672 * execution of a subsequent IRET instruction in the guest.
673 *
674 * - The remaining FFs (e.g. timers) can stay in place so that we will be
675 * able to generate interrupts that should cause #VMEXITs for the
676 * nested-guest.
677 */
678 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS;
679 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
680
681 /*
682 * Pause filter.
683 */
684 if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilter)
685 {
686 pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = pVmcbCtrl->u16PauseFilterCount;
687 if (pVM->cpum.ro.GuestFeatures.fSvmPauseFilterThreshold)
688 pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold = pVmcbCtrl->u16PauseFilterCount;
689 }
690
691 /*
692 * Interrupt shadow.
693 */
694 if (pVmcbCtrl->IntShadow.n.u1IntShadow)
695 {
696 LogFlow(("iemSvmVmrun: setting interrupt shadow. inhibit PC=%#RX64\n", pVmcbNstGst->u64RIP));
697 /** @todo will this cause trouble if the nested-guest is 64-bit but the guest is 32-bit? */
698 EMSetInhibitInterruptsPC(pVCpu, pVmcbNstGst->u64RIP);
699 }
700
701 /*
702 * TLB flush control.
703 * Currently disabled since it's redundant as we unconditionally flush the TLB
704 * in iemSvmWorldSwitch() below.
705 */
706# if 0
707 /** @todo @bugref{7243}: ASID based PGM TLB flushes. */
708 if ( pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE
709 || pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
710 || pVmcbCtrl->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
711 PGMFlushTLB(pVCpu, pVmcbNstGst->u64CR3, true /* fGlobal */);
712# endif
713
714 /*
715 * Copy the remaining guest state from the VMCB to the guest-CPU context.
716 */
717 pVCpu->cpum.GstCtx.gdtr.cbGdt = pVmcbNstGst->GDTR.u32Limit;
718 pVCpu->cpum.GstCtx.gdtr.pGdt = pVmcbNstGst->GDTR.u64Base;
719 pVCpu->cpum.GstCtx.idtr.cbIdt = pVmcbNstGst->IDTR.u32Limit;
720 pVCpu->cpum.GstCtx.idtr.pIdt = pVmcbNstGst->IDTR.u64Base;
721 CPUMSetGuestCR0(pVCpu, pVmcbNstGst->u64CR0);
722 CPUMSetGuestCR4(pVCpu, pVmcbNstGst->u64CR4);
723 pVCpu->cpum.GstCtx.cr3 = pVmcbNstGst->u64CR3;
724 pVCpu->cpum.GstCtx.cr2 = pVmcbNstGst->u64CR2;
725 pVCpu->cpum.GstCtx.dr[6] = pVmcbNstGst->u64DR6;
726 pVCpu->cpum.GstCtx.dr[7] = pVmcbNstGst->u64DR7;
727 pVCpu->cpum.GstCtx.rflags.u64 = pVmcbNstGst->u64RFlags;
728 pVCpu->cpum.GstCtx.rax = pVmcbNstGst->u64RAX;
729 pVCpu->cpum.GstCtx.rsp = pVmcbNstGst->u64RSP;
730 pVCpu->cpum.GstCtx.rip = pVmcbNstGst->u64RIP;
731 CPUMSetGuestMsrEferNoCheck(pVCpu, pVCpu->cpum.GstCtx.msrEFER, uValidEfer);
732 if (pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging)
733 pVCpu->cpum.GstCtx.msrPAT = pVmcbNstGst->u64PAT;
734
735 /* Mask DR6, DR7 bits mandatory set/clear bits. */
736 pVCpu->cpum.GstCtx.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
737 pVCpu->cpum.GstCtx.dr[6] |= X86_DR6_RA1_MASK;
738 pVCpu->cpum.GstCtx.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
739 pVCpu->cpum.GstCtx.dr[7] |= X86_DR7_RA1_MASK;
740
741 /*
742 * Check for pending virtual interrupts.
743 */
744 if (pVmcbCtrl->IntCtrl.n.u1VIrqPending)
745 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
746 else
747 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
748
749 /*
750 * Update PGM, IEM and others of a world-switch.
751 */
752 VBOXSTRICTRC rcStrict = iemSvmWorldSwitch(pVCpu);
753 if (rcStrict == VINF_SUCCESS)
754 { /* likely */ }
755 else if (RT_SUCCESS(rcStrict))
756 {
757 LogFlow(("iemSvmVmrun: iemSvmWorldSwitch returned %Rrc, setting passup status\n", VBOXSTRICTRC_VAL(rcStrict)));
758 rcStrict = iemSetPassUpStatus(pVCpu, rcStrict);
759 }
760 else
761 {
762 LogFlow(("iemSvmVmrun: iemSvmWorldSwitch unexpected failure. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
763 return rcStrict;
764 }
765
766 /*
767 * Clear global interrupt flags to allow interrupts in the guest.
768 */
769 pVCpu->cpum.GstCtx.hwvirt.fGif = true;
770
771 /*
772 * Event injection.
773 */
774 PCSVMEVENT pEventInject = &pVmcbCtrl->EventInject;
775 pVCpu->cpum.GstCtx.hwvirt.svm.fInterceptEvents = !pEventInject->n.u1Valid;
776 if (pEventInject->n.u1Valid)
777 {
778 uint8_t const uVector = pEventInject->n.u8Vector;
779 TRPMEVENT const enmType = HMSvmEventToTrpmEventType(pEventInject);
780 uint16_t const uErrorCode = pEventInject->n.u1ErrorCodeValid ? pEventInject->n.u32ErrorCode : 0;
781
782 /* Validate vectors for hardware exceptions, see AMD spec. 15.20 "Event Injection". */
783 if (RT_UNLIKELY(enmType == TRPM_32BIT_HACK))
784 {
785 Log(("iemSvmVmrun: Invalid event type =%#x -> #VMEXIT\n", (uint8_t)pEventInject->n.u3Type));
786 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
787 }
788 if (pEventInject->n.u3Type == SVM_EVENT_EXCEPTION)
789 {
790 if ( uVector == X86_XCPT_NMI
791 || uVector > X86_XCPT_LAST)
792 {
793 Log(("iemSvmVmrun: Invalid vector for hardware exception. uVector=%#x -> #VMEXIT\n", uVector));
794 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
795 }
796 if ( uVector == X86_XCPT_BR
797 && CPUMIsGuestInLongModeEx(IEM_GET_CTX(pVCpu)))
798 {
799 Log(("iemSvmVmrun: Cannot inject #BR when not in long mode -> #VMEXIT\n"));
800 return iemSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
801 }
802 /** @todo any others? */
803 }
804
805 /*
806 * Invalidate the exit interrupt-information field here. This field is fully updated
807 * on #VMEXIT as events other than the one below can also cause intercepts during
808 * their injection (e.g. exceptions).
809 */
810 pVmcbCtrl->ExitIntInfo.n.u1Valid = 0;
811
812 /*
813 * Clear the event injection valid bit here. While the AMD spec. mentions that the CPU
814 * clears this bit from the VMCB unconditionally on #VMEXIT, internally the CPU could be
815 * clearing it at any time, most likely before/after injecting the event. Since VirtualBox
816 * doesn't have any virtual-CPU internal representation of this bit, we clear/update the
817 * VMCB here. This also has the added benefit that we avoid the risk of injecting the event
818 * twice if we fallback to executing the nested-guest using hardware-assisted SVM after
819 * injecting the event through IEM here.
820 */
821 pVmcbCtrl->EventInject.n.u1Valid = 0;
822
823 /** @todo NRIP: Software interrupts can only be pushed properly if we support
824 * NRIP for the nested-guest to calculate the instruction length
825 * below. */
826 LogFlow(("iemSvmVmrun: Injecting event: %04x:%08RX64 vec=%#x type=%d uErr=%u cr2=%#RX64 cr3=%#RX64 efer=%#RX64\n",
827 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uVector, enmType, uErrorCode, pVCpu->cpum.GstCtx.cr2, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.msrEFER));
828
829 /*
830 * We shall not inject the event here right away. There may be paging mode related updates
831 * as a result of the world-switch above that are yet to be honored. Instead flag the event
832 * as pending for injection.
833 */
834 TRPMAssertTrap(pVCpu, uVector, enmType);
835 if (pEventInject->n.u1ErrorCodeValid)
836 TRPMSetErrorCode(pVCpu, uErrorCode);
837 if ( enmType == TRPM_TRAP
838 && uVector == X86_XCPT_PF)
839 TRPMSetFaultAddress(pVCpu, pVCpu->cpum.GstCtx.cr2);
840 }
841 else
842 LogFlow(("iemSvmVmrun: Entering nested-guest: %04x:%08RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64 efer=%#RX64 efl=%#x\n",
843 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER, pVCpu->cpum.GstCtx.rflags.u64));
844
845 LogFlow(("iemSvmVmrun: returns %d\n", VBOXSTRICTRC_VAL(rcStrict)));
846
847# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
848 /* If CLGI/STGI isn't intercepted we force IEM-only nested-guest execution here. */
849 if (HMSvmIsVGifActive(pVM))
850 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
851# endif
852
853 return rcStrict;
854 }
855
856 /* Shouldn't really happen as the caller should've validated the physical address already. */
857 Log(("iemSvmVmrun: Failed to read nested-guest VMCB at %#RGp (rc=%Rrc) -> #VMEXIT\n", GCPhysVmcb, rc));
858 return rc;
859}
860
861
862/**
863 * Checks if the event intercepts and performs the \#VMEXIT if the corresponding
864 * intercept is active.
865 *
866 * @returns Strict VBox status code.
867 * @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
868 * we're not executing a nested-guest.
869 * @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
870 * successfully.
871 * @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
872 * failed and a shutdown needs to be initiated for the geust.
873 *
874 * @returns VBox strict status code.
875 * @param pVCpu The cross context virtual CPU structure of the calling thread.
876 * @param u8Vector The interrupt or exception vector.
877 * @param fFlags The exception flags (see IEM_XCPT_FLAGS_XXX).
878 * @param uErr The error-code associated with the exception.
879 * @param uCr2 The CR2 value in case of a \#PF exception.
880 */
881IEM_STATIC VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPU pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2)
882{
883 Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
884
885 /*
886 * Handle SVM exception and software interrupt intercepts, see AMD spec. 15.12 "Exception Intercepts".
887 *
888 * - NMI intercepts have their own exit code and do not cause SVM_EXIT_XCPT_2 #VMEXITs.
889 * - External interrupts and software interrupts (INTn instruction) do not check the exception intercepts
890 * even when they use a vector in the range 0 to 31.
891 * - ICEBP should not trigger #DB intercept, but its own intercept.
892 * - For #PF exceptions, its intercept is checked before CR2 is written by the exception.
893 */
894 /* Check NMI intercept */
895 if ( u8Vector == X86_XCPT_NMI
896 && (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
897 && IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_NMI))
898 {
899 Log2(("iemHandleSvmNstGstEventIntercept: NMI intercept -> #VMEXIT\n"));
900 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_NMI, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
901 }
902
903 /* Check ICEBP intercept. */
904 if ( (fFlags & IEM_XCPT_FLAGS_ICEBP_INSTR)
905 && IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_ICEBP))
906 {
907 Log2(("iemHandleSvmNstGstEventIntercept: ICEBP intercept -> #VMEXIT\n"));
908 IEM_SVM_UPDATE_NRIP(pVCpu);
909 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_ICEBP, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
910 }
911
912 /* Check CPU exception intercepts. */
913 if ( (fFlags & IEM_XCPT_FLAGS_T_CPU_XCPT)
914 && IEM_IS_SVM_XCPT_INTERCEPT_SET(pVCpu, u8Vector))
915 {
916 Assert(u8Vector <= X86_XCPT_LAST);
917 uint64_t const uExitInfo1 = fFlags & IEM_XCPT_FLAGS_ERR ? uErr : 0;
918 uint64_t const uExitInfo2 = fFlags & IEM_XCPT_FLAGS_CR2 ? uCr2 : 0;
919 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists
920 && u8Vector == X86_XCPT_PF
921 && !(uErr & X86_TRAP_PF_ID))
922 {
923 PSVMVMCBCTRL pVmcbCtrl = &pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl;
924# ifdef IEM_WITH_CODE_TLB
925 uint8_t const *pbInstrBuf = pVCpu->iem.s.pbInstrBuf;
926 uint8_t const cbInstrBuf = pVCpu->iem.s.cbInstrBuf;
927 pVmcbCtrl->cbInstrFetched = RT_MIN(cbInstrBuf, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
928 if ( pbInstrBuf
929 && cbInstrBuf > 0)
930 memcpy(&pVmcbCtrl->abInstr[0], pbInstrBuf, pVmcbCtrl->cbInstrFetched);
931# else
932 uint8_t const cbOpcode = pVCpu->iem.s.cbOpcode;
933 pVmcbCtrl->cbInstrFetched = RT_MIN(cbOpcode, SVM_CTRL_GUEST_INSTR_BYTES_MAX);
934 if (cbOpcode > 0)
935 memcpy(&pVmcbCtrl->abInstr[0], &pVCpu->iem.s.abOpcode[0], pVmcbCtrl->cbInstrFetched);
936# endif
937 }
938 if (u8Vector == X86_XCPT_BR)
939 IEM_SVM_UPDATE_NRIP(pVCpu);
940 Log2(("iemHandleSvmNstGstEventIntercept: Xcpt intercept u32InterceptXcpt=%#RX32 u8Vector=%#x "
941 "uExitInfo1=%#RX64 uExitInfo2=%#RX64 -> #VMEXIT\n", pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb)->ctrl.u32InterceptXcpt,
942 u8Vector, uExitInfo1, uExitInfo2));
943 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_XCPT_0 + u8Vector, uExitInfo1, uExitInfo2);
944 }
945
946 /* Check software interrupt (INTn) intercepts. */
947 if ( (fFlags & ( IEM_XCPT_FLAGS_T_SOFT_INT
948 | IEM_XCPT_FLAGS_BP_INSTR
949 | IEM_XCPT_FLAGS_ICEBP_INSTR
950 | IEM_XCPT_FLAGS_OF_INSTR)) == IEM_XCPT_FLAGS_T_SOFT_INT
951 && IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INTN))
952 {
953 uint64_t const uExitInfo1 = IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? u8Vector : 0;
954 Log2(("iemHandleSvmNstGstEventIntercept: Software INT intercept (u8Vector=%#x) -> #VMEXIT\n", u8Vector));
955 IEM_SVM_UPDATE_NRIP(pVCpu);
956 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SWINT, uExitInfo1, 0 /* uExitInfo2 */);
957 }
958
959 return VINF_HM_INTERCEPT_NOT_ACTIVE;
960}
961
962
963/**
964 * Checks the SVM IO permission bitmap and performs the \#VMEXIT if the
965 * corresponding intercept is active.
966 *
967 * @returns Strict VBox status code.
968 * @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the intercept is not active or
969 * we're not executing a nested-guest.
970 * @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
971 * successfully.
972 * @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
973 * failed and a shutdown needs to be initiated for the geust.
974 *
975 * @returns VBox strict status code.
976 * @param pVCpu The cross context virtual CPU structure of the calling thread.
977 * @param u16Port The IO port being accessed.
978 * @param enmIoType The type of IO access.
979 * @param cbReg The IO operand size in bytes.
980 * @param cAddrSizeBits The address size bits (for 16, 32 or 64).
981 * @param iEffSeg The effective segment number.
982 * @param fRep Whether this is a repeating IO instruction (REP prefix).
983 * @param fStrIo Whether this is a string IO instruction.
984 * @param cbInstr The length of the IO instruction in bytes.
985 */
986IEM_STATIC VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPU pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
987 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr)
988{
989 Assert(IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT));
990 Assert(cAddrSizeBits == 16 || cAddrSizeBits == 32 || cAddrSizeBits == 64);
991 Assert(cbReg == 1 || cbReg == 2 || cbReg == 4 || cbReg == 8);
992
993 Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u)\n", u16Port, u16Port));
994
995 SVMIOIOEXITINFO IoExitInfo;
996 void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
997 bool const fIntercept = HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
998 &IoExitInfo);
999 if (fIntercept)
1000 {
1001 Log3(("iemSvmHandleIOIntercept: u16Port=%#x (%u) -> #VMEXIT\n", u16Port, u16Port));
1002 IEM_SVM_UPDATE_NRIP(pVCpu);
1003 return iemSvmVmexit(pVCpu, SVM_EXIT_IOIO, IoExitInfo.u, pVCpu->cpum.GstCtx.rip + cbInstr);
1004 }
1005
1006 /** @todo remove later (for debugging as VirtualBox always traps all IO
1007 * intercepts). */
1008 AssertMsgFailed(("iemSvmHandleIOIntercept: We expect an IO intercept here!\n"));
1009 return VINF_HM_INTERCEPT_NOT_ACTIVE;
1010}
1011
1012
1013/**
1014 * Checks the SVM MSR permission bitmap and performs the \#VMEXIT if the
1015 * corresponding intercept is active.
1016 *
1017 * @returns Strict VBox status code.
1018 * @retval VINF_HM_INTERCEPT_NOT_ACTIVE if the MSR permission bitmap does not
1019 * specify interception of the accessed MSR @a idMsr.
1020 * @retval VINF_SVM_VMEXIT if the intercept is active and the \#VMEXIT occurred
1021 * successfully.
1022 * @retval VERR_SVM_VMEXIT_FAILED if the intercept is active and the \#VMEXIT
1023 * failed and a shutdown needs to be initiated for the geust.
1024 *
1025 * @param pVCpu The cross context virtual CPU structure.
1026 * @param idMsr The MSR being accessed in the nested-guest.
1027 * @param fWrite Whether this is an MSR write access, @c false implies an
1028 * MSR read.
1029 * @param cbInstr The length of the MSR read/write instruction in bytes.
1030 */
1031IEM_STATIC VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPU pVCpu, uint32_t idMsr, bool fWrite)
1032{
1033 /*
1034 * Check if any MSRs are being intercepted.
1035 */
1036 Assert(CPUMIsGuestSvmCtrlInterceptSet(pVCpu, IEM_GET_CTX(pVCpu), SVM_CTRL_INTERCEPT_MSR_PROT));
1037 Assert(CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1038
1039 uint64_t const uExitInfo1 = fWrite ? SVM_EXIT1_MSR_WRITE : SVM_EXIT1_MSR_READ;
1040
1041 /*
1042 * Get the byte and bit offset of the permission bits corresponding to the MSR.
1043 */
1044 uint16_t offMsrpm;
1045 uint8_t uMsrpmBit;
1046 int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
1047 if (RT_SUCCESS(rc))
1048 {
1049 Assert(uMsrpmBit == 0 || uMsrpmBit == 2 || uMsrpmBit == 4 || uMsrpmBit == 6);
1050 Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1051 if (fWrite)
1052 ++uMsrpmBit;
1053
1054 /*
1055 * Check if the bit is set, if so, trigger a #VMEXIT.
1056 */
1057 uint8_t *pbMsrpm = (uint8_t *)pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
1058 pbMsrpm += offMsrpm;
1059 if (*pbMsrpm & RT_BIT(uMsrpmBit))
1060 {
1061 IEM_SVM_UPDATE_NRIP(pVCpu);
1062 return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1063 }
1064 }
1065 else
1066 {
1067 /*
1068 * This shouldn't happen, but if it does, cause a #VMEXIT and let the "host" (guest hypervisor) deal with it.
1069 */
1070 Log(("iemSvmHandleMsrIntercept: Invalid/out-of-range MSR %#RX32 fWrite=%RTbool -> #VMEXIT\n", idMsr, fWrite));
1071 return iemSvmVmexit(pVCpu, SVM_EXIT_MSR, uExitInfo1, 0 /* uExitInfo2 */);
1072 }
1073 return VINF_HM_INTERCEPT_NOT_ACTIVE;
1074}
1075
1076
1077
1078/**
1079 * Implements 'VMRUN'.
1080 */
1081IEM_CIMPL_DEF_0(iemCImpl_vmrun)
1082{
1083# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1084 RT_NOREF2(pVCpu, cbInstr);
1085 return VINF_EM_RAW_EMULATE_INSTR;
1086# else
1087 LogFlow(("iemCImpl_vmrun\n"));
1088 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmrun);
1089
1090 /** @todo Check effective address size using address size prefix. */
1091 RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1092 if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1093 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1094 {
1095 Log(("vmrun: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1096 return iemRaiseGeneralProtectionFault0(pVCpu);
1097 }
1098
1099 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
1100 {
1101 Log(("vmrun: Guest intercept -> #VMEXIT\n"));
1102 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMRUN, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1103 }
1104
1105 VBOXSTRICTRC rcStrict = iemSvmVmrun(pVCpu, cbInstr, GCPhysVmcb);
1106 if (rcStrict == VERR_SVM_VMEXIT_FAILED)
1107 {
1108 Assert(!CPUMIsGuestInSvmNestedHwVirtMode(IEM_GET_CTX(pVCpu)));
1109 rcStrict = VINF_EM_TRIPLE_FAULT;
1110 }
1111 return rcStrict;
1112# endif
1113}
1114
1115#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
1116
1117/**
1118 * Common code for iemCImpl_vmmcall and iemCImpl_vmcall (latter in IEMAllCImplVmxInstr.cpp.h).
1119 */
1120IEM_CIMPL_DEF_1(iemCImpl_Hypercall, uint16_t, uDisOpcode)
1121{
1122 if (EMAreHypercallInstructionsEnabled(pVCpu))
1123 {
1124 NOREF(uDisOpcode);
1125 VBOXSTRICTRC rcStrict = GIMHypercallEx(pVCpu, IEM_GET_CTX(pVCpu), uDisOpcode, cbInstr);
1126 if (RT_SUCCESS(rcStrict))
1127 {
1128 if (rcStrict == VINF_SUCCESS)
1129 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1130 if ( rcStrict == VINF_SUCCESS
1131 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
1132 return VINF_SUCCESS;
1133 AssertMsgReturn(rcStrict == VINF_GIM_R3_HYPERCALL, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1134 return rcStrict;
1135 }
1136 AssertMsgReturn( rcStrict == VERR_GIM_HYPERCALL_ACCESS_DENIED
1137 || rcStrict == VERR_GIM_HYPERCALLS_NOT_AVAILABLE
1138 || rcStrict == VERR_GIM_NOT_ENABLED
1139 || rcStrict == VERR_GIM_HYPERCALL_MEMORY_READ_FAILED
1140 || rcStrict == VERR_GIM_HYPERCALL_MEMORY_WRITE_FAILED,
1141 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), VERR_IEM_IPE_4);
1142
1143 /* Raise #UD on all failures. */
1144 }
1145 return iemRaiseUndefinedOpcode(pVCpu);
1146}
1147
1148/**
1149 * Implements 'VMMCALL'.
1150 */
1151IEM_CIMPL_DEF_0(iemCImpl_vmmcall)
1152{
1153 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
1154 {
1155 Log(("vmmcall: Guest intercept -> #VMEXIT\n"));
1156 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMMCALL, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1157 }
1158
1159#ifndef IN_RC
1160 /* This is a little bit more complicated than the VT-x version because HM/SVM may
1161 patch MOV CR8 instructions too speed up APIC.TPR access for 32-bit windows guests. */
1162 if (VM_IS_HM_ENABLED(pVCpu->CTX_SUFF(pVM)))
1163 {
1164 int rc = HMHCSvmMaybeMovTprHypercall(pVCpu, IEM_GET_CTX(pVCpu));
1165 if (RT_SUCCESS(rc))
1166 {
1167 Log(("vmmcall: MovTrp\n"));
1168 return VINF_SUCCESS;
1169 }
1170 }
1171#endif
1172
1173 /* Join forces with vmcall. */
1174 return IEM_CIMPL_CALL_1(iemCImpl_Hypercall, OP_VMMCALL);
1175}
1176
1177#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1178
1179/**
1180 * Implements 'VMLOAD'.
1181 */
1182IEM_CIMPL_DEF_0(iemCImpl_vmload)
1183{
1184# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1185 RT_NOREF2(pVCpu, cbInstr);
1186 return VINF_EM_RAW_EMULATE_INSTR;
1187# else
1188 LogFlow(("iemCImpl_vmload\n"));
1189 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmload);
1190
1191 /** @todo Check effective address size using address size prefix. */
1192 RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1193 if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1194 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1195 {
1196 Log(("vmload: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1197 return iemRaiseGeneralProtectionFault0(pVCpu);
1198 }
1199
1200 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
1201 {
1202 Log(("vmload: Guest intercept -> #VMEXIT\n"));
1203 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMLOAD, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1204 }
1205
1206 SVMVMCBSTATESAVE VmcbNstGst;
1207 VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1208 sizeof(SVMVMCBSTATESAVE));
1209 if (rcStrict == VINF_SUCCESS)
1210 {
1211 LogFlow(("vmload: Loading VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1212 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1213 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1214 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1215 HMSVM_SEG_REG_COPY_FROM_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1216
1217 pVCpu->cpum.GstCtx.msrKERNELGSBASE = VmcbNstGst.u64KernelGSBase;
1218 pVCpu->cpum.GstCtx.msrSTAR = VmcbNstGst.u64STAR;
1219 pVCpu->cpum.GstCtx.msrLSTAR = VmcbNstGst.u64LSTAR;
1220 pVCpu->cpum.GstCtx.msrCSTAR = VmcbNstGst.u64CSTAR;
1221 pVCpu->cpum.GstCtx.msrSFMASK = VmcbNstGst.u64SFMASK;
1222
1223 pVCpu->cpum.GstCtx.SysEnter.cs = VmcbNstGst.u64SysEnterCS;
1224 pVCpu->cpum.GstCtx.SysEnter.esp = VmcbNstGst.u64SysEnterESP;
1225 pVCpu->cpum.GstCtx.SysEnter.eip = VmcbNstGst.u64SysEnterEIP;
1226
1227 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1228 }
1229 return rcStrict;
1230# endif
1231}
1232
1233
1234/**
1235 * Implements 'VMSAVE'.
1236 */
1237IEM_CIMPL_DEF_0(iemCImpl_vmsave)
1238{
1239# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1240 RT_NOREF2(pVCpu, cbInstr);
1241 return VINF_EM_RAW_EMULATE_INSTR;
1242# else
1243 LogFlow(("iemCImpl_vmsave\n"));
1244 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, vmsave);
1245
1246 /** @todo Check effective address size using address size prefix. */
1247 RTGCPHYS const GCPhysVmcb = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1248 if ( (GCPhysVmcb & X86_PAGE_4K_OFFSET_MASK)
1249 || !PGMPhysIsGCPhysNormal(pVCpu->CTX_SUFF(pVM), GCPhysVmcb))
1250 {
1251 Log(("vmsave: VMCB physaddr (%#RGp) not valid -> #GP(0)\n", GCPhysVmcb));
1252 return iemRaiseGeneralProtectionFault0(pVCpu);
1253 }
1254
1255 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
1256 {
1257 Log(("vmsave: Guest intercept -> #VMEXIT\n"));
1258 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_VMSAVE, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1259 }
1260
1261 SVMVMCBSTATESAVE VmcbNstGst;
1262 VBOXSTRICTRC rcStrict = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), &VmcbNstGst, GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest),
1263 sizeof(SVMVMCBSTATESAVE));
1264 if (rcStrict == VINF_SUCCESS)
1265 {
1266 LogFlow(("vmsave: Saving VMCB at %#RGp enmEffAddrMode=%d\n", GCPhysVmcb, pVCpu->iem.s.enmEffAddrMode));
1267 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, FS, fs);
1268 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, GS, gs);
1269 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, TR, tr);
1270 HMSVM_SEG_REG_COPY_TO_VMCB(IEM_GET_CTX(pVCpu), &VmcbNstGst, LDTR, ldtr);
1271
1272 VmcbNstGst.u64KernelGSBase = pVCpu->cpum.GstCtx.msrKERNELGSBASE;
1273 VmcbNstGst.u64STAR = pVCpu->cpum.GstCtx.msrSTAR;
1274 VmcbNstGst.u64LSTAR = pVCpu->cpum.GstCtx.msrLSTAR;
1275 VmcbNstGst.u64CSTAR = pVCpu->cpum.GstCtx.msrCSTAR;
1276 VmcbNstGst.u64SFMASK = pVCpu->cpum.GstCtx.msrSFMASK;
1277
1278 VmcbNstGst.u64SysEnterCS = pVCpu->cpum.GstCtx.SysEnter.cs;
1279 VmcbNstGst.u64SysEnterESP = pVCpu->cpum.GstCtx.SysEnter.esp;
1280 VmcbNstGst.u64SysEnterEIP = pVCpu->cpum.GstCtx.SysEnter.eip;
1281
1282 rcStrict = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), GCPhysVmcb + RT_OFFSETOF(SVMVMCB, guest), &VmcbNstGst,
1283 sizeof(SVMVMCBSTATESAVE));
1284 if (rcStrict == VINF_SUCCESS)
1285 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1286 }
1287 return rcStrict;
1288# endif
1289}
1290
1291
1292/**
1293 * Implements 'CLGI'.
1294 */
1295IEM_CIMPL_DEF_0(iemCImpl_clgi)
1296{
1297# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1298 RT_NOREF2(pVCpu, cbInstr);
1299 return VINF_EM_RAW_EMULATE_INSTR;
1300# else
1301 LogFlow(("iemCImpl_clgi\n"));
1302 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, clgi);
1303 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
1304 {
1305 Log(("clgi: Guest intercept -> #VMEXIT\n"));
1306 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_CLGI, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1307 }
1308
1309 pVCpu->cpum.GstCtx.hwvirt.fGif = false;
1310 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1311
1312# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1313 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, true);
1314# else
1315 return VINF_SUCCESS;
1316# endif
1317# endif
1318}
1319
1320
1321/**
1322 * Implements 'STGI'.
1323 */
1324IEM_CIMPL_DEF_0(iemCImpl_stgi)
1325{
1326# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && !defined(IN_RING3)
1327 RT_NOREF2(pVCpu, cbInstr);
1328 return VINF_EM_RAW_EMULATE_INSTR;
1329# else
1330 LogFlow(("iemCImpl_stgi\n"));
1331 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, stgi);
1332 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_STGI))
1333 {
1334 Log2(("stgi: Guest intercept -> #VMEXIT\n"));
1335 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_STGI, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1336 }
1337
1338 pVCpu->cpum.GstCtx.hwvirt.fGif = true;
1339 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1340
1341# if defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM) && defined(IN_RING3)
1342 return EMR3SetExecutionPolicy(pVCpu->CTX_SUFF(pVM)->pUVM, EMEXECPOLICY_IEM_ALL, false);
1343# else
1344 return VINF_SUCCESS;
1345# endif
1346# endif
1347}
1348
1349
1350/**
1351 * Implements 'INVLPGA'.
1352 */
1353IEM_CIMPL_DEF_0(iemCImpl_invlpga)
1354{
1355 /** @todo Check effective address size using address size prefix. */
1356 RTGCPTR const GCPtrPage = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? pVCpu->cpum.GstCtx.rax : pVCpu->cpum.GstCtx.eax;
1357 /** @todo PGM needs virtual ASID support. */
1358# if 0
1359 uint32_t const uAsid = pVCpu->cpum.GstCtx.ecx;
1360# endif
1361
1362 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1363 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
1364 {
1365 Log2(("invlpga: Guest intercept (%RGp) -> #VMEXIT\n", GCPtrPage));
1366 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_INVLPGA, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1367 }
1368
1369 PGMInvalidatePage(pVCpu, GCPtrPage);
1370 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1371 return VINF_SUCCESS;
1372}
1373
1374
1375/**
1376 * Implements 'SKINIT'.
1377 */
1378IEM_CIMPL_DEF_0(iemCImpl_skinit)
1379{
1380 IEM_SVM_INSTR_COMMON_CHECKS(pVCpu, invlpga);
1381
1382 uint32_t uIgnore;
1383 uint32_t fFeaturesECX;
1384 CPUMGetGuestCpuId(pVCpu, 0x80000001, 0 /* iSubLeaf */, &uIgnore, &uIgnore, &fFeaturesECX, &uIgnore);
1385 if (!(fFeaturesECX & X86_CPUID_AMD_FEATURE_ECX_SKINIT))
1386 return iemRaiseUndefinedOpcode(pVCpu);
1387
1388 if (IEM_IS_SVM_CTRL_INTERCEPT_SET(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
1389 {
1390 Log2(("skinit: Guest intercept -> #VMEXIT\n"));
1391 IEM_RETURN_SVM_VMEXIT(pVCpu, SVM_EXIT_SKINIT, 0 /* uExitInfo1 */, 0 /* uExitInfo2 */);
1392 }
1393
1394 RT_NOREF(cbInstr);
1395 return VERR_IEM_INSTR_NOT_IMPLEMENTED;
1396}
1397
1398IEM_CIMPL_DEF_0(iemCImpl_svm_pause)
1399{
1400 bool fCheckIntercept = true;
1401 if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilter)
1402 {
1403 /* TSC based pause-filter thresholding. */
1404 if ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmPauseFilterThreshold
1405 && pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold > 0)
1406 {
1407 uint64_t const uTick = TMCpuTickGet(pVCpu);
1408 if (uTick - pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick > pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilterThreshold)
1409 pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter = IEM_GET_SVM_PAUSE_FILTER_COUNT(pVCpu);
1410 pVCpu->cpum.GstCtx.hwvirt.svm.uPrevPauseTick = uTick;
1411 }
1412
1413 /* Simple pause-filter counter. */
1414 if (pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter > 0)
1415 {
1416 --pVCpu->cpum.GstCtx.hwvirt.svm.cPauseFilter;
1417 fCheckIntercept = false;
1418 }
1419 }
1420
1421 if (fCheckIntercept)
1422 IEMOP_HLP_SVM_INSTR_INTERCEPT_AND_NRIP(pVCpu, SVM_CTRL_INTERCEPT_PAUSE, SVM_EXIT_PAUSE, 0, 0);
1423
1424 iemRegAddToRipAndClearRF(pVCpu, cbInstr);
1425 return VINF_SUCCESS;
1426}
1427
1428#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
1429
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